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Evan Chenga8e29892007-01-19 07:51:42 +00001//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +000020#include "ARMPerfectShuffle.h"
Evan Chenga8e29892007-01-19 07:51:42 +000021#include "ARMRegisterInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMTargetMachine.h"
Chris Lattner80ec2792009-08-02 00:34:36 +000024#include "ARMTargetObjectFile.h"
Evan Chenga8e29892007-01-19 07:51:42 +000025#include "llvm/CallingConv.h"
26#include "llvm/Constants.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +000027#include "llvm/Function.h"
Benjamin Kramer174101e2009-10-20 11:44:38 +000028#include "llvm/GlobalValue.h"
Evan Cheng27707472007-03-16 08:43:56 +000029#include "llvm/Instruction.h"
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +000030#include "llvm/Intrinsics.h"
Benjamin Kramer174101e2009-10-20 11:44:38 +000031#include "llvm/Type.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +000032#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +000033#include "llvm/CodeGen/MachineBasicBlock.h"
34#include "llvm/CodeGen/MachineFrameInfo.h"
35#include "llvm/CodeGen/MachineFunction.h"
36#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000037#include "llvm/CodeGen/MachineRegisterInfo.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +000038#include "llvm/CodeGen/PseudoSourceValue.h"
Evan Chenga8e29892007-01-19 07:51:42 +000039#include "llvm/CodeGen/SelectionDAG.h"
Evan Chengb6ab2542007-01-31 08:40:13 +000040#include "llvm/Target/TargetOptions.h"
Evan Chenga8e29892007-01-19 07:51:42 +000041#include "llvm/ADT/VectorExtras.h"
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +000042#include "llvm/Support/CommandLine.h"
Torok Edwinab7c09b2009-07-08 18:01:40 +000043#include "llvm/Support/ErrorHandling.h"
Evan Chengb01fad62007-03-12 23:30:29 +000044#include "llvm/Support/MathExtras.h"
Jim Grosbache801dc42009-12-12 01:40:06 +000045#include "llvm/Support/raw_ostream.h"
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +000046#include <sstream>
Evan Chenga8e29892007-01-19 07:51:42 +000047using namespace llvm;
48
Owen Andersone50ed302009-08-10 22:56:29 +000049static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +000050 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
52 CCState &State);
Owen Andersone50ed302009-08-10 22:56:29 +000053static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +000054 CCValAssign::LocInfo &LocInfo,
55 ISD::ArgFlagsTy &ArgFlags,
56 CCState &State);
Owen Andersone50ed302009-08-10 22:56:29 +000057static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +000058 CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags,
60 CCState &State);
Owen Andersone50ed302009-08-10 22:56:29 +000061static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +000062 CCValAssign::LocInfo &LocInfo,
63 ISD::ArgFlagsTy &ArgFlags,
64 CCState &State);
65
Owen Andersone50ed302009-08-10 22:56:29 +000066void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
67 EVT PromotedBitwiseVT) {
Bob Wilson5bafff32009-06-22 23:27:02 +000068 if (VT != PromotedLdStVT) {
Owen Anderson70671842009-08-10 20:18:46 +000069 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
Owen Andersond6662ad2009-08-10 20:46:15 +000070 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
71 PromotedLdStVT.getSimpleVT());
Bob Wilson5bafff32009-06-22 23:27:02 +000072
Owen Anderson70671842009-08-10 20:18:46 +000073 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
Jim Grosbach764ab522009-08-11 15:33:49 +000074 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
Owen Andersond6662ad2009-08-10 20:46:15 +000075 PromotedLdStVT.getSimpleVT());
Bob Wilson5bafff32009-06-22 23:27:02 +000076 }
77
Owen Andersone50ed302009-08-10 22:56:29 +000078 EVT ElemTy = VT.getVectorElementType();
Owen Anderson825b72b2009-08-11 20:47:22 +000079 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
Owen Anderson70671842009-08-10 20:18:46 +000080 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +000081 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
Owen Anderson70671842009-08-10 20:18:46 +000082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
Bob Wilson0696fdf2009-09-16 20:20:44 +000083 if (ElemTy != MVT::i32) {
84 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
85 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
86 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
87 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
88 }
Owen Anderson70671842009-08-10 20:18:46 +000089 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
Owen Anderson70671842009-08-10 20:18:46 +000091 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
Anton Korobeynikov8e6c2b92009-08-21 12:40:35 +000092 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
Bob Wilson5bafff32009-06-22 23:27:02 +000093 if (VT.isInteger()) {
Owen Anderson70671842009-08-10 20:18:46 +000094 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
Bob Wilson5bafff32009-06-22 23:27:02 +000097 }
98
99 // Promote all bit-wise operations.
100 if (VT.isInteger() && VT != PromotedBitwiseVT) {
Owen Anderson70671842009-08-10 20:18:46 +0000101 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
Owen Andersond6662ad2009-08-10 20:46:15 +0000102 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
103 PromotedBitwiseVT.getSimpleVT());
Owen Anderson70671842009-08-10 20:18:46 +0000104 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
Jim Grosbach764ab522009-08-11 15:33:49 +0000105 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
Owen Andersond6662ad2009-08-10 20:46:15 +0000106 PromotedBitwiseVT.getSimpleVT());
Owen Anderson70671842009-08-10 20:18:46 +0000107 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
Jim Grosbach764ab522009-08-11 15:33:49 +0000108 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
Owen Andersond6662ad2009-08-10 20:46:15 +0000109 PromotedBitwiseVT.getSimpleVT());
Bob Wilson5bafff32009-06-22 23:27:02 +0000110 }
Bob Wilson16330762009-09-16 00:17:28 +0000111
112 // Neon does not support vector divide/remainder operations.
113 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
Bob Wilson5bafff32009-06-22 23:27:02 +0000119}
120
Owen Andersone50ed302009-08-10 22:56:29 +0000121void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000122 addRegisterClass(VT, ARM::DPRRegisterClass);
Owen Anderson825b72b2009-08-11 20:47:22 +0000123 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
Bob Wilson5bafff32009-06-22 23:27:02 +0000124}
125
Owen Andersone50ed302009-08-10 22:56:29 +0000126void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000127 addRegisterClass(VT, ARM::QPRRegisterClass);
Owen Anderson825b72b2009-08-11 20:47:22 +0000128 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
Bob Wilson5bafff32009-06-22 23:27:02 +0000129}
130
Chris Lattnerf0144122009-07-28 03:13:23 +0000131static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
132 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
Chris Lattnerf26e03b2009-07-31 17:42:42 +0000133 return new TargetLoweringObjectFileMachO();
Chris Lattner80ec2792009-08-02 00:34:36 +0000134 return new ARMElfTargetObjectFile();
Chris Lattnerf0144122009-07-28 03:13:23 +0000135}
136
Evan Chenga8e29892007-01-19 07:51:42 +0000137ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
Evan Chenge7e0d622009-11-06 22:24:13 +0000138 : TargetLowering(TM, createTLOF(TM)) {
Evan Chenga8e29892007-01-19 07:51:42 +0000139 Subtarget = &TM.getSubtarget<ARMSubtarget>();
140
Evan Chengb1df8f22007-04-27 08:15:43 +0000141 if (Subtarget->isTargetDarwin()) {
Evan Chengb1df8f22007-04-27 08:15:43 +0000142 // Uses VFP for Thumb libfuncs if available.
143 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
144 // Single-precision floating-point arithmetic.
145 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
146 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
147 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
148 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
Evan Chenga8e29892007-01-19 07:51:42 +0000149
Evan Chengb1df8f22007-04-27 08:15:43 +0000150 // Double-precision floating-point arithmetic.
151 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
152 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
153 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
154 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
Evan Cheng193f8502007-01-31 09:30:58 +0000155
Evan Chengb1df8f22007-04-27 08:15:43 +0000156 // Single-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
158 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
159 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
160 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
161 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
162 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
163 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
164 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
Evan Chenga8e29892007-01-19 07:51:42 +0000165
Evan Chengb1df8f22007-04-27 08:15:43 +0000166 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
Evan Cheng193f8502007-01-31 09:30:58 +0000174
Evan Chengb1df8f22007-04-27 08:15:43 +0000175 // Double-precision comparisons.
176 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
177 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
178 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
179 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
180 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
181 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
182 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
183 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
Evan Chenga8e29892007-01-19 07:51:42 +0000184
Evan Chengb1df8f22007-04-27 08:15:43 +0000185 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
Evan Chenga8e29892007-01-19 07:51:42 +0000193
Evan Chengb1df8f22007-04-27 08:15:43 +0000194 // Floating-point to integer conversions.
195 // i64 conversions are done via library routines even when generating VFP
196 // instructions, so use the same ones.
197 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
198 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
199 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
200 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
Evan Chenga8e29892007-01-19 07:51:42 +0000201
Evan Chengb1df8f22007-04-27 08:15:43 +0000202 // Conversions between floating types.
203 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
204 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
205
206 // Integer to floating-point conversions.
207 // i64 conversions are done via library routines even when generating VFP
208 // instructions, so use the same ones.
Bob Wilson2a14c522009-03-20 23:16:43 +0000209 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
210 // e.g., __floatunsidf vs. __floatunssidfvfp.
Evan Chengb1df8f22007-04-27 08:15:43 +0000211 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
212 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
213 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
214 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
215 }
Evan Chenga8e29892007-01-19 07:51:42 +0000216 }
217
Bob Wilson2f954612009-05-22 17:38:41 +0000218 // These libcalls are not available in 32-bit.
219 setLibcallName(RTLIB::SHL_I128, 0);
220 setLibcallName(RTLIB::SRL_I128, 0);
221 setLibcallName(RTLIB::SRA_I128, 0);
222
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000223 // Libcalls should use the AAPCS base standard ABI, even if hard float
224 // is in effect, as per the ARM RTABI specification, section 4.1.2.
225 if (Subtarget->isAAPCS_ABI()) {
226 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
227 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
228 CallingConv::ARM_AAPCS);
229 }
230 }
231
David Goodwinf1daf7d2009-07-08 23:10:31 +0000232 if (Subtarget->isThumb1Only())
Owen Anderson825b72b2009-08-11 20:47:22 +0000233 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
Jim Grosbach30eae3c2009-04-07 20:34:09 +0000234 else
Owen Anderson825b72b2009-08-11 20:47:22 +0000235 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
David Goodwinf1daf7d2009-07-08 23:10:31 +0000236 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000237 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
238 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
Bob Wilson2dc4f542009-03-20 22:42:55 +0000239
Owen Anderson825b72b2009-08-11 20:47:22 +0000240 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000241 }
Bob Wilson5bafff32009-06-22 23:27:02 +0000242
243 if (Subtarget->hasNEON()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000244 addDRTypeForNEON(MVT::v2f32);
245 addDRTypeForNEON(MVT::v8i8);
246 addDRTypeForNEON(MVT::v4i16);
247 addDRTypeForNEON(MVT::v2i32);
248 addDRTypeForNEON(MVT::v1i64);
Bob Wilson5bafff32009-06-22 23:27:02 +0000249
Owen Anderson825b72b2009-08-11 20:47:22 +0000250 addQRTypeForNEON(MVT::v4f32);
251 addQRTypeForNEON(MVT::v2f64);
252 addQRTypeForNEON(MVT::v16i8);
253 addQRTypeForNEON(MVT::v8i16);
254 addQRTypeForNEON(MVT::v4i32);
255 addQRTypeForNEON(MVT::v2i64);
Bob Wilson5bafff32009-06-22 23:27:02 +0000256
Bob Wilson74dc72e2009-09-15 23:55:57 +0000257 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
258 // neither Neon nor VFP support any arithmetic operations on it.
259 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
260 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
261 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
262 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
263 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
264 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
265 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
266 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
267 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
268 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
269 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
270 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
271 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
272 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
273 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
274 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
275 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
276 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
277 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
278 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
279 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
280 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
281 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
282 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
283
Bob Wilson642b3292009-09-16 00:32:15 +0000284 // Neon does not support some operations on v1i64 and v2i64 types.
285 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
286 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
287 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
288 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
289
Bob Wilson5bafff32009-06-22 23:27:02 +0000290 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
291 setTargetDAGCombine(ISD::SHL);
292 setTargetDAGCombine(ISD::SRL);
293 setTargetDAGCombine(ISD::SRA);
294 setTargetDAGCombine(ISD::SIGN_EXTEND);
295 setTargetDAGCombine(ISD::ZERO_EXTEND);
296 setTargetDAGCombine(ISD::ANY_EXTEND);
297 }
298
Evan Cheng9f8cbd12007-05-18 00:19:34 +0000299 computeRegisterProperties();
Evan Chenga8e29892007-01-19 07:51:42 +0000300
301 // ARM does not have f32 extending load.
Owen Anderson825b72b2009-08-11 20:47:22 +0000302 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000303
Duncan Sandsf9c98e62008-01-23 20:39:46 +0000304 // ARM does not have i1 sign extending load.
Owen Anderson825b72b2009-08-11 20:47:22 +0000305 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Duncan Sandsf9c98e62008-01-23 20:39:46 +0000306
Evan Chenga8e29892007-01-19 07:51:42 +0000307 // ARM supports all 4 flavors of integer indexed load / store.
Evan Chenge88d5ce2009-07-02 07:28:31 +0000308 if (!Subtarget->isThumb1Only()) {
309 for (unsigned im = (unsigned)ISD::PRE_INC;
310 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000311 setIndexedLoadAction(im, MVT::i1, Legal);
312 setIndexedLoadAction(im, MVT::i8, Legal);
313 setIndexedLoadAction(im, MVT::i16, Legal);
314 setIndexedLoadAction(im, MVT::i32, Legal);
315 setIndexedStoreAction(im, MVT::i1, Legal);
316 setIndexedStoreAction(im, MVT::i8, Legal);
317 setIndexedStoreAction(im, MVT::i16, Legal);
318 setIndexedStoreAction(im, MVT::i32, Legal);
Evan Chenge88d5ce2009-07-02 07:28:31 +0000319 }
Evan Chenga8e29892007-01-19 07:51:42 +0000320 }
321
322 // i64 operation support.
Evan Cheng5b9fcd12009-07-07 01:17:28 +0000323 if (Subtarget->isThumb1Only()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000324 setOperationAction(ISD::MUL, MVT::i64, Expand);
325 setOperationAction(ISD::MULHU, MVT::i32, Expand);
326 setOperationAction(ISD::MULHS, MVT::i32, Expand);
327 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
328 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000329 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000330 setOperationAction(ISD::MUL, MVT::i64, Expand);
331 setOperationAction(ISD::MULHU, MVT::i32, Expand);
Evan Chengb6207242009-08-01 00:16:10 +0000332 if (!Subtarget->hasV6Ops())
Owen Anderson825b72b2009-08-11 20:47:22 +0000333 setOperationAction(ISD::MULHS, MVT::i32, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000334 }
Jim Grosbachc2b879f2009-10-31 19:38:01 +0000335 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
Jim Grosbachb4a976c2009-10-31 21:00:56 +0000336 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +0000337 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000338 setOperationAction(ISD::SRL, MVT::i64, Custom);
339 setOperationAction(ISD::SRA, MVT::i64, Custom);
Evan Chenga8e29892007-01-19 07:51:42 +0000340
341 // ARM does not have ROTL.
Owen Anderson825b72b2009-08-11 20:47:22 +0000342 setOperationAction(ISD::ROTL, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
344 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
David Goodwin24062ac2009-06-26 20:47:43 +0000345 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
Owen Anderson825b72b2009-08-11 20:47:22 +0000346 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000347
Lauro Ramos Venancio368f20f2007-03-16 22:54:16 +0000348 // Only ARMv6 has BSWAP.
349 if (!Subtarget->hasV6Ops())
Owen Anderson825b72b2009-08-11 20:47:22 +0000350 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Lauro Ramos Venancio368f20f2007-03-16 22:54:16 +0000351
Evan Chenga8e29892007-01-19 07:51:42 +0000352 // These are expanded into libcalls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000353 setOperationAction(ISD::SDIV, MVT::i32, Expand);
354 setOperationAction(ISD::UDIV, MVT::i32, Expand);
355 setOperationAction(ISD::SREM, MVT::i32, Expand);
356 setOperationAction(ISD::UREM, MVT::i32, Expand);
357 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
358 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
Bob Wilson2dc4f542009-03-20 22:42:55 +0000359
Owen Anderson825b72b2009-08-11 20:47:22 +0000360 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
361 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
362 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
363 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
Bob Wilsonddb16df2009-10-30 05:45:42 +0000364 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Evan Chenga8e29892007-01-19 07:51:42 +0000365
Evan Chenga8e29892007-01-19 07:51:42 +0000366 // Use the default implementation.
Owen Anderson825b72b2009-08-11 20:47:22 +0000367 setOperationAction(ISD::VASTART, MVT::Other, Custom);
368 setOperationAction(ISD::VAARG, MVT::Other, Expand);
369 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
370 setOperationAction(ISD::VAEND, MVT::Other, Expand);
371 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
372 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Jim Grosbachbff39232009-08-12 17:38:44 +0000373 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
374 // FIXME: Shouldn't need this, since no register is used, but the legalizer
375 // doesn't yet know how to not do that for SjLj.
376 setExceptionSelectorRegister(ARM::R0);
Evan Cheng86198642009-08-07 00:34:42 +0000377 if (Subtarget->isThumb())
Owen Anderson825b72b2009-08-11 20:47:22 +0000378 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Evan Cheng86198642009-08-07 00:34:42 +0000379 else
Owen Anderson825b72b2009-08-11 20:47:22 +0000380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
Jim Grosbach3728e962009-12-10 00:11:09 +0000381 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
Evan Chenga8e29892007-01-19 07:51:42 +0000382
Evan Chengd27c9fc2009-07-03 01:43:10 +0000383 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000386 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
Evan Chenga8e29892007-01-19 07:51:42 +0000388
David Goodwinf1daf7d2009-07-08 23:10:31 +0000389 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
Jim Grosbache5165492009-11-09 00:11:35 +0000390 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR iff target supports vfp2.
Owen Anderson825b72b2009-08-11 20:47:22 +0000391 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +0000392
393 // We want to custom lower some of our intrinsics.
Owen Anderson825b72b2009-08-11 20:47:22 +0000394 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +0000395
Owen Anderson825b72b2009-08-11 20:47:22 +0000396 setOperationAction(ISD::SETCC, MVT::i32, Expand);
397 setOperationAction(ISD::SETCC, MVT::f32, Expand);
398 setOperationAction(ISD::SETCC, MVT::f64, Expand);
399 setOperationAction(ISD::SELECT, MVT::i32, Expand);
400 setOperationAction(ISD::SELECT, MVT::f32, Expand);
401 setOperationAction(ISD::SELECT, MVT::f64, Expand);
402 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
403 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
404 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
Evan Chenga8e29892007-01-19 07:51:42 +0000405
Owen Anderson825b72b2009-08-11 20:47:22 +0000406 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
407 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
408 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
409 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
410 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
Evan Chenga8e29892007-01-19 07:51:42 +0000411
Dan Gohmanf96e4de2007-10-11 23:21:31 +0000412 // We don't support sin/cos/fmod/copysign/pow
Owen Anderson825b72b2009-08-11 20:47:22 +0000413 setOperationAction(ISD::FSIN, MVT::f64, Expand);
414 setOperationAction(ISD::FSIN, MVT::f32, Expand);
415 setOperationAction(ISD::FCOS, MVT::f32, Expand);
416 setOperationAction(ISD::FCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FREM, MVT::f64, Expand);
418 setOperationAction(ISD::FREM, MVT::f32, Expand);
David Goodwinf1daf7d2009-07-08 23:10:31 +0000419 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000420 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
421 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
Evan Cheng110cf482008-04-01 01:50:16 +0000422 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000423 setOperationAction(ISD::FPOW, MVT::f64, Expand);
424 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Bob Wilson2dc4f542009-03-20 22:42:55 +0000425
Evan Chenga8e29892007-01-19 07:51:42 +0000426 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
David Goodwinf1daf7d2009-07-08 23:10:31 +0000427 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000428 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
429 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
430 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
431 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
Evan Cheng110cf482008-04-01 01:50:16 +0000432 }
Evan Chenga8e29892007-01-19 07:51:42 +0000433
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +0000434 // We have target-specific dag combine patterns for the following nodes:
Jim Grosbache5165492009-11-09 00:11:35 +0000435 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
Chris Lattnerd1980a52009-03-12 06:52:53 +0000436 setTargetDAGCombine(ISD::ADD);
437 setTargetDAGCombine(ISD::SUB);
Bob Wilson2dc4f542009-03-20 22:42:55 +0000438
Evan Chenga8e29892007-01-19 07:51:42 +0000439 setStackPointerRegisterToSaveRestore(ARM::SP);
Evan Chenga8e29892007-01-19 07:51:42 +0000440 setSchedulingPreference(SchedulingForRegPressure);
Dale Johannesen8dd86c12007-05-17 21:31:21 +0000441
Evan Chengbc9b7542009-08-15 07:59:10 +0000442 // FIXME: If-converter should use instruction latency to determine
443 // profitability rather than relying on fixed limits.
444 if (Subtarget->getCPUString() == "generic") {
445 // Generic (and overly aggressive) if-conversion limits.
446 setIfCvtBlockSizeLimit(10);
447 setIfCvtDupBlockSizeLimit(2);
448 } else if (Subtarget->hasV6Ops()) {
449 setIfCvtBlockSizeLimit(2);
450 setIfCvtDupBlockSizeLimit(1);
451 } else {
452 setIfCvtBlockSizeLimit(3);
453 setIfCvtDupBlockSizeLimit(2);
Evan Cheng8557c2b2009-06-19 01:51:50 +0000454 }
455
Dale Johannesen8dd86c12007-05-17 21:31:21 +0000456 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
Bob Wilsone6abdff2009-05-18 20:55:32 +0000457 // Do not enable CodePlacementOpt for now: it currently runs after the
458 // ARMConstantIslandPass and messes up branch relaxation and placement
459 // of constant islands.
460 // benefitFromCodePlacementOpt = true;
Evan Chenga8e29892007-01-19 07:51:42 +0000461}
462
Evan Chenga8e29892007-01-19 07:51:42 +0000463const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
464 switch (Opcode) {
465 default: return 0;
466 case ARMISD::Wrapper: return "ARMISD::Wrapper";
Evan Chenga8e29892007-01-19 07:51:42 +0000467 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
468 case ARMISD::CALL: return "ARMISD::CALL";
Evan Cheng277f0742007-06-19 21:05:09 +0000469 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
Evan Chenga8e29892007-01-19 07:51:42 +0000470 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
471 case ARMISD::tCALL: return "ARMISD::tCALL";
472 case ARMISD::BRCOND: return "ARMISD::BRCOND";
473 case ARMISD::BR_JT: return "ARMISD::BR_JT";
Evan Cheng5657c012009-07-29 02:18:14 +0000474 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
Evan Chenga8e29892007-01-19 07:51:42 +0000475 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
476 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
477 case ARMISD::CMP: return "ARMISD::CMP";
David Goodwinc0309b42009-06-29 15:33:01 +0000478 case ARMISD::CMPZ: return "ARMISD::CMPZ";
Evan Chenga8e29892007-01-19 07:51:42 +0000479 case ARMISD::CMPFP: return "ARMISD::CMPFP";
480 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
481 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
482 case ARMISD::CMOV: return "ARMISD::CMOV";
483 case ARMISD::CNEG: return "ARMISD::CNEG";
Bob Wilson2dc4f542009-03-20 22:42:55 +0000484
Evan Chenga8e29892007-01-19 07:51:42 +0000485 case ARMISD::FTOSI: return "ARMISD::FTOSI";
486 case ARMISD::FTOUI: return "ARMISD::FTOUI";
487 case ARMISD::SITOF: return "ARMISD::SITOF";
488 case ARMISD::UITOF: return "ARMISD::UITOF";
Evan Chenga8e29892007-01-19 07:51:42 +0000489
490 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
491 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
492 case ARMISD::RRX: return "ARMISD::RRX";
Bob Wilson2dc4f542009-03-20 22:42:55 +0000493
Jim Grosbache5165492009-11-09 00:11:35 +0000494 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
495 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000496
Evan Chengc5942082009-10-28 06:55:03 +0000497 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
498 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
499
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000500 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
Bob Wilson5bafff32009-06-22 23:27:02 +0000501
Evan Cheng86198642009-08-07 00:34:42 +0000502 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
503
Jim Grosbach3728e962009-12-10 00:11:09 +0000504 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
505 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
506
Bob Wilson5bafff32009-06-22 23:27:02 +0000507 case ARMISD::VCEQ: return "ARMISD::VCEQ";
508 case ARMISD::VCGE: return "ARMISD::VCGE";
509 case ARMISD::VCGEU: return "ARMISD::VCGEU";
510 case ARMISD::VCGT: return "ARMISD::VCGT";
511 case ARMISD::VCGTU: return "ARMISD::VCGTU";
512 case ARMISD::VTST: return "ARMISD::VTST";
513
514 case ARMISD::VSHL: return "ARMISD::VSHL";
515 case ARMISD::VSHRs: return "ARMISD::VSHRs";
516 case ARMISD::VSHRu: return "ARMISD::VSHRu";
517 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
518 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
519 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
520 case ARMISD::VSHRN: return "ARMISD::VSHRN";
521 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
522 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
523 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
524 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
525 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
526 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
527 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
528 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
529 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
530 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
531 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
532 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
533 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
534 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000535 case ARMISD::VDUP: return "ARMISD::VDUP";
Bob Wilson0ce37102009-08-14 05:08:32 +0000536 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000537 case ARMISD::VEXT: return "ARMISD::VEXT";
Bob Wilsond8e17572009-08-12 22:31:50 +0000538 case ARMISD::VREV64: return "ARMISD::VREV64";
539 case ARMISD::VREV32: return "ARMISD::VREV32";
540 case ARMISD::VREV16: return "ARMISD::VREV16";
Anton Korobeynikov051cfd62009-08-21 12:41:42 +0000541 case ARMISD::VZIP: return "ARMISD::VZIP";
542 case ARMISD::VUZP: return "ARMISD::VUZP";
543 case ARMISD::VTRN: return "ARMISD::VTRN";
Evan Chenga8e29892007-01-19 07:51:42 +0000544 }
545}
546
Bill Wendlingb4202b82009-07-01 18:50:55 +0000547/// getFunctionAlignment - Return the Log2 alignment of this function.
Bill Wendling20c568f2009-06-30 22:38:32 +0000548unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
Evan Cheng048e36f2009-10-02 06:57:25 +0000549 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
Bill Wendling20c568f2009-06-30 22:38:32 +0000550}
551
Evan Chenga8e29892007-01-19 07:51:42 +0000552//===----------------------------------------------------------------------===//
553// Lowering Code
554//===----------------------------------------------------------------------===//
555
Evan Chenga8e29892007-01-19 07:51:42 +0000556/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
557static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
558 switch (CC) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000559 default: llvm_unreachable("Unknown condition code!");
Evan Chenga8e29892007-01-19 07:51:42 +0000560 case ISD::SETNE: return ARMCC::NE;
561 case ISD::SETEQ: return ARMCC::EQ;
562 case ISD::SETGT: return ARMCC::GT;
563 case ISD::SETGE: return ARMCC::GE;
564 case ISD::SETLT: return ARMCC::LT;
565 case ISD::SETLE: return ARMCC::LE;
566 case ISD::SETUGT: return ARMCC::HI;
567 case ISD::SETUGE: return ARMCC::HS;
568 case ISD::SETULT: return ARMCC::LO;
569 case ISD::SETULE: return ARMCC::LS;
570 }
571}
572
Bob Wilsoncd3b9a42009-09-09 23:14:54 +0000573/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
574static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
Evan Chenga8e29892007-01-19 07:51:42 +0000575 ARMCC::CondCodes &CondCode2) {
Evan Chenga8e29892007-01-19 07:51:42 +0000576 CondCode2 = ARMCC::AL;
577 switch (CC) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000578 default: llvm_unreachable("Unknown FP condition!");
Evan Chenga8e29892007-01-19 07:51:42 +0000579 case ISD::SETEQ:
580 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
581 case ISD::SETGT:
582 case ISD::SETOGT: CondCode = ARMCC::GT; break;
583 case ISD::SETGE:
584 case ISD::SETOGE: CondCode = ARMCC::GE; break;
585 case ISD::SETOLT: CondCode = ARMCC::MI; break;
Bob Wilsoncd3b9a42009-09-09 23:14:54 +0000586 case ISD::SETOLE: CondCode = ARMCC::LS; break;
Evan Chenga8e29892007-01-19 07:51:42 +0000587 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
588 case ISD::SETO: CondCode = ARMCC::VC; break;
589 case ISD::SETUO: CondCode = ARMCC::VS; break;
590 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
591 case ISD::SETUGT: CondCode = ARMCC::HI; break;
592 case ISD::SETUGE: CondCode = ARMCC::PL; break;
593 case ISD::SETLT:
594 case ISD::SETULT: CondCode = ARMCC::LT; break;
595 case ISD::SETLE:
596 case ISD::SETULE: CondCode = ARMCC::LE; break;
597 case ISD::SETNE:
598 case ISD::SETUNE: CondCode = ARMCC::NE; break;
599 }
Evan Chenga8e29892007-01-19 07:51:42 +0000600}
601
Bob Wilson1f595bb2009-04-17 19:07:39 +0000602//===----------------------------------------------------------------------===//
603// Calling Convention Implementation
Bob Wilson1f595bb2009-04-17 19:07:39 +0000604//===----------------------------------------------------------------------===//
605
606#include "ARMGenCallingConv.inc"
607
608// APCS f64 is in register pairs, possibly split to stack
Owen Andersone50ed302009-08-10 22:56:29 +0000609static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson5bafff32009-06-22 23:27:02 +0000610 CCValAssign::LocInfo &LocInfo,
611 CCState &State, bool CanFail) {
612 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
613
614 // Try to get the first register.
615 if (unsigned Reg = State.AllocateReg(RegList, 4))
616 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
617 else {
618 // For the 2nd half of a v2f64, do not fail.
619 if (CanFail)
620 return false;
621
622 // Put the whole thing on the stack.
623 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
624 State.AllocateStack(8, 4),
625 LocVT, LocInfo));
626 return true;
627 }
628
629 // Try to get the second register.
630 if (unsigned Reg = State.AllocateReg(RegList, 4))
631 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
632 else
633 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
634 State.AllocateStack(4, 4),
635 LocVT, LocInfo));
636 return true;
637}
638
Owen Andersone50ed302009-08-10 22:56:29 +0000639static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +0000640 CCValAssign::LocInfo &LocInfo,
641 ISD::ArgFlagsTy &ArgFlags,
642 CCState &State) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000643 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
644 return false;
Owen Anderson825b72b2009-08-11 20:47:22 +0000645 if (LocVT == MVT::v2f64 &&
Bob Wilson5bafff32009-06-22 23:27:02 +0000646 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
647 return false;
Bob Wilsone65586b2009-04-17 20:40:45 +0000648 return true; // we handled it
Bob Wilson1f595bb2009-04-17 19:07:39 +0000649}
650
651// AAPCS f64 is in aligned register pairs
Owen Andersone50ed302009-08-10 22:56:29 +0000652static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson5bafff32009-06-22 23:27:02 +0000653 CCValAssign::LocInfo &LocInfo,
654 CCState &State, bool CanFail) {
655 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
656 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
657
658 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
659 if (Reg == 0) {
660 // For the 2nd half of a v2f64, do not just fail.
661 if (CanFail)
662 return false;
663
664 // Put the whole thing on the stack.
665 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
666 State.AllocateStack(8, 8),
667 LocVT, LocInfo));
668 return true;
669 }
670
671 unsigned i;
672 for (i = 0; i < 2; ++i)
673 if (HiRegList[i] == Reg)
674 break;
675
676 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
677 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
678 LocVT, LocInfo));
679 return true;
680}
681
Owen Andersone50ed302009-08-10 22:56:29 +0000682static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +0000683 CCValAssign::LocInfo &LocInfo,
684 ISD::ArgFlagsTy &ArgFlags,
685 CCState &State) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000686 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
687 return false;
Owen Anderson825b72b2009-08-11 20:47:22 +0000688 if (LocVT == MVT::v2f64 &&
Bob Wilson5bafff32009-06-22 23:27:02 +0000689 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
690 return false;
691 return true; // we handled it
692}
693
Owen Andersone50ed302009-08-10 22:56:29 +0000694static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson5bafff32009-06-22 23:27:02 +0000695 CCValAssign::LocInfo &LocInfo, CCState &State) {
Bob Wilson1f595bb2009-04-17 19:07:39 +0000696 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
697 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
698
Bob Wilsone65586b2009-04-17 20:40:45 +0000699 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
700 if (Reg == 0)
701 return false; // we didn't handle it
Bob Wilson1f595bb2009-04-17 19:07:39 +0000702
Bob Wilsone65586b2009-04-17 20:40:45 +0000703 unsigned i;
704 for (i = 0; i < 2; ++i)
705 if (HiRegList[i] == Reg)
706 break;
Bob Wilson1f595bb2009-04-17 19:07:39 +0000707
Bob Wilson5bafff32009-06-22 23:27:02 +0000708 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bob Wilsone65586b2009-04-17 20:40:45 +0000709 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
Bob Wilson5bafff32009-06-22 23:27:02 +0000710 LocVT, LocInfo));
711 return true;
Bob Wilson1f595bb2009-04-17 19:07:39 +0000712}
713
Owen Andersone50ed302009-08-10 22:56:29 +0000714static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +0000715 CCValAssign::LocInfo &LocInfo,
716 ISD::ArgFlagsTy &ArgFlags,
717 CCState &State) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000718 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
719 return false;
Owen Anderson825b72b2009-08-11 20:47:22 +0000720 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
Bob Wilson5bafff32009-06-22 23:27:02 +0000721 return false;
Bob Wilsone65586b2009-04-17 20:40:45 +0000722 return true; // we handled it
Bob Wilson1f595bb2009-04-17 19:07:39 +0000723}
724
Owen Andersone50ed302009-08-10 22:56:29 +0000725static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
Bob Wilson1f595bb2009-04-17 19:07:39 +0000726 CCValAssign::LocInfo &LocInfo,
727 ISD::ArgFlagsTy &ArgFlags,
728 CCState &State) {
729 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
730 State);
731}
732
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000733/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
734/// given CallingConvention value.
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000735CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000736 bool Return,
737 bool isVarArg) const {
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000738 switch (CC) {
739 default:
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000740 llvm_unreachable("Unsupported calling convention");
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000741 case CallingConv::C:
742 case CallingConv::Fast:
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000743 // Use target triple & subtarget features to do actual dispatch.
744 if (Subtarget->isAAPCS_ABI()) {
745 if (Subtarget->hasVFP2() &&
746 FloatABIType == FloatABI::Hard && !isVarArg)
747 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
748 else
749 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
750 } else
751 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000752 case CallingConv::ARM_AAPCS_VFP:
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000753 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000754 case CallingConv::ARM_AAPCS:
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000755 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000756 case CallingConv::ARM_APCS:
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000757 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
Anton Korobeynikov385f5a92009-06-16 18:50:49 +0000758 }
759}
760
Dan Gohman98ca4f22009-08-05 01:29:28 +0000761/// LowerCallResult - Lower the result values of a call into the
762/// appropriate copies out of appropriate physical registers.
763SDValue
764ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000765 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000766 const SmallVectorImpl<ISD::InputArg> &Ins,
767 DebugLoc dl, SelectionDAG &DAG,
768 SmallVectorImpl<SDValue> &InVals) {
Bob Wilson1f595bb2009-04-17 19:07:39 +0000769
Bob Wilson1f595bb2009-04-17 19:07:39 +0000770 // Assign locations to each value returned by this call.
771 SmallVector<CCValAssign, 16> RVLocs;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000772 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
Owen Andersone922c022009-07-22 00:24:57 +0000773 RVLocs, *DAG.getContext());
Dan Gohman98ca4f22009-08-05 01:29:28 +0000774 CCInfo.AnalyzeCallResult(Ins,
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000775 CCAssignFnForNode(CallConv, /* Return*/ true,
776 isVarArg));
Bob Wilson1f595bb2009-04-17 19:07:39 +0000777
778 // Copy all of the result registers out of their specified physreg.
779 for (unsigned i = 0; i != RVLocs.size(); ++i) {
780 CCValAssign VA = RVLocs[i];
781
Bob Wilson80915242009-04-25 00:33:20 +0000782 SDValue Val;
Bob Wilson1f595bb2009-04-17 19:07:39 +0000783 if (VA.needsCustom()) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000784 // Handle f64 or half of a v2f64.
Owen Anderson825b72b2009-08-11 20:47:22 +0000785 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
Bob Wilson1f595bb2009-04-17 19:07:39 +0000786 InFlag);
Bob Wilson4d59e1d2009-04-24 17:00:36 +0000787 Chain = Lo.getValue(1);
788 InFlag = Lo.getValue(2);
Bob Wilson1f595bb2009-04-17 19:07:39 +0000789 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson825b72b2009-08-11 20:47:22 +0000790 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
Bob Wilson4d59e1d2009-04-24 17:00:36 +0000791 InFlag);
792 Chain = Hi.getValue(1);
793 InFlag = Hi.getValue(2);
Jim Grosbache5165492009-11-09 00:11:35 +0000794 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Bob Wilson5bafff32009-06-22 23:27:02 +0000795
Owen Anderson825b72b2009-08-11 20:47:22 +0000796 if (VA.getLocVT() == MVT::v2f64) {
797 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
798 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
799 DAG.getConstant(0, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +0000800
801 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson825b72b2009-08-11 20:47:22 +0000802 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Bob Wilson5bafff32009-06-22 23:27:02 +0000803 Chain = Lo.getValue(1);
804 InFlag = Lo.getValue(2);
805 VA = RVLocs[++i]; // skip ahead to next loc
Owen Anderson825b72b2009-08-11 20:47:22 +0000806 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
Bob Wilson5bafff32009-06-22 23:27:02 +0000807 Chain = Hi.getValue(1);
808 InFlag = Hi.getValue(2);
Jim Grosbache5165492009-11-09 00:11:35 +0000809 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Owen Anderson825b72b2009-08-11 20:47:22 +0000810 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
811 DAG.getConstant(1, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +0000812 }
Bob Wilson1f595bb2009-04-17 19:07:39 +0000813 } else {
Bob Wilson80915242009-04-25 00:33:20 +0000814 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
815 InFlag);
Bob Wilson4d59e1d2009-04-24 17:00:36 +0000816 Chain = Val.getValue(1);
817 InFlag = Val.getValue(2);
Bob Wilson1f595bb2009-04-17 19:07:39 +0000818 }
Bob Wilson80915242009-04-25 00:33:20 +0000819
820 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000821 default: llvm_unreachable("Unknown loc info!");
Bob Wilson80915242009-04-25 00:33:20 +0000822 case CCValAssign::Full: break;
823 case CCValAssign::BCvt:
824 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
825 break;
826 }
827
Dan Gohman98ca4f22009-08-05 01:29:28 +0000828 InVals.push_back(Val);
Bob Wilson1f595bb2009-04-17 19:07:39 +0000829 }
830
Dan Gohman98ca4f22009-08-05 01:29:28 +0000831 return Chain;
Bob Wilson1f595bb2009-04-17 19:07:39 +0000832}
833
834/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
835/// by "Src" to address "Dst" of size "Size". Alignment information is
Bob Wilsondee46d72009-04-17 20:35:10 +0000836/// specified by the specific parameter attribute. The copy will be passed as
Bob Wilson1f595bb2009-04-17 19:07:39 +0000837/// a byval function parameter.
838/// Sometimes what we are copying is the end of a larger object, the part that
839/// does not fit in registers.
840static SDValue
841CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
842 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
843 DebugLoc dl) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000844 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
Bob Wilson1f595bb2009-04-17 19:07:39 +0000845 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
846 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
847}
848
Bob Wilsondee46d72009-04-17 20:35:10 +0000849/// LowerMemOpCallTo - Store the argument to the stack.
Bob Wilson1f595bb2009-04-17 19:07:39 +0000850SDValue
Dan Gohman98ca4f22009-08-05 01:29:28 +0000851ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
852 SDValue StackPtr, SDValue Arg,
853 DebugLoc dl, SelectionDAG &DAG,
854 const CCValAssign &VA,
855 ISD::ArgFlagsTy Flags) {
Bob Wilson1f595bb2009-04-17 19:07:39 +0000856 unsigned LocMemOffset = VA.getLocMemOffset();
857 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
858 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
859 if (Flags.isByVal()) {
860 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
861 }
862 return DAG.getStore(Chain, dl, Arg, PtrOff,
863 PseudoSourceValue::getStack(), LocMemOffset);
Evan Chenga8e29892007-01-19 07:51:42 +0000864}
865
Dan Gohman98ca4f22009-08-05 01:29:28 +0000866void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000867 SDValue Chain, SDValue &Arg,
868 RegsToPassVector &RegsToPass,
869 CCValAssign &VA, CCValAssign &NextVA,
870 SDValue &StackPtr,
871 SmallVector<SDValue, 8> &MemOpChains,
872 ISD::ArgFlagsTy Flags) {
Bob Wilson5bafff32009-06-22 23:27:02 +0000873
Jim Grosbache5165492009-11-09 00:11:35 +0000874 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson825b72b2009-08-11 20:47:22 +0000875 DAG.getVTList(MVT::i32, MVT::i32), Arg);
Bob Wilson5bafff32009-06-22 23:27:02 +0000876 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
877
878 if (NextVA.isRegLoc())
879 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
880 else {
881 assert(NextVA.isMemLoc());
882 if (StackPtr.getNode() == 0)
883 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
884
Dan Gohman98ca4f22009-08-05 01:29:28 +0000885 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
886 dl, DAG, NextVA,
887 Flags));
Bob Wilson5bafff32009-06-22 23:27:02 +0000888 }
889}
890
Dan Gohman98ca4f22009-08-05 01:29:28 +0000891/// LowerCall - Lowering a call into a callseq_start <-
Evan Chengfc403422007-02-03 08:53:01 +0000892/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
893/// nodes.
Dan Gohman98ca4f22009-08-05 01:29:28 +0000894SDValue
895ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000896 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000897 bool isTailCall,
898 const SmallVectorImpl<ISD::OutputArg> &Outs,
899 const SmallVectorImpl<ISD::InputArg> &Ins,
900 DebugLoc dl, SelectionDAG &DAG,
901 SmallVectorImpl<SDValue> &InVals) {
Evan Chenga8e29892007-01-19 07:51:42 +0000902
Bob Wilson1f595bb2009-04-17 19:07:39 +0000903 // Analyze operands of the call, assigning locations to each operand.
904 SmallVector<CCValAssign, 16> ArgLocs;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000905 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
906 *DAG.getContext());
907 CCInfo.AnalyzeCallOperands(Outs,
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000908 CCAssignFnForNode(CallConv, /* Return*/ false,
909 isVarArg));
Evan Chenga8e29892007-01-19 07:51:42 +0000910
Bob Wilson1f595bb2009-04-17 19:07:39 +0000911 // Get a count of how many bytes are to be pushed on the stack.
912 unsigned NumBytes = CCInfo.getNextStackOffset();
Evan Chenga8e29892007-01-19 07:51:42 +0000913
914 // Adjust the stack pointer for the new arguments...
915 // These operations are automatically eliminated by the prolog/epilog pass
Chris Lattnere563bbc2008-10-11 22:08:30 +0000916 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
Evan Chenga8e29892007-01-19 07:51:42 +0000917
Owen Anderson825b72b2009-08-11 20:47:22 +0000918 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
Evan Chenga8e29892007-01-19 07:51:42 +0000919
Bob Wilson5bafff32009-06-22 23:27:02 +0000920 RegsToPassVector RegsToPass;
Bob Wilson1f595bb2009-04-17 19:07:39 +0000921 SmallVector<SDValue, 8> MemOpChains;
Evan Chenga8e29892007-01-19 07:51:42 +0000922
Bob Wilson1f595bb2009-04-17 19:07:39 +0000923 // Walk the register/memloc assignments, inserting copies/loads. In the case
Bob Wilsondee46d72009-04-17 20:35:10 +0000924 // of tail call optimization, arguments are handled later.
Bob Wilson1f595bb2009-04-17 19:07:39 +0000925 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
926 i != e;
927 ++i, ++realArgIdx) {
928 CCValAssign &VA = ArgLocs[i];
Dan Gohman98ca4f22009-08-05 01:29:28 +0000929 SDValue Arg = Outs[realArgIdx].Val;
930 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
Evan Chenga8e29892007-01-19 07:51:42 +0000931
Bob Wilson1f595bb2009-04-17 19:07:39 +0000932 // Promote the value if needed.
933 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000934 default: llvm_unreachable("Unknown loc info!");
Bob Wilson1f595bb2009-04-17 19:07:39 +0000935 case CCValAssign::Full: break;
936 case CCValAssign::SExt:
937 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
938 break;
939 case CCValAssign::ZExt:
940 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
941 break;
942 case CCValAssign::AExt:
943 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
944 break;
945 case CCValAssign::BCvt:
946 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
947 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000948 }
949
Anton Korobeynikov567d14f2009-08-05 19:04:42 +0000950 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
Bob Wilson1f595bb2009-04-17 19:07:39 +0000951 if (VA.needsCustom()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000952 if (VA.getLocVT() == MVT::v2f64) {
953 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
954 DAG.getConstant(0, MVT::i32));
955 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
956 DAG.getConstant(1, MVT::i32));
Bob Wilson1f595bb2009-04-17 19:07:39 +0000957
Dan Gohman98ca4f22009-08-05 01:29:28 +0000958 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
Bob Wilson5bafff32009-06-22 23:27:02 +0000959 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
960
961 VA = ArgLocs[++i]; // skip ahead to next loc
962 if (VA.isRegLoc()) {
Dan Gohman98ca4f22009-08-05 01:29:28 +0000963 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
Bob Wilson5bafff32009-06-22 23:27:02 +0000964 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
965 } else {
966 assert(VA.isMemLoc());
967 if (StackPtr.getNode() == 0)
968 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
969
Dan Gohman98ca4f22009-08-05 01:29:28 +0000970 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
971 dl, DAG, VA, Flags));
Bob Wilson5bafff32009-06-22 23:27:02 +0000972 }
973 } else {
Dan Gohman98ca4f22009-08-05 01:29:28 +0000974 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
Bob Wilson5bafff32009-06-22 23:27:02 +0000975 StackPtr, MemOpChains, Flags);
Bob Wilson1f595bb2009-04-17 19:07:39 +0000976 }
977 } else if (VA.isRegLoc()) {
978 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
979 } else {
980 assert(VA.isMemLoc());
981 if (StackPtr.getNode() == 0)
982 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
983
Dan Gohman98ca4f22009-08-05 01:29:28 +0000984 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
985 dl, DAG, VA, Flags));
Bob Wilson1f595bb2009-04-17 19:07:39 +0000986 }
Evan Chenga8e29892007-01-19 07:51:42 +0000987 }
988
989 if (!MemOpChains.empty())
Owen Anderson825b72b2009-08-11 20:47:22 +0000990 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Evan Chenga8e29892007-01-19 07:51:42 +0000991 &MemOpChains[0], MemOpChains.size());
992
993 // Build a sequence of copy-to-reg nodes chained together with token chain
994 // and flag operands which copy the outgoing args into the appropriate regs.
Dan Gohman475871a2008-07-27 21:46:04 +0000995 SDValue InFlag;
Evan Chenga8e29892007-01-19 07:51:42 +0000996 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
Bob Wilson2dc4f542009-03-20 22:42:55 +0000997 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
Dale Johannesen33c960f2009-02-04 20:06:27 +0000998 RegsToPass[i].second, InFlag);
Evan Chenga8e29892007-01-19 07:51:42 +0000999 InFlag = Chain.getValue(1);
1000 }
1001
Bill Wendling056292f2008-09-16 21:48:12 +00001002 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1003 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1004 // node so that legalize doesn't hack it.
Evan Chenga8e29892007-01-19 07:51:42 +00001005 bool isDirect = false;
1006 bool isARMFunc = false;
Evan Cheng277f0742007-06-19 21:05:09 +00001007 bool isLocalARMFunc = false;
Evan Chenge7e0d622009-11-06 22:24:13 +00001008 MachineFunction &MF = DAG.getMachineFunction();
1009 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
Evan Chenga8e29892007-01-19 07:51:42 +00001010 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1011 GlobalValue *GV = G->getGlobal();
Evan Chenga8e29892007-01-19 07:51:42 +00001012 isDirect = true;
Chris Lattner4fb63d02009-07-15 04:12:33 +00001013 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
Evan Cheng970a4192007-01-19 19:28:01 +00001014 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
Evan Chenga8e29892007-01-19 07:51:42 +00001015 getTargetMachine().getRelocationModel() != Reloc::Static;
1016 isARMFunc = !Subtarget->isThumb() || isStub;
Evan Cheng277f0742007-06-19 21:05:09 +00001017 // ARM call to a local ARM function is predicable.
1018 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
Evan Chengc60e76d2007-01-30 20:37:08 +00001019 // tBX takes a register source operand.
David Goodwinf1daf7d2009-07-08 23:10:31 +00001020 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001021 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Evan Chenge4e4ed32009-08-28 23:18:09 +00001022 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +00001023 ARMPCLabelIndex,
1024 ARMCP::CPValue, 4);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001025 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001026 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001027 Callee = DAG.getLoad(getPointerTy(), dl,
Evan Cheng9eda6892009-10-31 03:39:36 +00001028 DAG.getEntryNode(), CPAddr,
1029 PseudoSourceValue::getConstantPool(), 0);
Evan Chenge7e0d622009-11-06 22:24:13 +00001030 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001031 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
Dale Johannesen33c960f2009-02-04 20:06:27 +00001032 getPointerTy(), Callee, PICLabel);
Evan Chengc60e76d2007-01-30 20:37:08 +00001033 } else
1034 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
Bill Wendling056292f2008-09-16 21:48:12 +00001035 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Evan Chenga8e29892007-01-19 07:51:42 +00001036 isDirect = true;
Evan Cheng970a4192007-01-19 19:28:01 +00001037 bool isStub = Subtarget->isTargetDarwin() &&
Evan Chenga8e29892007-01-19 07:51:42 +00001038 getTargetMachine().getRelocationModel() != Reloc::Static;
1039 isARMFunc = !Subtarget->isThumb() || isStub;
Evan Chengc60e76d2007-01-30 20:37:08 +00001040 // tBX takes a register source operand.
1041 const char *Sym = S->getSymbol();
David Goodwinf1daf7d2009-07-08 23:10:31 +00001042 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001043 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Owen Anderson1d0be152009-08-13 21:58:54 +00001044 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
Evan Chenge4e4ed32009-08-28 23:18:09 +00001045 Sym, ARMPCLabelIndex, 4);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001046 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001047 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001048 Callee = DAG.getLoad(getPointerTy(), dl,
Evan Cheng9eda6892009-10-31 03:39:36 +00001049 DAG.getEntryNode(), CPAddr,
1050 PseudoSourceValue::getConstantPool(), 0);
Evan Chenge7e0d622009-11-06 22:24:13 +00001051 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001052 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
Dale Johannesen33c960f2009-02-04 20:06:27 +00001053 getPointerTy(), Callee, PICLabel);
Evan Chengc60e76d2007-01-30 20:37:08 +00001054 } else
Bill Wendling056292f2008-09-16 21:48:12 +00001055 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
Evan Chenga8e29892007-01-19 07:51:42 +00001056 }
1057
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +00001058 // FIXME: handle tail calls differently.
1059 unsigned CallOpc;
Evan Chengb6207242009-08-01 00:16:10 +00001060 if (Subtarget->isThumb()) {
1061 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +00001062 CallOpc = ARMISD::CALL_NOLINK;
1063 else
1064 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1065 } else {
1066 CallOpc = (isDirect || Subtarget->hasV5TOps())
Evan Cheng277f0742007-06-19 21:05:09 +00001067 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1068 : ARMISD::CALL_NOLINK;
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +00001069 }
David Goodwinf1daf7d2009-07-08 23:10:31 +00001070 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
Lauro Ramos Venanciob8a93a42007-03-27 16:19:21 +00001071 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
Owen Anderson825b72b2009-08-11 20:47:22 +00001072 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
Lauro Ramos Venancio64c88d72007-03-20 17:57:23 +00001073 InFlag = Chain.getValue(1);
1074 }
1075
Dan Gohman475871a2008-07-27 21:46:04 +00001076 std::vector<SDValue> Ops;
Evan Chenga8e29892007-01-19 07:51:42 +00001077 Ops.push_back(Chain);
1078 Ops.push_back(Callee);
1079
1080 // Add argument registers to the end of the list so that they are known live
1081 // into the call.
1082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1083 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1084 RegsToPass[i].second.getValueType()));
1085
Gabor Greifba36cb52008-08-28 21:40:38 +00001086 if (InFlag.getNode())
Evan Chenga8e29892007-01-19 07:51:42 +00001087 Ops.push_back(InFlag);
Duncan Sands4bdcb612008-07-02 17:40:58 +00001088 // Returns a chain and a flag for retval copy to use.
Owen Anderson825b72b2009-08-11 20:47:22 +00001089 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
Duncan Sands4bdcb612008-07-02 17:40:58 +00001090 &Ops[0], Ops.size());
Evan Chenga8e29892007-01-19 07:51:42 +00001091 InFlag = Chain.getValue(1);
1092
Chris Lattnere563bbc2008-10-11 22:08:30 +00001093 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1094 DAG.getIntPtrConstant(0, true), InFlag);
Dan Gohman98ca4f22009-08-05 01:29:28 +00001095 if (!Ins.empty())
Evan Chenga8e29892007-01-19 07:51:42 +00001096 InFlag = Chain.getValue(1);
1097
Bob Wilson1f595bb2009-04-17 19:07:39 +00001098 // Handle result values, copying them out of physregs into vregs that we
1099 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00001100 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1101 dl, DAG, InVals);
Evan Chenga8e29892007-01-19 07:51:42 +00001102}
1103
Dan Gohman98ca4f22009-08-05 01:29:28 +00001104SDValue
1105ARMTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00001106 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001107 const SmallVectorImpl<ISD::OutputArg> &Outs,
1108 DebugLoc dl, SelectionDAG &DAG) {
Bob Wilson2dc4f542009-03-20 22:42:55 +00001109
Bob Wilsondee46d72009-04-17 20:35:10 +00001110 // CCValAssign - represent the assignment of the return value to a location.
Bob Wilson1f595bb2009-04-17 19:07:39 +00001111 SmallVector<CCValAssign, 16> RVLocs;
Bob Wilson1f595bb2009-04-17 19:07:39 +00001112
Bob Wilsondee46d72009-04-17 20:35:10 +00001113 // CCState - Info about the registers and stack slots.
Dan Gohman98ca4f22009-08-05 01:29:28 +00001114 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1115 *DAG.getContext());
Bob Wilson1f595bb2009-04-17 19:07:39 +00001116
Dan Gohman98ca4f22009-08-05 01:29:28 +00001117 // Analyze outgoing return values.
Anton Korobeynikov567d14f2009-08-05 19:04:42 +00001118 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1119 isVarArg));
Bob Wilson1f595bb2009-04-17 19:07:39 +00001120
1121 // If this is the first return lowered for this function, add
1122 // the regs to the liveout set for the function.
1123 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1124 for (unsigned i = 0; i != RVLocs.size(); ++i)
1125 if (RVLocs[i].isRegLoc())
1126 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Evan Chenga8e29892007-01-19 07:51:42 +00001127 }
1128
Bob Wilson1f595bb2009-04-17 19:07:39 +00001129 SDValue Flag;
1130
1131 // Copy the result values into the output registers.
1132 for (unsigned i = 0, realRVLocIdx = 0;
1133 i != RVLocs.size();
1134 ++i, ++realRVLocIdx) {
1135 CCValAssign &VA = RVLocs[i];
1136 assert(VA.isRegLoc() && "Can only return in registers!");
1137
Dan Gohman98ca4f22009-08-05 01:29:28 +00001138 SDValue Arg = Outs[realRVLocIdx].Val;
Bob Wilson1f595bb2009-04-17 19:07:39 +00001139
1140 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00001141 default: llvm_unreachable("Unknown loc info!");
Bob Wilson1f595bb2009-04-17 19:07:39 +00001142 case CCValAssign::Full: break;
1143 case CCValAssign::BCvt:
1144 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1145 break;
1146 }
1147
Bob Wilson1f595bb2009-04-17 19:07:39 +00001148 if (VA.needsCustom()) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001149 if (VA.getLocVT() == MVT::v2f64) {
Bob Wilson5bafff32009-06-22 23:27:02 +00001150 // Extract the first half and return it in two registers.
Owen Anderson825b72b2009-08-11 20:47:22 +00001151 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1152 DAG.getConstant(0, MVT::i32));
Jim Grosbache5165492009-11-09 00:11:35 +00001153 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson825b72b2009-08-11 20:47:22 +00001154 DAG.getVTList(MVT::i32, MVT::i32), Half);
Bob Wilson5bafff32009-06-22 23:27:02 +00001155
1156 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1157 Flag = Chain.getValue(1);
1158 VA = RVLocs[++i]; // skip ahead to next loc
1159 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1160 HalfGPRs.getValue(1), Flag);
1161 Flag = Chain.getValue(1);
1162 VA = RVLocs[++i]; // skip ahead to next loc
1163
1164 // Extract the 2nd half and fall through to handle it as an f64 value.
Owen Anderson825b72b2009-08-11 20:47:22 +00001165 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1166 DAG.getConstant(1, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +00001167 }
1168 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1169 // available.
Jim Grosbache5165492009-11-09 00:11:35 +00001170 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson825b72b2009-08-11 20:47:22 +00001171 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001172 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
Bob Wilson4d59e1d2009-04-24 17:00:36 +00001173 Flag = Chain.getValue(1);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001174 VA = RVLocs[++i]; // skip ahead to next loc
1175 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1176 Flag);
1177 } else
1178 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1179
Bob Wilsondee46d72009-04-17 20:35:10 +00001180 // Guarantee that all emitted copies are
1181 // stuck together, avoiding something bad.
Bob Wilson1f595bb2009-04-17 19:07:39 +00001182 Flag = Chain.getValue(1);
1183 }
1184
1185 SDValue result;
1186 if (Flag.getNode())
Owen Anderson825b72b2009-08-11 20:47:22 +00001187 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001188 else // Return Void
Owen Anderson825b72b2009-08-11 20:47:22 +00001189 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001190
1191 return result;
Evan Chenga8e29892007-01-19 07:51:42 +00001192}
1193
Bob Wilsonb62d2572009-11-03 00:02:05 +00001194// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1195// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1196// one of the above mentioned nodes. It has to be wrapped because otherwise
1197// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1198// be used to form addressing mode. These wrapped nodes will be selected
1199// into MOVi.
Dan Gohman475871a2008-07-27 21:46:04 +00001200static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
Owen Andersone50ed302009-08-10 22:56:29 +00001201 EVT PtrVT = Op.getValueType();
Dale Johannesenb300d2a2009-02-07 00:55:49 +00001202 // FIXME there is no actual debug info here
1203 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001204 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
Dan Gohman475871a2008-07-27 21:46:04 +00001205 SDValue Res;
Evan Chenga8e29892007-01-19 07:51:42 +00001206 if (CP->isMachineConstantPoolEntry())
1207 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1208 CP->getAlignment());
1209 else
1210 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1211 CP->getAlignment());
Owen Anderson825b72b2009-08-11 20:47:22 +00001212 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
Evan Chenga8e29892007-01-19 07:51:42 +00001213}
1214
Bob Wilsonddb16df2009-10-30 05:45:42 +00001215SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001216 MachineFunction &MF = DAG.getMachineFunction();
1217 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1218 unsigned ARMPCLabelIndex = 0;
Bob Wilsonddb16df2009-10-30 05:45:42 +00001219 DebugLoc DL = Op.getDebugLoc();
Bob Wilson907eebd2009-11-02 20:59:23 +00001220 EVT PtrVT = getPointerTy();
Bob Wilsonddb16df2009-10-30 05:45:42 +00001221 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
Bob Wilson907eebd2009-11-02 20:59:23 +00001222 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1223 SDValue CPAddr;
1224 if (RelocM == Reloc::Static) {
1225 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1226 } else {
1227 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
Evan Chenge7e0d622009-11-06 22:24:13 +00001228 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Bob Wilson907eebd2009-11-02 20:59:23 +00001229 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1230 ARMCP::CPBlockAddress,
1231 PCAdj);
1232 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1233 }
1234 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1235 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1236 PseudoSourceValue::getConstantPool(), 0);
1237 if (RelocM == Reloc::Static)
1238 return Result;
Evan Chenge7e0d622009-11-06 22:24:13 +00001239 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Bob Wilson907eebd2009-11-02 20:59:23 +00001240 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
Bob Wilsonddb16df2009-10-30 05:45:42 +00001241}
1242
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001243// Lower ISD::GlobalTLSAddress using the "general dynamic" model
Dan Gohman475871a2008-07-27 21:46:04 +00001244SDValue
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001245ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1246 SelectionDAG &DAG) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00001247 DebugLoc dl = GA->getDebugLoc();
Owen Andersone50ed302009-08-10 22:56:29 +00001248 EVT PtrVT = getPointerTy();
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001249 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
Evan Chenge7e0d622009-11-06 22:24:13 +00001250 MachineFunction &MF = DAG.getMachineFunction();
1251 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1252 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001253 ARMConstantPoolValue *CPV =
Evan Chenge4e4ed32009-08-28 23:18:09 +00001254 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +00001255 ARMCP::CPValue, PCAdj, "tlsgd", true);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001256 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001257 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
Evan Cheng9eda6892009-10-31 03:39:36 +00001258 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1259 PseudoSourceValue::getConstantPool(), 0);
Dan Gohman475871a2008-07-27 21:46:04 +00001260 SDValue Chain = Argument.getValue(1);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001261
Evan Chenge7e0d622009-11-06 22:24:13 +00001262 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001263 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001264
1265 // call __tls_get_addr.
1266 ArgListTy Args;
1267 ArgListEntry Entry;
1268 Entry.Node = Argument;
Owen Anderson1d0be152009-08-13 21:58:54 +00001269 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001270 Args.push_back(Entry);
Dale Johannesen7d2ad622009-01-30 23:10:59 +00001271 // FIXME: is there useful debug info available here?
Dan Gohman475871a2008-07-27 21:46:04 +00001272 std::pair<SDValue, SDValue> CallResult =
Evan Cheng59bc0602009-08-14 19:11:20 +00001273 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1274 false, false, false, false,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001275 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
Bill Wendling3ea3c242009-12-22 02:10:19 +00001276 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl,
1277 DAG.GetOrdering(Chain.getNode()));
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001278 return CallResult.first;
1279}
1280
1281// Lower ISD::GlobalTLSAddress using the "initial exec" or
1282// "local exec" model.
Dan Gohman475871a2008-07-27 21:46:04 +00001283SDValue
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001284ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
Bob Wilson2dc4f542009-03-20 22:42:55 +00001285 SelectionDAG &DAG) {
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001286 GlobalValue *GV = GA->getGlobal();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001287 DebugLoc dl = GA->getDebugLoc();
Dan Gohman475871a2008-07-27 21:46:04 +00001288 SDValue Offset;
1289 SDValue Chain = DAG.getEntryNode();
Owen Andersone50ed302009-08-10 22:56:29 +00001290 EVT PtrVT = getPointerTy();
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001291 // Get the Thread Pointer
Dale Johannesen33c960f2009-02-04 20:06:27 +00001292 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001293
Chris Lattner4fb63d02009-07-15 04:12:33 +00001294 if (GV->isDeclaration()) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001295 MachineFunction &MF = DAG.getMachineFunction();
1296 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1297 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1298 // Initial exec model.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001299 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1300 ARMConstantPoolValue *CPV =
Evan Chenge4e4ed32009-08-28 23:18:09 +00001301 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +00001302 ARMCP::CPValue, PCAdj, "gottpoff", true);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001303 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001304 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Evan Cheng9eda6892009-10-31 03:39:36 +00001305 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1306 PseudoSourceValue::getConstantPool(), 0);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001307 Chain = Offset.getValue(1);
1308
Evan Chenge7e0d622009-11-06 22:24:13 +00001309 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001310 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001311
Evan Cheng9eda6892009-10-31 03:39:36 +00001312 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1313 PseudoSourceValue::getConstantPool(), 0);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001314 } else {
1315 // local exec model
Evan Chenge4e4ed32009-08-28 23:18:09 +00001316 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
Evan Cheng1606e8e2009-03-13 07:51:59 +00001317 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001318 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
Evan Cheng9eda6892009-10-31 03:39:36 +00001319 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1320 PseudoSourceValue::getConstantPool(), 0);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001321 }
1322
1323 // The address of the thread local variable is the add of the thread
1324 // pointer with the offset of the variable.
Dale Johannesen33c960f2009-02-04 20:06:27 +00001325 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001326}
1327
Dan Gohman475871a2008-07-27 21:46:04 +00001328SDValue
1329ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00001330 // TODO: implement the "local dynamic" model
1331 assert(Subtarget->isTargetELF() &&
1332 "TLS not implemented for non-ELF targets");
1333 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1334 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1335 // otherwise use the "Local Exec" TLS Model
1336 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1337 return LowerToTLSGeneralDynamicModel(GA, DAG);
1338 else
1339 return LowerToTLSExecModels(GA, DAG);
1340}
1341
Dan Gohman475871a2008-07-27 21:46:04 +00001342SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
Bob Wilson2dc4f542009-03-20 22:42:55 +00001343 SelectionDAG &DAG) {
Owen Andersone50ed302009-08-10 22:56:29 +00001344 EVT PtrVT = getPointerTy();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001345 DebugLoc dl = Op.getDebugLoc();
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001346 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1347 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1348 if (RelocM == Reloc::PIC_) {
Rafael Espindolabb46f522009-01-15 20:18:42 +00001349 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001350 ARMConstantPoolValue *CPV =
Evan Chenge4e4ed32009-08-28 23:18:09 +00001351 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
Evan Cheng1606e8e2009-03-13 07:51:59 +00001352 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001353 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001354 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
Anton Korobeynikov249fb332009-10-07 00:06:35 +00001355 CPAddr,
1356 PseudoSourceValue::getConstantPool(), 0);
Dan Gohman475871a2008-07-27 21:46:04 +00001357 SDValue Chain = Result.getValue(1);
Dale Johannesenb300d2a2009-02-07 00:55:49 +00001358 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001359 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001360 if (!UseGOTOFF)
Anton Korobeynikov249fb332009-10-07 00:06:35 +00001361 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1362 PseudoSourceValue::getGOT(), 0);
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001363 return Result;
1364 } else {
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +00001365 // If we have T2 ops, we can materialize the address directly via movt/movw
1366 // pair. This is always cheaper.
1367 if (Subtarget->useMovt()) {
1368 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1369 DAG.getTargetGlobalAddress(GV, PtrVT));
1370 } else {
1371 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1372 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1373 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1374 PseudoSourceValue::getConstantPool(), 0);
1375 }
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001376 }
1377}
1378
Dan Gohman475871a2008-07-27 21:46:04 +00001379SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
Bob Wilson2dc4f542009-03-20 22:42:55 +00001380 SelectionDAG &DAG) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001381 MachineFunction &MF = DAG.getMachineFunction();
1382 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1383 unsigned ARMPCLabelIndex = 0;
Owen Andersone50ed302009-08-10 22:56:29 +00001384 EVT PtrVT = getPointerTy();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001385 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001386 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1387 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
Dan Gohman475871a2008-07-27 21:46:04 +00001388 SDValue CPAddr;
Evan Chenga8e29892007-01-19 07:51:42 +00001389 if (RelocM == Reloc::Static)
Evan Cheng1606e8e2009-03-13 07:51:59 +00001390 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
Evan Chenga8e29892007-01-19 07:51:42 +00001391 else {
Evan Chenge7e0d622009-11-06 22:24:13 +00001392 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Evan Chenge4e4ed32009-08-28 23:18:09 +00001393 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1394 ARMConstantPoolValue *CPV =
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +00001395 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001396 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Evan Chenga8e29892007-01-19 07:51:42 +00001397 }
Owen Anderson825b72b2009-08-11 20:47:22 +00001398 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Evan Chenga8e29892007-01-19 07:51:42 +00001399
Evan Cheng9eda6892009-10-31 03:39:36 +00001400 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1401 PseudoSourceValue::getConstantPool(), 0);
Dan Gohman475871a2008-07-27 21:46:04 +00001402 SDValue Chain = Result.getValue(1);
Evan Chenga8e29892007-01-19 07:51:42 +00001403
1404 if (RelocM == Reloc::PIC_) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001405 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001406 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
Evan Chenga8e29892007-01-19 07:51:42 +00001407 }
Evan Chenge4e4ed32009-08-28 23:18:09 +00001408
Evan Cheng63476a82009-09-03 07:04:02 +00001409 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
Evan Cheng9eda6892009-10-31 03:39:36 +00001410 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1411 PseudoSourceValue::getGOT(), 0);
Evan Chenga8e29892007-01-19 07:51:42 +00001412
1413 return Result;
1414}
1415
Dan Gohman475871a2008-07-27 21:46:04 +00001416SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
Bob Wilson2dc4f542009-03-20 22:42:55 +00001417 SelectionDAG &DAG){
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001418 assert(Subtarget->isTargetELF() &&
1419 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
Evan Chenge7e0d622009-11-06 22:24:13 +00001420 MachineFunction &MF = DAG.getMachineFunction();
1421 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1422 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Owen Andersone50ed302009-08-10 22:56:29 +00001423 EVT PtrVT = getPointerTy();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001424 DebugLoc dl = Op.getDebugLoc();
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001425 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
Owen Anderson1d0be152009-08-13 21:58:54 +00001426 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1427 "_GLOBAL_OFFSET_TABLE_",
Evan Chenge4e4ed32009-08-28 23:18:09 +00001428 ARMPCLabelIndex, PCAdj);
Evan Cheng1606e8e2009-03-13 07:51:59 +00001429 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001430 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Anton Korobeynikov249fb332009-10-07 00:06:35 +00001431 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1432 PseudoSourceValue::getConstantPool(), 0);
Evan Chenge7e0d622009-11-06 22:24:13 +00001433 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001434 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00001435}
1436
Jim Grosbach0e0da732009-05-12 23:59:14 +00001437SDValue
1438ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001439 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Jim Grosbach0e0da732009-05-12 23:59:14 +00001440 DebugLoc dl = Op.getDebugLoc();
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +00001441 switch (IntNo) {
Dan Gohman475871a2008-07-27 21:46:04 +00001442 default: return SDValue(); // Don't custom lower most intrinsics.
Bob Wilson916afdb2009-08-04 00:25:01 +00001443 case Intrinsic::arm_thread_pointer: {
Owen Andersone50ed302009-08-10 22:56:29 +00001444 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Bob Wilson916afdb2009-08-04 00:25:01 +00001445 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1446 }
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001447 case Intrinsic::eh_sjlj_lsda: {
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001448 MachineFunction &MF = DAG.getMachineFunction();
Evan Chenge7e0d622009-11-06 22:24:13 +00001449 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1450 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001451 EVT PtrVT = getPointerTy();
1452 DebugLoc dl = Op.getDebugLoc();
1453 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1454 SDValue CPAddr;
1455 unsigned PCAdj = (RelocM != Reloc::PIC_)
1456 ? 0 : (Subtarget->isThumb() ? 4 : 8);
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001457 ARMConstantPoolValue *CPV =
Jim Grosbach3fb2b1e2009-09-01 01:57:56 +00001458 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1459 ARMCP::CPLSDA, PCAdj);
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001460 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
Owen Anderson825b72b2009-08-11 20:47:22 +00001461 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001462 SDValue Result =
Evan Cheng9eda6892009-10-31 03:39:36 +00001463 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1464 PseudoSourceValue::getConstantPool(), 0);
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001465 SDValue Chain = Result.getValue(1);
1466
1467 if (RelocM == Reloc::PIC_) {
Evan Chenge7e0d622009-11-06 22:24:13 +00001468 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
Jim Grosbach1b747ad2009-08-11 00:09:57 +00001469 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1470 }
1471 return Result;
1472 }
Jim Grosbachf9570122009-05-14 00:46:35 +00001473 case Intrinsic::eh_sjlj_setjmp:
Owen Anderson825b72b2009-08-11 20:47:22 +00001474 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +00001475 }
1476}
1477
Jim Grosbach7c03dbd2009-12-14 21:24:16 +00001478static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1479 const ARMSubtarget *Subtarget) {
Jim Grosbach3728e962009-12-10 00:11:09 +00001480 DebugLoc dl = Op.getDebugLoc();
1481 SDValue Op5 = Op.getOperand(5);
1482 SDValue Res;
1483 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1484 if (isDeviceBarrier) {
Jim Grosbach7c03dbd2009-12-14 21:24:16 +00001485 if (Subtarget->hasV7Ops())
1486 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1487 else
1488 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1489 DAG.getConstant(0, MVT::i32));
Jim Grosbach3728e962009-12-10 00:11:09 +00001490 } else {
Jim Grosbach7c03dbd2009-12-14 21:24:16 +00001491 if (Subtarget->hasV7Ops())
1492 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1493 else
1494 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1495 DAG.getConstant(0, MVT::i32));
Jim Grosbach3728e962009-12-10 00:11:09 +00001496 }
1497 return Res;
1498}
1499
Dan Gohman475871a2008-07-27 21:46:04 +00001500static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
Bob Wilson2dc4f542009-03-20 22:42:55 +00001501 unsigned VarArgsFrameIndex) {
Evan Chenga8e29892007-01-19 07:51:42 +00001502 // vastart just stores the address of the VarArgsFrameIndex slot into the
1503 // memory location argument.
Dale Johannesen33c960f2009-02-04 20:06:27 +00001504 DebugLoc dl = Op.getDebugLoc();
Owen Andersone50ed302009-08-10 22:56:29 +00001505 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
Dan Gohman475871a2008-07-27 21:46:04 +00001506 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
Dan Gohman69de1932008-02-06 22:27:42 +00001507 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Dale Johannesen33c960f2009-02-04 20:06:27 +00001508 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
Evan Chenga8e29892007-01-19 07:51:42 +00001509}
1510
Dan Gohman475871a2008-07-27 21:46:04 +00001511SDValue
Evan Cheng86198642009-08-07 00:34:42 +00001512ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1513 SDNode *Node = Op.getNode();
1514 DebugLoc dl = Node->getDebugLoc();
Owen Andersone50ed302009-08-10 22:56:29 +00001515 EVT VT = Node->getValueType(0);
Evan Cheng86198642009-08-07 00:34:42 +00001516 SDValue Chain = Op.getOperand(0);
1517 SDValue Size = Op.getOperand(1);
1518 SDValue Align = Op.getOperand(2);
1519
1520 // Chain the dynamic stack allocation so that it doesn't modify the stack
1521 // pointer when other instructions are using the stack.
1522 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1523
1524 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1525 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1526 if (AlignVal > StackAlign)
1527 // Do this now since selection pass cannot introduce new target
1528 // independent node.
1529 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1530
1531 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1532 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1533 // do even more horrible hack later.
1534 MachineFunction &MF = DAG.getMachineFunction();
1535 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1536 if (AFI->isThumb1OnlyFunction()) {
1537 bool Negate = true;
1538 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1539 if (C) {
1540 uint32_t Val = C->getZExtValue();
1541 if (Val <= 508 && ((Val & 3) == 0))
1542 Negate = false;
1543 }
1544 if (Negate)
1545 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1546 }
1547
Owen Anderson825b72b2009-08-11 20:47:22 +00001548 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
Evan Cheng86198642009-08-07 00:34:42 +00001549 SDValue Ops1[] = { Chain, Size, Align };
1550 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1551 Chain = Res.getValue(1);
1552 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1553 DAG.getIntPtrConstant(0, true), SDValue());
1554 SDValue Ops2[] = { Res, Chain };
1555 return DAG.getMergeValues(Ops2, 2, dl);
1556}
1557
1558SDValue
Bob Wilson5bafff32009-06-22 23:27:02 +00001559ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1560 SDValue &Root, SelectionDAG &DAG,
1561 DebugLoc dl) {
1562 MachineFunction &MF = DAG.getMachineFunction();
1563 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1564
1565 TargetRegisterClass *RC;
David Goodwinf1daf7d2009-07-08 23:10:31 +00001566 if (AFI->isThumb1OnlyFunction())
Bob Wilson5bafff32009-06-22 23:27:02 +00001567 RC = ARM::tGPRRegisterClass;
1568 else
1569 RC = ARM::GPRRegisterClass;
1570
1571 // Transform the arguments stored in physical registers into virtual ones.
1572 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Owen Anderson825b72b2009-08-11 20:47:22 +00001573 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00001574
1575 SDValue ArgValue2;
1576 if (NextVA.isMemLoc()) {
1577 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1578 MachineFrameInfo *MFI = MF.getFrameInfo();
David Greene3f2bf852009-11-12 20:49:22 +00001579 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset(),
1580 true, false);
Bob Wilson5bafff32009-06-22 23:27:02 +00001581
1582 // Create load node to retrieve arguments from the stack.
1583 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
Evan Cheng9eda6892009-10-31 03:39:36 +00001584 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1585 PseudoSourceValue::getFixedStack(FI), 0);
Bob Wilson5bafff32009-06-22 23:27:02 +00001586 } else {
1587 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
Owen Anderson825b72b2009-08-11 20:47:22 +00001588 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00001589 }
1590
Jim Grosbache5165492009-11-09 00:11:35 +00001591 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
Bob Wilson5bafff32009-06-22 23:27:02 +00001592}
1593
1594SDValue
Dan Gohman98ca4f22009-08-05 01:29:28 +00001595ARMTargetLowering::LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00001596 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001597 const SmallVectorImpl<ISD::InputArg>
1598 &Ins,
1599 DebugLoc dl, SelectionDAG &DAG,
1600 SmallVectorImpl<SDValue> &InVals) {
1601
Bob Wilson1f595bb2009-04-17 19:07:39 +00001602 MachineFunction &MF = DAG.getMachineFunction();
1603 MachineFrameInfo *MFI = MF.getFrameInfo();
1604
Bob Wilson1f595bb2009-04-17 19:07:39 +00001605 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1606
1607 // Assign locations to all of the incoming arguments.
1608 SmallVector<CCValAssign, 16> ArgLocs;
Dan Gohman98ca4f22009-08-05 01:29:28 +00001609 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1610 *DAG.getContext());
1611 CCInfo.AnalyzeFormalArguments(Ins,
Anton Korobeynikov567d14f2009-08-05 19:04:42 +00001612 CCAssignFnForNode(CallConv, /* Return*/ false,
1613 isVarArg));
Bob Wilson1f595bb2009-04-17 19:07:39 +00001614
1615 SmallVector<SDValue, 16> ArgValues;
1616
1617 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1618 CCValAssign &VA = ArgLocs[i];
1619
Bob Wilsondee46d72009-04-17 20:35:10 +00001620 // Arguments stored in registers.
Bob Wilson1f595bb2009-04-17 19:07:39 +00001621 if (VA.isRegLoc()) {
Owen Andersone50ed302009-08-10 22:56:29 +00001622 EVT RegVT = VA.getLocVT();
Bob Wilson1f595bb2009-04-17 19:07:39 +00001623
Bob Wilson5bafff32009-06-22 23:27:02 +00001624 SDValue ArgValue;
Bob Wilson1f595bb2009-04-17 19:07:39 +00001625 if (VA.needsCustom()) {
Bob Wilson5bafff32009-06-22 23:27:02 +00001626 // f64 and vector types are split up into multiple registers or
1627 // combinations of registers and stack slots.
Owen Anderson825b72b2009-08-11 20:47:22 +00001628 RegVT = MVT::i32;
Bob Wilson1f595bb2009-04-17 19:07:39 +00001629
Owen Anderson825b72b2009-08-11 20:47:22 +00001630 if (VA.getLocVT() == MVT::v2f64) {
Bob Wilson5bafff32009-06-22 23:27:02 +00001631 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
Dan Gohman98ca4f22009-08-05 01:29:28 +00001632 Chain, DAG, dl);
Bob Wilson5bafff32009-06-22 23:27:02 +00001633 VA = ArgLocs[++i]; // skip ahead to next loc
1634 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
Dan Gohman98ca4f22009-08-05 01:29:28 +00001635 Chain, DAG, dl);
Owen Anderson825b72b2009-08-11 20:47:22 +00001636 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1637 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
Bob Wilson5bafff32009-06-22 23:27:02 +00001638 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
Owen Anderson825b72b2009-08-11 20:47:22 +00001639 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
Bob Wilson5bafff32009-06-22 23:27:02 +00001640 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1641 } else
Dan Gohman98ca4f22009-08-05 01:29:28 +00001642 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001643
Bob Wilson5bafff32009-06-22 23:27:02 +00001644 } else {
1645 TargetRegisterClass *RC;
Anton Korobeynikov567d14f2009-08-05 19:04:42 +00001646
Owen Anderson825b72b2009-08-11 20:47:22 +00001647 if (RegVT == MVT::f32)
Bob Wilson5bafff32009-06-22 23:27:02 +00001648 RC = ARM::SPRRegisterClass;
Owen Anderson825b72b2009-08-11 20:47:22 +00001649 else if (RegVT == MVT::f64)
Bob Wilson5bafff32009-06-22 23:27:02 +00001650 RC = ARM::DPRRegisterClass;
Owen Anderson825b72b2009-08-11 20:47:22 +00001651 else if (RegVT == MVT::v2f64)
Anton Korobeynikov567d14f2009-08-05 19:04:42 +00001652 RC = ARM::QPRRegisterClass;
Owen Anderson825b72b2009-08-11 20:47:22 +00001653 else if (RegVT == MVT::i32)
Anton Korobeynikov058c2512009-08-05 20:15:19 +00001654 RC = (AFI->isThumb1OnlyFunction() ?
1655 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
Bob Wilson5bafff32009-06-22 23:27:02 +00001656 else
Anton Korobeynikov058c2512009-08-05 20:15:19 +00001657 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
Bob Wilson5bafff32009-06-22 23:27:02 +00001658
1659 // Transform the arguments in physical registers into virtual ones.
1660 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00001661 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001662 }
1663
1664 // If this is an 8 or 16-bit value, it is really passed promoted
1665 // to 32 bits. Insert an assert[sz]ext to capture this, then
1666 // truncate to the right size.
1667 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00001668 default: llvm_unreachable("Unknown loc info!");
Bob Wilson1f595bb2009-04-17 19:07:39 +00001669 case CCValAssign::Full: break;
1670 case CCValAssign::BCvt:
1671 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1672 break;
1673 case CCValAssign::SExt:
1674 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1675 DAG.getValueType(VA.getValVT()));
1676 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1677 break;
1678 case CCValAssign::ZExt:
1679 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1680 DAG.getValueType(VA.getValVT()));
1681 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1682 break;
1683 }
1684
Dan Gohman98ca4f22009-08-05 01:29:28 +00001685 InVals.push_back(ArgValue);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001686
1687 } else { // VA.isRegLoc()
1688
1689 // sanity check
1690 assert(VA.isMemLoc());
Owen Anderson825b72b2009-08-11 20:47:22 +00001691 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
Bob Wilson1f595bb2009-04-17 19:07:39 +00001692
1693 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
David Greene3f2bf852009-11-12 20:49:22 +00001694 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1695 true, false);
Bob Wilson1f595bb2009-04-17 19:07:39 +00001696
Bob Wilsondee46d72009-04-17 20:35:10 +00001697 // Create load nodes to retrieve arguments from the stack.
Bob Wilson1f595bb2009-04-17 19:07:39 +00001698 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
Evan Cheng9eda6892009-10-31 03:39:36 +00001699 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1700 PseudoSourceValue::getFixedStack(FI), 0));
Bob Wilson1f595bb2009-04-17 19:07:39 +00001701 }
1702 }
1703
1704 // varargs
Evan Chenga8e29892007-01-19 07:51:42 +00001705 if (isVarArg) {
1706 static const unsigned GPRArgRegs[] = {
1707 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1708 };
1709
Bob Wilsondee46d72009-04-17 20:35:10 +00001710 unsigned NumGPRs = CCInfo.getFirstUnallocated
1711 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
Bob Wilson1f595bb2009-04-17 19:07:39 +00001712
Lauro Ramos Venancio600c3832007-02-23 20:32:57 +00001713 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1714 unsigned VARegSize = (4 - NumGPRs) * 4;
1715 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
Rafael Espindolac1382b72009-10-30 14:33:14 +00001716 unsigned ArgOffset = CCInfo.getNextStackOffset();
Evan Chenga8e29892007-01-19 07:51:42 +00001717 if (VARegSaveSize) {
1718 // If this function is vararg, store any remaining integer argument regs
1719 // to their spots on the stack so that they may be loaded by deferencing
1720 // the result of va_next.
1721 AFI->setVarArgsRegSaveSize(VARegSaveSize);
Lauro Ramos Venancio600c3832007-02-23 20:32:57 +00001722 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
David Greene3f2bf852009-11-12 20:49:22 +00001723 VARegSaveSize - VARegSize,
1724 true, false);
Dan Gohman475871a2008-07-27 21:46:04 +00001725 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
Evan Chenga8e29892007-01-19 07:51:42 +00001726
Dan Gohman475871a2008-07-27 21:46:04 +00001727 SmallVector<SDValue, 4> MemOps;
Evan Chenga8e29892007-01-19 07:51:42 +00001728 for (; NumGPRs < 4; ++NumGPRs) {
Bob Wilson1f595bb2009-04-17 19:07:39 +00001729 TargetRegisterClass *RC;
David Goodwinf1daf7d2009-07-08 23:10:31 +00001730 if (AFI->isThumb1OnlyFunction())
Bob Wilson1f595bb2009-04-17 19:07:39 +00001731 RC = ARM::tGPRRegisterClass;
Jim Grosbach30eae3c2009-04-07 20:34:09 +00001732 else
Bob Wilson1f595bb2009-04-17 19:07:39 +00001733 RC = ARM::GPRRegisterClass;
1734
Bob Wilson998e1252009-04-20 18:36:57 +00001735 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
Owen Anderson825b72b2009-08-11 20:47:22 +00001736 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
Evan Cheng9eda6892009-10-31 03:39:36 +00001737 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1738 PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0);
Evan Chenga8e29892007-01-19 07:51:42 +00001739 MemOps.push_back(Store);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001740 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
Evan Chenga8e29892007-01-19 07:51:42 +00001741 DAG.getConstant(4, getPointerTy()));
1742 }
1743 if (!MemOps.empty())
Owen Anderson825b72b2009-08-11 20:47:22 +00001744 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Dan Gohman98ca4f22009-08-05 01:29:28 +00001745 &MemOps[0], MemOps.size());
Evan Chenga8e29892007-01-19 07:51:42 +00001746 } else
1747 // This will point to the next argument passed via stack.
David Greene3f2bf852009-11-12 20:49:22 +00001748 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset, true, false);
Evan Chenga8e29892007-01-19 07:51:42 +00001749 }
1750
Dan Gohman98ca4f22009-08-05 01:29:28 +00001751 return Chain;
Evan Chenga8e29892007-01-19 07:51:42 +00001752}
1753
1754/// isFloatingPointZero - Return true if this is +0.0.
Dan Gohman475871a2008-07-27 21:46:04 +00001755static bool isFloatingPointZero(SDValue Op) {
Evan Chenga8e29892007-01-19 07:51:42 +00001756 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
Dale Johanneseneaf08942007-08-31 04:03:46 +00001757 return CFP->getValueAPF().isPosZero();
Gabor Greifba36cb52008-08-28 21:40:38 +00001758 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
Evan Chenga8e29892007-01-19 07:51:42 +00001759 // Maybe this has already been legalized into the constant pool?
1760 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
Dan Gohman475871a2008-07-27 21:46:04 +00001761 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
Evan Chenga8e29892007-01-19 07:51:42 +00001762 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1763 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
Dale Johanneseneaf08942007-08-31 04:03:46 +00001764 return CFP->getValueAPF().isPosZero();
Evan Chenga8e29892007-01-19 07:51:42 +00001765 }
1766 }
1767 return false;
1768}
1769
Evan Chenga8e29892007-01-19 07:51:42 +00001770/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1771/// the given operands.
Evan Cheng06b53c02009-11-12 07:13:11 +00001772SDValue
1773ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1774 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) {
Gabor Greifba36cb52008-08-28 21:40:38 +00001775 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001776 unsigned C = RHSC->getZExtValue();
Evan Cheng06b53c02009-11-12 07:13:11 +00001777 if (!isLegalICmpImmediate(C)) {
Evan Chenga8e29892007-01-19 07:51:42 +00001778 // Constant does not fit, try adjusting it by one?
1779 switch (CC) {
1780 default: break;
1781 case ISD::SETLT:
Evan Chenga8e29892007-01-19 07:51:42 +00001782 case ISD::SETGE:
Evan Cheng06b53c02009-11-12 07:13:11 +00001783 if (isLegalICmpImmediate(C-1)) {
Evan Cheng9a2ef952007-02-02 01:53:26 +00001784 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
Owen Anderson825b72b2009-08-11 20:47:22 +00001785 RHS = DAG.getConstant(C-1, MVT::i32);
Evan Cheng9a2ef952007-02-02 01:53:26 +00001786 }
1787 break;
1788 case ISD::SETULT:
1789 case ISD::SETUGE:
Evan Cheng06b53c02009-11-12 07:13:11 +00001790 if (C > 0 && isLegalICmpImmediate(C-1)) {
Evan Cheng9a2ef952007-02-02 01:53:26 +00001791 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
Owen Anderson825b72b2009-08-11 20:47:22 +00001792 RHS = DAG.getConstant(C-1, MVT::i32);
Evan Chenga8e29892007-01-19 07:51:42 +00001793 }
1794 break;
1795 case ISD::SETLE:
Evan Chenga8e29892007-01-19 07:51:42 +00001796 case ISD::SETGT:
Evan Cheng06b53c02009-11-12 07:13:11 +00001797 if (isLegalICmpImmediate(C+1)) {
Evan Cheng9a2ef952007-02-02 01:53:26 +00001798 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
Owen Anderson825b72b2009-08-11 20:47:22 +00001799 RHS = DAG.getConstant(C+1, MVT::i32);
Evan Cheng9a2ef952007-02-02 01:53:26 +00001800 }
1801 break;
1802 case ISD::SETULE:
1803 case ISD::SETUGT:
Evan Cheng06b53c02009-11-12 07:13:11 +00001804 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
Evan Cheng9a2ef952007-02-02 01:53:26 +00001805 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
Owen Anderson825b72b2009-08-11 20:47:22 +00001806 RHS = DAG.getConstant(C+1, MVT::i32);
Evan Chenga8e29892007-01-19 07:51:42 +00001807 }
1808 break;
1809 }
1810 }
1811 }
1812
1813 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001814 ARMISD::NodeType CompareType;
1815 switch (CondCode) {
1816 default:
1817 CompareType = ARMISD::CMP;
1818 break;
1819 case ARMCC::EQ:
1820 case ARMCC::NE:
David Goodwinc0309b42009-06-29 15:33:01 +00001821 // Uses only Z Flag
1822 CompareType = ARMISD::CMPZ;
Lauro Ramos Venancio99966632007-04-02 01:30:03 +00001823 break;
1824 }
Owen Anderson825b72b2009-08-11 20:47:22 +00001825 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1826 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
Evan Chenga8e29892007-01-19 07:51:42 +00001827}
1828
1829/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
Bob Wilson2dc4f542009-03-20 22:42:55 +00001830static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
Dale Johannesende064702009-02-06 21:50:26 +00001831 DebugLoc dl) {
Dan Gohman475871a2008-07-27 21:46:04 +00001832 SDValue Cmp;
Evan Chenga8e29892007-01-19 07:51:42 +00001833 if (!isFloatingPointZero(RHS))
Owen Anderson825b72b2009-08-11 20:47:22 +00001834 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
Evan Chenga8e29892007-01-19 07:51:42 +00001835 else
Owen Anderson825b72b2009-08-11 20:47:22 +00001836 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1837 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
Evan Chenga8e29892007-01-19 07:51:42 +00001838}
1839
Evan Cheng06b53c02009-11-12 07:13:11 +00001840SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
Owen Andersone50ed302009-08-10 22:56:29 +00001841 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +00001842 SDValue LHS = Op.getOperand(0);
1843 SDValue RHS = Op.getOperand(1);
Evan Chenga8e29892007-01-19 07:51:42 +00001844 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
Dan Gohman475871a2008-07-27 21:46:04 +00001845 SDValue TrueVal = Op.getOperand(2);
1846 SDValue FalseVal = Op.getOperand(3);
Dale Johannesende064702009-02-06 21:50:26 +00001847 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001848
Owen Anderson825b72b2009-08-11 20:47:22 +00001849 if (LHS.getValueType() == MVT::i32) {
Dan Gohman475871a2008-07-27 21:46:04 +00001850 SDValue ARMCC;
Owen Anderson825b72b2009-08-11 20:47:22 +00001851 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Evan Cheng06b53c02009-11-12 07:13:11 +00001852 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
Dale Johannesende064702009-02-06 21:50:26 +00001853 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
Evan Chenga8e29892007-01-19 07:51:42 +00001854 }
1855
1856 ARMCC::CondCodes CondCode, CondCode2;
Bob Wilsoncd3b9a42009-09-09 23:14:54 +00001857 FPCCToARMCC(CC, CondCode, CondCode2);
Evan Chenga8e29892007-01-19 07:51:42 +00001858
Owen Anderson825b72b2009-08-11 20:47:22 +00001859 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1860 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Dale Johannesende064702009-02-06 21:50:26 +00001861 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1862 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
Evan Cheng0e1d3792007-07-05 07:18:20 +00001863 ARMCC, CCR, Cmp);
Evan Chenga8e29892007-01-19 07:51:42 +00001864 if (CondCode2 != ARMCC::AL) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001865 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
Evan Chenga8e29892007-01-19 07:51:42 +00001866 // FIXME: Needs another CMP because flag can have but one use.
Dale Johannesende064702009-02-06 21:50:26 +00001867 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001868 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
Dale Johannesende064702009-02-06 21:50:26 +00001869 Result, TrueVal, ARMCC2, CCR, Cmp2);
Evan Chenga8e29892007-01-19 07:51:42 +00001870 }
1871 return Result;
1872}
1873
Evan Cheng06b53c02009-11-12 07:13:11 +00001874SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00001875 SDValue Chain = Op.getOperand(0);
Evan Chenga8e29892007-01-19 07:51:42 +00001876 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
Dan Gohman475871a2008-07-27 21:46:04 +00001877 SDValue LHS = Op.getOperand(2);
1878 SDValue RHS = Op.getOperand(3);
1879 SDValue Dest = Op.getOperand(4);
Dale Johannesende064702009-02-06 21:50:26 +00001880 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001881
Owen Anderson825b72b2009-08-11 20:47:22 +00001882 if (LHS.getValueType() == MVT::i32) {
Dan Gohman475871a2008-07-27 21:46:04 +00001883 SDValue ARMCC;
Owen Anderson825b72b2009-08-11 20:47:22 +00001884 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Evan Cheng06b53c02009-11-12 07:13:11 +00001885 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
Owen Anderson825b72b2009-08-11 20:47:22 +00001886 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
Dale Johannesende064702009-02-06 21:50:26 +00001887 Chain, Dest, ARMCC, CCR,Cmp);
Evan Chenga8e29892007-01-19 07:51:42 +00001888 }
1889
Owen Anderson825b72b2009-08-11 20:47:22 +00001890 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
Evan Chenga8e29892007-01-19 07:51:42 +00001891 ARMCC::CondCodes CondCode, CondCode2;
Bob Wilsoncd3b9a42009-09-09 23:14:54 +00001892 FPCCToARMCC(CC, CondCode, CondCode2);
Bob Wilson2dc4f542009-03-20 22:42:55 +00001893
Dale Johannesende064702009-02-06 21:50:26 +00001894 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
Owen Anderson825b72b2009-08-11 20:47:22 +00001895 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1896 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1897 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
Dan Gohman475871a2008-07-27 21:46:04 +00001898 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
Dale Johannesende064702009-02-06 21:50:26 +00001899 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
Evan Chenga8e29892007-01-19 07:51:42 +00001900 if (CondCode2 != ARMCC::AL) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001901 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
Dan Gohman475871a2008-07-27 21:46:04 +00001902 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
Dale Johannesende064702009-02-06 21:50:26 +00001903 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
Evan Chenga8e29892007-01-19 07:51:42 +00001904 }
1905 return Res;
1906}
1907
Dan Gohman475871a2008-07-27 21:46:04 +00001908SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Table = Op.getOperand(1);
1911 SDValue Index = Op.getOperand(2);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001912 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001913
Owen Andersone50ed302009-08-10 22:56:29 +00001914 EVT PTy = getPointerTy();
Evan Chenga8e29892007-01-19 07:51:42 +00001915 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1916 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
Bob Wilson3eadf002009-07-14 18:44:34 +00001917 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
Dan Gohman475871a2008-07-27 21:46:04 +00001918 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
Owen Anderson825b72b2009-08-11 20:47:22 +00001919 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
Evan Chenge7c329b2009-07-28 20:53:24 +00001920 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1921 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
Evan Cheng66ac5312009-07-25 00:33:29 +00001922 if (Subtarget->isThumb2()) {
1923 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1924 // which does another jump to the destination. This also makes it easier
1925 // to translate it to TBB / TBH later.
1926 // FIXME: This might not work if the function is extremely large.
Owen Anderson825b72b2009-08-11 20:47:22 +00001927 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
Evan Cheng5657c012009-07-29 02:18:14 +00001928 Addr, Op.getOperand(2), JTI, UId);
Evan Cheng66ac5312009-07-25 00:33:29 +00001929 }
Evan Cheng66ac5312009-07-25 00:33:29 +00001930 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
Evan Cheng9eda6892009-10-31 03:39:36 +00001931 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
1932 PseudoSourceValue::getJumpTable(), 0);
Evan Cheng66ac5312009-07-25 00:33:29 +00001933 Chain = Addr.getValue(1);
Dale Johannesen33c960f2009-02-04 20:06:27 +00001934 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
Owen Anderson825b72b2009-08-11 20:47:22 +00001935 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
Evan Cheng66ac5312009-07-25 00:33:29 +00001936 } else {
Evan Cheng9eda6892009-10-31 03:39:36 +00001937 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
1938 PseudoSourceValue::getJumpTable(), 0);
Evan Cheng66ac5312009-07-25 00:33:29 +00001939 Chain = Addr.getValue(1);
Owen Anderson825b72b2009-08-11 20:47:22 +00001940 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
Evan Cheng66ac5312009-07-25 00:33:29 +00001941 }
Evan Chenga8e29892007-01-19 07:51:42 +00001942}
1943
Dan Gohman475871a2008-07-27 21:46:04 +00001944static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
Dale Johannesende064702009-02-06 21:50:26 +00001945 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001946 unsigned Opc =
1947 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
Owen Anderson825b72b2009-08-11 20:47:22 +00001948 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1949 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
Evan Chenga8e29892007-01-19 07:51:42 +00001950}
1951
Dan Gohman475871a2008-07-27 21:46:04 +00001952static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
Owen Andersone50ed302009-08-10 22:56:29 +00001953 EVT VT = Op.getValueType();
Dale Johannesende064702009-02-06 21:50:26 +00001954 DebugLoc dl = Op.getDebugLoc();
Evan Chenga8e29892007-01-19 07:51:42 +00001955 unsigned Opc =
1956 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1957
Owen Anderson825b72b2009-08-11 20:47:22 +00001958 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
Dale Johannesende064702009-02-06 21:50:26 +00001959 return DAG.getNode(Opc, dl, VT, Op);
Evan Chenga8e29892007-01-19 07:51:42 +00001960}
1961
Dan Gohman475871a2008-07-27 21:46:04 +00001962static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
Evan Chenga8e29892007-01-19 07:51:42 +00001963 // Implement fcopysign with a fabs and a conditional fneg.
Dan Gohman475871a2008-07-27 21:46:04 +00001964 SDValue Tmp0 = Op.getOperand(0);
1965 SDValue Tmp1 = Op.getOperand(1);
Dale Johannesende064702009-02-06 21:50:26 +00001966 DebugLoc dl = Op.getDebugLoc();
Owen Andersone50ed302009-08-10 22:56:29 +00001967 EVT VT = Op.getValueType();
1968 EVT SrcVT = Tmp1.getValueType();
Dale Johannesende064702009-02-06 21:50:26 +00001969 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1970 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
Owen Anderson825b72b2009-08-11 20:47:22 +00001971 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1972 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
Dale Johannesende064702009-02-06 21:50:26 +00001973 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
Evan Chenga8e29892007-01-19 07:51:42 +00001974}
1975
Jim Grosbach0e0da732009-05-12 23:59:14 +00001976SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1977 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1978 MFI->setFrameAddressIsTaken(true);
Owen Andersone50ed302009-08-10 22:56:29 +00001979 EVT VT = Op.getValueType();
Jim Grosbach0e0da732009-05-12 23:59:14 +00001980 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1981 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
Evan Chengcd828612009-06-18 23:14:30 +00001982 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
Jim Grosbach0e0da732009-05-12 23:59:14 +00001983 ? ARM::R7 : ARM::R11;
1984 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1985 while (Depth--)
1986 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1987 return FrameAddr;
1988}
1989
Dan Gohman475871a2008-07-27 21:46:04 +00001990SDValue
Dale Johannesen0f502f62009-02-03 22:26:09 +00001991ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
Dan Gohman475871a2008-07-27 21:46:04 +00001992 SDValue Chain,
1993 SDValue Dst, SDValue Src,
1994 SDValue Size, unsigned Align,
Dan Gohman707e0182008-04-12 04:36:06 +00001995 bool AlwaysInline,
Dan Gohman1f13c682008-04-28 17:15:20 +00001996 const Value *DstSV, uint64_t DstSVOff,
1997 const Value *SrcSV, uint64_t SrcSVOff){
Evan Cheng4102eb52007-10-22 22:11:27 +00001998 // Do repeated 4-byte loads and stores. To be improved.
Dan Gohman707e0182008-04-12 04:36:06 +00001999 // This requires 4-byte alignment.
2000 if ((Align & 3) != 0)
Dan Gohman475871a2008-07-27 21:46:04 +00002001 return SDValue();
Dan Gohman707e0182008-04-12 04:36:06 +00002002 // This requires the copy size to be a constant, preferrably
2003 // within a subtarget-specific limit.
2004 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
2005 if (!ConstantSize)
Dan Gohman475871a2008-07-27 21:46:04 +00002006 return SDValue();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002007 uint64_t SizeVal = ConstantSize->getZExtValue();
Dan Gohman707e0182008-04-12 04:36:06 +00002008 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
Dan Gohman475871a2008-07-27 21:46:04 +00002009 return SDValue();
Dan Gohman707e0182008-04-12 04:36:06 +00002010
2011 unsigned BytesLeft = SizeVal & 3;
2012 unsigned NumMemOps = SizeVal >> 2;
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002013 unsigned EmittedNumMemOps = 0;
Owen Anderson825b72b2009-08-11 20:47:22 +00002014 EVT VT = MVT::i32;
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002015 unsigned VTSize = 4;
Evan Cheng4102eb52007-10-22 22:11:27 +00002016 unsigned i = 0;
Evan Chenge5e7ce42007-05-18 01:19:57 +00002017 const unsigned MAX_LOADS_IN_LDM = 6;
Dan Gohman475871a2008-07-27 21:46:04 +00002018 SDValue TFOps[MAX_LOADS_IN_LDM];
2019 SDValue Loads[MAX_LOADS_IN_LDM];
Dan Gohman1f13c682008-04-28 17:15:20 +00002020 uint64_t SrcOff = 0, DstOff = 0;
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002021
Evan Cheng4102eb52007-10-22 22:11:27 +00002022 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
2023 // same number of stores. The loads and stores will get combined into
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002024 // ldm/stm later on.
Evan Cheng4102eb52007-10-22 22:11:27 +00002025 while (EmittedNumMemOps < NumMemOps) {
2026 for (i = 0;
2027 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Dale Johannesen0f502f62009-02-03 22:26:09 +00002028 Loads[i] = DAG.getLoad(VT, dl, Chain,
Owen Anderson825b72b2009-08-11 20:47:22 +00002029 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2030 DAG.getConstant(SrcOff, MVT::i32)),
Dan Gohman1f13c682008-04-28 17:15:20 +00002031 SrcSV, SrcSVOff + SrcOff);
Evan Cheng4102eb52007-10-22 22:11:27 +00002032 TFOps[i] = Loads[i].getValue(1);
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002033 SrcOff += VTSize;
2034 }
Owen Anderson825b72b2009-08-11 20:47:22 +00002035 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002036
Evan Cheng4102eb52007-10-22 22:11:27 +00002037 for (i = 0;
2038 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
Dale Johannesen0f502f62009-02-03 22:26:09 +00002039 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
Owen Anderson825b72b2009-08-11 20:47:22 +00002040 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2041 DAG.getConstant(DstOff, MVT::i32)),
Dan Gohman1f13c682008-04-28 17:15:20 +00002042 DstSV, DstSVOff + DstOff);
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002043 DstOff += VTSize;
2044 }
Owen Anderson825b72b2009-08-11 20:47:22 +00002045 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
Evan Cheng4102eb52007-10-22 22:11:27 +00002046
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002047 EmittedNumMemOps += i;
2048 }
2049
Bob Wilson2dc4f542009-03-20 22:42:55 +00002050 if (BytesLeft == 0)
Evan Cheng4102eb52007-10-22 22:11:27 +00002051 return Chain;
2052
2053 // Issue loads / stores for the trailing (1 - 3) bytes.
2054 unsigned BytesLeftSave = BytesLeft;
2055 i = 0;
2056 while (BytesLeft) {
2057 if (BytesLeft >= 2) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002058 VT = MVT::i16;
Evan Cheng4102eb52007-10-22 22:11:27 +00002059 VTSize = 2;
2060 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +00002061 VT = MVT::i8;
Evan Cheng4102eb52007-10-22 22:11:27 +00002062 VTSize = 1;
2063 }
2064
Dale Johannesen0f502f62009-02-03 22:26:09 +00002065 Loads[i] = DAG.getLoad(VT, dl, Chain,
Owen Anderson825b72b2009-08-11 20:47:22 +00002066 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2067 DAG.getConstant(SrcOff, MVT::i32)),
Dan Gohman1f13c682008-04-28 17:15:20 +00002068 SrcSV, SrcSVOff + SrcOff);
Evan Cheng4102eb52007-10-22 22:11:27 +00002069 TFOps[i] = Loads[i].getValue(1);
2070 ++i;
2071 SrcOff += VTSize;
2072 BytesLeft -= VTSize;
2073 }
Owen Anderson825b72b2009-08-11 20:47:22 +00002074 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
Evan Cheng4102eb52007-10-22 22:11:27 +00002075
2076 i = 0;
2077 BytesLeft = BytesLeftSave;
2078 while (BytesLeft) {
2079 if (BytesLeft >= 2) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002080 VT = MVT::i16;
Evan Cheng4102eb52007-10-22 22:11:27 +00002081 VTSize = 2;
2082 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +00002083 VT = MVT::i8;
Evan Cheng4102eb52007-10-22 22:11:27 +00002084 VTSize = 1;
2085 }
2086
Dale Johannesen0f502f62009-02-03 22:26:09 +00002087 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
Owen Anderson825b72b2009-08-11 20:47:22 +00002088 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2089 DAG.getConstant(DstOff, MVT::i32)),
Dan Gohman1f13c682008-04-28 17:15:20 +00002090 DstSV, DstSVOff + DstOff);
Evan Cheng4102eb52007-10-22 22:11:27 +00002091 ++i;
2092 DstOff += VTSize;
2093 BytesLeft -= VTSize;
2094 }
Owen Anderson825b72b2009-08-11 20:47:22 +00002095 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
Dale Johannesen8dd86c12007-05-17 21:31:21 +00002096}
2097
Duncan Sands1607f052008-12-01 11:39:25 +00002098static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
Dan Gohman475871a2008-07-27 21:46:04 +00002099 SDValue Op = N->getOperand(0);
Dale Johannesende064702009-02-06 21:50:26 +00002100 DebugLoc dl = N->getDebugLoc();
Owen Anderson825b72b2009-08-11 20:47:22 +00002101 if (N->getValueType(0) == MVT::f64) {
Jim Grosbache5165492009-11-09 00:11:35 +00002102 // Turn i64->f64 into VMOVDRR.
Owen Anderson825b72b2009-08-11 20:47:22 +00002103 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2104 DAG.getConstant(0, MVT::i32));
2105 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2106 DAG.getConstant(1, MVT::i32));
Jim Grosbache5165492009-11-09 00:11:35 +00002107 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
Evan Chengc7c77292008-11-04 19:57:48 +00002108 }
Bob Wilson2dc4f542009-03-20 22:42:55 +00002109
Jim Grosbache5165492009-11-09 00:11:35 +00002110 // Turn f64->i64 into VMOVRRD.
2111 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
Owen Anderson825b72b2009-08-11 20:47:22 +00002112 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
Bob Wilson2dc4f542009-03-20 22:42:55 +00002113
Chris Lattner27a6c732007-11-24 07:07:01 +00002114 // Merge the pieces into a single i64 value.
Owen Anderson825b72b2009-08-11 20:47:22 +00002115 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
Chris Lattner27a6c732007-11-24 07:07:01 +00002116}
2117
Bob Wilson5bafff32009-06-22 23:27:02 +00002118/// getZeroVector - Returns a vector of specified type with all zero elements.
2119///
Owen Andersone50ed302009-08-10 22:56:29 +00002120static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
Bob Wilson5bafff32009-06-22 23:27:02 +00002121 assert(VT.isVector() && "Expected a vector type");
2122
2123 // Zero vectors are used to represent vector negation and in those cases
2124 // will be implemented with the NEON VNEG instruction. However, VNEG does
2125 // not support i64 elements, so sometimes the zero vectors will need to be
2126 // explicitly constructed. For those cases, and potentially other uses in
Anton Korobeynikov2ba62ef2009-09-08 22:51:43 +00002127 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
Bob Wilson5bafff32009-06-22 23:27:02 +00002128 // to their dest type. This ensures they get CSE'd.
2129 SDValue Vec;
Anton Korobeynikov2ba62ef2009-09-08 22:51:43 +00002130 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2131 SmallVector<SDValue, 8> Ops;
2132 MVT TVT;
2133
2134 if (VT.getSizeInBits() == 64) {
2135 Ops.assign(8, Cst); TVT = MVT::v8i8;
2136 } else {
2137 Ops.assign(16, Cst); TVT = MVT::v16i8;
2138 }
2139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
Bob Wilson5bafff32009-06-22 23:27:02 +00002140
2141 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2142}
2143
2144/// getOnesVector - Returns a vector of specified type with all bits set.
2145///
Owen Andersone50ed302009-08-10 22:56:29 +00002146static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
Bob Wilson5bafff32009-06-22 23:27:02 +00002147 assert(VT.isVector() && "Expected a vector type");
2148
Bob Wilson929ffa22009-10-30 20:13:25 +00002149 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
Anton Korobeynikov2ba62ef2009-09-08 22:51:43 +00002150 // dest type. This ensures they get CSE'd.
Bob Wilson5bafff32009-06-22 23:27:02 +00002151 SDValue Vec;
Anton Korobeynikov2ba62ef2009-09-08 22:51:43 +00002152 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2153 SmallVector<SDValue, 8> Ops;
2154 MVT TVT;
2155
2156 if (VT.getSizeInBits() == 64) {
2157 Ops.assign(8, Cst); TVT = MVT::v8i8;
2158 } else {
2159 Ops.assign(16, Cst); TVT = MVT::v16i8;
2160 }
2161 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
Bob Wilson5bafff32009-06-22 23:27:02 +00002162
2163 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2164}
2165
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002166/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2167/// i32 values and take a 2 x i32 value to shift plus a shift amount.
Evan Cheng06b53c02009-11-12 07:13:11 +00002168SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) {
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002169 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2170 EVT VT = Op.getValueType();
2171 unsigned VTBits = VT.getSizeInBits();
2172 DebugLoc dl = Op.getDebugLoc();
2173 SDValue ShOpLo = Op.getOperand(0);
2174 SDValue ShOpHi = Op.getOperand(1);
2175 SDValue ShAmt = Op.getOperand(2);
2176 SDValue ARMCC;
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +00002177 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002178
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +00002179 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2180
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002181 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2182 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2183 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2184 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2185 DAG.getConstant(VTBits, MVT::i32));
2186 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2187 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +00002188 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002189
2190 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2191 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
Evan Cheng06b53c02009-11-12 07:13:11 +00002192 ARMCC, DAG, dl);
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +00002193 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
Jim Grosbachb4a976c2009-10-31 21:00:56 +00002194 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2195 CCR, Cmp);
2196
2197 SDValue Ops[2] = { Lo, Hi };
2198 return DAG.getMergeValues(Ops, 2, dl);
2199}
2200
Jim Grosbachc2b879f2009-10-31 19:38:01 +00002201/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2202/// i32 values and take a 2 x i32 value to shift plus a shift amount.
Evan Cheng06b53c02009-11-12 07:13:11 +00002203SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) {
Jim Grosbachc2b879f2009-10-31 19:38:01 +00002204 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2205 EVT VT = Op.getValueType();
2206 unsigned VTBits = VT.getSizeInBits();
2207 DebugLoc dl = Op.getDebugLoc();
2208 SDValue ShOpLo = Op.getOperand(0);
2209 SDValue ShOpHi = Op.getOperand(1);
2210 SDValue ShAmt = Op.getOperand(2);
2211 SDValue ARMCC;
2212
2213 assert(Op.getOpcode() == ISD::SHL_PARTS);
2214 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2215 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2216 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2217 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2218 DAG.getConstant(VTBits, MVT::i32));
2219 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2220 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2221
2222 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2223 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2224 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
Evan Cheng06b53c02009-11-12 07:13:11 +00002225 ARMCC, DAG, dl);
Jim Grosbachc2b879f2009-10-31 19:38:01 +00002226 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2227 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2228 CCR, Cmp);
2229
2230 SDValue Ops[2] = { Lo, Hi };
2231 return DAG.getMergeValues(Ops, 2, dl);
2232}
2233
Bob Wilson5bafff32009-06-22 23:27:02 +00002234static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2235 const ARMSubtarget *ST) {
Owen Andersone50ed302009-08-10 22:56:29 +00002236 EVT VT = N->getValueType(0);
Bob Wilson5bafff32009-06-22 23:27:02 +00002237 DebugLoc dl = N->getDebugLoc();
2238
2239 // Lower vector shifts on NEON to use VSHL.
2240 if (VT.isVector()) {
2241 assert(ST->hasNEON() && "unexpected vector shift");
2242
2243 // Left shifts translate directly to the vshiftu intrinsic.
2244 if (N->getOpcode() == ISD::SHL)
2245 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Owen Anderson825b72b2009-08-11 20:47:22 +00002246 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
Bob Wilson5bafff32009-06-22 23:27:02 +00002247 N->getOperand(0), N->getOperand(1));
2248
2249 assert((N->getOpcode() == ISD::SRA ||
2250 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2251
2252 // NEON uses the same intrinsics for both left and right shifts. For
2253 // right shifts, the shift amounts are negative, so negate the vector of
2254 // shift amounts.
Owen Andersone50ed302009-08-10 22:56:29 +00002255 EVT ShiftVT = N->getOperand(1).getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00002256 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2257 getZeroVector(ShiftVT, DAG, dl),
2258 N->getOperand(1));
2259 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2260 Intrinsic::arm_neon_vshifts :
2261 Intrinsic::arm_neon_vshiftu);
2262 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
Owen Anderson825b72b2009-08-11 20:47:22 +00002263 DAG.getConstant(vshiftInt, MVT::i32),
Bob Wilson5bafff32009-06-22 23:27:02 +00002264 N->getOperand(0), NegatedCount);
2265 }
2266
Eli Friedmance392eb2009-08-22 03:13:10 +00002267 // We can get here for a node like i32 = ISD::SHL i32, i64
2268 if (VT != MVT::i64)
2269 return SDValue();
2270
2271 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
Chris Lattner27a6c732007-11-24 07:07:01 +00002272 "Unknown shift to lower!");
Duncan Sands1607f052008-12-01 11:39:25 +00002273
Chris Lattner27a6c732007-11-24 07:07:01 +00002274 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2275 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00002276 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
Duncan Sands1607f052008-12-01 11:39:25 +00002277 return SDValue();
Bob Wilson2dc4f542009-03-20 22:42:55 +00002278
Chris Lattner27a6c732007-11-24 07:07:01 +00002279 // If we are in thumb mode, we don't have RRX.
David Goodwinf1daf7d2009-07-08 23:10:31 +00002280 if (ST->isThumb1Only()) return SDValue();
Bob Wilson2dc4f542009-03-20 22:42:55 +00002281
Chris Lattner27a6c732007-11-24 07:07:01 +00002282 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
Owen Anderson825b72b2009-08-11 20:47:22 +00002283 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2284 DAG.getConstant(0, MVT::i32));
2285 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2286 DAG.getConstant(1, MVT::i32));
Bob Wilson2dc4f542009-03-20 22:42:55 +00002287
Chris Lattner27a6c732007-11-24 07:07:01 +00002288 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2289 // captures the result into a carry flag.
2290 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
Owen Anderson825b72b2009-08-11 20:47:22 +00002291 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
Bob Wilson2dc4f542009-03-20 22:42:55 +00002292
Chris Lattner27a6c732007-11-24 07:07:01 +00002293 // The low part is an ARMISD::RRX operand, which shifts the carry in.
Owen Anderson825b72b2009-08-11 20:47:22 +00002294 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
Bob Wilson2dc4f542009-03-20 22:42:55 +00002295
Chris Lattner27a6c732007-11-24 07:07:01 +00002296 // Merge the pieces into a single i64 value.
Owen Anderson825b72b2009-08-11 20:47:22 +00002297 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
Chris Lattner27a6c732007-11-24 07:07:01 +00002298}
2299
Bob Wilson5bafff32009-06-22 23:27:02 +00002300static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2301 SDValue TmpOp0, TmpOp1;
2302 bool Invert = false;
2303 bool Swap = false;
2304 unsigned Opc = 0;
2305
2306 SDValue Op0 = Op.getOperand(0);
2307 SDValue Op1 = Op.getOperand(1);
2308 SDValue CC = Op.getOperand(2);
Owen Andersone50ed302009-08-10 22:56:29 +00002309 EVT VT = Op.getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00002310 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2311 DebugLoc dl = Op.getDebugLoc();
2312
2313 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2314 switch (SetCCOpcode) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002315 default: llvm_unreachable("Illegal FP comparison"); break;
Bob Wilson5bafff32009-06-22 23:27:02 +00002316 case ISD::SETUNE:
2317 case ISD::SETNE: Invert = true; // Fallthrough
2318 case ISD::SETOEQ:
2319 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2320 case ISD::SETOLT:
2321 case ISD::SETLT: Swap = true; // Fallthrough
2322 case ISD::SETOGT:
2323 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2324 case ISD::SETOLE:
2325 case ISD::SETLE: Swap = true; // Fallthrough
2326 case ISD::SETOGE:
2327 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2328 case ISD::SETUGE: Swap = true; // Fallthrough
2329 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2330 case ISD::SETUGT: Swap = true; // Fallthrough
2331 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2332 case ISD::SETUEQ: Invert = true; // Fallthrough
2333 case ISD::SETONE:
2334 // Expand this to (OLT | OGT).
2335 TmpOp0 = Op0;
2336 TmpOp1 = Op1;
2337 Opc = ISD::OR;
2338 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2339 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2340 break;
2341 case ISD::SETUO: Invert = true; // Fallthrough
2342 case ISD::SETO:
2343 // Expand this to (OLT | OGE).
2344 TmpOp0 = Op0;
2345 TmpOp1 = Op1;
2346 Opc = ISD::OR;
2347 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2348 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2349 break;
2350 }
2351 } else {
2352 // Integer comparisons.
2353 switch (SetCCOpcode) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002354 default: llvm_unreachable("Illegal integer comparison"); break;
Bob Wilson5bafff32009-06-22 23:27:02 +00002355 case ISD::SETNE: Invert = true;
2356 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2357 case ISD::SETLT: Swap = true;
2358 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2359 case ISD::SETLE: Swap = true;
2360 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2361 case ISD::SETULT: Swap = true;
2362 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2363 case ISD::SETULE: Swap = true;
2364 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2365 }
2366
Nick Lewycky7f6aa2b2009-07-08 03:04:38 +00002367 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
Bob Wilson5bafff32009-06-22 23:27:02 +00002368 if (Opc == ARMISD::VCEQ) {
2369
2370 SDValue AndOp;
2371 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2372 AndOp = Op0;
2373 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2374 AndOp = Op1;
2375
2376 // Ignore bitconvert.
2377 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2378 AndOp = AndOp.getOperand(0);
2379
2380 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2381 Opc = ARMISD::VTST;
2382 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2383 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2384 Invert = !Invert;
2385 }
2386 }
2387 }
2388
2389 if (Swap)
2390 std::swap(Op0, Op1);
2391
2392 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2393
2394 if (Invert)
2395 Result = DAG.getNOT(dl, Result, VT);
2396
2397 return Result;
2398}
2399
2400/// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2401/// VMOV instruction, and if so, return the constant being splatted.
2402static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2403 unsigned SplatBitSize, SelectionDAG &DAG) {
2404 switch (SplatBitSize) {
2405 case 8:
2406 // Any 1-byte value is OK.
2407 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
Owen Anderson825b72b2009-08-11 20:47:22 +00002408 return DAG.getTargetConstant(SplatBits, MVT::i8);
Bob Wilson5bafff32009-06-22 23:27:02 +00002409
2410 case 16:
2411 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2412 if ((SplatBits & ~0xff) == 0 ||
2413 (SplatBits & ~0xff00) == 0)
Owen Anderson825b72b2009-08-11 20:47:22 +00002414 return DAG.getTargetConstant(SplatBits, MVT::i16);
Bob Wilson5bafff32009-06-22 23:27:02 +00002415 break;
2416
2417 case 32:
2418 // NEON's 32-bit VMOV supports splat values where:
2419 // * only one byte is nonzero, or
2420 // * the least significant byte is 0xff and the second byte is nonzero, or
2421 // * the least significant 2 bytes are 0xff and the third is nonzero.
2422 if ((SplatBits & ~0xff) == 0 ||
2423 (SplatBits & ~0xff00) == 0 ||
2424 (SplatBits & ~0xff0000) == 0 ||
2425 (SplatBits & ~0xff000000) == 0)
Owen Anderson825b72b2009-08-11 20:47:22 +00002426 return DAG.getTargetConstant(SplatBits, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002427
2428 if ((SplatBits & ~0xffff) == 0 &&
2429 ((SplatBits | SplatUndef) & 0xff) == 0xff)
Owen Anderson825b72b2009-08-11 20:47:22 +00002430 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002431
2432 if ((SplatBits & ~0xffffff) == 0 &&
2433 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
Owen Anderson825b72b2009-08-11 20:47:22 +00002434 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002435
2436 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2437 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2438 // VMOV.I32. A (very) minor optimization would be to replicate the value
2439 // and fall through here to test for a valid 64-bit splat. But, then the
2440 // caller would also need to check and handle the change in size.
2441 break;
2442
2443 case 64: {
2444 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2445 uint64_t BitMask = 0xff;
2446 uint64_t Val = 0;
2447 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2448 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2449 Val |= BitMask;
2450 else if ((SplatBits & BitMask) != 0)
2451 return SDValue();
2452 BitMask <<= 8;
2453 }
Owen Anderson825b72b2009-08-11 20:47:22 +00002454 return DAG.getTargetConstant(Val, MVT::i64);
Bob Wilson5bafff32009-06-22 23:27:02 +00002455 }
2456
2457 default:
Torok Edwinc23197a2009-07-14 16:55:14 +00002458 llvm_unreachable("unexpected size for isVMOVSplat");
Bob Wilson5bafff32009-06-22 23:27:02 +00002459 break;
2460 }
2461
2462 return SDValue();
2463}
2464
2465/// getVMOVImm - If this is a build_vector of constants which can be
2466/// formed by using a VMOV instruction of the specified element size,
2467/// return the constant being splatted. The ByteSize field indicates the
2468/// number of bytes of each element [1248].
2469SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2470 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2471 APInt SplatBits, SplatUndef;
2472 unsigned SplatBitSize;
2473 bool HasAnyUndefs;
2474 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2475 HasAnyUndefs, ByteSize * 8))
2476 return SDValue();
2477
2478 if (SplatBitSize > ByteSize * 8)
2479 return SDValue();
2480
2481 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2482 SplatBitSize, DAG);
2483}
2484
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002485static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2486 bool &ReverseVEXT, unsigned &Imm) {
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002487 unsigned NumElts = VT.getVectorNumElements();
2488 ReverseVEXT = false;
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002489 Imm = M[0];
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002490
2491 // If this is a VEXT shuffle, the immediate value is the index of the first
2492 // element. The other shuffle indices must be the successive elements after
2493 // the first one.
2494 unsigned ExpectedElt = Imm;
2495 for (unsigned i = 1; i < NumElts; ++i) {
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002496 // Increment the expected index. If it wraps around, it may still be
2497 // a VEXT but the source vectors must be swapped.
2498 ExpectedElt += 1;
2499 if (ExpectedElt == NumElts * 2) {
2500 ExpectedElt = 0;
2501 ReverseVEXT = true;
2502 }
2503
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002504 if (ExpectedElt != static_cast<unsigned>(M[i]))
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002505 return false;
2506 }
2507
2508 // Adjust the index value if the source operands will be swapped.
2509 if (ReverseVEXT)
2510 Imm -= NumElts;
2511
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002512 return true;
2513}
2514
Bob Wilson8bb9e482009-07-26 00:39:34 +00002515/// isVREVMask - Check if a vector shuffle corresponds to a VREV
2516/// instruction with the specified blocksize. (The order of the elements
2517/// within each block of the vector is reversed.)
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002518static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2519 unsigned BlockSize) {
Bob Wilson8bb9e482009-07-26 00:39:34 +00002520 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2521 "Only possible block sizes for VREV are: 16, 32, 64");
2522
Bob Wilson8bb9e482009-07-26 00:39:34 +00002523 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
Bob Wilson20d10812009-10-21 21:36:27 +00002524 if (EltSz == 64)
2525 return false;
2526
2527 unsigned NumElts = VT.getVectorNumElements();
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002528 unsigned BlockElts = M[0] + 1;
Bob Wilson8bb9e482009-07-26 00:39:34 +00002529
2530 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2531 return false;
2532
2533 for (unsigned i = 0; i < NumElts; ++i) {
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002534 if ((unsigned) M[i] !=
Bob Wilson8bb9e482009-07-26 00:39:34 +00002535 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2536 return false;
2537 }
2538
2539 return true;
2540}
2541
Bob Wilsonc692cb72009-08-21 20:54:19 +00002542static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2543 unsigned &WhichResult) {
Bob Wilson20d10812009-10-21 21:36:27 +00002544 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2545 if (EltSz == 64)
2546 return false;
2547
Bob Wilsonc692cb72009-08-21 20:54:19 +00002548 unsigned NumElts = VT.getVectorNumElements();
2549 WhichResult = (M[0] == 0 ? 0 : 1);
2550 for (unsigned i = 0; i < NumElts; i += 2) {
2551 if ((unsigned) M[i] != i + WhichResult ||
2552 (unsigned) M[i+1] != i + NumElts + WhichResult)
2553 return false;
2554 }
2555 return true;
2556}
2557
Bob Wilson324f4f12009-12-03 06:40:55 +00002558/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2559/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2560/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2561static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2562 unsigned &WhichResult) {
2563 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2564 if (EltSz == 64)
2565 return false;
2566
2567 unsigned NumElts = VT.getVectorNumElements();
2568 WhichResult = (M[0] == 0 ? 0 : 1);
2569 for (unsigned i = 0; i < NumElts; i += 2) {
2570 if ((unsigned) M[i] != i + WhichResult ||
2571 (unsigned) M[i+1] != i + WhichResult)
2572 return false;
2573 }
2574 return true;
2575}
2576
Bob Wilsonc692cb72009-08-21 20:54:19 +00002577static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2578 unsigned &WhichResult) {
Bob Wilson20d10812009-10-21 21:36:27 +00002579 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2580 if (EltSz == 64)
2581 return false;
2582
Bob Wilsonc692cb72009-08-21 20:54:19 +00002583 unsigned NumElts = VT.getVectorNumElements();
2584 WhichResult = (M[0] == 0 ? 0 : 1);
2585 for (unsigned i = 0; i != NumElts; ++i) {
2586 if ((unsigned) M[i] != 2 * i + WhichResult)
2587 return false;
2588 }
2589
2590 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
Bob Wilson20d10812009-10-21 21:36:27 +00002591 if (VT.is64BitVector() && EltSz == 32)
Bob Wilsonc692cb72009-08-21 20:54:19 +00002592 return false;
2593
2594 return true;
2595}
2596
Bob Wilson324f4f12009-12-03 06:40:55 +00002597/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
2598/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2599/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
2600static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2601 unsigned &WhichResult) {
2602 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2603 if (EltSz == 64)
2604 return false;
2605
2606 unsigned Half = VT.getVectorNumElements() / 2;
2607 WhichResult = (M[0] == 0 ? 0 : 1);
2608 for (unsigned j = 0; j != 2; ++j) {
2609 unsigned Idx = WhichResult;
2610 for (unsigned i = 0; i != Half; ++i) {
2611 if ((unsigned) M[i + j * Half] != Idx)
2612 return false;
2613 Idx += 2;
2614 }
2615 }
2616
2617 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2618 if (VT.is64BitVector() && EltSz == 32)
2619 return false;
2620
2621 return true;
2622}
2623
Bob Wilsonc692cb72009-08-21 20:54:19 +00002624static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2625 unsigned &WhichResult) {
Bob Wilson20d10812009-10-21 21:36:27 +00002626 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2627 if (EltSz == 64)
2628 return false;
2629
Bob Wilsonc692cb72009-08-21 20:54:19 +00002630 unsigned NumElts = VT.getVectorNumElements();
2631 WhichResult = (M[0] == 0 ? 0 : 1);
2632 unsigned Idx = WhichResult * NumElts / 2;
2633 for (unsigned i = 0; i != NumElts; i += 2) {
2634 if ((unsigned) M[i] != Idx ||
2635 (unsigned) M[i+1] != Idx + NumElts)
2636 return false;
2637 Idx += 1;
2638 }
2639
2640 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
Bob Wilson20d10812009-10-21 21:36:27 +00002641 if (VT.is64BitVector() && EltSz == 32)
Bob Wilsonc692cb72009-08-21 20:54:19 +00002642 return false;
2643
2644 return true;
2645}
2646
Bob Wilson324f4f12009-12-03 06:40:55 +00002647/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
2648/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2649/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
2650static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2651 unsigned &WhichResult) {
2652 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2653 if (EltSz == 64)
2654 return false;
2655
2656 unsigned NumElts = VT.getVectorNumElements();
2657 WhichResult = (M[0] == 0 ? 0 : 1);
2658 unsigned Idx = WhichResult * NumElts / 2;
2659 for (unsigned i = 0; i != NumElts; i += 2) {
2660 if ((unsigned) M[i] != Idx ||
2661 (unsigned) M[i+1] != Idx)
2662 return false;
2663 Idx += 1;
2664 }
2665
2666 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2667 if (VT.is64BitVector() && EltSz == 32)
2668 return false;
2669
2670 return true;
2671}
2672
2673
Owen Andersone50ed302009-08-10 22:56:29 +00002674static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
Bob Wilson5bafff32009-06-22 23:27:02 +00002675 // Canonicalize all-zeros and all-ones vectors.
Bob Wilsond06791f2009-08-13 01:57:47 +00002676 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
Bob Wilson5bafff32009-06-22 23:27:02 +00002677 if (ConstVal->isNullValue())
2678 return getZeroVector(VT, DAG, dl);
2679 if (ConstVal->isAllOnesValue())
2680 return getOnesVector(VT, DAG, dl);
2681
Owen Andersone50ed302009-08-10 22:56:29 +00002682 EVT CanonicalVT;
Bob Wilson5bafff32009-06-22 23:27:02 +00002683 if (VT.is64BitVector()) {
2684 switch (Val.getValueType().getSizeInBits()) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002685 case 8: CanonicalVT = MVT::v8i8; break;
2686 case 16: CanonicalVT = MVT::v4i16; break;
2687 case 32: CanonicalVT = MVT::v2i32; break;
2688 case 64: CanonicalVT = MVT::v1i64; break;
Torok Edwinc23197a2009-07-14 16:55:14 +00002689 default: llvm_unreachable("unexpected splat element type"); break;
Bob Wilson5bafff32009-06-22 23:27:02 +00002690 }
2691 } else {
2692 assert(VT.is128BitVector() && "unknown splat vector size");
2693 switch (Val.getValueType().getSizeInBits()) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002694 case 8: CanonicalVT = MVT::v16i8; break;
2695 case 16: CanonicalVT = MVT::v8i16; break;
2696 case 32: CanonicalVT = MVT::v4i32; break;
2697 case 64: CanonicalVT = MVT::v2i64; break;
Torok Edwinc23197a2009-07-14 16:55:14 +00002698 default: llvm_unreachable("unexpected splat element type"); break;
Bob Wilson5bafff32009-06-22 23:27:02 +00002699 }
2700 }
2701
2702 // Build a canonical splat for this value.
2703 SmallVector<SDValue, 8> Ops;
2704 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2705 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2706 Ops.size());
2707 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2708}
2709
2710// If this is a case we can't handle, return null and let the default
2711// expansion code take care of it.
2712static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
Bob Wilsond06791f2009-08-13 01:57:47 +00002713 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
Bob Wilson5bafff32009-06-22 23:27:02 +00002714 DebugLoc dl = Op.getDebugLoc();
Owen Andersone50ed302009-08-10 22:56:29 +00002715 EVT VT = Op.getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00002716
2717 APInt SplatBits, SplatUndef;
2718 unsigned SplatBitSize;
2719 bool HasAnyUndefs;
2720 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
Anton Korobeynikov71624cc2009-08-29 00:08:18 +00002721 if (SplatBitSize <= 64) {
2722 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2723 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2724 if (Val.getNode())
2725 return BuildSplat(Val, VT, DAG, dl);
2726 }
Bob Wilsoncf661e22009-07-30 00:31:25 +00002727 }
2728
2729 // If there are only 2 elements in a 128-bit vector, insert them into an
2730 // undef vector. This handles the common case for 128-bit vector argument
2731 // passing, where the insertions should be translated to subreg accesses
2732 // with no real instructions.
2733 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2734 SDValue Val = DAG.getUNDEF(VT);
2735 SDValue Op0 = Op.getOperand(0);
2736 SDValue Op1 = Op.getOperand(1);
2737 if (Op0.getOpcode() != ISD::UNDEF)
2738 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2739 DAG.getIntPtrConstant(0));
2740 if (Op1.getOpcode() != ISD::UNDEF)
2741 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2742 DAG.getIntPtrConstant(1));
2743 return Val;
Bob Wilson5bafff32009-06-22 23:27:02 +00002744 }
2745
2746 return SDValue();
2747}
2748
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002749/// isShuffleMaskLegal - Targets can use this to indicate that they only
2750/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2751/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2752/// are assumed to be legal.
2753bool
2754ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2755 EVT VT) const {
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002756 if (VT.getVectorNumElements() == 4 &&
2757 (VT.is128BitVector() || VT.is64BitVector())) {
2758 unsigned PFIndexes[4];
2759 for (unsigned i = 0; i != 4; ++i) {
2760 if (M[i] < 0)
2761 PFIndexes[i] = 8;
2762 else
2763 PFIndexes[i] = M[i];
2764 }
2765
2766 // Compute the index in the perfect shuffle table.
2767 unsigned PFTableIndex =
2768 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2769 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2770 unsigned Cost = (PFEntry >> 30);
2771
2772 if (Cost <= 4)
2773 return true;
2774 }
2775
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002776 bool ReverseVEXT;
Bob Wilsonc692cb72009-08-21 20:54:19 +00002777 unsigned Imm, WhichResult;
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002778
2779 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2780 isVREVMask(M, VT, 64) ||
2781 isVREVMask(M, VT, 32) ||
2782 isVREVMask(M, VT, 16) ||
Bob Wilsonc692cb72009-08-21 20:54:19 +00002783 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2784 isVTRNMask(M, VT, WhichResult) ||
2785 isVUZPMask(M, VT, WhichResult) ||
Bob Wilson324f4f12009-12-03 06:40:55 +00002786 isVZIPMask(M, VT, WhichResult) ||
2787 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
2788 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
2789 isVZIP_v_undef_Mask(M, VT, WhichResult));
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002790}
2791
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002792/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2793/// the specified operations to build the shuffle.
2794static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2795 SDValue RHS, SelectionDAG &DAG,
2796 DebugLoc dl) {
2797 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2798 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2799 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2800
2801 enum {
2802 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2803 OP_VREV,
2804 OP_VDUP0,
2805 OP_VDUP1,
2806 OP_VDUP2,
2807 OP_VDUP3,
2808 OP_VEXT1,
2809 OP_VEXT2,
2810 OP_VEXT3,
2811 OP_VUZPL, // VUZP, left result
2812 OP_VUZPR, // VUZP, right result
2813 OP_VZIPL, // VZIP, left result
2814 OP_VZIPR, // VZIP, right result
2815 OP_VTRNL, // VTRN, left result
2816 OP_VTRNR // VTRN, right result
2817 };
2818
2819 if (OpNum == OP_COPY) {
2820 if (LHSID == (1*9+2)*9+3) return LHS;
2821 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2822 return RHS;
2823 }
2824
2825 SDValue OpLHS, OpRHS;
2826 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2827 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2828 EVT VT = OpLHS.getValueType();
2829
2830 switch (OpNum) {
2831 default: llvm_unreachable("Unknown shuffle opcode!");
2832 case OP_VREV:
2833 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2834 case OP_VDUP0:
2835 case OP_VDUP1:
2836 case OP_VDUP2:
2837 case OP_VDUP3:
2838 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
Anton Korobeynikov051cfd62009-08-21 12:41:42 +00002839 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002840 case OP_VEXT1:
2841 case OP_VEXT2:
2842 case OP_VEXT3:
2843 return DAG.getNode(ARMISD::VEXT, dl, VT,
2844 OpLHS, OpRHS,
2845 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2846 case OP_VUZPL:
2847 case OP_VUZPR:
Anton Korobeynikov051cfd62009-08-21 12:41:42 +00002848 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002849 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2850 case OP_VZIPL:
2851 case OP_VZIPR:
Anton Korobeynikov051cfd62009-08-21 12:41:42 +00002852 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002853 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2854 case OP_VTRNL:
2855 case OP_VTRNR:
Anton Korobeynikov051cfd62009-08-21 12:41:42 +00002856 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2857 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002858 }
2859}
2860
Bob Wilson5bafff32009-06-22 23:27:02 +00002861static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002862 SDValue V1 = Op.getOperand(0);
2863 SDValue V2 = Op.getOperand(1);
Bob Wilsond8e17572009-08-12 22:31:50 +00002864 DebugLoc dl = Op.getDebugLoc();
2865 EVT VT = Op.getValueType();
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002866 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002867 SmallVector<int, 8> ShuffleMask;
Bob Wilsond8e17572009-08-12 22:31:50 +00002868
Bob Wilson28865062009-08-13 02:13:04 +00002869 // Convert shuffles that are directly supported on NEON to target-specific
2870 // DAG nodes, instead of keeping them as shuffles and matching them again
2871 // during code selection. This is more efficient and avoids the possibility
2872 // of inconsistencies between legalization and selection.
Bob Wilsonbfcbb502009-08-13 06:01:30 +00002873 // FIXME: floating-point vectors should be canonicalized to integer vectors
2874 // of the same time so that they get CSEd properly.
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002875 SVN->getMask(ShuffleMask);
2876
2877 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
Bob Wilson0ce37102009-08-14 05:08:32 +00002878 int Lane = SVN->getSplatIndex();
Anton Korobeynikov2ae0eec2009-11-02 00:12:06 +00002879 // If this is undef splat, generate it via "just" vdup, if possible.
2880 if (Lane == -1) Lane = 0;
2881
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002882 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2883 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
Bob Wilsonc1d287b2009-08-14 05:13:08 +00002884 }
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002885 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002886 DAG.getConstant(Lane, MVT::i32));
Bob Wilson0ce37102009-08-14 05:08:32 +00002887 }
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002888
2889 bool ReverseVEXT;
2890 unsigned Imm;
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002891 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002892 if (ReverseVEXT)
Bob Wilsonc692cb72009-08-21 20:54:19 +00002893 std::swap(V1, V2);
2894 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
Bob Wilsonde95c1b82009-08-19 17:03:43 +00002895 DAG.getConstant(Imm, MVT::i32));
2896 }
2897
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002898 if (isVREVMask(ShuffleMask, VT, 64))
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002899 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002900 if (isVREVMask(ShuffleMask, VT, 32))
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002901 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +00002902 if (isVREVMask(ShuffleMask, VT, 16))
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002903 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2904
Bob Wilsonc692cb72009-08-21 20:54:19 +00002905 // Check for Neon shuffles that modify both input vectors in place.
2906 // If both results are used, i.e., if there are two shuffles with the same
2907 // source operands and with masks corresponding to both results of one of
2908 // these operations, DAG memoization will ensure that a single node is
2909 // used for both shuffles.
2910 unsigned WhichResult;
2911 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2912 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2913 V1, V2).getValue(WhichResult);
2914 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2915 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2916 V1, V2).getValue(WhichResult);
2917 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2918 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2919 V1, V2).getValue(WhichResult);
2920
Bob Wilson324f4f12009-12-03 06:40:55 +00002921 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
2922 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2923 V1, V1).getValue(WhichResult);
2924 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2925 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2926 V1, V1).getValue(WhichResult);
2927 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2928 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2929 V1, V1).getValue(WhichResult);
2930
Bob Wilsonc692cb72009-08-21 20:54:19 +00002931 // If the shuffle is not directly supported and it has 4 elements, use
2932 // the PerfectShuffle-generated table to synthesize it from other shuffles.
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +00002933 if (VT.getVectorNumElements() == 4 &&
2934 (VT.is128BitVector() || VT.is64BitVector())) {
2935 unsigned PFIndexes[4];
2936 for (unsigned i = 0; i != 4; ++i) {
2937 if (ShuffleMask[i] < 0)
2938 PFIndexes[i] = 8;
2939 else
2940 PFIndexes[i] = ShuffleMask[i];
2941 }
2942
2943 // Compute the index in the perfect shuffle table.
2944 unsigned PFTableIndex =
2945 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2946
2947 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2948 unsigned Cost = (PFEntry >> 30);
2949
2950 if (Cost <= 4)
2951 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2952 }
Bob Wilsond8e17572009-08-12 22:31:50 +00002953
Bob Wilson22cac0d2009-08-14 05:16:33 +00002954 return SDValue();
Bob Wilson5bafff32009-06-22 23:27:02 +00002955}
2956
Bob Wilson5bafff32009-06-22 23:27:02 +00002957static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
Owen Andersone50ed302009-08-10 22:56:29 +00002958 EVT VT = Op.getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00002959 DebugLoc dl = Op.getDebugLoc();
Bob Wilson5bafff32009-06-22 23:27:02 +00002960 SDValue Vec = Op.getOperand(0);
2961 SDValue Lane = Op.getOperand(1);
Bob Wilson934f98b2009-10-15 23:12:05 +00002962 assert(VT == MVT::i32 &&
2963 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
2964 "unexpected type for custom-lowering vector extract");
2965 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
Bob Wilson5bafff32009-06-22 23:27:02 +00002966}
2967
Bob Wilsona6d65862009-08-03 20:36:38 +00002968static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2969 // The only time a CONCAT_VECTORS operation can have legal types is when
2970 // two 64-bit vectors are concatenated to a 128-bit vector.
2971 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2972 "unexpected CONCAT_VECTORS");
2973 DebugLoc dl = Op.getDebugLoc();
Owen Anderson825b72b2009-08-11 20:47:22 +00002974 SDValue Val = DAG.getUNDEF(MVT::v2f64);
Bob Wilsona6d65862009-08-03 20:36:38 +00002975 SDValue Op0 = Op.getOperand(0);
2976 SDValue Op1 = Op.getOperand(1);
2977 if (Op0.getOpcode() != ISD::UNDEF)
Owen Anderson825b72b2009-08-11 20:47:22 +00002978 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2979 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
Bob Wilsona6d65862009-08-03 20:36:38 +00002980 DAG.getIntPtrConstant(0));
2981 if (Op1.getOpcode() != ISD::UNDEF)
Owen Anderson825b72b2009-08-11 20:47:22 +00002982 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2983 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
Bob Wilsona6d65862009-08-03 20:36:38 +00002984 DAG.getIntPtrConstant(1));
2985 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
Bob Wilson5bafff32009-06-22 23:27:02 +00002986}
2987
Dan Gohman475871a2008-07-27 21:46:04 +00002988SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
Evan Chenga8e29892007-01-19 07:51:42 +00002989 switch (Op.getOpcode()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002990 default: llvm_unreachable("Don't know how to custom lower this!");
Evan Chenga8e29892007-01-19 07:51:42 +00002991 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
Bob Wilsonddb16df2009-10-30 05:45:42 +00002992 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00002993 case ISD::GlobalAddress:
2994 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2995 LowerGlobalAddressELF(Op, DAG);
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +00002996 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
Evan Cheng06b53c02009-11-12 07:13:11 +00002997 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2998 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
Evan Chenga8e29892007-01-19 07:51:42 +00002999 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
Evan Cheng86198642009-08-07 00:34:42 +00003000 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Evan Chenga8e29892007-01-19 07:51:42 +00003001 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
Jim Grosbach7c03dbd2009-12-14 21:24:16 +00003002 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
Evan Chenga8e29892007-01-19 07:51:42 +00003003 case ISD::SINT_TO_FP:
3004 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3005 case ISD::FP_TO_SINT:
3006 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3007 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Nate Begemanbcc5f362007-01-29 22:58:52 +00003008 case ISD::RETURNADDR: break;
Jim Grosbach0e0da732009-05-12 23:59:14 +00003009 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +00003010 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
Lauro Ramos Venancioe0cb36b2007-11-08 17:20:05 +00003011 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Duncan Sands1607f052008-12-01 11:39:25 +00003012 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
Bob Wilson5bafff32009-06-22 23:27:02 +00003013 case ISD::SHL:
Chris Lattner27a6c732007-11-24 07:07:01 +00003014 case ISD::SRL:
Bob Wilson5bafff32009-06-22 23:27:02 +00003015 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
Evan Cheng06b53c02009-11-12 07:13:11 +00003016 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
Jim Grosbachbcf2f2c2009-10-31 21:42:19 +00003017 case ISD::SRL_PARTS:
Evan Cheng06b53c02009-11-12 07:13:11 +00003018 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
Bob Wilson5bafff32009-06-22 23:27:02 +00003019 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3020 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3021 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
Bob Wilson5bafff32009-06-22 23:27:02 +00003022 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
Bob Wilsona6d65862009-08-03 20:36:38 +00003023 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
Evan Chenga8e29892007-01-19 07:51:42 +00003024 }
Dan Gohman475871a2008-07-27 21:46:04 +00003025 return SDValue();
Evan Chenga8e29892007-01-19 07:51:42 +00003026}
3027
Duncan Sands1607f052008-12-01 11:39:25 +00003028/// ReplaceNodeResults - Replace the results of node with an illegal result
3029/// type with new values built out of custom code.
Duncan Sands1607f052008-12-01 11:39:25 +00003030void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3031 SmallVectorImpl<SDValue>&Results,
3032 SelectionDAG &DAG) {
Chris Lattner27a6c732007-11-24 07:07:01 +00003033 switch (N->getOpcode()) {
Duncan Sands1607f052008-12-01 11:39:25 +00003034 default:
Torok Edwinc23197a2009-07-14 16:55:14 +00003035 llvm_unreachable("Don't know how to custom expand this!");
Duncan Sands1607f052008-12-01 11:39:25 +00003036 return;
3037 case ISD::BIT_CONVERT:
3038 Results.push_back(ExpandBIT_CONVERT(N, DAG));
3039 return;
Chris Lattner27a6c732007-11-24 07:07:01 +00003040 case ISD::SRL:
Duncan Sands1607f052008-12-01 11:39:25 +00003041 case ISD::SRA: {
Bob Wilson5bafff32009-06-22 23:27:02 +00003042 SDValue Res = LowerShift(N, DAG, Subtarget);
Duncan Sands1607f052008-12-01 11:39:25 +00003043 if (Res.getNode())
3044 Results.push_back(Res);
3045 return;
3046 }
Chris Lattner27a6c732007-11-24 07:07:01 +00003047 }
3048}
Chris Lattner27a6c732007-11-24 07:07:01 +00003049
Evan Chenga8e29892007-01-19 07:51:42 +00003050//===----------------------------------------------------------------------===//
3051// ARM Scheduler Hooks
3052//===----------------------------------------------------------------------===//
3053
3054MachineBasicBlock *
Jim Grosbache801dc42009-12-12 01:40:06 +00003055ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3056 MachineBasicBlock *BB,
3057 unsigned Size) const {
Jim Grosbach5278eb82009-12-11 01:42:04 +00003058 unsigned dest = MI->getOperand(0).getReg();
3059 unsigned ptr = MI->getOperand(1).getReg();
3060 unsigned oldval = MI->getOperand(2).getReg();
3061 unsigned newval = MI->getOperand(3).getReg();
3062 unsigned scratch = BB->getParent()->getRegInfo()
3063 .createVirtualRegister(ARM::GPRRegisterClass);
3064 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3065 DebugLoc dl = MI->getDebugLoc();
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003066 bool isThumb2 = Subtarget->isThumb2();
Jim Grosbach5278eb82009-12-11 01:42:04 +00003067
3068 unsigned ldrOpc, strOpc;
3069 switch (Size) {
3070 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003071 case 1:
3072 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3073 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3074 break;
3075 case 2:
3076 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3077 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3078 break;
3079 case 4:
3080 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3081 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3082 break;
Jim Grosbach5278eb82009-12-11 01:42:04 +00003083 }
3084
3085 MachineFunction *MF = BB->getParent();
3086 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3087 MachineFunction::iterator It = BB;
3088 ++It; // insert the new blocks after the current block
3089
3090 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3091 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3092 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3093 MF->insert(It, loop1MBB);
3094 MF->insert(It, loop2MBB);
3095 MF->insert(It, exitMBB);
3096 exitMBB->transferSuccessors(BB);
3097
3098 // thisMBB:
3099 // ...
3100 // fallthrough --> loop1MBB
3101 BB->addSuccessor(loop1MBB);
3102
3103 // loop1MBB:
3104 // ldrex dest, [ptr]
3105 // cmp dest, oldval
3106 // bne exitMBB
3107 BB = loop1MBB;
3108 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003109 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
Jim Grosbach5278eb82009-12-11 01:42:04 +00003110 .addReg(dest).addReg(oldval));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003111 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3112 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003113 BB->addSuccessor(loop2MBB);
3114 BB->addSuccessor(exitMBB);
3115
3116 // loop2MBB:
3117 // strex scratch, newval, [ptr]
3118 // cmp scratch, #0
3119 // bne loop1MBB
3120 BB = loop2MBB;
3121 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3122 .addReg(ptr));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003123 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
Jim Grosbach5278eb82009-12-11 01:42:04 +00003124 .addReg(scratch).addImm(0));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003125 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3126 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003127 BB->addSuccessor(loop1MBB);
3128 BB->addSuccessor(exitMBB);
3129
3130 // exitMBB:
3131 // ...
3132 BB = exitMBB;
Jim Grosbach5efaed32010-01-15 00:18:34 +00003133
3134 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3135
Jim Grosbach5278eb82009-12-11 01:42:04 +00003136 return BB;
3137}
3138
3139MachineBasicBlock *
Jim Grosbache801dc42009-12-12 01:40:06 +00003140ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3141 unsigned Size, unsigned BinOpcode) const {
Jim Grosbachc3c23542009-12-14 04:22:04 +00003142 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3143 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3144
3145 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3146 MachineFunction *F = BB->getParent();
3147 MachineFunction::iterator It = BB;
3148 ++It;
3149
3150 unsigned dest = MI->getOperand(0).getReg();
3151 unsigned ptr = MI->getOperand(1).getReg();
3152 unsigned incr = MI->getOperand(2).getReg();
3153 DebugLoc dl = MI->getDebugLoc();
Rafael Espindolafda60d32009-12-18 16:59:39 +00003154
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003155 bool isThumb2 = Subtarget->isThumb2();
Jim Grosbachc3c23542009-12-14 04:22:04 +00003156 unsigned ldrOpc, strOpc;
3157 switch (Size) {
3158 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003159 case 1:
3160 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
Jakob Stoklund Olesen15913c92010-01-13 19:54:39 +00003161 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003162 break;
3163 case 2:
3164 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3165 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3166 break;
3167 case 4:
3168 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3169 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3170 break;
Jim Grosbachc3c23542009-12-14 04:22:04 +00003171 }
3172
3173 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3174 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3175 F->insert(It, loopMBB);
3176 F->insert(It, exitMBB);
3177 exitMBB->transferSuccessors(BB);
3178
3179 MachineRegisterInfo &RegInfo = F->getRegInfo();
3180 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3181 unsigned scratch2 = (!BinOpcode) ? incr :
3182 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3183
3184 // thisMBB:
3185 // ...
3186 // fallthrough --> loopMBB
3187 BB->addSuccessor(loopMBB);
3188
3189 // loopMBB:
3190 // ldrex dest, ptr
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003191 // <binop> scratch2, dest, incr
3192 // strex scratch, scratch2, ptr
Jim Grosbachc3c23542009-12-14 04:22:04 +00003193 // cmp scratch, #0
3194 // bne- loopMBB
3195 // fallthrough --> exitMBB
3196 BB = loopMBB;
3197 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
Jim Grosbachc67b5562009-12-15 00:12:35 +00003198 if (BinOpcode) {
3199 // operand order needs to go the other way for NAND
3200 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3201 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3202 addReg(incr).addReg(dest)).addReg(0);
3203 else
3204 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3205 addReg(dest).addReg(incr)).addReg(0);
3206 }
Jim Grosbachc3c23542009-12-14 04:22:04 +00003207
3208 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3209 .addReg(ptr));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003210 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
Jim Grosbachc3c23542009-12-14 04:22:04 +00003211 .addReg(scratch).addImm(0));
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003212 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3213 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
Jim Grosbachc3c23542009-12-14 04:22:04 +00003214
3215 BB->addSuccessor(loopMBB);
3216 BB->addSuccessor(exitMBB);
3217
3218 // exitMBB:
3219 // ...
3220 BB = exitMBB;
Evan Cheng102ebf12009-12-21 19:53:39 +00003221
3222 F->DeleteMachineInstr(MI); // The instruction is gone now.
3223
Jim Grosbachc3c23542009-12-14 04:22:04 +00003224 return BB;
Jim Grosbache801dc42009-12-12 01:40:06 +00003225}
3226
3227MachineBasicBlock *
Evan Chengff9b3732008-01-30 18:18:23 +00003228ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Evan Chengfb2e7522009-09-18 21:02:19 +00003229 MachineBasicBlock *BB,
3230 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
Evan Chenga8e29892007-01-19 07:51:42 +00003231 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
Dale Johannesenb6728402009-02-13 02:25:56 +00003232 DebugLoc dl = MI->getDebugLoc();
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003233 bool isThumb2 = Subtarget->isThumb2();
Evan Chenga8e29892007-01-19 07:51:42 +00003234 switch (MI->getOpcode()) {
Evan Cheng86198642009-08-07 00:34:42 +00003235 default:
Jim Grosbach5278eb82009-12-11 01:42:04 +00003236 MI->dump();
Evan Cheng86198642009-08-07 00:34:42 +00003237 llvm_unreachable("Unexpected instr type to insert");
Jim Grosbach5278eb82009-12-11 01:42:04 +00003238
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003239 case ARM::ATOMIC_LOAD_ADD_I8:
3240 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3241 case ARM::ATOMIC_LOAD_ADD_I16:
3242 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3243 case ARM::ATOMIC_LOAD_ADD_I32:
3244 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003245
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003246 case ARM::ATOMIC_LOAD_AND_I8:
3247 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3248 case ARM::ATOMIC_LOAD_AND_I16:
3249 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3250 case ARM::ATOMIC_LOAD_AND_I32:
3251 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003252
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003253 case ARM::ATOMIC_LOAD_OR_I8:
3254 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3255 case ARM::ATOMIC_LOAD_OR_I16:
3256 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3257 case ARM::ATOMIC_LOAD_OR_I32:
3258 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003259
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003260 case ARM::ATOMIC_LOAD_XOR_I8:
3261 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3262 case ARM::ATOMIC_LOAD_XOR_I16:
3263 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3264 case ARM::ATOMIC_LOAD_XOR_I32:
3265 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
Jim Grosbache801dc42009-12-12 01:40:06 +00003266
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003267 case ARM::ATOMIC_LOAD_NAND_I8:
3268 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3269 case ARM::ATOMIC_LOAD_NAND_I16:
3270 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3271 case ARM::ATOMIC_LOAD_NAND_I32:
3272 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
Jim Grosbache801dc42009-12-12 01:40:06 +00003273
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003274 case ARM::ATOMIC_LOAD_SUB_I8:
3275 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3276 case ARM::ATOMIC_LOAD_SUB_I16:
3277 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3278 case ARM::ATOMIC_LOAD_SUB_I32:
3279 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
Jim Grosbache801dc42009-12-12 01:40:06 +00003280
Jim Grosbacha36c8f22009-12-14 20:14:59 +00003281 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3282 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3283 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
Jim Grosbache801dc42009-12-12 01:40:06 +00003284
3285 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3286 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3287 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
Jim Grosbach5278eb82009-12-11 01:42:04 +00003288
Evan Cheng007ea272009-08-12 05:17:19 +00003289 case ARM::tMOVCCr_pseudo: {
Evan Chenga8e29892007-01-19 07:51:42 +00003290 // To "insert" a SELECT_CC instruction, we actually have to insert the
3291 // diamond control-flow pattern. The incoming instruction knows the
3292 // destination vreg to set, the condition code register to branch on, the
3293 // true/false values to select between, and a branch opcode to use.
3294 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Dan Gohman8e5f2c62008-07-07 23:14:23 +00003295 MachineFunction::iterator It = BB;
Evan Chenga8e29892007-01-19 07:51:42 +00003296 ++It;
3297
3298 // thisMBB:
3299 // ...
3300 // TrueVal = ...
3301 // cmpTY ccX, r1, r2
3302 // bCC copy1MBB
3303 // fallthrough --> copy0MBB
3304 MachineBasicBlock *thisMBB = BB;
Dan Gohman8e5f2c62008-07-07 23:14:23 +00003305 MachineFunction *F = BB->getParent();
3306 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3307 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
Dale Johannesenb6728402009-02-13 02:25:56 +00003308 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
Evan Cheng0e1d3792007-07-05 07:18:20 +00003309 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
Dan Gohman8e5f2c62008-07-07 23:14:23 +00003310 F->insert(It, copy0MBB);
3311 F->insert(It, sinkMBB);
Evan Chenga8e29892007-01-19 07:51:42 +00003312 // Update machine-CFG edges by first adding all successors of the current
3313 // block to the new block which will contain the Phi node for the select.
Evan Chengce319102009-09-19 09:51:03 +00003314 // Also inform sdisel of the edge changes.
3315 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3316 E = BB->succ_end(); I != E; ++I) {
3317 EM->insert(std::make_pair(*I, sinkMBB));
3318 sinkMBB->addSuccessor(*I);
3319 }
Evan Chenga8e29892007-01-19 07:51:42 +00003320 // Next, remove all successors of the current block, and add the true
3321 // and fallthrough blocks as its successors.
Evan Chengce319102009-09-19 09:51:03 +00003322 while (!BB->succ_empty())
Evan Chenga8e29892007-01-19 07:51:42 +00003323 BB->removeSuccessor(BB->succ_begin());
3324 BB->addSuccessor(copy0MBB);
3325 BB->addSuccessor(sinkMBB);
3326
3327 // copy0MBB:
3328 // %FalseValue = ...
3329 // # fallthrough to sinkMBB
3330 BB = copy0MBB;
3331
3332 // Update machine-CFG edges
3333 BB->addSuccessor(sinkMBB);
3334
3335 // sinkMBB:
3336 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3337 // ...
3338 BB = sinkMBB;
Dale Johannesenb6728402009-02-13 02:25:56 +00003339 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
Evan Chenga8e29892007-01-19 07:51:42 +00003340 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3341 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3342
Dan Gohman8e5f2c62008-07-07 23:14:23 +00003343 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
Evan Chenga8e29892007-01-19 07:51:42 +00003344 return BB;
3345 }
Evan Cheng86198642009-08-07 00:34:42 +00003346
3347 case ARM::tANDsp:
3348 case ARM::tADDspr_:
3349 case ARM::tSUBspi_:
3350 case ARM::t2SUBrSPi_:
3351 case ARM::t2SUBrSPi12_:
3352 case ARM::t2SUBrSPs_: {
3353 MachineFunction *MF = BB->getParent();
3354 unsigned DstReg = MI->getOperand(0).getReg();
3355 unsigned SrcReg = MI->getOperand(1).getReg();
3356 bool DstIsDead = MI->getOperand(0).isDead();
3357 bool SrcIsKill = MI->getOperand(1).isKill();
3358
3359 if (SrcReg != ARM::SP) {
3360 // Copy the source to SP from virtual register.
3361 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3362 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3363 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3364 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3365 .addReg(SrcReg, getKillRegState(SrcIsKill));
3366 }
3367
3368 unsigned OpOpc = 0;
3369 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3370 switch (MI->getOpcode()) {
3371 default:
3372 llvm_unreachable("Unexpected pseudo instruction!");
3373 case ARM::tANDsp:
3374 OpOpc = ARM::tAND;
3375 NeedPred = true;
3376 break;
3377 case ARM::tADDspr_:
3378 OpOpc = ARM::tADDspr;
3379 break;
3380 case ARM::tSUBspi_:
3381 OpOpc = ARM::tSUBspi;
3382 break;
3383 case ARM::t2SUBrSPi_:
3384 OpOpc = ARM::t2SUBrSPi;
3385 NeedPred = true; NeedCC = true;
3386 break;
3387 case ARM::t2SUBrSPi12_:
3388 OpOpc = ARM::t2SUBrSPi12;
3389 NeedPred = true;
3390 break;
3391 case ARM::t2SUBrSPs_:
3392 OpOpc = ARM::t2SUBrSPs;
3393 NeedPred = true; NeedCC = true; NeedOp3 = true;
3394 break;
3395 }
3396 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3397 if (OpOpc == ARM::tAND)
3398 AddDefaultT1CC(MIB);
3399 MIB.addReg(ARM::SP);
3400 MIB.addOperand(MI->getOperand(2));
3401 if (NeedOp3)
3402 MIB.addOperand(MI->getOperand(3));
3403 if (NeedPred)
3404 AddDefaultPred(MIB);
3405 if (NeedCC)
3406 AddDefaultCC(MIB);
3407
3408 // Copy the result from SP to virtual register.
3409 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3410 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3411 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3412 BuildMI(BB, dl, TII->get(CopyOpc))
3413 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3414 .addReg(ARM::SP);
3415 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3416 return BB;
3417 }
Evan Chenga8e29892007-01-19 07:51:42 +00003418 }
3419}
3420
3421//===----------------------------------------------------------------------===//
3422// ARM Optimization Hooks
3423//===----------------------------------------------------------------------===//
3424
Chris Lattnerd1980a52009-03-12 06:52:53 +00003425static
3426SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3427 TargetLowering::DAGCombinerInfo &DCI) {
Chris Lattnerd1980a52009-03-12 06:52:53 +00003428 SelectionDAG &DAG = DCI.DAG;
3429 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Owen Andersone50ed302009-08-10 22:56:29 +00003430 EVT VT = N->getValueType(0);
Chris Lattnerd1980a52009-03-12 06:52:53 +00003431 unsigned Opc = N->getOpcode();
3432 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3433 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3434 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3435 ISD::CondCode CC = ISD::SETCC_INVALID;
3436
3437 if (isSlctCC) {
3438 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3439 } else {
3440 SDValue CCOp = Slct.getOperand(0);
3441 if (CCOp.getOpcode() == ISD::SETCC)
3442 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3443 }
3444
3445 bool DoXform = false;
3446 bool InvCC = false;
3447 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3448 "Bad input!");
3449
3450 if (LHS.getOpcode() == ISD::Constant &&
3451 cast<ConstantSDNode>(LHS)->isNullValue()) {
3452 DoXform = true;
3453 } else if (CC != ISD::SETCC_INVALID &&
3454 RHS.getOpcode() == ISD::Constant &&
3455 cast<ConstantSDNode>(RHS)->isNullValue()) {
3456 std::swap(LHS, RHS);
3457 SDValue Op0 = Slct.getOperand(0);
Owen Andersone50ed302009-08-10 22:56:29 +00003458 EVT OpVT = isSlctCC ? Op0.getValueType() :
Chris Lattnerd1980a52009-03-12 06:52:53 +00003459 Op0.getOperand(0).getValueType();
3460 bool isInt = OpVT.isInteger();
3461 CC = ISD::getSetCCInverse(CC, isInt);
3462
3463 if (!TLI.isCondCodeLegal(CC, OpVT))
3464 return SDValue(); // Inverse operator isn't legal.
3465
3466 DoXform = true;
3467 InvCC = true;
3468 }
3469
3470 if (DoXform) {
3471 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3472 if (isSlctCC)
3473 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3474 Slct.getOperand(0), Slct.getOperand(1), CC);
3475 SDValue CCOp = Slct.getOperand(0);
3476 if (InvCC)
3477 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3478 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3479 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3480 CCOp, OtherOp, Result);
3481 }
3482 return SDValue();
3483}
3484
3485/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3486static SDValue PerformADDCombine(SDNode *N,
3487 TargetLowering::DAGCombinerInfo &DCI) {
3488 // added by evan in r37685 with no testcase.
3489 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
Bob Wilson2dc4f542009-03-20 22:42:55 +00003490
Chris Lattnerd1980a52009-03-12 06:52:53 +00003491 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3492 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3493 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3494 if (Result.getNode()) return Result;
3495 }
3496 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3497 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3498 if (Result.getNode()) return Result;
3499 }
Bob Wilson2dc4f542009-03-20 22:42:55 +00003500
Chris Lattnerd1980a52009-03-12 06:52:53 +00003501 return SDValue();
3502}
3503
3504/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3505static SDValue PerformSUBCombine(SDNode *N,
3506 TargetLowering::DAGCombinerInfo &DCI) {
3507 // added by evan in r37685 with no testcase.
3508 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
Bob Wilson2dc4f542009-03-20 22:42:55 +00003509
Chris Lattnerd1980a52009-03-12 06:52:53 +00003510 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3511 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3512 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3513 if (Result.getNode()) return Result;
3514 }
Bob Wilson2dc4f542009-03-20 22:42:55 +00003515
Chris Lattnerd1980a52009-03-12 06:52:53 +00003516 return SDValue();
3517}
3518
Jim Grosbache5165492009-11-09 00:11:35 +00003519/// PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
3520static SDValue PerformVMOVRRDCombine(SDNode *N,
Bob Wilson2dc4f542009-03-20 22:42:55 +00003521 TargetLowering::DAGCombinerInfo &DCI) {
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003522 // fmrrd(fmdrr x, y) -> x,y
Dan Gohman475871a2008-07-27 21:46:04 +00003523 SDValue InDouble = N->getOperand(0);
Jim Grosbache5165492009-11-09 00:11:35 +00003524 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003525 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
Dan Gohman475871a2008-07-27 21:46:04 +00003526 return SDValue();
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003527}
3528
Bob Wilson5bafff32009-06-22 23:27:02 +00003529/// getVShiftImm - Check if this is a valid build_vector for the immediate
3530/// operand of a vector shift operation, where all the elements of the
3531/// build_vector must have the same constant integer value.
3532static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3533 // Ignore bit_converts.
3534 while (Op.getOpcode() == ISD::BIT_CONVERT)
3535 Op = Op.getOperand(0);
3536 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3537 APInt SplatBits, SplatUndef;
3538 unsigned SplatBitSize;
3539 bool HasAnyUndefs;
3540 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3541 HasAnyUndefs, ElementBits) ||
3542 SplatBitSize > ElementBits)
3543 return false;
3544 Cnt = SplatBits.getSExtValue();
3545 return true;
3546}
3547
3548/// isVShiftLImm - Check if this is a valid build_vector for the immediate
3549/// operand of a vector shift left operation. That value must be in the range:
3550/// 0 <= Value < ElementBits for a left shift; or
3551/// 0 <= Value <= ElementBits for a long left shift.
Owen Andersone50ed302009-08-10 22:56:29 +00003552static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
Bob Wilson5bafff32009-06-22 23:27:02 +00003553 assert(VT.isVector() && "vector shift count is not a vector type");
3554 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3555 if (! getVShiftImm(Op, ElementBits, Cnt))
3556 return false;
3557 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3558}
3559
3560/// isVShiftRImm - Check if this is a valid build_vector for the immediate
3561/// operand of a vector shift right operation. For a shift opcode, the value
3562/// is positive, but for an intrinsic the value count must be negative. The
3563/// absolute value must be in the range:
3564/// 1 <= |Value| <= ElementBits for a right shift; or
3565/// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
Owen Andersone50ed302009-08-10 22:56:29 +00003566static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
Bob Wilson5bafff32009-06-22 23:27:02 +00003567 int64_t &Cnt) {
3568 assert(VT.isVector() && "vector shift count is not a vector type");
3569 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3570 if (! getVShiftImm(Op, ElementBits, Cnt))
3571 return false;
3572 if (isIntrinsic)
3573 Cnt = -Cnt;
3574 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3575}
3576
3577/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3578static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3579 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3580 switch (IntNo) {
3581 default:
3582 // Don't do anything for most intrinsics.
3583 break;
3584
3585 // Vector shifts: check for immediate versions and lower them.
3586 // Note: This is done during DAG combining instead of DAG legalizing because
3587 // the build_vectors for 64-bit vector element shift counts are generally
3588 // not legal, and it is hard to see their values after they get legalized to
3589 // loads from a constant pool.
3590 case Intrinsic::arm_neon_vshifts:
3591 case Intrinsic::arm_neon_vshiftu:
3592 case Intrinsic::arm_neon_vshiftls:
3593 case Intrinsic::arm_neon_vshiftlu:
3594 case Intrinsic::arm_neon_vshiftn:
3595 case Intrinsic::arm_neon_vrshifts:
3596 case Intrinsic::arm_neon_vrshiftu:
3597 case Intrinsic::arm_neon_vrshiftn:
3598 case Intrinsic::arm_neon_vqshifts:
3599 case Intrinsic::arm_neon_vqshiftu:
3600 case Intrinsic::arm_neon_vqshiftsu:
3601 case Intrinsic::arm_neon_vqshiftns:
3602 case Intrinsic::arm_neon_vqshiftnu:
3603 case Intrinsic::arm_neon_vqshiftnsu:
3604 case Intrinsic::arm_neon_vqrshiftns:
3605 case Intrinsic::arm_neon_vqrshiftnu:
3606 case Intrinsic::arm_neon_vqrshiftnsu: {
Owen Andersone50ed302009-08-10 22:56:29 +00003607 EVT VT = N->getOperand(1).getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00003608 int64_t Cnt;
3609 unsigned VShiftOpc = 0;
3610
3611 switch (IntNo) {
3612 case Intrinsic::arm_neon_vshifts:
3613 case Intrinsic::arm_neon_vshiftu:
3614 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3615 VShiftOpc = ARMISD::VSHL;
3616 break;
3617 }
3618 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3619 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3620 ARMISD::VSHRs : ARMISD::VSHRu);
3621 break;
3622 }
3623 return SDValue();
3624
3625 case Intrinsic::arm_neon_vshiftls:
3626 case Intrinsic::arm_neon_vshiftlu:
3627 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3628 break;
Torok Edwinc23197a2009-07-14 16:55:14 +00003629 llvm_unreachable("invalid shift count for vshll intrinsic");
Bob Wilson5bafff32009-06-22 23:27:02 +00003630
3631 case Intrinsic::arm_neon_vrshifts:
3632 case Intrinsic::arm_neon_vrshiftu:
3633 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3634 break;
3635 return SDValue();
3636
3637 case Intrinsic::arm_neon_vqshifts:
3638 case Intrinsic::arm_neon_vqshiftu:
3639 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3640 break;
3641 return SDValue();
3642
3643 case Intrinsic::arm_neon_vqshiftsu:
3644 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3645 break;
Torok Edwinc23197a2009-07-14 16:55:14 +00003646 llvm_unreachable("invalid shift count for vqshlu intrinsic");
Bob Wilson5bafff32009-06-22 23:27:02 +00003647
3648 case Intrinsic::arm_neon_vshiftn:
3649 case Intrinsic::arm_neon_vrshiftn:
3650 case Intrinsic::arm_neon_vqshiftns:
3651 case Intrinsic::arm_neon_vqshiftnu:
3652 case Intrinsic::arm_neon_vqshiftnsu:
3653 case Intrinsic::arm_neon_vqrshiftns:
3654 case Intrinsic::arm_neon_vqrshiftnu:
3655 case Intrinsic::arm_neon_vqrshiftnsu:
3656 // Narrowing shifts require an immediate right shift.
3657 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3658 break;
Torok Edwinc23197a2009-07-14 16:55:14 +00003659 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
Bob Wilson5bafff32009-06-22 23:27:02 +00003660
3661 default:
Torok Edwinc23197a2009-07-14 16:55:14 +00003662 llvm_unreachable("unhandled vector shift");
Bob Wilson5bafff32009-06-22 23:27:02 +00003663 }
3664
3665 switch (IntNo) {
3666 case Intrinsic::arm_neon_vshifts:
3667 case Intrinsic::arm_neon_vshiftu:
3668 // Opcode already set above.
3669 break;
3670 case Intrinsic::arm_neon_vshiftls:
3671 case Intrinsic::arm_neon_vshiftlu:
3672 if (Cnt == VT.getVectorElementType().getSizeInBits())
3673 VShiftOpc = ARMISD::VSHLLi;
3674 else
3675 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3676 ARMISD::VSHLLs : ARMISD::VSHLLu);
3677 break;
3678 case Intrinsic::arm_neon_vshiftn:
3679 VShiftOpc = ARMISD::VSHRN; break;
3680 case Intrinsic::arm_neon_vrshifts:
3681 VShiftOpc = ARMISD::VRSHRs; break;
3682 case Intrinsic::arm_neon_vrshiftu:
3683 VShiftOpc = ARMISD::VRSHRu; break;
3684 case Intrinsic::arm_neon_vrshiftn:
3685 VShiftOpc = ARMISD::VRSHRN; break;
3686 case Intrinsic::arm_neon_vqshifts:
3687 VShiftOpc = ARMISD::VQSHLs; break;
3688 case Intrinsic::arm_neon_vqshiftu:
3689 VShiftOpc = ARMISD::VQSHLu; break;
3690 case Intrinsic::arm_neon_vqshiftsu:
3691 VShiftOpc = ARMISD::VQSHLsu; break;
3692 case Intrinsic::arm_neon_vqshiftns:
3693 VShiftOpc = ARMISD::VQSHRNs; break;
3694 case Intrinsic::arm_neon_vqshiftnu:
3695 VShiftOpc = ARMISD::VQSHRNu; break;
3696 case Intrinsic::arm_neon_vqshiftnsu:
3697 VShiftOpc = ARMISD::VQSHRNsu; break;
3698 case Intrinsic::arm_neon_vqrshiftns:
3699 VShiftOpc = ARMISD::VQRSHRNs; break;
3700 case Intrinsic::arm_neon_vqrshiftnu:
3701 VShiftOpc = ARMISD::VQRSHRNu; break;
3702 case Intrinsic::arm_neon_vqrshiftnsu:
3703 VShiftOpc = ARMISD::VQRSHRNsu; break;
3704 }
3705
3706 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
Owen Anderson825b72b2009-08-11 20:47:22 +00003707 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +00003708 }
3709
3710 case Intrinsic::arm_neon_vshiftins: {
Owen Andersone50ed302009-08-10 22:56:29 +00003711 EVT VT = N->getOperand(1).getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00003712 int64_t Cnt;
3713 unsigned VShiftOpc = 0;
3714
3715 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3716 VShiftOpc = ARMISD::VSLI;
3717 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3718 VShiftOpc = ARMISD::VSRI;
3719 else {
Torok Edwinc23197a2009-07-14 16:55:14 +00003720 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
Bob Wilson5bafff32009-06-22 23:27:02 +00003721 }
3722
3723 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3724 N->getOperand(1), N->getOperand(2),
Owen Anderson825b72b2009-08-11 20:47:22 +00003725 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +00003726 }
3727
3728 case Intrinsic::arm_neon_vqrshifts:
3729 case Intrinsic::arm_neon_vqrshiftu:
3730 // No immediate versions of these to check for.
3731 break;
3732 }
3733
3734 return SDValue();
3735}
3736
3737/// PerformShiftCombine - Checks for immediate versions of vector shifts and
3738/// lowers them. As with the vector shift intrinsics, this is done during DAG
3739/// combining instead of DAG legalizing because the build_vectors for 64-bit
3740/// vector element shift counts are generally not legal, and it is hard to see
3741/// their values after they get legalized to loads from a constant pool.
3742static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3743 const ARMSubtarget *ST) {
Owen Andersone50ed302009-08-10 22:56:29 +00003744 EVT VT = N->getValueType(0);
Bob Wilson5bafff32009-06-22 23:27:02 +00003745
3746 // Nothing to be done for scalar shifts.
3747 if (! VT.isVector())
3748 return SDValue();
3749
3750 assert(ST->hasNEON() && "unexpected vector shift");
3751 int64_t Cnt;
3752
3753 switch (N->getOpcode()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00003754 default: llvm_unreachable("unexpected shift opcode");
Bob Wilson5bafff32009-06-22 23:27:02 +00003755
3756 case ISD::SHL:
3757 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3758 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
Owen Anderson825b72b2009-08-11 20:47:22 +00003759 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +00003760 break;
3761
3762 case ISD::SRA:
3763 case ISD::SRL:
3764 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3765 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3766 ARMISD::VSHRs : ARMISD::VSHRu);
3767 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
Owen Anderson825b72b2009-08-11 20:47:22 +00003768 DAG.getConstant(Cnt, MVT::i32));
Bob Wilson5bafff32009-06-22 23:27:02 +00003769 }
3770 }
3771 return SDValue();
3772}
3773
3774/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3775/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3776static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3777 const ARMSubtarget *ST) {
3778 SDValue N0 = N->getOperand(0);
3779
3780 // Check for sign- and zero-extensions of vector extract operations of 8-
3781 // and 16-bit vector elements. NEON supports these directly. They are
3782 // handled during DAG combining because type legalization will promote them
3783 // to 32-bit types and it is messy to recognize the operations after that.
3784 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3785 SDValue Vec = N0.getOperand(0);
3786 SDValue Lane = N0.getOperand(1);
Owen Andersone50ed302009-08-10 22:56:29 +00003787 EVT VT = N->getValueType(0);
3788 EVT EltVT = N0.getValueType();
Bob Wilson5bafff32009-06-22 23:27:02 +00003789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3790
Owen Anderson825b72b2009-08-11 20:47:22 +00003791 if (VT == MVT::i32 &&
3792 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
Bob Wilson5bafff32009-06-22 23:27:02 +00003793 TLI.isTypeLegal(Vec.getValueType())) {
3794
3795 unsigned Opc = 0;
3796 switch (N->getOpcode()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00003797 default: llvm_unreachable("unexpected opcode");
Bob Wilson5bafff32009-06-22 23:27:02 +00003798 case ISD::SIGN_EXTEND:
3799 Opc = ARMISD::VGETLANEs;
3800 break;
3801 case ISD::ZERO_EXTEND:
3802 case ISD::ANY_EXTEND:
3803 Opc = ARMISD::VGETLANEu;
3804 break;
3805 }
3806 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3807 }
3808 }
3809
3810 return SDValue();
3811}
3812
Dan Gohman475871a2008-07-27 21:46:04 +00003813SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
Bob Wilson2dc4f542009-03-20 22:42:55 +00003814 DAGCombinerInfo &DCI) const {
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003815 switch (N->getOpcode()) {
3816 default: break;
Chris Lattnerd1980a52009-03-12 06:52:53 +00003817 case ISD::ADD: return PerformADDCombine(N, DCI);
3818 case ISD::SUB: return PerformSUBCombine(N, DCI);
Jim Grosbache5165492009-11-09 00:11:35 +00003819 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
Bob Wilson5bafff32009-06-22 23:27:02 +00003820 case ISD::INTRINSIC_WO_CHAIN:
3821 return PerformIntrinsicCombine(N, DCI.DAG);
3822 case ISD::SHL:
3823 case ISD::SRA:
3824 case ISD::SRL:
3825 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3826 case ISD::SIGN_EXTEND:
3827 case ISD::ZERO_EXTEND:
3828 case ISD::ANY_EXTEND:
3829 return PerformExtendCombine(N, DCI.DAG, Subtarget);
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003830 }
Dan Gohman475871a2008-07-27 21:46:04 +00003831 return SDValue();
Chris Lattnerf1b1c5e2007-11-27 22:36:16 +00003832}
3833
Bill Wendlingaf566342009-08-15 21:21:19 +00003834bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3835 if (!Subtarget->hasV6Ops())
3836 // Pre-v6 does not support unaligned mem access.
3837 return false;
3838 else if (!Subtarget->hasV6Ops()) {
3839 // v6 may or may not support unaligned mem access.
3840 if (!Subtarget->isTargetDarwin())
3841 return false;
3842 }
3843
3844 switch (VT.getSimpleVT().SimpleTy) {
3845 default:
3846 return false;
3847 case MVT::i8:
3848 case MVT::i16:
3849 case MVT::i32:
3850 return true;
3851 // FIXME: VLD1 etc with standard alignment is legal.
3852 }
3853}
3854
Evan Chenge6c835f2009-08-14 20:09:37 +00003855static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3856 if (V < 0)
3857 return false;
3858
3859 unsigned Scale = 1;
3860 switch (VT.getSimpleVT().SimpleTy) {
3861 default: return false;
3862 case MVT::i1:
3863 case MVT::i8:
3864 // Scale == 1;
3865 break;
3866 case MVT::i16:
3867 // Scale == 2;
3868 Scale = 2;
3869 break;
3870 case MVT::i32:
3871 // Scale == 4;
3872 Scale = 4;
3873 break;
3874 }
3875
3876 if ((V & (Scale - 1)) != 0)
3877 return false;
3878 V /= Scale;
3879 return V == (V & ((1LL << 5) - 1));
3880}
3881
3882static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3883 const ARMSubtarget *Subtarget) {
3884 bool isNeg = false;
3885 if (V < 0) {
3886 isNeg = true;
3887 V = - V;
3888 }
3889
3890 switch (VT.getSimpleVT().SimpleTy) {
3891 default: return false;
3892 case MVT::i1:
3893 case MVT::i8:
3894 case MVT::i16:
3895 case MVT::i32:
3896 // + imm12 or - imm8
3897 if (isNeg)
3898 return V == (V & ((1LL << 8) - 1));
3899 return V == (V & ((1LL << 12) - 1));
3900 case MVT::f32:
3901 case MVT::f64:
3902 // Same as ARM mode. FIXME: NEON?
3903 if (!Subtarget->hasVFP2())
3904 return false;
3905 if ((V & 3) != 0)
3906 return false;
3907 V >>= 2;
3908 return V == (V & ((1LL << 8) - 1));
3909 }
3910}
3911
Evan Chengb01fad62007-03-12 23:30:29 +00003912/// isLegalAddressImmediate - Return true if the integer value can be used
3913/// as the offset of the target addressing mode for load / store of the
3914/// given type.
Owen Andersone50ed302009-08-10 22:56:29 +00003915static bool isLegalAddressImmediate(int64_t V, EVT VT,
Chris Lattner37caf8c2007-04-09 23:33:39 +00003916 const ARMSubtarget *Subtarget) {
Evan Cheng961f8792007-03-13 20:37:59 +00003917 if (V == 0)
3918 return true;
3919
Evan Cheng65011532009-03-09 19:15:00 +00003920 if (!VT.isSimple())
3921 return false;
3922
Evan Chenge6c835f2009-08-14 20:09:37 +00003923 if (Subtarget->isThumb1Only())
3924 return isLegalT1AddressImmediate(V, VT);
3925 else if (Subtarget->isThumb2())
3926 return isLegalT2AddressImmediate(V, VT, Subtarget);
Evan Chengb01fad62007-03-12 23:30:29 +00003927
Evan Chenge6c835f2009-08-14 20:09:37 +00003928 // ARM mode.
Evan Chengb01fad62007-03-12 23:30:29 +00003929 if (V < 0)
3930 V = - V;
Owen Anderson825b72b2009-08-11 20:47:22 +00003931 switch (VT.getSimpleVT().SimpleTy) {
Evan Chengb01fad62007-03-12 23:30:29 +00003932 default: return false;
Owen Anderson825b72b2009-08-11 20:47:22 +00003933 case MVT::i1:
3934 case MVT::i8:
3935 case MVT::i32:
Evan Chengb01fad62007-03-12 23:30:29 +00003936 // +- imm12
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003937 return V == (V & ((1LL << 12) - 1));
Owen Anderson825b72b2009-08-11 20:47:22 +00003938 case MVT::i16:
Evan Chengb01fad62007-03-12 23:30:29 +00003939 // +- imm8
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003940 return V == (V & ((1LL << 8) - 1));
Owen Anderson825b72b2009-08-11 20:47:22 +00003941 case MVT::f32:
3942 case MVT::f64:
Evan Chenge6c835f2009-08-14 20:09:37 +00003943 if (!Subtarget->hasVFP2()) // FIXME: NEON?
Evan Chengb01fad62007-03-12 23:30:29 +00003944 return false;
Evan Cheng0b0a9a92007-05-03 02:00:18 +00003945 if ((V & 3) != 0)
Evan Chengb01fad62007-03-12 23:30:29 +00003946 return false;
3947 V >>= 2;
Anton Korobeynikov7c1c2612008-02-20 11:22:39 +00003948 return V == (V & ((1LL << 8) - 1));
Evan Chengb01fad62007-03-12 23:30:29 +00003949 }
Evan Chenga8e29892007-01-19 07:51:42 +00003950}
3951
Evan Chenge6c835f2009-08-14 20:09:37 +00003952bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3953 EVT VT) const {
3954 int Scale = AM.Scale;
3955 if (Scale < 0)
3956 return false;
3957
3958 switch (VT.getSimpleVT().SimpleTy) {
3959 default: return false;
3960 case MVT::i1:
3961 case MVT::i8:
3962 case MVT::i16:
3963 case MVT::i32:
3964 if (Scale == 1)
3965 return true;
3966 // r + r << imm
3967 Scale = Scale & ~1;
3968 return Scale == 2 || Scale == 4 || Scale == 8;
3969 case MVT::i64:
3970 // r + r
3971 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3972 return true;
3973 return false;
3974 case MVT::isVoid:
3975 // Note, we allow "void" uses (basically, uses that aren't loads or
3976 // stores), because arm allows folding a scale into many arithmetic
3977 // operations. This should be made more precise and revisited later.
3978
3979 // Allow r << imm, but the imm has to be a multiple of two.
3980 if (Scale & 1) return false;
3981 return isPowerOf2_32(Scale);
3982 }
3983}
3984
Chris Lattner37caf8c2007-04-09 23:33:39 +00003985/// isLegalAddressingMode - Return true if the addressing mode represented
3986/// by AM is legal for this target, for a load/store of the specified type.
Bob Wilson2dc4f542009-03-20 22:42:55 +00003987bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattner37caf8c2007-04-09 23:33:39 +00003988 const Type *Ty) const {
Owen Andersone50ed302009-08-10 22:56:29 +00003989 EVT VT = getValueType(Ty, true);
Bob Wilson2c7dab12009-04-08 17:55:28 +00003990 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
Evan Chengb01fad62007-03-12 23:30:29 +00003991 return false;
Bob Wilson2dc4f542009-03-20 22:42:55 +00003992
Chris Lattner37caf8c2007-04-09 23:33:39 +00003993 // Can never fold addr of global into load/store.
Bob Wilson2dc4f542009-03-20 22:42:55 +00003994 if (AM.BaseGV)
Chris Lattner37caf8c2007-04-09 23:33:39 +00003995 return false;
Bob Wilson2dc4f542009-03-20 22:42:55 +00003996
Chris Lattner37caf8c2007-04-09 23:33:39 +00003997 switch (AM.Scale) {
3998 case 0: // no scale reg, must be "r+i" or "r", or "i".
3999 break;
4000 case 1:
Evan Chenge6c835f2009-08-14 20:09:37 +00004001 if (Subtarget->isThumb1Only())
Chris Lattner37caf8c2007-04-09 23:33:39 +00004002 return false;
Chris Lattner5a3d40d2007-04-13 06:50:55 +00004003 // FALL THROUGH.
Chris Lattner37caf8c2007-04-09 23:33:39 +00004004 default:
Chris Lattner5a3d40d2007-04-13 06:50:55 +00004005 // ARM doesn't support any R+R*scale+imm addr modes.
4006 if (AM.BaseOffs)
4007 return false;
Bob Wilson2dc4f542009-03-20 22:42:55 +00004008
Bob Wilson2c7dab12009-04-08 17:55:28 +00004009 if (!VT.isSimple())
4010 return false;
4011
Evan Chenge6c835f2009-08-14 20:09:37 +00004012 if (Subtarget->isThumb2())
4013 return isLegalT2ScaledAddressingMode(AM, VT);
4014
Chris Lattnereb13d1b2007-04-10 03:48:29 +00004015 int Scale = AM.Scale;
Owen Anderson825b72b2009-08-11 20:47:22 +00004016 switch (VT.getSimpleVT().SimpleTy) {
Chris Lattner37caf8c2007-04-09 23:33:39 +00004017 default: return false;
Owen Anderson825b72b2009-08-11 20:47:22 +00004018 case MVT::i1:
4019 case MVT::i8:
4020 case MVT::i32:
Chris Lattnereb13d1b2007-04-10 03:48:29 +00004021 if (Scale < 0) Scale = -Scale;
4022 if (Scale == 1)
Chris Lattner37caf8c2007-04-09 23:33:39 +00004023 return true;
4024 // r + r << imm
Chris Lattnere1152942007-04-11 16:17:12 +00004025 return isPowerOf2_32(Scale & ~1);
Owen Anderson825b72b2009-08-11 20:47:22 +00004026 case MVT::i16:
Evan Chenge6c835f2009-08-14 20:09:37 +00004027 case MVT::i64:
Chris Lattner37caf8c2007-04-09 23:33:39 +00004028 // r + r
Chris Lattnereb13d1b2007-04-10 03:48:29 +00004029 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
Chris Lattner37caf8c2007-04-09 23:33:39 +00004030 return true;
Chris Lattnere1152942007-04-11 16:17:12 +00004031 return false;
Bob Wilson2dc4f542009-03-20 22:42:55 +00004032
Owen Anderson825b72b2009-08-11 20:47:22 +00004033 case MVT::isVoid:
Chris Lattner37caf8c2007-04-09 23:33:39 +00004034 // Note, we allow "void" uses (basically, uses that aren't loads or
4035 // stores), because arm allows folding a scale into many arithmetic
4036 // operations. This should be made more precise and revisited later.
Bob Wilson2dc4f542009-03-20 22:42:55 +00004037
Chris Lattner37caf8c2007-04-09 23:33:39 +00004038 // Allow r << imm, but the imm has to be a multiple of two.
Evan Chenge6c835f2009-08-14 20:09:37 +00004039 if (Scale & 1) return false;
4040 return isPowerOf2_32(Scale);
Chris Lattner37caf8c2007-04-09 23:33:39 +00004041 }
4042 break;
Evan Chengb01fad62007-03-12 23:30:29 +00004043 }
Chris Lattner37caf8c2007-04-09 23:33:39 +00004044 return true;
Evan Chengb01fad62007-03-12 23:30:29 +00004045}
4046
Evan Cheng77e47512009-11-11 19:05:52 +00004047/// isLegalICmpImmediate - Return true if the specified immediate is legal
4048/// icmp immediate, that is the target has icmp instructions which can compare
4049/// a register against the immediate without having to materialize the
4050/// immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +00004051bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
Evan Cheng77e47512009-11-11 19:05:52 +00004052 if (!Subtarget->isThumb())
4053 return ARM_AM::getSOImmVal(Imm) != -1;
4054 if (Subtarget->isThumb2())
4055 return ARM_AM::getT2SOImmVal(Imm) != -1;
Evan Cheng06b53c02009-11-12 07:13:11 +00004056 return Imm >= 0 && Imm <= 255;
Evan Cheng77e47512009-11-11 19:05:52 +00004057}
4058
Owen Andersone50ed302009-08-10 22:56:29 +00004059static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
Evan Chenge88d5ce2009-07-02 07:28:31 +00004060 bool isSEXTLoad, SDValue &Base,
4061 SDValue &Offset, bool &isInc,
4062 SelectionDAG &DAG) {
Evan Chenga8e29892007-01-19 07:51:42 +00004063 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4064 return false;
4065
Owen Anderson825b72b2009-08-11 20:47:22 +00004066 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
Evan Chenga8e29892007-01-19 07:51:42 +00004067 // AddressingMode 3
4068 Base = Ptr->getOperand(0);
4069 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004070 int RHSC = (int)RHS->getZExtValue();
Evan Chenga8e29892007-01-19 07:51:42 +00004071 if (RHSC < 0 && RHSC > -256) {
Evan Chenge88d5ce2009-07-02 07:28:31 +00004072 assert(Ptr->getOpcode() == ISD::ADD);
Evan Chenga8e29892007-01-19 07:51:42 +00004073 isInc = false;
4074 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4075 return true;
4076 }
4077 }
4078 isInc = (Ptr->getOpcode() == ISD::ADD);
4079 Offset = Ptr->getOperand(1);
4080 return true;
Owen Anderson825b72b2009-08-11 20:47:22 +00004081 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
Evan Chenga8e29892007-01-19 07:51:42 +00004082 // AddressingMode 2
4083 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00004084 int RHSC = (int)RHS->getZExtValue();
Evan Chenga8e29892007-01-19 07:51:42 +00004085 if (RHSC < 0 && RHSC > -0x1000) {
Evan Chenge88d5ce2009-07-02 07:28:31 +00004086 assert(Ptr->getOpcode() == ISD::ADD);
Evan Chenga8e29892007-01-19 07:51:42 +00004087 isInc = false;
4088 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4089 Base = Ptr->getOperand(0);
4090 return true;
4091 }
4092 }
4093
4094 if (Ptr->getOpcode() == ISD::ADD) {
4095 isInc = true;
4096 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4097 if (ShOpcVal != ARM_AM::no_shift) {
4098 Base = Ptr->getOperand(1);
4099 Offset = Ptr->getOperand(0);
4100 } else {
4101 Base = Ptr->getOperand(0);
4102 Offset = Ptr->getOperand(1);
4103 }
4104 return true;
4105 }
4106
4107 isInc = (Ptr->getOpcode() == ISD::ADD);
4108 Base = Ptr->getOperand(0);
4109 Offset = Ptr->getOperand(1);
4110 return true;
4111 }
4112
Jim Grosbache5165492009-11-09 00:11:35 +00004113 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
Evan Chenga8e29892007-01-19 07:51:42 +00004114 return false;
4115}
4116
Owen Andersone50ed302009-08-10 22:56:29 +00004117static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
Evan Chenge88d5ce2009-07-02 07:28:31 +00004118 bool isSEXTLoad, SDValue &Base,
4119 SDValue &Offset, bool &isInc,
4120 SelectionDAG &DAG) {
4121 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4122 return false;
4123
4124 Base = Ptr->getOperand(0);
4125 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4126 int RHSC = (int)RHS->getZExtValue();
4127 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4128 assert(Ptr->getOpcode() == ISD::ADD);
4129 isInc = false;
4130 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4131 return true;
4132 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4133 isInc = Ptr->getOpcode() == ISD::ADD;
4134 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4135 return true;
4136 }
4137 }
4138
4139 return false;
4140}
4141
Evan Chenga8e29892007-01-19 07:51:42 +00004142/// getPreIndexedAddressParts - returns true by value, base pointer and
4143/// offset pointer and addressing mode by reference if the node's address
4144/// can be legally represented as pre-indexed load / store address.
4145bool
Dan Gohman475871a2008-07-27 21:46:04 +00004146ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4147 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +00004148 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +00004149 SelectionDAG &DAG) const {
Evan Chenge88d5ce2009-07-02 07:28:31 +00004150 if (Subtarget->isThumb1Only())
Evan Chenga8e29892007-01-19 07:51:42 +00004151 return false;
4152
Owen Andersone50ed302009-08-10 22:56:29 +00004153 EVT VT;
Dan Gohman475871a2008-07-27 21:46:04 +00004154 SDValue Ptr;
Evan Chenga8e29892007-01-19 07:51:42 +00004155 bool isSEXTLoad = false;
4156 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4157 Ptr = LD->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +00004158 VT = LD->getMemoryVT();
Evan Chenga8e29892007-01-19 07:51:42 +00004159 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4160 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4161 Ptr = ST->getBasePtr();
Dan Gohmanb625f2f2008-01-30 00:15:11 +00004162 VT = ST->getMemoryVT();
Evan Chenga8e29892007-01-19 07:51:42 +00004163 } else
4164 return false;
4165
4166 bool isInc;
Evan Chenge88d5ce2009-07-02 07:28:31 +00004167 bool isLegal = false;
Evan Chenge6c835f2009-08-14 20:09:37 +00004168 if (Subtarget->isThumb2())
Evan Chenge88d5ce2009-07-02 07:28:31 +00004169 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4170 Offset, isInc, DAG);
Jim Grosbach764ab522009-08-11 15:33:49 +00004171 else
Evan Chenge88d5ce2009-07-02 07:28:31 +00004172 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
Evan Cheng04129572009-07-02 06:44:30 +00004173 Offset, isInc, DAG);
Evan Chenge88d5ce2009-07-02 07:28:31 +00004174 if (!isLegal)
4175 return false;
4176
4177 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4178 return true;
Evan Chenga8e29892007-01-19 07:51:42 +00004179}
4180
4181/// getPostIndexedAddressParts - returns true by value, base pointer and
4182/// offset pointer and addressing mode by reference if this node can be
4183/// combined with a load / store to form a post-indexed load / store.
4184bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +00004185 SDValue &Base,
4186 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +00004187 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +00004188 SelectionDAG &DAG) const {
Evan Chenge88d5ce2009-07-02 07:28:31 +00004189 if (Subtarget->isThumb1Only())
Evan Chenga8e29892007-01-19 07:51:42 +00004190 return false;
4191
Owen Andersone50ed302009-08-10 22:56:29 +00004192 EVT VT;
Dan Gohman475871a2008-07-27 21:46:04 +00004193 SDValue Ptr;
Evan Chenga8e29892007-01-19 07:51:42 +00004194 bool isSEXTLoad = false;
4195 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Dan Gohmanb625f2f2008-01-30 00:15:11 +00004196 VT = LD->getMemoryVT();
Evan Chenga8e29892007-01-19 07:51:42 +00004197 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4198 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Dan Gohmanb625f2f2008-01-30 00:15:11 +00004199 VT = ST->getMemoryVT();
Evan Chenga8e29892007-01-19 07:51:42 +00004200 } else
4201 return false;
4202
4203 bool isInc;
Evan Chenge88d5ce2009-07-02 07:28:31 +00004204 bool isLegal = false;
Evan Chenge6c835f2009-08-14 20:09:37 +00004205 if (Subtarget->isThumb2())
Evan Chenge88d5ce2009-07-02 07:28:31 +00004206 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
Evan Chenga8e29892007-01-19 07:51:42 +00004207 isInc, DAG);
Jim Grosbach764ab522009-08-11 15:33:49 +00004208 else
Evan Chenge88d5ce2009-07-02 07:28:31 +00004209 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4210 isInc, DAG);
4211 if (!isLegal)
4212 return false;
4213
4214 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4215 return true;
Evan Chenga8e29892007-01-19 07:51:42 +00004216}
4217
Dan Gohman475871a2008-07-27 21:46:04 +00004218void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +00004219 const APInt &Mask,
Bob Wilson2dc4f542009-03-20 22:42:55 +00004220 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00004221 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +00004222 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +00004223 unsigned Depth) const {
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00004224 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Chenga8e29892007-01-19 07:51:42 +00004225 switch (Op.getOpcode()) {
4226 default: break;
4227 case ARMISD::CMOV: {
4228 // Bits are known zero/one if known on the LHS and RHS.
Dan Gohmanea859be2007-06-22 14:59:07 +00004229 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
Evan Chenga8e29892007-01-19 07:51:42 +00004230 if (KnownZero == 0 && KnownOne == 0) return;
4231
Dan Gohmanfd29e0e2008-02-13 00:35:47 +00004232 APInt KnownZeroRHS, KnownOneRHS;
Dan Gohmanea859be2007-06-22 14:59:07 +00004233 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4234 KnownZeroRHS, KnownOneRHS, Depth+1);
Evan Chenga8e29892007-01-19 07:51:42 +00004235 KnownZero &= KnownZeroRHS;
4236 KnownOne &= KnownOneRHS;
4237 return;
4238 }
4239 }
4240}
4241
4242//===----------------------------------------------------------------------===//
4243// ARM Inline Assembly Support
4244//===----------------------------------------------------------------------===//
4245
4246/// getConstraintType - Given a constraint letter, return the type of
4247/// constraint it is for this target.
4248ARMTargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +00004249ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4250 if (Constraint.size() == 1) {
4251 switch (Constraint[0]) {
4252 default: break;
4253 case 'l': return C_RegisterClass;
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004254 case 'w': return C_RegisterClass;
Chris Lattner4234f572007-03-25 02:14:49 +00004255 }
Evan Chenga8e29892007-01-19 07:51:42 +00004256 }
Chris Lattner4234f572007-03-25 02:14:49 +00004257 return TargetLowering::getConstraintType(Constraint);
Evan Chenga8e29892007-01-19 07:51:42 +00004258}
4259
Bob Wilson2dc4f542009-03-20 22:42:55 +00004260std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +00004261ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +00004262 EVT VT) const {
Evan Chenga8e29892007-01-19 07:51:42 +00004263 if (Constraint.size() == 1) {
Jakob Stoklund Olesen09bf0032010-01-14 18:19:56 +00004264 // GCC ARM Constraint Letters
Evan Chenga8e29892007-01-19 07:51:42 +00004265 switch (Constraint[0]) {
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004266 case 'l':
Jakob Stoklund Olesen09bf0032010-01-14 18:19:56 +00004267 if (Subtarget->isThumb())
Jim Grosbach30eae3c2009-04-07 20:34:09 +00004268 return std::make_pair(0U, ARM::tGPRRegisterClass);
4269 else
4270 return std::make_pair(0U, ARM::GPRRegisterClass);
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004271 case 'r':
4272 return std::make_pair(0U, ARM::GPRRegisterClass);
4273 case 'w':
Owen Anderson825b72b2009-08-11 20:47:22 +00004274 if (VT == MVT::f32)
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004275 return std::make_pair(0U, ARM::SPRRegisterClass);
Bob Wilson5afffae2009-12-18 01:03:29 +00004276 if (VT.getSizeInBits() == 64)
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004277 return std::make_pair(0U, ARM::DPRRegisterClass);
Evan Chengd831cda2009-12-08 23:06:22 +00004278 if (VT.getSizeInBits() == 128)
4279 return std::make_pair(0U, ARM::QPRRegisterClass);
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004280 break;
Evan Chenga8e29892007-01-19 07:51:42 +00004281 }
4282 }
4283 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4284}
4285
4286std::vector<unsigned> ARMTargetLowering::
4287getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +00004288 EVT VT) const {
Evan Chenga8e29892007-01-19 07:51:42 +00004289 if (Constraint.size() != 1)
4290 return std::vector<unsigned>();
4291
4292 switch (Constraint[0]) { // GCC ARM Constraint Letters
4293 default: break;
4294 case 'l':
Jim Grosbach30eae3c2009-04-07 20:34:09 +00004295 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4296 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4297 0);
Evan Chenga8e29892007-01-19 07:51:42 +00004298 case 'r':
4299 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4300 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4301 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4302 ARM::R12, ARM::LR, 0);
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004303 case 'w':
Owen Anderson825b72b2009-08-11 20:47:22 +00004304 if (VT == MVT::f32)
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004305 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4306 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4307 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4308 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4309 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4310 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4311 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4312 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
Bob Wilson5afffae2009-12-18 01:03:29 +00004313 if (VT.getSizeInBits() == 64)
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004314 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4315 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4316 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4317 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
Evan Chengd831cda2009-12-08 23:06:22 +00004318 if (VT.getSizeInBits() == 128)
4319 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4320 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
Chris Lattnerc4e3f8e2007-04-02 17:24:08 +00004321 break;
Evan Chenga8e29892007-01-19 07:51:42 +00004322 }
4323
4324 return std::vector<unsigned>();
4325}
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004326
4327/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4328/// vector. If it is invalid, don't add anything to Ops.
4329void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4330 char Constraint,
4331 bool hasMemory,
4332 std::vector<SDValue>&Ops,
4333 SelectionDAG &DAG) const {
4334 SDValue Result(0, 0);
4335
4336 switch (Constraint) {
4337 default: break;
4338 case 'I': case 'J': case 'K': case 'L':
4339 case 'M': case 'N': case 'O':
4340 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4341 if (!C)
4342 return;
4343
4344 int64_t CVal64 = C->getSExtValue();
4345 int CVal = (int) CVal64;
4346 // None of these constraints allow values larger than 32 bits. Check
4347 // that the value fits in an int.
4348 if (CVal != CVal64)
4349 return;
4350
4351 switch (Constraint) {
4352 case 'I':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004353 if (Subtarget->isThumb1Only()) {
4354 // This must be a constant between 0 and 255, for ADD
4355 // immediates.
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004356 if (CVal >= 0 && CVal <= 255)
4357 break;
David Goodwinf1daf7d2009-07-08 23:10:31 +00004358 } else if (Subtarget->isThumb2()) {
4359 // A constant that can be used as an immediate value in a
4360 // data-processing instruction.
4361 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4362 break;
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004363 } else {
4364 // A constant that can be used as an immediate value in a
4365 // data-processing instruction.
4366 if (ARM_AM::getSOImmVal(CVal) != -1)
4367 break;
4368 }
4369 return;
4370
4371 case 'J':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004372 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004373 // This must be a constant between -255 and -1, for negated ADD
4374 // immediates. This can be used in GCC with an "n" modifier that
4375 // prints the negated value, for use with SUB instructions. It is
4376 // not useful otherwise but is implemented for compatibility.
4377 if (CVal >= -255 && CVal <= -1)
4378 break;
4379 } else {
4380 // This must be a constant between -4095 and 4095. It is not clear
4381 // what this constraint is intended for. Implemented for
4382 // compatibility with GCC.
4383 if (CVal >= -4095 && CVal <= 4095)
4384 break;
4385 }
4386 return;
4387
4388 case 'K':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004389 if (Subtarget->isThumb1Only()) {
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004390 // A 32-bit value where only one byte has a nonzero value. Exclude
4391 // zero to match GCC. This constraint is used by GCC internally for
4392 // constants that can be loaded with a move/shift combination.
4393 // It is not useful otherwise but is implemented for compatibility.
4394 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4395 break;
David Goodwinf1daf7d2009-07-08 23:10:31 +00004396 } else if (Subtarget->isThumb2()) {
4397 // A constant whose bitwise inverse can be used as an immediate
4398 // value in a data-processing instruction. This can be used in GCC
4399 // with a "B" modifier that prints the inverted value, for use with
4400 // BIC and MVN instructions. It is not useful otherwise but is
4401 // implemented for compatibility.
4402 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4403 break;
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004404 } else {
4405 // A constant whose bitwise inverse can be used as an immediate
4406 // value in a data-processing instruction. This can be used in GCC
4407 // with a "B" modifier that prints the inverted value, for use with
4408 // BIC and MVN instructions. It is not useful otherwise but is
4409 // implemented for compatibility.
4410 if (ARM_AM::getSOImmVal(~CVal) != -1)
4411 break;
4412 }
4413 return;
4414
4415 case 'L':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004416 if (Subtarget->isThumb1Only()) {
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004417 // This must be a constant between -7 and 7,
4418 // for 3-operand ADD/SUB immediate instructions.
4419 if (CVal >= -7 && CVal < 7)
4420 break;
David Goodwinf1daf7d2009-07-08 23:10:31 +00004421 } else if (Subtarget->isThumb2()) {
4422 // A constant whose negation can be used as an immediate value in a
4423 // data-processing instruction. This can be used in GCC with an "n"
4424 // modifier that prints the negated value, for use with SUB
4425 // instructions. It is not useful otherwise but is implemented for
4426 // compatibility.
4427 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4428 break;
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004429 } else {
4430 // A constant whose negation can be used as an immediate value in a
4431 // data-processing instruction. This can be used in GCC with an "n"
4432 // modifier that prints the negated value, for use with SUB
4433 // instructions. It is not useful otherwise but is implemented for
4434 // compatibility.
4435 if (ARM_AM::getSOImmVal(-CVal) != -1)
4436 break;
4437 }
4438 return;
4439
4440 case 'M':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004441 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004442 // This must be a multiple of 4 between 0 and 1020, for
4443 // ADD sp + immediate.
4444 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4445 break;
4446 } else {
4447 // A power of two or a constant between 0 and 32. This is used in
4448 // GCC for the shift amount on shifted register operands, but it is
4449 // useful in general for any shift amounts.
4450 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4451 break;
4452 }
4453 return;
4454
4455 case 'N':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004456 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004457 // This must be a constant between 0 and 31, for shift amounts.
4458 if (CVal >= 0 && CVal <= 31)
4459 break;
4460 }
4461 return;
4462
4463 case 'O':
David Goodwinf1daf7d2009-07-08 23:10:31 +00004464 if (Subtarget->isThumb()) { // FIXME thumb2
Bob Wilsonbf6396b2009-04-01 17:58:54 +00004465 // This must be a multiple of 4 between -508 and 508, for
4466 // ADD/SUB sp = sp + immediate.
4467 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4468 break;
4469 }
4470 return;
4471 }
4472 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4473 break;
4474 }
4475
4476 if (Result.getNode()) {
4477 Ops.push_back(Result);
4478 return;
4479 }
4480 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4481 Ops, DAG);
4482}
Anton Korobeynikov48e19352009-09-23 19:04:09 +00004483
4484bool
4485ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4486 // The ARM target isn't yet aware of offsets.
4487 return false;
4488}
Evan Cheng39382422009-10-28 01:44:26 +00004489
4490int ARM::getVFPf32Imm(const APFloat &FPImm) {
4491 APInt Imm = FPImm.bitcastToAPInt();
4492 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4493 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4494 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4495
4496 // We can handle 4 bits of mantissa.
4497 // mantissa = (16+UInt(e:f:g:h))/16.
4498 if (Mantissa & 0x7ffff)
4499 return -1;
4500 Mantissa >>= 19;
4501 if ((Mantissa & 0xf) != Mantissa)
4502 return -1;
4503
4504 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4505 if (Exp < -3 || Exp > 4)
4506 return -1;
4507 Exp = ((Exp+3) & 0x7) ^ 4;
4508
4509 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4510}
4511
4512int ARM::getVFPf64Imm(const APFloat &FPImm) {
4513 APInt Imm = FPImm.bitcastToAPInt();
4514 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4515 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4516 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4517
4518 // We can handle 4 bits of mantissa.
4519 // mantissa = (16+UInt(e:f:g:h))/16.
4520 if (Mantissa & 0xffffffffffffLL)
4521 return -1;
4522 Mantissa >>= 48;
4523 if ((Mantissa & 0xf) != Mantissa)
4524 return -1;
4525
4526 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4527 if (Exp < -3 || Exp > 4)
4528 return -1;
4529 Exp = ((Exp+3) & 0x7) ^ 4;
4530
4531 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4532}
4533
4534/// isFPImmLegal - Returns true if the target can instruction select the
4535/// specified FP immediate natively. If false, the legalizer will
4536/// materialize the FP immediate as a load from a constant pool.
4537bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4538 if (!Subtarget->hasVFP3())
4539 return false;
4540 if (VT == MVT::f32)
4541 return ARM::getVFPf32Imm(Imm) != -1;
4542 if (VT == MVT::f64)
4543 return ARM::getVFPf64Imm(Imm) != -1;
4544 return false;
4545}