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Evan Cheng3f32d652008-06-04 09:18:41 +00001//===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the live stack slot analysis pass. It is analogous to
11// live interval analysis except it's analyzing liveness of stack slots rather
12// than registers.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "livestacks"
17#include "llvm/CodeGen/LiveStackAnalysis.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/Target/TargetRegisterInfo.h"
20#include "llvm/Support/Debug.h"
21#include "llvm/ADT/Statistic.h"
22using namespace llvm;
23
24char LiveStacks::ID = 0;
25static RegisterPass<LiveStacks> X("livestacks", "Live Stack Slot Analysis");
26
27void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
Evan Chengef901c52008-09-22 22:26:15 +000028 AU.setPreservesAll();
Evan Chengbbeeb2a2008-09-22 20:58:04 +000029 MachineFunctionPass::getAnalysisUsage(AU);
Evan Cheng3f32d652008-06-04 09:18:41 +000030}
31
32void LiveStacks::releaseMemory() {
33 // Release VNInfo memroy regions after all VNInfo objects are dtor'd.
34 VNInfoAllocator.Reset();
Evan Chengc781a242009-05-03 18:32:42 +000035 S2IMap.clear();
36 S2RCMap.clear();
Evan Cheng3f32d652008-06-04 09:18:41 +000037}
38
39bool LiveStacks::runOnMachineFunction(MachineFunction &) {
40 // FIXME: No analysis is being done right now. We are relying on the
41 // register allocators to provide the information.
42 return false;
43}
44
45/// print - Implement the dump method.
Evan Chengc781a242009-05-03 18:32:42 +000046void LiveStacks::print(std::ostream &O, const Module*) const {
Evan Cheng3f32d652008-06-04 09:18:41 +000047 O << "********** INTERVALS **********\n";
48 for (const_iterator I = begin(), E = end(); I != E; ++I) {
49 I->second.print(O);
Evan Chengc781a242009-05-03 18:32:42 +000050 int Slot = I->first;
51 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
52 if (RC)
53 O << " [" << RC->getName() << "]\n";
54 else
55 O << " [Unknown]\n";
Evan Cheng3f32d652008-06-04 09:18:41 +000056 }
57}