Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 1 | //===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 10 | // This file contains the Sparc implementation of the TargetInstrInfo class. |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 14 | #ifndef SPARCINSTRUCTIONINFO_H |
| 15 | #define SPARCINSTRUCTIONINFO_H |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 16 | |
| 17 | #include "llvm/Target/TargetInstrInfo.h" |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 18 | #include "SparcRegisterInfo.h" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 19 | |
| 20 | namespace llvm { |
| 21 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 22 | /// SPII - This namespace holds all of the target specific flags that |
Brian Gaeke | 7d7ac63 | 2004-07-16 10:31:59 +0000 | [diff] [blame] | 23 | /// instruction info tracks. |
| 24 | /// |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 25 | namespace SPII { |
Brian Gaeke | 7d7ac63 | 2004-07-16 10:31:59 +0000 | [diff] [blame] | 26 | enum { |
| 27 | Pseudo = (1<<0), |
| 28 | Load = (1<<1), |
| 29 | Store = (1<<2), |
| 30 | DelaySlot = (1<<3) |
| 31 | }; |
Chris Lattner | d74ea2b | 2006-05-24 17:04:05 +0000 | [diff] [blame] | 32 | } |
Brian Gaeke | 7d7ac63 | 2004-07-16 10:31:59 +0000 | [diff] [blame] | 33 | |
Chris Lattner | 6410552 | 2008-01-01 01:03:04 +0000 | [diff] [blame] | 34 | class SparcInstrInfo : public TargetInstrInfoImpl { |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 35 | const SparcRegisterInfo RI; |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 36 | const SparcSubtarget& Subtarget; |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 37 | public: |
Dan Gohman | 950a4c4 | 2008-03-25 22:06:05 +0000 | [diff] [blame] | 38 | explicit SparcInstrInfo(SparcSubtarget &ST); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 39 | |
| 40 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
| 41 | /// such, whenever a client has an instance of instruction info, it should |
| 42 | /// always be able to get register info as well (through this method). |
| 43 | /// |
Dan Gohman | c9f5f3f | 2008-05-14 01:58:56 +0000 | [diff] [blame] | 44 | virtual const SparcRegisterInfo &getRegisterInfo() const { return RI; } |
Chris Lattner | 1d6dc97 | 2004-07-25 06:19:04 +0000 | [diff] [blame] | 45 | |
Evan Cheng | 04ee5a1 | 2009-01-20 19:12:24 +0000 | [diff] [blame] | 46 | /// Return true if the instruction is a register to register move and return |
| 47 | /// the source and dest operands and their sub-register indices by reference. |
Chris Lattner | 1d6dc97 | 2004-07-25 06:19:04 +0000 | [diff] [blame] | 48 | virtual bool isMoveInstr(const MachineInstr &MI, |
Evan Cheng | 04ee5a1 | 2009-01-20 19:12:24 +0000 | [diff] [blame] | 49 | unsigned &SrcReg, unsigned &DstReg, |
| 50 | unsigned &SrcSubIdx, unsigned &DstSubIdx) const; |
Chris Lattner | 5ccc722 | 2006-02-03 06:44:54 +0000 | [diff] [blame] | 51 | |
| 52 | /// isLoadFromStackSlot - If the specified machine instruction is a direct |
| 53 | /// load from a stack slot, return the virtual or physical register number of |
| 54 | /// the destination along with the FrameIndex of the loaded stack slot. If |
| 55 | /// not, return 0. This predicate must return 0 if the instruction has |
| 56 | /// any side effects other than loading from the stack slot. |
Dan Gohman | cbad42c | 2008-11-18 19:49:32 +0000 | [diff] [blame] | 57 | virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, |
| 58 | int &FrameIndex) const; |
Chris Lattner | 5ccc722 | 2006-02-03 06:44:54 +0000 | [diff] [blame] | 59 | |
| 60 | /// isStoreToStackSlot - If the specified machine instruction is a direct |
| 61 | /// store to a stack slot, return the virtual or physical register number of |
| 62 | /// the source reg along with the FrameIndex of the loaded stack slot. If |
| 63 | /// not, return 0. This predicate must return 0 if the instruction has |
| 64 | /// any side effects other than storing to the stack slot. |
Dan Gohman | cbad42c | 2008-11-18 19:49:32 +0000 | [diff] [blame] | 65 | virtual unsigned isStoreToStackSlot(const MachineInstr *MI, |
| 66 | int &FrameIndex) const; |
Chris Lattner | e87146a | 2006-10-24 16:39:19 +0000 | [diff] [blame] | 67 | |
| 68 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 69 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 70 | MachineBasicBlock *FBB, |
Stuart Hastings | 3bf9125 | 2010-06-17 22:43:56 +0000 | [diff] [blame] | 71 | const SmallVectorImpl<MachineOperand> &Cond, |
| 72 | DebugLoc DL) const; |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 73 | |
Jakob Stoklund Olesen | 8e18a1a | 2010-07-11 07:56:09 +0000 | [diff] [blame^] | 74 | virtual void copyPhysReg(MachineBasicBlock &MBB, |
| 75 | MachineBasicBlock::iterator I, DebugLoc DL, |
| 76 | unsigned DestReg, unsigned SrcReg, |
| 77 | bool KillSrc) const; |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 78 | |
| 79 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 80 | MachineBasicBlock::iterator MBBI, |
| 81 | unsigned SrcReg, bool isKill, int FrameIndex, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 82 | const TargetRegisterClass *RC, |
| 83 | const TargetRegisterInfo *TRI) const; |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 84 | |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 85 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 86 | MachineBasicBlock::iterator MBBI, |
| 87 | unsigned DestReg, int FrameIndex, |
Evan Cheng | 746ad69 | 2010-05-06 19:06:44 +0000 | [diff] [blame] | 88 | const TargetRegisterClass *RC, |
| 89 | const TargetRegisterInfo *TRI) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 90 | |
Dan Gohman | c54baa2 | 2008-12-03 18:43:12 +0000 | [diff] [blame] | 91 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 92 | MachineInstr* MI, |
| 93 | const SmallVectorImpl<unsigned> &Ops, |
| 94 | int FrameIndex) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 95 | |
Dan Gohman | c54baa2 | 2008-12-03 18:43:12 +0000 | [diff] [blame] | 96 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 97 | MachineInstr* MI, |
| 98 | const SmallVectorImpl<unsigned> &Ops, |
| 99 | MachineInstr* LoadMI) const { |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 100 | return 0; |
| 101 | } |
Chris Lattner | db486a6 | 2009-09-15 17:46:24 +0000 | [diff] [blame] | 102 | |
| 103 | unsigned getGlobalBaseReg(MachineFunction *MF) const; |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | } |
| 107 | |
| 108 | #endif |