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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8e23e815ad1136721acdfcce76975a37c8a2c036 / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: 4b0822d023e705a50c72c92e17f28897d44da51d [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]29#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]30#include "llvm/Support/MathExtras.h"
Nick Lewycky476b2422010-12-19 20:43:38 +0000[diff] [blame]31#include <cctype>
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]32using namespace llvm;
33
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]34namespace llvm {
35TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
36 bool isLocal = GV->hasLocalLinkage();
37 bool isDeclaration = GV->isDeclaration();
38 // FIXME: what should we do for protected and internal visibility?
39 // For variables, is internal different from hidden?
40 bool isHidden = GV->hasHiddenVisibility();
41
42 if (reloc == Reloc::PIC_) {
43 if (isLocal || isHidden)
44 return TLSModel::LocalDynamic;
45 else
46 return TLSModel::GeneralDynamic;
47 } else {
48 if (!isDeclaration || isHidden)
49 return TLSModel::LocalExec;
50 else
51 return TLSModel::InitialExec;
52 }
53}
54}
55
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]56/// InitLibcallNames - Set default libcall names.
57///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]58static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]59 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]60 Names[RTLIB::SHL_I32] = "__ashlsi3";
61 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]62 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]63 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]64 Names[RTLIB::SRL_I32] = "__lshrsi3";
65 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]66 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]67 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]68 Names[RTLIB::SRA_I32] = "__ashrsi3";
69 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]70 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]71 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]72 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]73 Names[RTLIB::MUL_I32] = "__mulsi3";
74 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]75 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]76 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]77 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]78 Names[RTLIB::SDIV_I32] = "__divsi3";
79 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]80 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]81 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]82 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]83 Names[RTLIB::UDIV_I32] = "__udivsi3";
84 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]85 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]86 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]87 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]88 Names[RTLIB::SREM_I32] = "__modsi3";
89 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]90 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]91 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]92 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]93 Names[RTLIB::UREM_I32] = "__umodsi3";
94 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]95 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng8e23e812011-04-01 00:42:02 +0000[diff] [blame^]96
97 // These are generally not available.
98 Names[RTLIB::SDIVREM_I8] = 0;
99 Names[RTLIB::SDIVREM_I16] = 0;
100 Names[RTLIB::SDIVREM_I32] = 0;
101 Names[RTLIB::SDIVREM_I64] = 0;
102 Names[RTLIB::SDIVREM_I128] = 0;
103 Names[RTLIB::UDIVREM_I8] = 0;
104 Names[RTLIB::UDIVREM_I16] = 0;
105 Names[RTLIB::UDIVREM_I32] = 0;
106 Names[RTLIB::UDIVREM_I64] = 0;
107 Names[RTLIB::UDIVREM_I128] = 0;
108
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::NEG_I32] = "__negsi2";
110 Names[RTLIB::NEG_I64] = "__negdi2";
111 Names[RTLIB::ADD_F32] = "__addsf3";
112 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]113 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]114 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]115 Names[RTLIB::SUB_F32] = "__subsf3";
116 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]117 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]118 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]119 Names[RTLIB::MUL_F32] = "__mulsf3";
120 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]121 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]122 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]123 Names[RTLIB::DIV_F32] = "__divsf3";
124 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]125 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]126 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]127 Names[RTLIB::REM_F32] = "fmodf";
128 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]129 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]130 Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]131 Names[RTLIB::POWI_F32] = "__powisf2";
132 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]133 Names[RTLIB::POWI_F80] = "__powixf2";
134 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]135 Names[RTLIB::SQRT_F32] = "sqrtf";
136 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]137 Names[RTLIB::SQRT_F80] = "sqrtl";
138 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]139 Names[RTLIB::LOG_F32] = "logf";
140 Names[RTLIB::LOG_F64] = "log";
141 Names[RTLIB::LOG_F80] = "logl";
142 Names[RTLIB::LOG_PPCF128] = "logl";
143 Names[RTLIB::LOG2_F32] = "log2f";
144 Names[RTLIB::LOG2_F64] = "log2";
145 Names[RTLIB::LOG2_F80] = "log2l";
146 Names[RTLIB::LOG2_PPCF128] = "log2l";
147 Names[RTLIB::LOG10_F32] = "log10f";
148 Names[RTLIB::LOG10_F64] = "log10";
149 Names[RTLIB::LOG10_F80] = "log10l";
150 Names[RTLIB::LOG10_PPCF128] = "log10l";
151 Names[RTLIB::EXP_F32] = "expf";
152 Names[RTLIB::EXP_F64] = "exp";
153 Names[RTLIB::EXP_F80] = "expl";
154 Names[RTLIB::EXP_PPCF128] = "expl";
155 Names[RTLIB::EXP2_F32] = "exp2f";
156 Names[RTLIB::EXP2_F64] = "exp2";
157 Names[RTLIB::EXP2_F80] = "exp2l";
158 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]159 Names[RTLIB::SIN_F32] = "sinf";
160 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]161 Names[RTLIB::SIN_F80] = "sinl";
162 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]163 Names[RTLIB::COS_F32] = "cosf";
164 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]165 Names[RTLIB::COS_F80] = "cosl";
166 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]167 Names[RTLIB::POW_F32] = "powf";
168 Names[RTLIB::POW_F64] = "pow";
169 Names[RTLIB::POW_F80] = "powl";
170 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]171 Names[RTLIB::CEIL_F32] = "ceilf";
172 Names[RTLIB::CEIL_F64] = "ceil";
173 Names[RTLIB::CEIL_F80] = "ceill";
174 Names[RTLIB::CEIL_PPCF128] = "ceill";
175 Names[RTLIB::TRUNC_F32] = "truncf";
176 Names[RTLIB::TRUNC_F64] = "trunc";
177 Names[RTLIB::TRUNC_F80] = "truncl";
178 Names[RTLIB::TRUNC_PPCF128] = "truncl";
179 Names[RTLIB::RINT_F32] = "rintf";
180 Names[RTLIB::RINT_F64] = "rint";
181 Names[RTLIB::RINT_F80] = "rintl";
182 Names[RTLIB::RINT_PPCF128] = "rintl";
183 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
184 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
185 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
186 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
187 Names[RTLIB::FLOOR_F32] = "floorf";
188 Names[RTLIB::FLOOR_F64] = "floor";
189 Names[RTLIB::FLOOR_F80] = "floorl";
190 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]191 Names[RTLIB::COPYSIGN_F32] = "copysignf";
192 Names[RTLIB::COPYSIGN_F64] = "copysign";
193 Names[RTLIB::COPYSIGN_F80] = "copysignl";
194 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]195 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]196 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
197 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]198 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]199 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
200 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
201 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
202 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
204 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]205 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
206 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]207 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]208 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
209 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]210 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
211 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]212 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]213 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]214 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]215 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]216 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]217 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]218 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
220 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]221 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
222 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]223 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]224 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
225 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]226 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
227 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]228 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]229 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
230 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]231 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]232 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]233 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]234 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]235 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
236 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]237 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
238 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]239 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
240 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]241 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
242 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]243 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
244 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
245 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
246 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]247 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
248 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]249 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
250 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]251 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
252 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]253 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
254 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
255 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
256 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
257 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
258 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]259 Names[RTLIB::OEQ_F32] = "__eqsf2";
260 Names[RTLIB::OEQ_F64] = "__eqdf2";
261 Names[RTLIB::UNE_F32] = "__nesf2";
262 Names[RTLIB::UNE_F64] = "__nedf2";
263 Names[RTLIB::OGE_F32] = "__gesf2";
264 Names[RTLIB::OGE_F64] = "__gedf2";
265 Names[RTLIB::OLT_F32] = "__ltsf2";
266 Names[RTLIB::OLT_F64] = "__ltdf2";
267 Names[RTLIB::OLE_F32] = "__lesf2";
268 Names[RTLIB::OLE_F64] = "__ledf2";
269 Names[RTLIB::OGT_F32] = "__gtsf2";
270 Names[RTLIB::OGT_F64] = "__gtdf2";
271 Names[RTLIB::UO_F32] = "__unordsf2";
272 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]273 Names[RTLIB::O_F32] = "__unordsf2";
274 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]275 Names[RTLIB::MEMCPY] = "memcpy";
276 Names[RTLIB::MEMMOVE] = "memmove";
277 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]278 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]279 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
280 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
281 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
282 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]283 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
284 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
285 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
286 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]287 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
288 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
289 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
290 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
291 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
292 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
293 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
294 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
295 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
296 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
297 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
298 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
299 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
300 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
301 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
302 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
303 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
304 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
305 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
306 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
307 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
308 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
309 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
310 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]311}
312
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]313/// InitLibcallCallingConvs - Set default libcall CallingConvs.
314///
315static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
316 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
317 CCs[i] = CallingConv::C;
318 }
319}
320
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]321/// getFPEXT - Return the FPEXT_*_* value for the given types, or
322/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]323RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]324 if (OpVT == MVT::f32) {
325 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]326 return FPEXT_F32_F64;
327 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]328
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]329 return UNKNOWN_LIBCALL;
330}
331
332/// getFPROUND - Return the FPROUND_*_* value for the given types, or
333/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]334RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]335 if (RetVT == MVT::f32) {
336 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]337 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]338 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]339 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]340 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]341 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]342 } else if (RetVT == MVT::f64) {
343 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]344 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]345 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]346 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]347 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]348
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]349 return UNKNOWN_LIBCALL;
350}
351
352/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
353/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]354RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]355 if (OpVT == MVT::f32) {
356 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]357 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]358 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]359 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]360 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]361 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]362 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]363 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]364 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]365 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]366 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]367 if (RetVT == MVT::i8)
368 return FPTOSINT_F64_I8;
369 if (RetVT == MVT::i16)
370 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]371 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]372 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]374 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]377 } else if (OpVT == MVT::f80) {
378 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]379 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]380 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]381 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]382 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]383 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]384 } else if (OpVT == MVT::ppcf128) {
385 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]386 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]387 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]388 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]389 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]390 return FPTOSINT_PPCF128_I128;
391 }
392 return UNKNOWN_LIBCALL;
393}
394
395/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
396/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]397RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]398 if (OpVT == MVT::f32) {
399 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]400 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]401 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]402 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]403 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]404 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]405 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]406 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]407 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]408 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]409 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]410 if (RetVT == MVT::i8)
411 return FPTOUINT_F64_I8;
412 if (RetVT == MVT::i16)
413 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]414 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]415 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]417 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]420 } else if (OpVT == MVT::f80) {
421 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]422 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]423 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]424 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]425 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]426 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]427 } else if (OpVT == MVT::ppcf128) {
428 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]429 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]430 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]431 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]432 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]433 return FPTOUINT_PPCF128_I128;
434 }
435 return UNKNOWN_LIBCALL;
436}
437
438/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
439/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]440RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]441 if (OpVT == MVT::i32) {
442 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]443 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]444 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]445 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]446 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]447 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]448 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]449 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 } else if (OpVT == MVT::i64) {
451 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]452 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]453 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]454 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]455 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]456 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]457 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]458 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]459 } else if (OpVT == MVT::i128) {
460 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]461 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]462 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]463 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]464 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]465 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]466 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return SINTTOFP_I128_PPCF128;
468 }
469 return UNKNOWN_LIBCALL;
470}
471
472/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
473/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]474RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]475 if (OpVT == MVT::i32) {
476 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]477 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]478 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]479 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]480 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]481 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]482 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]483 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]484 } else if (OpVT == MVT::i64) {
485 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]486 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]487 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]488 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]489 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]490 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]491 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]492 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]493 } else if (OpVT == MVT::i128) {
494 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]495 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]496 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]497 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]498 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]499 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]500 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]501 return UINTTOFP_I128_PPCF128;
502 }
503 return UNKNOWN_LIBCALL;
504}
505
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]506/// InitCmpLibcallCCs - Set default comparison libcall CC.
507///
508static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
509 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
510 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
511 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
512 CCs[RTLIB::UNE_F32] = ISD::SETNE;
513 CCs[RTLIB::UNE_F64] = ISD::SETNE;
514 CCs[RTLIB::OGE_F32] = ISD::SETGE;
515 CCs[RTLIB::OGE_F64] = ISD::SETGE;
516 CCs[RTLIB::OLT_F32] = ISD::SETLT;
517 CCs[RTLIB::OLT_F64] = ISD::SETLT;
518 CCs[RTLIB::OLE_F32] = ISD::SETLE;
519 CCs[RTLIB::OLE_F64] = ISD::SETLE;
520 CCs[RTLIB::OGT_F32] = ISD::SETGT;
521 CCs[RTLIB::OGT_F64] = ISD::SETGT;
522 CCs[RTLIB::UO_F32] = ISD::SETNE;
523 CCs[RTLIB::UO_F64] = ISD::SETNE;
524 CCs[RTLIB::O_F32] = ISD::SETEQ;
525 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]526}
527
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]528/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]529TargetLowering::TargetLowering(const TargetMachine &tm,
530 const TargetLoweringObjectFile *tlof)
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]531 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]532 // All operations default to being supported.
533 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]534 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]535 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]536 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]537 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]538
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]539 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]540 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]541 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]542 for (unsigned IM = (unsigned)ISD::PRE_INC;
543 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]544 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
545 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]546 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]547
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]548 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]549 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]551 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]552
553 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]554 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]555
556 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]557 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]558 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]559 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
560 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
561 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]562
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]563 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]564 setOperationAction(ISD::FLOG , MVT::f64, Expand);
565 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
566 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
567 setOperationAction(ISD::FEXP , MVT::f64, Expand);
568 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
569 setOperationAction(ISD::FLOG , MVT::f32, Expand);
570 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
571 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
572 setOperationAction(ISD::FEXP , MVT::f32, Expand);
573 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]574
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]575 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]576 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]577
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]578 IsLittleEndian = TD->isLittleEndian();
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]579 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]580 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]581 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]582 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng05219282011-01-06 06:52:41 +0000[diff] [blame]583 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
584 = maxStoresPerMemmoveOptSize = 4;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]585 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]586 UseUnderscoreSetJmp = false;
587 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]588 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]589 IntDivIsCheap = false;
590 Pow2DivIsCheap = false;
Chris Lattnerde189be2010-11-30 18:12:52 +0000[diff] [blame]591 JumpIsExpensive = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]592 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]593 ExceptionPointerRegister = 0;
594 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]595 BooleanContents = UndefinedBooleanContent;
Evan Cheng211ffa12010-05-19 20:19:50 +0000[diff] [blame]596 SchedPreferenceInfo = Sched::Latency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]597 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]598 JumpBufAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]599 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]600 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]601 ShouldFoldAtomicFences = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]602
603 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]604 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]605 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]606}
607
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]608TargetLowering::~TargetLowering() {
609 delete &TLOF;
610}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]611
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]612MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
613 return MVT::getIntegerVT(8*TD->getPointerSize());
614}
615
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]616/// canOpTrap - Returns true if the operation can trap for the value type.
617/// VT must be a legal type.
618bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
619 assert(isTypeLegal(VT));
620 switch (Op) {
621 default:
622 return false;
623 case ISD::FDIV:
624 case ISD::FREM:
625 case ISD::SDIV:
626 case ISD::UDIV:
627 case ISD::SREM:
628 case ISD::UREM:
629 return true;
630 }
631}
632
633
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]634static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]635 unsigned &NumIntermediates,
636 EVT &RegisterVT,
637 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]638 // Figure out the right, legal destination reg to copy into.
639 unsigned NumElts = VT.getVectorNumElements();
640 MVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]641
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]642 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]643
644 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]645 // could break down into LHS/RHS like LegalizeDAG does.
646 if (!isPowerOf2_32(NumElts)) {
647 NumVectorRegs = NumElts;
648 NumElts = 1;
649 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]650
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]651 // Divide the input until we get to a supported size. This will always
652 // end with a scalar if the target doesn't support vectors.
653 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
654 NumElts >>= 1;
655 NumVectorRegs <<= 1;
656 }
657
658 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]659
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]660 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
661 if (!TLI->isTypeLegal(NewVT))
662 NewVT = EltTy;
663 IntermediateVT = NewVT;
664
665 EVT DestVT = TLI->getRegisterType(NewVT);
666 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]667 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]668 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]669
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]670 // Otherwise, promotion or legal types use the same number of registers as
671 // the vector decimated to the appropriate level.
672 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]673}
674
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]675/// isLegalRC - Return true if the value types that can be represented by the
676/// specified register class are all legal.
677bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
678 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
679 I != E; ++I) {
680 if (isTypeLegal(*I))
681 return true;
682 }
683 return false;
684}
685
686/// hasLegalSuperRegRegClasses - Return true if the specified register class
687/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]688bool
689TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]690 if (*RC->superregclasses_begin() == 0)
691 return false;
692 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
693 E = RC->superregclasses_end(); I != E; ++I) {
694 const TargetRegisterClass *RRC = *I;
695 if (isLegalRC(RRC))
696 return true;
697 }
698 return false;
699}
700
701/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]702/// of the register class for the specified type and its associated "cost".
703std::pair<const TargetRegisterClass*, uint8_t>
704TargetLowering::findRepresentativeClass(EVT VT) const {
705 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
706 if (!RC)
707 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]708 const TargetRegisterClass *BestRC = RC;
709 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
710 E = RC->superregclasses_end(); I != E; ++I) {
711 const TargetRegisterClass *RRC = *I;
712 if (RRC->isASubClass() || !isLegalRC(RRC))
713 continue;
714 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]715 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]716 BestRC = RRC;
717 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]718 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]719}
720
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]721
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]722/// computeRegisterProperties - Once all of the register classes are added,
723/// this allows us to compute derived properties we expose.
724void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]725 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]726 "Too many value types for ValueTypeActions to hold!");
727
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]728 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]729 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]730 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]731 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]732 }
733 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]734 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]735
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]736 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]737 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]738 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]739 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]740
741 // Every integer value type larger than this largest register takes twice as
742 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]743 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]744 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
745 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]746 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]747 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]748 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
749 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]750 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]751 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]752
753 // Inspect all of the ValueType's smaller than the largest integer
754 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]755 unsigned LegalIntReg = LargestIntReg;
756 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]757 IntReg >= (unsigned)MVT::i1; --IntReg) {
758 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]759 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]760 LegalIntReg = IntReg;
761 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]762 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]763 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]764 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]765 }
766 }
767
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]768 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]769 if (!isTypeLegal(MVT::ppcf128)) {
770 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
771 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
772 TransformToType[MVT::ppcf128] = MVT::f64;
773 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]774 }
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]775
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]776 // Decide how to handle f64. If the target does not have native f64 support,
777 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]778 if (!isTypeLegal(MVT::f64)) {
779 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
780 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
781 TransformToType[MVT::f64] = MVT::i64;
782 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]783 }
784
785 // Decide how to handle f32. If the target does not have native support for
786 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]787 if (!isTypeLegal(MVT::f32)) {
788 if (isTypeLegal(MVT::f64)) {
789 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
790 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
791 TransformToType[MVT::f32] = MVT::f64;
792 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]793 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]794 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
795 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
796 TransformToType[MVT::f32] = MVT::i32;
797 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]798 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]799 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]800
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]801 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]802 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
803 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]804 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]805 if (isTypeLegal(VT)) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]806
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]807 // Determine if there is a legal wider type. If so, we should promote to
808 // that wider vector type.
809 EVT EltVT = VT.getVectorElementType();
810 unsigned NElts = VT.getVectorNumElements();
811 if (NElts != 1) {
812 bool IsLegalWiderType = false;
813 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
814 EVT SVT = (MVT::SimpleValueType)nVT;
815 if (SVT.getVectorElementType() == EltVT &&
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]816 SVT.getVectorNumElements() > NElts &&
Dale Johannesene93d99c2010-10-20 21:32:10 +0000[diff] [blame]817 isTypeLegal(SVT)) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]818 TransformToType[i] = SVT;
819 RegisterTypeForVT[i] = SVT;
820 NumRegistersForVT[i] = 1;
821 ValueTypeActions.setTypeAction(VT, Promote);
822 IsLegalWiderType = true;
823 break;
824 }
825 }
826 if (IsLegalWiderType) continue;
827 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]828
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]829 MVT IntermediateVT;
830 EVT RegisterVT;
831 unsigned NumIntermediates;
832 NumRegistersForVT[i] =
833 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
834 RegisterVT, this);
835 RegisterTypeForVT[i] = RegisterVT;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]836
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]837 EVT NVT = VT.getPow2VectorType();
838 if (NVT == VT) {
839 // Type is already a power of 2. The default action is to split.
840 TransformToType[i] = MVT::Other;
841 ValueTypeActions.setTypeAction(VT, Expand);
842 } else {
843 TransformToType[i] = NVT;
844 ValueTypeActions.setTypeAction(VT, Promote);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]845 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]846 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]847
848 // Determine the 'representative' register class for each value type.
849 // An representative register class is the largest (meaning one which is
850 // not a sub-register class / subreg register class) legal register class for
851 // a group of value types. For example, on i386, i8, i16, and i32
852 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]853 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]854 const TargetRegisterClass* RRC;
855 uint8_t Cost;
856 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
857 RepRegClassForVT[i] = RRC;
858 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]859 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]860}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]861
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]862const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
863 return NULL;
864}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]865
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]866
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]867MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]868 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]869}
870
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]871MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
872 return MVT::i32; // return the default value
873}
874
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]875/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]876/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
877/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
878/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]879///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]880/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]881/// register. It also returns the VT and quantity of the intermediate values
882/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]883///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]884unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]885 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]886 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]887 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]888 unsigned NumElts = VT.getVectorNumElements();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]889
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]890 // If there is a wider vector type with the same element type as this one,
891 // we should widen to that legal vector type. This handles things like
892 // <2 x float> -> <4 x float>.
Chris Lattneraafe6262010-08-25 23:00:45 +0000[diff] [blame]893 if (NumElts != 1 && getTypeAction(VT) == Promote) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]894 RegisterVT = getTypeToTransformTo(Context, VT);
895 if (isTypeLegal(RegisterVT)) {
896 IntermediateVT = RegisterVT;
897 NumIntermediates = 1;
898 return 1;
899 }
900 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]901
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]902 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]903 EVT EltTy = VT.getVectorElementType();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]904
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]905 unsigned NumVectorRegs = 1;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]906
907 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]908 // could break down into LHS/RHS like LegalizeDAG does.
909 if (!isPowerOf2_32(NumElts)) {
910 NumVectorRegs = NumElts;
911 NumElts = 1;
912 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]913
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]914 // Divide the input until we get to a supported size. This will always
915 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]916 while (NumElts > 1 && !isTypeLegal(
917 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]918 NumElts >>= 1;
919 NumVectorRegs <<= 1;
920 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]921
922 NumIntermediates = NumVectorRegs;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]923
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]924 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]925 if (!isTypeLegal(NewVT))
926 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]927 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]928
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]929 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]930 RegisterVT = DestVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]931 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]932 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]933
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]934 // Otherwise, promotion or legal types use the same number of registers as
935 // the vector decimated to the appropriate level.
936 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]937}
938
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]939/// Get the EVTs and ArgFlags collections that represent the legalized return
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]940/// type of the given function. This does not require a DAG or a return value,
941/// and is suitable for use before any DAGs for the function are constructed.
942/// TODO: Move this out of TargetLowering.cpp.
943void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
944 SmallVectorImpl<ISD::OutputArg> &Outs,
945 const TargetLowering &TLI,
946 SmallVectorImpl<uint64_t> *Offsets) {
947 SmallVector<EVT, 4> ValueVTs;
948 ComputeValueVTs(TLI, ReturnType, ValueVTs);
949 unsigned NumValues = ValueVTs.size();
950 if (NumValues == 0) return;
951 unsigned Offset = 0;
952
953 for (unsigned j = 0, f = NumValues; j != f; ++j) {
954 EVT VT = ValueVTs[j];
955 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
956
957 if (attr & Attribute::SExt)
958 ExtendKind = ISD::SIGN_EXTEND;
959 else if (attr & Attribute::ZExt)
960 ExtendKind = ISD::ZERO_EXTEND;
961
962 // FIXME: C calling convention requires the return type to be promoted to
963 // at least 32-bit. But this is not necessary for non-C calling
964 // conventions. The frontend should mark functions whose return values
965 // require promoting with signext or zeroext attributes.
966 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
967 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
968 if (VT.bitsLT(MinVT))
969 VT = MinVT;
970 }
971
972 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
973 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
974 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
975 PartVT.getTypeForEVT(ReturnType->getContext()));
976
977 // 'inreg' on function refers to return value
978 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
979 if (attr & Attribute::InReg)
980 Flags.setInReg();
981
982 // Propagate extension type if any
983 if (attr & Attribute::SExt)
984 Flags.setSExt();
985 else if (attr & Attribute::ZExt)
986 Flags.setZExt();
987
988 for (unsigned i = 0; i < NumParts; ++i) {
989 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
990 if (Offsets) {
991 Offsets->push_back(Offset);
992 Offset += PartSize;
993 }
994 }
995 }
996}
997
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]998/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]999/// function arguments in the caller parameter area. This is the actual
1000/// alignment, not its logarithm.
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1001unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]1002 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]1003}
1004
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1005/// getJumpTableEncoding - Return the entry encoding for a jump table in the
1006/// current function. The returned value is a member of the
1007/// MachineJumpTableInfo::JTEntryKind enum.
1008unsigned TargetLowering::getJumpTableEncoding() const {
1009 // In non-pic modes, just use the address of a block.
1010 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1011 return MachineJumpTableInfo::EK_BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1012
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1013 // In PIC mode, if the target supports a GPRel32 directive, use it.
1014 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1015 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1016
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]1017 // Otherwise, use a label difference.
1018 return MachineJumpTableInfo::EK_LabelDifference32;
1019}
1020
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1021SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1022 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1023 // If our PIC model is GP relative, use the global offset table as the base.
1024 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1025 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1026 return Table;
1027}
1028
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1029/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1030/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1031/// MCExpr.
1032const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1033TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1034 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1035 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1036 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1037}
1038
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1039bool
1040TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1041 // Assume that everything is safe in static mode.
1042 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1043 return true;
1044
1045 // In dynamic-no-pic mode, assume that known defined values are safe.
1046 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1047 GA &&
1048 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1049 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1050 return true;
1051
1052 // Otherwise assume nothing is safe.
1053 return false;
1054}
1055
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1056//===----------------------------------------------------------------------===//
1057// Optimization Methods
1058//===----------------------------------------------------------------------===//
1059
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1060/// ShrinkDemandedConstant - Check to see if the specified operand of the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1061/// specified instruction is a constant integer. If so, check to see if there
1062/// are any bits set in the constant that are not demanded. If so, shrink the
1063/// constant and return true.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1064bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1065 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1066 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1067
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1068 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1069 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1070 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1071 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1072 case ISD::AND:
1073 case ISD::OR: {
1074 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1075 if (!C) return false;
1076
1077 if (Op.getOpcode() == ISD::XOR &&
1078 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1079 return false;
1080
1081 // if we can expand it to have all bits set, do it
1082 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1083 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1084 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1085 DAG.getConstant(Demanded &
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1086 C->getAPIntValue(),
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1087 VT));
1088 return CombineTo(Op, New);
1089 }
1090
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1091 break;
1092 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1093 }
1094
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1095 return false;
1096}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1097
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1098/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1099/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1100/// cast, but it could be generalized for targets with other types of
1101/// implicit widening casts.
1102bool
1103TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1104 unsigned BitWidth,
1105 const APInt &Demanded,
1106 DebugLoc dl) {
1107 assert(Op.getNumOperands() == 2 &&
1108 "ShrinkDemandedOp only supports binary operators!");
1109 assert(Op.getNode()->getNumValues() == 1 &&
1110 "ShrinkDemandedOp only supports nodes with one result!");
1111
1112 // Don't do this if the node has another user, which may require the
1113 // full value.
1114 if (!Op.getNode()->hasOneUse())
1115 return false;
1116
1117 // Search for the smallest integer type with free casts to and from
1118 // Op's type. For expedience, just check power-of-2 integer types.
1119 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1120 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1121 if (!isPowerOf2_32(SmallVTBits))
1122 SmallVTBits = NextPowerOf2(SmallVTBits);
1123 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1124 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1125 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1126 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1127 // We found a type with free casts.
1128 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1129 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1130 Op.getNode()->getOperand(0)),
1131 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1132 Op.getNode()->getOperand(1)));
1133 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1134 return CombineTo(Op, Z);
1135 }
1136 }
1137 return false;
1138}
1139
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1140/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1141/// DemandedMask bits of the result of Op are ever used downstream. If we can
1142/// use this information to simplify Op, create a new simplified DAG node and
1143/// return true, returning the original and new nodes in Old and New. Otherwise,
1144/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1145/// the expression (used to simplify the caller). The KnownZero/One bits may
1146/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1147bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1148 const APInt &DemandedMask,
1149 APInt &KnownZero,
1150 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1151 TargetLoweringOpt &TLO,
1152 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1153 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1154 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1155 "Mask size mismatches value type size!");
1156 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1157 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1158
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1159 // Don't know anything.
1160 KnownZero = KnownOne = APInt(BitWidth, 0);
1161
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1162 // Other users may use these bits.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1163 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1164 if (Depth != 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1165 // If not at the root, Just compute the KnownZero/KnownOne bits to
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1166 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1167 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1168 return false;
1169 }
1170 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1171 // just set the NewMask to all bits.
1172 NewMask = APInt::getAllOnesValue(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1173 } else if (DemandedMask == 0) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1174 // Not demanding any bits from Op.
1175 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1176 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1177 return false;
1178 } else if (Depth == 6) { // Limit search depth.
1179 return false;
1180 }
1181
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1182 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1183 switch (Op.getOpcode()) {
1184 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1185 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1186 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1187 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1188 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1189 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1190 // If the RHS is a constant, check to see if the LHS would be zero without
1191 // using the bits from the RHS. Below, we use knowledge about the RHS to
1192 // simplify the LHS, here we're using information from the LHS to simplify
1193 // the RHS.
1194 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1195 APInt LHSZero, LHSOne;
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1196 // Do not increment Depth here; that can cause an infinite loop.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1197 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dale Johannesen97fd9a52011-01-10 21:53:07 +0000[diff] [blame]1198 LHSZero, LHSOne, Depth);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1199 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1200 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1201 return TLO.CombineTo(Op, Op.getOperand(0));
1202 // If any of the set bits in the RHS are known zero on the LHS, shrink
1203 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1204 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1205 return true;
1206 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1207
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1208 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1209 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1210 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1211 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1212 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1213 KnownZero2, KnownOne2, TLO, Depth+1))
1214 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1215 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1216
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1217 // If all of the demanded bits are known one on one side, return the other.
1218 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1219 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1220 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1221 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222 return TLO.CombineTo(Op, Op.getOperand(1));
1223 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1224 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1225 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1226 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1227 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1228 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1229 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1230 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1231 return true;
1232
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1233 // Output known-1 bits are only known if set in both the LHS & RHS.
1234 KnownOne &= KnownOne2;
1235 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1236 KnownZero |= KnownZero2;
1237 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1238 case ISD::OR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1239 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1240 KnownOne, TLO, Depth+1))
1241 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1242 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1243 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1244 KnownZero2, KnownOne2, TLO, Depth+1))
1245 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1246 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1247
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1248 // If all of the demanded bits are known zero on one side, return the other.
1249 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1250 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1251 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1252 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1253 return TLO.CombineTo(Op, Op.getOperand(1));
1254 // If all of the potentially set bits on one side are known to be set on
1255 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1256 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1257 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1258 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1259 return TLO.CombineTo(Op, Op.getOperand(1));
1260 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1261 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1262 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1263 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1264 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1265 return true;
1266
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1267 // Output known-0 bits are only known if clear in both the LHS & RHS.
1268 KnownZero &= KnownZero2;
1269 // Output known-1 are known to be set if set in either the LHS | RHS.
1270 KnownOne |= KnownOne2;
1271 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1272 case ISD::XOR:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1273 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1274 KnownOne, TLO, Depth+1))
1275 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1276 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1277 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1278 KnownOne2, TLO, Depth+1))
1279 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1280 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1281
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1282 // If all of the demanded bits are known zero on one side, return the other.
1283 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1284 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1285 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1286 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1287 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1288 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1289 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1290 return true;
1291
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1292 // If all of the unknown bits are known to be zero on one side or the other
1293 // (but not both) turn this into an *inclusive* or.
1294 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1295 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1296 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1297 Op.getOperand(0),
1298 Op.getOperand(1)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1299
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1300 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1301 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1302 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1303 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1304
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1305 // If all of the demanded bits on one side are known, and all of the set
1306 // bits on that side are also known to be set on the other side, turn this
1307 // into an AND, as we know the bits will be cleared.
1308 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1309 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1310 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1311 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1312 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1313 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1314 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1315 }
1316 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1317
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1318 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1319 // for XOR, we prefer to force bits to 1 if they will make a -1.
1320 // if we can't force bits, try to shrink constant
1321 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1322 APInt Expanded = C->getAPIntValue() | (~NewMask);
1323 // if we can expand it to have all bits set, do it
1324 if (Expanded.isAllOnesValue()) {
1325 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1326 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1327 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1328 TLO.DAG.getConstant(Expanded, VT));
1329 return TLO.CombineTo(Op, New);
1330 }
1331 // if it already has all the bits set, nothing to change
1332 // but don't shrink either!
1333 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1334 return true;
1335 }
1336 }
1337
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1338 KnownZero = KnownZeroOut;
1339 KnownOne = KnownOneOut;
1340 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1341 case ISD::SELECT:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1342 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1343 KnownOne, TLO, Depth+1))
1344 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1345 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1346 KnownOne2, TLO, Depth+1))
1347 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1348 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1349 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1350
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1351 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1352 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1353 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1354
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1355 // Only known if known in both the LHS and RHS.
1356 KnownOne &= KnownOne2;
1357 KnownZero &= KnownZero2;
1358 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1359 case ISD::SELECT_CC:
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1360 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1361 KnownOne, TLO, Depth+1))
1362 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1363 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1364 KnownOne2, TLO, Depth+1))
1365 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1366 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1367 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1368
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1369 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1370 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1371 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1372
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1373 // Only known if known in both the LHS and RHS.
1374 KnownOne &= KnownOne2;
1375 KnownZero &= KnownZero2;
1376 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1377 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1378 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1379 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1380 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1381
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1382 // If the shift count is an invalid immediate, don't do anything.
1383 if (ShAmt >= BitWidth)
1384 break;
1385
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1386 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1387 // single shift. We can do this if the bottom bits (which are shifted
1388 // out) are never demanded.
1389 if (InOp.getOpcode() == ISD::SRL &&
1390 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1391 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1392 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1393 unsigned Opc = ISD::SHL;
1394 int Diff = ShAmt-C1;
1395 if (Diff < 0) {
1396 Diff = -Diff;
1397 Opc = ISD::SRL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1398 }
1399
1400 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1401 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1402 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1403 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1404 InOp.getOperand(0), NewSA));
1405 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1406 }
1407
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1408 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1409 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1410 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1411
1412 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1413 // are not demanded. This will likely allow the anyext to be folded away.
1414 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1415 SDValue InnerOp = InOp.getNode()->getOperand(0);
1416 EVT InnerVT = InnerOp.getValueType();
1417 if ((APInt::getHighBitsSet(BitWidth,
1418 BitWidth - InnerVT.getSizeInBits()) &
1419 DemandedMask) == 0 &&
1420 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]1421 EVT ShTy = getShiftAmountTy(InnerVT);
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1422 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1423 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1424 SDValue NarrowShl =
1425 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1426 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1427 return
1428 TLO.CombineTo(Op,
1429 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1430 NarrowShl));
1431 }
1432 }
1433
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1434 KnownZero <<= SA->getZExtValue();
1435 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1436 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1437 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1438 }
1439 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1440 case ISD::SRL:
1441 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1442 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1443 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1444 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1445 SDValue InOp = Op.getOperand(0);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1446
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1447 // If the shift count is an invalid immediate, don't do anything.
1448 if (ShAmt >= BitWidth)
1449 break;
1450
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1451 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1452 // single shift. We can do this if the top bits (which are shifted out)
1453 // are never demanded.
1454 if (InOp.getOpcode() == ISD::SHL &&
1455 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1456 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1457 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1458 unsigned Opc = ISD::SRL;
1459 int Diff = ShAmt-C1;
1460 if (Diff < 0) {
1461 Diff = -Diff;
1462 Opc = ISD::SHL;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1463 }
1464
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1465 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1466 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1467 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1468 InOp.getOperand(0), NewSA));
1469 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1470 }
1471
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1472 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1473 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1474 KnownZero, KnownOne, TLO, Depth+1))
1475 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1476 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1477 KnownZero = KnownZero.lshr(ShAmt);
1478 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1479
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1480 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1481 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1482 }
1483 break;
1484 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1485 // If this is an arithmetic shift right and only the low-bit is set, we can
1486 // always convert this into a logical shr, even if the shift amount is
1487 // variable. The low bit of the shift cannot be an input sign bit unless
1488 // the shift amount is >= the size of the datatype, which is undefined.
1489 if (DemandedMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1490 return TLO.CombineTo(Op,
1491 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1492 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1493
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1494 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1495 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1496 unsigned ShAmt = SA->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1497
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1498 // If the shift count is an invalid immediate, don't do anything.
1499 if (ShAmt >= BitWidth)
1500 break;
1501
1502 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1503
1504 // If any of the demanded bits are produced by the sign extension, we also
1505 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1506 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1507 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1508 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1509
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1510 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1511 KnownZero, KnownOne, TLO, Depth+1))
1512 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1513 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1514 KnownZero = KnownZero.lshr(ShAmt);
1515 KnownOne = KnownOne.lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1516
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1517 // Handle the sign bit, adjusted to where it is now in the mask.
1518 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1519
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1520 // If the input sign bit is known to be zero, or if none of the top bits
1521 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1522 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1523 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1524 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1525 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1526 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1527 KnownOne |= HighBits;
1528 }
1529 }
1530 break;
1531 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1532 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1533
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1534 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1535 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1536 APInt NewBits =
1537 APInt::getHighBitsSet(BitWidth,
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1538 BitWidth - EVT.getScalarType().getSizeInBits());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1539
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1540 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1541 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1542 return TLO.CombineTo(Op, Op.getOperand(0));
1543
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1544 APInt InSignBit =
1545 APInt::getSignBit(EVT.getScalarType().getSizeInBits()).zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1546 APInt InputDemandedBits =
1547 APInt::getLowBitsSet(BitWidth,
1548 EVT.getScalarType().getSizeInBits()) &
1549 NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1550
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1551 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1552 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1553 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1554
1555 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1556 KnownZero, KnownOne, TLO, Depth+1))
1557 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1558 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1559
1560 // If the sign bit of the input is known set or clear, then we know the
1561 // top bits of the result.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1562
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1563 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1564 if (KnownZero.intersects(InSignBit))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1565 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1566 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1567
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1568 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1569 KnownOne |= NewBits;
1570 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1571 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1572 KnownZero &= ~NewBits;
1573 KnownOne &= ~NewBits;
1574 }
1575 break;
1576 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1577 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1578 unsigned OperandBitWidth =
1579 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1580 APInt InMask = NewMask.trunc(OperandBitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1581
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1582 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1583 APInt NewBits =
1584 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1585 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1586 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1587 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1588 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1589
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1590 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1591 KnownZero, KnownOne, TLO, Depth+1))
1592 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1593 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1594 KnownZero = KnownZero.zext(BitWidth);
1595 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1596 KnownZero |= NewBits;
1597 break;
1598 }
1599 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1600 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1601 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1602 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1603 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1604 APInt NewBits = ~InMask & NewMask;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1605
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1606 // If none of the top bits are demanded, convert this into an any_extend.
1607 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1608 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1609 Op.getValueType(),
1610 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1611
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1612 // Since some of the sign extended bits are demanded, we know that the sign
1613 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1614 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1615 InDemandedBits |= InSignBit;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1616 InDemandedBits = InDemandedBits.trunc(InBits);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1617
1618 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1619 KnownOne, TLO, Depth+1))
1620 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1621 KnownZero = KnownZero.zext(BitWidth);
1622 KnownOne = KnownOne.zext(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1623
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1624 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1625 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1626 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1627 Op.getValueType(),
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1628 Op.getOperand(0)));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1629
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1630 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1631 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1632 KnownOne |= NewBits;
1633 KnownZero &= ~NewBits;
1634 } else { // Otherwise, top bits aren't known.
1635 KnownOne &= ~NewBits;
1636 KnownZero &= ~NewBits;
1637 }
1638 break;
1639 }
1640 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1641 unsigned OperandBitWidth =
1642 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1643 APInt InMask = NewMask.trunc(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1644 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1645 KnownZero, KnownOne, TLO, Depth+1))
1646 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1647 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1648 KnownZero = KnownZero.zext(BitWidth);
1649 KnownOne = KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1650 break;
1651 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1652 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1653 // Simplify the input, using demanded bit information, and compute the known
1654 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1655 unsigned OperandBitWidth =
1656 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1657 APInt TruncMask = NewMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1658 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1659 KnownZero, KnownOne, TLO, Depth+1))
1660 return true;
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1661 KnownZero = KnownZero.trunc(BitWidth);
1662 KnownOne = KnownOne.trunc(BitWidth);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1663
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1664 // If the input is only used by this truncate, see if we can shrink it based
1665 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1666 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1667 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1668 switch (In.getOpcode()) {
1669 default: break;
1670 case ISD::SRL:
1671 // Shrink SRL by a constant if none of the high bits shifted in are
1672 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1673 if (TLO.LegalTypes() &&
1674 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1675 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1676 // undesirable.
1677 break;
1678 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1679 if (!ShAmt)
1680 break;
1681 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1682 OperandBitWidth - BitWidth);
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]1683 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1684
1685 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1686 // None of the shifted in bits are needed. Add a truncate of the
1687 // shift input, then shift it.
1688 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1689 Op.getValueType(),
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1690 In.getOperand(0));
1691 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1692 Op.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1693 NewTrunc,
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1694 In.getOperand(1)));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1695 }
1696 break;
1697 }
1698 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1699
1700 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1701 break;
1702 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1703 case ISD::AssertZext: {
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1704 // Demand all the bits of the input that are demanded in the output.
1705 // The low bits are obvious; the high bits are demanded because we're
1706 // asserting that they're zero here.
1707 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1708 KnownZero, KnownOne, TLO, Depth+1))
1709 return true;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1710 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1711
1712 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1713 APInt InMask = APInt::getLowBitsSet(BitWidth,
1714 VT.getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1715 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1716 break;
1717 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1718 case ISD::BITCAST:
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1719#if 0
1720 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1721 // is demanded, turn this into a FGETSIGN.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1722 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1723 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1724 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1725 // Only do this xform if FGETSIGN is valid or if before legalize.
1726 if (!TLO.AfterLegalize ||
1727 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1728 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1729 // place. We expect the SHL to be eliminated by other optimizations.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1730 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1731 Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1732 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1733 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1734 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1735 Sign, ShAmt));
1736 }
1737 }
1738#endif
1739 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1740 case ISD::ADD:
1741 case ISD::MUL:
1742 case ISD::SUB: {
1743 // Add, Sub, and Mul don't demand any bits in positions beyond that
1744 // of the highest bit demanded of them.
1745 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1746 BitWidth - NewMask.countLeadingZeros());
1747 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1748 KnownOne2, TLO, Depth+1))
1749 return true;
1750 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1751 KnownOne2, TLO, Depth+1))
1752 return true;
1753 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1754 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1755 return true;
1756 }
1757 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1758 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1759 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1760 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1761 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1762 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1763
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1764 // If we know the value of all of the demanded bits, return this as a
1765 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1766 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1767 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1768
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1769 return false;
1770}
1771
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1772/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1773/// in Mask are known to be either zero or one and return them in the
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1774/// KnownZero/KnownOne bitsets.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1775void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1776 const APInt &Mask,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1777 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1778 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1779 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1780 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1781 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1782 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1783 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1784 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1785 "Should use MaskedValueIsZero if you don't know whether Op"
1786 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1787 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1788}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1789
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1790/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1791/// targets that want to expose additional information about sign bits to the
1792/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1793unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1794 unsigned Depth) const {
1795 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1796 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1797 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1798 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1799 "Should use ComputeNumSignBits if you don't know whether Op"
1800 " is a target node!");
1801 return 1;
1802}
1803
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1804/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1805/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1806/// determine which bit is set.
1807///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1808static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1809 // A left-shift of a constant one will have exactly one bit set, because
1810 // shifting the bit off the end is undefined.
1811 if (Val.getOpcode() == ISD::SHL)
1812 if (ConstantSDNode *C =
1813 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1814 if (C->getAPIntValue() == 1)
1815 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1816
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1817 // Similarly, a right-shift of a constant sign-bit will have exactly
1818 // one bit set.
1819 if (Val.getOpcode() == ISD::SRL)
1820 if (ConstantSDNode *C =
1821 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1822 if (C->getAPIntValue().isSignBit())
1823 return true;
1824
1825 // More could be done here, though the above checks are enough
1826 // to handle some common cases.
1827
1828 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1829 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1830 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1831 APInt Mask = APInt::getAllOnesValue(BitWidth);
1832 APInt KnownZero, KnownOne;
1833 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1834 return (KnownZero.countPopulation() == BitWidth - 1) &&
1835 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1836}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1837
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1838/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1839/// and cc. If it is unable to simplify it, return a null SDValue.
1840SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1841TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1842 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1843 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1844 SelectionDAG &DAG = DCI.DAG;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1845 LLVMContext &Context = *DAG.getContext();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1846
1847 // These setcc operations always fold.
1848 switch (Cond) {
1849 default: break;
1850 case ISD::SETFALSE:
1851 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1852 case ISD::SETTRUE:
1853 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1854 }
1855
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1856 if (isa<ConstantSDNode>(N0.getNode())) {
1857 // Ensure that the constant occurs on the RHS, and fold constant
1858 // comparisons.
1859 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1860 }
1861
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1862 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1863 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1864
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1865 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1866 // equality comparison, then we're just comparing whether X itself is
1867 // zero.
1868 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1869 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1870 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1871 const APInt &ShAmt
1872 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1873 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1874 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1875 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1876 // (srl (ctlz x), 5) == 0 -> X != 0
1877 // (srl (ctlz x), 5) != 1 -> X != 0
1878 Cond = ISD::SETNE;
1879 } else {
1880 // (srl (ctlz x), 5) != 0 -> X == 0
1881 // (srl (ctlz x), 5) == 1 -> X == 0
1882 Cond = ISD::SETEQ;
1883 }
1884 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1885 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1886 Zero, Cond);
1887 }
1888 }
1889
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1890 SDValue CTPOP = N0;
1891 // Look through truncs that don't change the value of a ctpop.
1892 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1893 CTPOP = N0.getOperand(0);
1894
1895 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
Benjamin Kramerc9b6a3e2011-01-17 18:00:28 +0000[diff] [blame]1896 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
Benjamin Kramerd8228922011-01-17 12:04:57 +0000[diff] [blame]1897 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1898 EVT CTVT = CTPOP.getValueType();
1899 SDValue CTOp = CTPOP.getOperand(0);
1900
1901 // (ctpop x) u< 2 -> (x & x-1) == 0
1902 // (ctpop x) u> 1 -> (x & x-1) != 0
1903 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1904 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1905 DAG.getConstant(1, CTVT));
1906 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1907 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1908 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1909 }
1910
1911 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1912 }
1913
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1914 // If the LHS is '(and load, const)', the RHS is 0,
1915 // the test is for equality or unsigned, and all 1 bits of the const are
1916 // in the same partial word, see if we can shorten the load.
1917 if (DCI.isBeforeLegalize() &&
1918 N0.getOpcode() == ISD::AND && C1 == 0 &&
1919 N0.getNode()->hasOneUse() &&
1920 isa<LoadSDNode>(N0.getOperand(0)) &&
1921 N0.getOperand(0).getNode()->hasOneUse() &&
1922 isa<ConstantSDNode>(N0.getOperand(1))) {
1923 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1924 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1925 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1926 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1927 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1928 unsigned maskWidth = origWidth;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1929 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1930 // 8 bits, but have to be careful...
1931 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1932 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1933 const APInt &Mask =
1934 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1935 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1936 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1937 for (unsigned offset=0; offset<origWidth/width; offset++) {
1938 if ((newMask & Mask) == Mask) {
1939 if (!TD->isLittleEndian())
1940 bestOffset = (origWidth/width - offset - 1) * (width/8);
1941 else
1942 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1943 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1944 bestWidth = width;
1945 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1946 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1947 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1948 }
1949 }
1950 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1951 if (bestWidth) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1952 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1953 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1954 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1955 SDValue Ptr = Lod->getBasePtr();
1956 if (bestOffset != 0)
1957 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1958 DAG.getConstant(bestOffset, PtrType));
1959 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1960 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
Chris Lattnerecf42c42010-09-21 16:36:31 +0000[diff] [blame]1961 Lod->getPointerInfo().getWithOffset(bestOffset),
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]1962 false, false, NewAlign);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]1963 return DAG.getSetCC(dl, VT,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1964 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1965 DAG.getConstant(bestMask.trunc(bestWidth),
1966 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1967 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1968 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1969 }
1970 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1971
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1972 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1973 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1974 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1975
1976 // If the comparison constant has bits in the upper part, the
1977 // zero-extended value could never match.
1978 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1979 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1980 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1981 case ISD::SETUGT:
1982 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1983 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1984 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1985 case ISD::SETULE:
1986 case ISD::SETNE: return DAG.getConstant(1, VT);
1987 case ISD::SETGT:
1988 case ISD::SETGE:
1989 // True if the sign bit of C1 is set.
1990 return DAG.getConstant(C1.isNegative(), VT);
1991 case ISD::SETLT:
1992 case ISD::SETLE:
1993 // True if the sign bit of C1 isn't set.
1994 return DAG.getConstant(C1.isNonNegative(), VT);
1995 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]1996 break;
1997 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1998 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1999
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2000 // Otherwise, we can perform the comparison with the low bits.
2001 switch (Cond) {
2002 case ISD::SETEQ:
2003 case ISD::SETNE:
2004 case ISD::SETUGT:
2005 case ISD::SETUGE:
2006 case ISD::SETULT:
2007 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2008 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2009 if (DCI.isBeforeLegalizeOps() ||
2010 (isOperationLegal(ISD::SETCC, newVT) &&
2011 getCondCodeAction(Cond, newVT)==Legal))
2012 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Jay Foad40f8f622010-12-07 08:25:19 +0000[diff] [blame]2013 DAG.getConstant(C1.trunc(InSize), newVT),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2014 Cond);
2015 break;
2016 }
2017 default:
2018 break; // todo, be more careful with signed comparisons
2019 }
2020 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2021 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2022 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2023 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2024 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2025 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2026
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]2027 // If the constant doesn't fit into the number of bits for the source of
2028 // the sign extension, it is impossible for both sides to be equal.
2029 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2030 return DAG.getConstant(Cond == ISD::SETNE, VT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2031
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2032 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2033 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2034 if (Op0Ty == ExtSrcTy) {
2035 ZextOp = N0.getOperand(0);
2036 } else {
2037 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2038 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2039 DAG.getConstant(Imm, Op0Ty));
2040 }
2041 if (!DCI.isCalledByLegalizer())
2042 DCI.AddToWorklist(ZextOp.getNode());
2043 // Otherwise, make this a use of a zext.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2044 return DAG.getSetCC(dl, VT, ZextOp,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2045 DAG.getConstant(C1 & APInt::getLowBitsSet(
2046 ExtDstTyBits,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2047 ExtSrcTyBits),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2048 ExtDstTy),
2049 Cond);
2050 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2051 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2052 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2053 if (N0.getOpcode() == ISD::SETCC &&
2054 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2055 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2056 if (TrueWhenTrue)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2057 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2058 // Invert the condition.
2059 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2060 CC = ISD::getSetCCInverse(CC,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2061 N0.getOperand(0).getValueType().isInteger());
2062 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2063 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2064
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2065 if ((N0.getOpcode() == ISD::XOR ||
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2066 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2067 N0.getOperand(0).getOpcode() == ISD::XOR &&
2068 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2069 isa<ConstantSDNode>(N0.getOperand(1)) &&
2070 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2071 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2072 // can only do this if the top bits are known zero.
2073 unsigned BitWidth = N0.getValueSizeInBits();
2074 if (DAG.MaskedValueIsZero(N0,
2075 APInt::getHighBitsSet(BitWidth,
2076 BitWidth-1))) {
2077 // Okay, get the un-inverted input value.
2078 SDValue Val;
2079 if (N0.getOpcode() == ISD::XOR)
2080 Val = N0.getOperand(0);
2081 else {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2082 assert(N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2083 N0.getOperand(0).getOpcode() == ISD::XOR);
2084 // ((X^1)&1)^1 -> X & 1
2085 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2086 N0.getOperand(0).getOperand(0),
2087 N0.getOperand(1));
2088 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2089
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2090 return DAG.getSetCC(dl, VT, Val, N1,
2091 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2092 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2093 } else if (N1C->getAPIntValue() == 1 &&
2094 (VT == MVT::i1 ||
2095 getBooleanContents() == ZeroOrOneBooleanContent)) {
2096 SDValue Op0 = N0;
2097 if (Op0.getOpcode() == ISD::TRUNCATE)
2098 Op0 = Op0.getOperand(0);
2099
2100 if ((Op0.getOpcode() == ISD::XOR) &&
2101 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2102 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2103 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2104 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2105 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2106 Cond);
2107 } else if (Op0.getOpcode() == ISD::AND &&
2108 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2109 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2110 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2111 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2112 Op0 = DAG.getNode(ISD::AND, dl, VT,
2113 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2114 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2115 else if (Op0.getValueType().bitsLT(VT))
2116 Op0 = DAG.getNode(ISD::AND, dl, VT,
2117 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2118 DAG.getConstant(1, VT));
2119
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2120 return DAG.getSetCC(dl, VT, Op0,
2121 DAG.getConstant(0, Op0.getValueType()),
2122 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2123 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2124 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2125 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2126
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2127 APInt MinVal, MaxVal;
2128 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2129 if (ISD::isSignedIntSetCC(Cond)) {
2130 MinVal = APInt::getSignedMinValue(OperandBitSize);
2131 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2132 } else {
2133 MinVal = APInt::getMinValue(OperandBitSize);
2134 MaxVal = APInt::getMaxValue(OperandBitSize);
2135 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2136
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2137 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2138 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2139 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2140 // X >= C0 --> X > (C0-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2141 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2142 DAG.getConstant(C1-1, N1.getValueType()),
2143 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2144 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2145
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2146 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2147 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2148 // X <= C0 --> X < (C0+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2149 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2150 DAG.getConstant(C1+1, N1.getValueType()),
2151 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2152 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2153
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2154 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2155 return DAG.getConstant(0, VT); // X < MIN --> false
2156 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2157 return DAG.getConstant(1, VT); // X >= MIN --> true
2158 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2159 return DAG.getConstant(0, VT); // X > MAX --> false
2160 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2161 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2162
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2163 // Canonicalize setgt X, Min --> setne X, Min
2164 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2165 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2166 // Canonicalize setlt X, Max --> setne X, Max
2167 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2168 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2169
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2170 // If we have setult X, 1, turn it into seteq X, 0
2171 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2172 return DAG.getSetCC(dl, VT, N0,
2173 DAG.getConstant(MinVal, N0.getValueType()),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2174 ISD::SETEQ);
2175 // If we have setugt X, Max-1, turn it into seteq X, Max
2176 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2177 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2178 DAG.getConstant(MaxVal, N0.getValueType()),
2179 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2180
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2181 // If we have "setcc X, C0", check to see if we can shrink the immediate
2182 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2183
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2184 // SETUGT X, SINTMAX -> SETLT X, 0
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2185 if (Cond == ISD::SETUGT &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2186 C1 == APInt::getSignedMaxValue(OperandBitSize))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2187 return DAG.getSetCC(dl, VT, N0,
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2188 DAG.getConstant(0, N1.getValueType()),
2189 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2190
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2191 // SETULT X, SINTMIN -> SETGT X, -1
2192 if (Cond == ISD::SETULT &&
2193 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2194 SDValue ConstMinusOne =
2195 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2196 N1.getValueType());
2197 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2198 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2199
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2200 // Fold bit comparisons when we can.
2201 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2202 (VT == N0.getValueType() ||
2203 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2204 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2205 if (ConstantSDNode *AndRHS =
2206 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2207 EVT ShiftTy = DCI.isBeforeLegalize() ?
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2208 getPointerTy() : getShiftAmountTy(N0.getValueType());
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2209 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2210 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2211 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2212 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2213 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2214 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2215 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2216 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2217 // (X & 8) == 8 --> (X & 8) >> 3
2218 // Perform the xform if C1 is a single bit.
2219 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2220 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2221 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2222 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2223 }
2224 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2225 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2226 }
2227
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2228 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2229 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2230 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2231 if (O.getNode()) return O;
2232 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2233 // If the RHS of an FP comparison is a constant, simplify it away in
2234 // some cases.
2235 if (CFP->getValueAPF().isNaN()) {
2236 // If an operand is known to be a nan, we can fold it.
2237 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2238 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2239 case 0: // Known false.
2240 return DAG.getConstant(0, VT);
2241 case 1: // Known true.
2242 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2243 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2244 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2245 }
2246 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2247
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2248 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2249 // constant if knowing that the operand is non-nan is enough. We prefer to
2250 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2251 // materialize 0.0.
2252 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2253 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2254
2255 // If the condition is not legal, see if we can find an equivalent one
2256 // which is legal.
2257 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2258 // If the comparison was an awkward floating-point == or != and one of
2259 // the comparison operands is infinity or negative infinity, convert the
2260 // condition to a less-awkward <= or >=.
2261 if (CFP->getValueAPF().isInfinity()) {
2262 if (CFP->getValueAPF().isNegative()) {
2263 if (Cond == ISD::SETOEQ &&
2264 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2265 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2266 if (Cond == ISD::SETUEQ &&
2267 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2268 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2269 if (Cond == ISD::SETUNE &&
2270 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2271 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2272 if (Cond == ISD::SETONE &&
2273 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2274 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2275 } else {
2276 if (Cond == ISD::SETOEQ &&
2277 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2278 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2279 if (Cond == ISD::SETUEQ &&
2280 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2281 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2282 if (Cond == ISD::SETUNE &&
2283 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2284 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2285 if (Cond == ISD::SETONE &&
2286 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2287 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2288 }
2289 }
2290 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2291 }
2292
2293 if (N0 == N1) {
2294 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2295 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2296 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2297 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2298 if (UOF == 2) // FP operators that are undefined on NaNs.
2299 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2300 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2301 return DAG.getConstant(UOF, VT);
2302 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2303 // if it is not already.
2304 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2305 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2306 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2307 }
2308
2309 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2310 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2311 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2312 N0.getOpcode() == ISD::XOR) {
2313 // Simplify (X+Y) == (X+Z) --> Y == Z
2314 if (N0.getOpcode() == N1.getOpcode()) {
2315 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2316 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2317 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2318 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2319 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2320 // If X op Y == Y op X, try other combinations.
2321 if (N0.getOperand(0) == N1.getOperand(1))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2322 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2323 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2324 if (N0.getOperand(1) == N1.getOperand(0))
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2325 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2326 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2327 }
2328 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2329
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2330 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2331 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2332 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2333 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2334 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2335 DAG.getConstant(RHSC->getAPIntValue()-
2336 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2337 N0.getValueType()), Cond);
2338 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2339
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2340 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2341 if (N0.getOpcode() == ISD::XOR)
2342 // If we know that all of the inverted bits are zero, don't bother
2343 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2344 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2345 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2346 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2347 DAG.getConstant(LHSR->getAPIntValue() ^
2348 RHSC->getAPIntValue(),
2349 N0.getValueType()),
2350 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2351 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2352
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2353 // Turn (C1-X) == C2 --> X == C1-C2
2354 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2355 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2356 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2357 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2358 DAG.getConstant(SUBC->getAPIntValue() -
2359 RHSC->getAPIntValue(),
2360 N0.getValueType()),
2361 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2362 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2363 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2364 }
2365
2366 // Simplify (X+Z) == X --> Z == 0
2367 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2368 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2369 DAG.getConstant(0, N0.getValueType()), Cond);
2370 if (N0.getOperand(1) == N1) {
2371 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2372 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2373 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2374 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2375 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2376 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2377 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2378 N1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2379 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2380 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2381 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2382 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2383 }
2384 }
2385 }
2386
2387 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2388 N1.getOpcode() == ISD::XOR) {
2389 // Simplify X == (X+Z) --> Z == 0
2390 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2391 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2392 DAG.getConstant(0, N1.getValueType()), Cond);
2393 } else if (N1.getOperand(1) == N0) {
2394 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2395 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2396 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2397 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2398 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2399 // X == (Z-X) --> X<<1 == Z
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2400 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2401 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2402 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2403 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2404 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2405 }
2406 }
2407 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2408
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2409 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2410 // Note that where y is variable and is known to have at most
2411 // one bit set (for example, if it is z&1) we cannot do this;
2412 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2413 if (N0.getOpcode() == ISD::AND)
2414 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2415 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2416 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2417 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2418 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2419 }
2420 }
2421 if (N1.getOpcode() == ISD::AND)
2422 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2423 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2424 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2425 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2426 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2427 }
2428 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2429 }
2430
2431 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2432 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2433 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2434 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2435 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2436 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2437 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2438 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2439 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2440 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2441 break;
2442 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2443 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2444 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2445 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2446 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2447 Temp = DAG.getNOT(dl, N0, MVT::i1);
2448 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2449 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2450 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2451 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2452 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2453 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2454 Temp = DAG.getNOT(dl, N1, MVT::i1);
2455 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2456 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2457 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2458 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2459 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2460 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2461 Temp = DAG.getNOT(dl, N0, MVT::i1);
2462 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2463 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2464 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2465 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2466 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2467 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2468 Temp = DAG.getNOT(dl, N1, MVT::i1);
2469 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2470 break;
2471 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2472 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2473 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2474 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2475 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2476 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2477 }
2478 return N0;
2479 }
2480
2481 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2482 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2483}
2484
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2485/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2486/// node is a GlobalAddress + offset.
Chris Lattner0a9481f2011-02-13 22:25:43 +0000[diff] [blame]2487bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2488 int64_t &Offset) const {
2489 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2490 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2491 GA = GASD->getGlobal();
2492 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2493 return true;
2494 }
2495
2496 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2497 SDValue N1 = N->getOperand(0);
2498 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2499 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2500 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2501 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2502 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2503 return true;
2504 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2505 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2506 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2507 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2508 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2509 return true;
2510 }
2511 }
2512 }
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]2513
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2514 return false;
2515}
2516
2517
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2518SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2519PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2520 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2521 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2522}
2523
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2524//===----------------------------------------------------------------------===//
2525// Inline Assembler Implementation Methods
2526//===----------------------------------------------------------------------===//
2527
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2528
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2529TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2530TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2531 // FIXME: lots more standard ones to handle.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2532 if (Constraint.size() == 1) {
2533 switch (Constraint[0]) {
2534 default: break;
2535 case 'r': return C_RegisterClass;
2536 case 'm': // memory
2537 case 'o': // offsetable
2538 case 'V': // not offsetable
2539 return C_Memory;
2540 case 'i': // Simple Integer or Relocatable Constant
2541 case 'n': // Simple Integer
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2542 case 'E': // Floating Point Constant
2543 case 'F': // Floating Point Constant
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2544 case 's': // Relocatable Constant
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2545 case 'p': // Address.
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2546 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2547 case 'I': // Target registers.
2548 case 'J':
2549 case 'K':
2550 case 'L':
2551 case 'M':
2552 case 'N':
2553 case 'O':
2554 case 'P':
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2555 case '<':
2556 case '>':
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2557 return C_Other;
2558 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2559 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2560
2561 if (Constraint.size() > 1 && Constraint[0] == '{' &&
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2562 Constraint[Constraint.size()-1] == '}')
2563 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2564 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2565}
2566
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2567/// LowerXConstraint - try to replace an X constraint, which matches anything,
2568/// with another that has more specific requirements based on the type of the
2569/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2570const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2571 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2572 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2573 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2574 return "f"; // works for many targets
2575 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2576}
2577
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2578/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2579/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2580void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2581 char ConstraintLetter,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2582 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2583 SelectionDAG &DAG) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2584 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2585 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2586 case 'X': // Allows any operand; labels (basic block) use this.
2587 if (Op.getOpcode() == ISD::BasicBlock) {
2588 Ops.push_back(Op);
2589 return;
2590 }
2591 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2592 case 'i': // Simple Integer or Relocatable Constant
2593 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2594 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2595 // These operands are interested in values of the form (GV+C), where C may
2596 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2597 // is possible and fine if either GV or C are missing.
2598 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2599 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2600
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2601 // If we have "(add GV, C)", pull out GV/C
2602 if (Op.getOpcode() == ISD::ADD) {
2603 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2604 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2605 if (C == 0 || GA == 0) {
2606 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2607 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2608 }
2609 if (C == 0 || GA == 0)
2610 C = 0, GA = 0;
2611 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2612
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2613 // If we find a valid operand, map to the TargetXXX version so that the
2614 // value itself doesn't get selected.
2615 if (GA) { // Either &GV or &GV+C
2616 if (ConstraintLetter != 'n') {
2617 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2618 if (C) Offs += C->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2619 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2620 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2621 Op.getValueType(), Offs));
2622 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2623 }
2624 }
2625 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2626 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2627 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2628 // gcc prints these as sign extended. Sign extend value to 64 bits
2629 // now; without this it would get ZExt'd later in
2630 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2631 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2632 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2633 return;
2634 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2635 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2636 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2637 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2638 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2639}
2640
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2641std::vector<unsigned> TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2642getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2643 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2644 return std::vector<unsigned>();
2645}
2646
2647
2648std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2649getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2650 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2651 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2652 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2653 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2654
2655 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2656 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2657
2658 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2659 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2660 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2661 E = RI->regclass_end(); RCI != E; ++RCI) {
2662 const TargetRegisterClass *RC = *RCI;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2663
2664 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2665 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2666 bool isLegal = false;
2667 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2668 I != E; ++I) {
2669 if (isTypeLegal(*I)) {
2670 isLegal = true;
2671 break;
2672 }
2673 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2674
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2675 if (!isLegal) continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2676
2677 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2678 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2679 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2680 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2681 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2682 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2683
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2684 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2685}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2686
2687//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2688// Constraint Selection.
2689
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2690/// isMatchingInputConstraint - Return true of this is an input operand that is
2691/// a matching constraint like "4".
2692bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2693 assert(!ConstraintCode.empty() && "No known constraint!");
2694 return isdigit(ConstraintCode[0]);
2695}
2696
2697/// getMatchedOperand - If this is an input matching constraint, this method
2698/// returns the output operand it matches.
2699unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2700 assert(!ConstraintCode.empty() && "No known constraint!");
2701 return atoi(ConstraintCode.c_str());
2702}
2703
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2704
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2705/// ParseConstraints - Split up the constraint string from the inline
2706/// assembly value into the specific constraints and their prefixes,
2707/// and also tie in the associated operand values.
2708/// If this returns an empty vector, and if the constraint string itself
2709/// isn't empty, there was an error parsing.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2710TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2711 ImmutableCallSite CS) const {
2712 /// ConstraintOperands - Information about all of the constraints.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2713 AsmOperandInfoVector ConstraintOperands;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2714 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2715 unsigned maCount = 0; // Largest number of multiple alternative constraints.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2716
2717 // Do a prepass over the constraints, canonicalizing them, and building up the
2718 // ConstraintOperands list.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2719 InlineAsm::ConstraintInfoVector
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2720 ConstraintInfos = IA->ParseConstraints();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2721
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2722 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2723 unsigned ResNo = 0; // ResNo - The result number of the next output.
2724
2725 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2726 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2727 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2728
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2729 // Update multiple alternative constraint count.
2730 if (OpInfo.multipleAlternatives.size() > maCount)
2731 maCount = OpInfo.multipleAlternatives.size();
2732
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2733 OpInfo.ConstraintVT = MVT::Other;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2734
2735 // Compute the value type for each operand.
2736 switch (OpInfo.Type) {
2737 case InlineAsm::isOutput:
2738 // Indirect outputs just consume an argument.
2739 if (OpInfo.isIndirect) {
2740 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2741 break;
2742 }
2743
2744 // The return value of the call is this value. As such, there is no
2745 // corresponding argument.
2746 assert(!CS.getType()->isVoidTy() &&
2747 "Bad inline asm!");
2748 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2749 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2750 } else {
2751 assert(ResNo == 0 && "Asm only has one result!");
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2752 OpInfo.ConstraintVT = getValueType(CS.getType());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2753 }
2754 ++ResNo;
2755 break;
2756 case InlineAsm::isInput:
2757 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2758 break;
2759 case InlineAsm::isClobber:
2760 // Nothing to do.
2761 break;
2762 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2763
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2764 if (OpInfo.CallOperandVal) {
2765 const llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2766 if (OpInfo.isIndirect) {
2767 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2768 if (!PtrTy)
2769 report_fatal_error("Indirect operand for inline asm not a pointer!");
2770 OpTy = PtrTy->getElementType();
2771 }
2772 // If OpTy is not a single value, it may be a struct/union that we
2773 // can tile with integers.
2774 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2775 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2776 switch (BitSize) {
2777 default: break;
2778 case 1:
2779 case 8:
2780 case 16:
2781 case 32:
2782 case 64:
2783 case 128:
Dale Johannesen71365d32010-11-09 01:15:07 +0000[diff] [blame]2784 OpInfo.ConstraintVT =
2785 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2786 break;
2787 }
2788 } else if (dyn_cast<PointerType>(OpTy)) {
2789 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2790 } else {
2791 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2792 }
2793 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2794 }
2795
2796 // If we have multiple alternative constraints, select the best alternative.
2797 if (ConstraintInfos.size()) {
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2798 if (maCount) {
2799 unsigned bestMAIndex = 0;
2800 int bestWeight = -1;
2801 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2802 int weight = -1;
2803 unsigned maIndex;
2804 // Compute the sums of the weights for each alternative, keeping track
2805 // of the best (highest weight) one so far.
2806 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2807 int weightSum = 0;
2808 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2809 cIndex != eIndex; ++cIndex) {
2810 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2811 if (OpInfo.Type == InlineAsm::isClobber)
2812 continue;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2813
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2814 // If this is an output operand with a matching input operand,
2815 // look up the matching input. If their types mismatch, e.g. one
2816 // is an integer, the other is floating point, or their sizes are
2817 // different, flag it as an maCantMatch.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2818 if (OpInfo.hasMatchingInput()) {
2819 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2820 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2821 if ((OpInfo.ConstraintVT.isInteger() !=
2822 Input.ConstraintVT.isInteger()) ||
2823 (OpInfo.ConstraintVT.getSizeInBits() !=
2824 Input.ConstraintVT.getSizeInBits())) {
2825 weightSum = -1; // Can't match.
2826 break;
2827 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2828 }
2829 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2830 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2831 if (weight == -1) {
2832 weightSum = -1;
2833 break;
2834 }
2835 weightSum += weight;
2836 }
2837 // Update best.
2838 if (weightSum > bestWeight) {
2839 bestWeight = weightSum;
2840 bestMAIndex = maIndex;
2841 }
2842 }
2843
2844 // Now select chosen alternative in each constraint.
2845 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2846 cIndex != eIndex; ++cIndex) {
2847 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2848 if (cInfo.Type == InlineAsm::isClobber)
2849 continue;
2850 cInfo.selectAlternative(bestMAIndex);
2851 }
2852 }
2853 }
2854
2855 // Check and hook up tied operands, choose constraint code to use.
2856 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2857 cIndex != eIndex; ++cIndex) {
2858 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]2859
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2860 // If this is an output operand with a matching input operand, look up the
2861 // matching input. If their types mismatch, e.g. one is an integer, the
2862 // other is floating point, or their sizes are different, flag it as an
2863 // error.
2864 if (OpInfo.hasMatchingInput()) {
2865 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2866
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2867 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2868 if ((OpInfo.ConstraintVT.isInteger() !=
2869 Input.ConstraintVT.isInteger()) ||
2870 (OpInfo.ConstraintVT.getSizeInBits() !=
2871 Input.ConstraintVT.getSizeInBits())) {
2872 report_fatal_error("Unsupported asm: input constraint"
2873 " with a matching output constraint of"
2874 " incompatible type!");
2875 }
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2876 }
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2877
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2878 }
2879 }
2880
2881 return ConstraintOperands;
2882}
2883
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2884
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2885/// getConstraintGenerality - Return an integer indicating how general CT
2886/// is.
2887static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2888 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2889 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2890 case TargetLowering::C_Other:
2891 case TargetLowering::C_Unknown:
2892 return 0;
2893 case TargetLowering::C_Register:
2894 return 1;
2895 case TargetLowering::C_RegisterClass:
2896 return 2;
2897 case TargetLowering::C_Memory:
2898 return 3;
2899 }
2900}
2901
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2902/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2903/// This object must already have been set up with the operand type
2904/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2905TargetLowering::ConstraintWeight
2906 TargetLowering::getMultipleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2907 AsmOperandInfo &info, int maIndex) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2908 InlineAsm::ConstraintCodeVector *rCodes;
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2909 if (maIndex >= (int)info.multipleAlternatives.size())
2910 rCodes = &info.Codes;
2911 else
2912 rCodes = &info.multipleAlternatives[maIndex].Codes;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2913 ConstraintWeight BestWeight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2914
2915 // Loop over the options, keeping track of the most general one.
John Thompson67aff162010-09-21 22:04:54 +0000[diff] [blame]2916 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2917 ConstraintWeight weight =
2918 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2919 if (weight > BestWeight)
2920 BestWeight = weight;
2921 }
2922
2923 return BestWeight;
2924}
2925
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2926/// Examine constraint type and operand type and determine a weight value.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2927/// This object must already have been set up with the operand type
2928/// and the current alternative constraint selected.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2929TargetLowering::ConstraintWeight
2930 TargetLowering::getSingleConstraintMatchWeight(
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2931 AsmOperandInfo &info, const char *constraint) const {
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2932 ConstraintWeight weight = CW_Invalid;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2933 Value *CallOperandVal = info.CallOperandVal;
2934 // If we don't have a value, we can't do a match,
2935 // but allow it at the lowest weight.
2936 if (CallOperandVal == NULL)
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2937 return CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2938 // Look at the constraint type.
2939 switch (*constraint) {
2940 case 'i': // immediate integer.
2941 case 'n': // immediate integer with a known value.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2942 if (isa<ConstantInt>(CallOperandVal))
2943 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2944 break;
2945 case 's': // non-explicit intregal immediate.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2946 if (isa<GlobalValue>(CallOperandVal))
2947 weight = CW_Constant;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2948 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2949 case 'E': // immediate float if host format.
2950 case 'F': // immediate float.
2951 if (isa<ConstantFP>(CallOperandVal))
2952 weight = CW_Constant;
2953 break;
2954 case '<': // memory operand with autodecrement.
2955 case '>': // memory operand with autoincrement.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2956 case 'm': // memory operand.
2957 case 'o': // offsettable memory operand
2958 case 'V': // non-offsettable memory operand
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2959 weight = CW_Memory;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2960 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2961 case 'r': // general register.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2962 case 'g': // general register, memory operand or immediate integer.
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2963 // note: Clang converts "g" to "imr".
2964 if (CallOperandVal->getType()->isIntegerTy())
2965 weight = CW_Register;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2966 break;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2967 case 'X': // any operand.
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2968 default:
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]2969 weight = CW_Default;
John Thompsoneac6e1d2010-09-13 18:15:37 +0000[diff] [blame]2970 break;
2971 }
2972 return weight;
2973}
2974
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2975/// ChooseConstraint - If there are multiple different constraints that we
2976/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]2977/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2978/// Other -> immediates and magic values
2979/// Register -> one specific register
2980/// RegisterClass -> a group of regs
2981/// Memory -> memory
2982/// Ideally, we would pick the most specific constraint possible: if we have
2983/// something that fits into a register, we would pick it. The problem here
2984/// is that if we have something that could either be in a register or in
2985/// memory that use of the register could cause selection of *other*
2986/// operands to fail: they might only succeed if we pick memory. Because of
2987/// this the heuristic we use is:
2988///
2989/// 1) If there is an 'other' constraint, and if the operand is valid for
2990/// that constraint, use it. This makes us take advantage of 'i'
2991/// constraints when available.
2992/// 2) Otherwise, pick the most general constraint present. This prefers
2993/// 'm' over 'r', for example.
2994///
2995static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2996 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2997 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2998 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2999 unsigned BestIdx = 0;
3000 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3001 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3002
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3003 // Loop over the options, keeping track of the most general one.
3004 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3005 TargetLowering::ConstraintType CType =
3006 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3007
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3008 // If this is an 'other' constraint, see if the operand is valid for it.
3009 // For example, on X86 we might have an 'rI' constraint. If the operand
3010 // is an integer in the range [0..31] we want to use I (saving a load
3011 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3012 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3013 assert(OpInfo.Codes[i].size() == 1 &&
3014 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3015 std::vector<SDValue> ResultOps;
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3016 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3017 ResultOps, *DAG);
3018 if (!ResultOps.empty()) {
3019 BestType = CType;
3020 BestIdx = i;
3021 break;
3022 }
3023 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3024
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]3025 // Things with matching constraints can only be registers, per gcc
3026 // documentation. This mainly affects "g" constraints.
3027 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3028 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3029
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3030 // This constraint letter is more general than the previous one, use it.
3031 int Generality = getConstraintGenerality(CType);
3032 if (Generality > BestGenerality) {
3033 BestType = CType;
3034 BestIdx = i;
3035 BestGenerality = Generality;
3036 }
3037 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3038
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3039 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3040 OpInfo.ConstraintType = BestType;
3041}
3042
3043/// ComputeConstraintToUse - Determines the constraint code and constraint
3044/// type to use for the specific AsmOperandInfo, setting
3045/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3046void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3047 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]3048 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3049 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3050
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3051 // Single-letter constraints ('r') are very common.
3052 if (OpInfo.Codes.size() == 1) {
3053 OpInfo.ConstraintCode = OpInfo.Codes[0];
3054 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3055 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]3056 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3057 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3058
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3059 // 'X' matches anything.
3060 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3061 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3062 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]3063 // the result, which is not what we want to look at; leave them alone.
3064 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3065 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3066 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3067 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]3068 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3069
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]3070 // Otherwise, try to resolve it to something we know about by looking at
3071 // the actual operand type.
3072 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3073 OpInfo.ConstraintCode = Repl;
3074 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3075 }
3076 }
3077}
3078
3079//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]3080// Loop Strength Reduction hooks
3081//===----------------------------------------------------------------------===//
3082
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3083/// isLegalAddressingMode - Return true if the addressing mode represented
3084/// by AM is legal for this target, for a load/store of the specified type.
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3085bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3086 const Type *Ty) const {
3087 // The default implementation of this implements a conservative RISCy, r+r and
3088 // r+i addr mode.
3089
3090 // Allows a sign-extended 16-bit immediate field.
3091 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3092 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3093
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3094 // No global is ever allowed as a base.
3095 if (AM.BaseGV)
3096 return false;
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3097
3098 // Only support r+r,
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3099 switch (AM.Scale) {
3100 case 0: // "r+i" or just "i", depending on HasBaseReg.
3101 break;
3102 case 1:
3103 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3104 return false;
3105 // Otherwise we have r+r or r+i.
3106 break;
3107 case 2:
3108 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3109 return false;
3110 // Allow 2*r as r+r.
3111 break;
3112 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3113
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]3114 return true;
3115}
3116
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3117/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3118/// return a DAG expression to select that will generate the same value by
3119/// multiplying by a magic number. See:
3120/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3121SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3122 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3123 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3124 DebugLoc dl= N->getDebugLoc();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3125
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3126 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3127 // FIXME: We should be more aggressive here.
3128 if (!isTypeLegal(VT))
3129 return SDValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3130
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3131 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]3132 APInt::ms magics = d.magic();
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3133
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3134 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3135 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3136 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3137 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3138 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3139 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3140 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3141 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3142 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3143 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3144 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3145 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3146 // If d > 0 and m < 0, add the numerator
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3147 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3148 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3149 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3150 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3151 }
3152 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]3153 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3154 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3155 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3156 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3157 }
3158 // Shift right algebraic if shift value is nonzero
3159 if (magics.s > 0) {
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3160 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3161 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3162 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3163 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3164 }
3165 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3166 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3167 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3168 getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3169 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3170 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3171 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3172}
3173
3174/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3175/// return a DAG expression to select that will generate the same value by
3176/// multiplying by a magic number. See:
3177/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3178SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
3179 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]3180 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3181 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3182
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3183 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3184 // FIXME: We should be more aggressive here.
3185 if (!isTypeLegal(VT))
3186 return SDValue();
3187
3188 // FIXME: We should use a narrower constant when the upper
3189 // bits are known to be zero.
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3190 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3191 APInt::mu magics = N1C.magicu();
3192
3193 SDValue Q = N->getOperand(0);
3194
3195 // If the divisor is even, we can avoid using the expensive fixup by shifting
3196 // the divided value upfront.
3197 if (magics.a != 0 && !N1C[0]) {
3198 unsigned Shift = N1C.countTrailingZeros();
3199 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3200 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3201 if (Created)
3202 Created->push_back(Q.getNode());
3203
3204 // Get magic number for the shifted divisor.
3205 magics = N1C.lshr(Shift).magicu(Shift);
3206 assert(magics.a == 0 && "Should use cheap fixup now");
3207 }
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3208
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3209 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3210 // FIXME: We should support doing a MUL in a wider type
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3211 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3212 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]3213 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3214 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3215 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]3216 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]3217 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3218 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3219 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3220
3221 if (magics.a == 0) {
Benjamin Kramer1c10b8d2011-03-17 20:39:14 +0000[diff] [blame]3222 assert(magics.s < N1C.getBitWidth() &&
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]3223 "We shouldn't generate an undefined shift!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3224 return DAG.getNode(ISD::SRL, dl, VT, Q,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3225 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3226 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3227 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3228 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3229 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3230 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3231 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3232 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3233 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]3234 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3235 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]3236 Created->push_back(NPQ.getNode());
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000[diff] [blame]3237 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Owen Anderson95771af2011-02-25 21:41:48 +0000[diff] [blame]3238 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]3239 }
3240}