David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 1 | //===- ARMBaseInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the Base ARM implementation of the TargetInstrInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #include "ARMBaseInstrInfo.h" |
| 15 | #include "ARM.h" |
| 16 | #include "ARMAddressingModes.h" |
| 17 | #include "ARMGenInstrInfo.inc" |
| 18 | #include "ARMMachineFunctionInfo.h" |
| 19 | #include "llvm/ADT/STLExtras.h" |
| 20 | #include "llvm/CodeGen/LiveVariables.h" |
| 21 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 23 | #include "llvm/CodeGen/MachineJumpTableInfo.h" |
| 24 | #include "llvm/Target/TargetAsmInfo.h" |
| 25 | #include "llvm/Support/CommandLine.h" |
Torok Edwin | c25e758 | 2009-07-11 20:10:48 +0000 | [diff] [blame] | 26 | #include "llvm/Support/ErrorHandling.h" |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 27 | using namespace llvm; |
| 28 | |
| 29 | static cl::opt<bool> |
| 30 | EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden, |
| 31 | cl::desc("Enable ARM 2-addr to 3-addr conv")); |
| 32 | |
Chris Lattner | d90183d | 2009-08-02 05:20:37 +0000 | [diff] [blame] | 33 | ARMBaseInstrInfo::ARMBaseInstrInfo() |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 34 | : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 35 | } |
| 36 | |
| 37 | MachineInstr * |
| 38 | ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, |
| 39 | MachineBasicBlock::iterator &MBBI, |
| 40 | LiveVariables *LV) const { |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 41 | // FIXME: Thumb2 support. |
| 42 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 43 | if (!EnableARM3Addr) |
| 44 | return NULL; |
| 45 | |
| 46 | MachineInstr *MI = MBBI; |
| 47 | MachineFunction &MF = *MI->getParent()->getParent(); |
| 48 | unsigned TSFlags = MI->getDesc().TSFlags; |
| 49 | bool isPre = false; |
| 50 | switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) { |
| 51 | default: return NULL; |
| 52 | case ARMII::IndexModePre: |
| 53 | isPre = true; |
| 54 | break; |
| 55 | case ARMII::IndexModePost: |
| 56 | break; |
| 57 | } |
| 58 | |
| 59 | // Try splitting an indexed load/store to an un-indexed one plus an add/sub |
| 60 | // operation. |
| 61 | unsigned MemOpc = getUnindexedOpcode(MI->getOpcode()); |
| 62 | if (MemOpc == 0) |
| 63 | return NULL; |
| 64 | |
| 65 | MachineInstr *UpdateMI = NULL; |
| 66 | MachineInstr *MemMI = NULL; |
| 67 | unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); |
| 68 | const TargetInstrDesc &TID = MI->getDesc(); |
| 69 | unsigned NumOps = TID.getNumOperands(); |
| 70 | bool isLoad = !TID.mayStore(); |
| 71 | const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); |
| 72 | const MachineOperand &Base = MI->getOperand(2); |
| 73 | const MachineOperand &Offset = MI->getOperand(NumOps-3); |
| 74 | unsigned WBReg = WB.getReg(); |
| 75 | unsigned BaseReg = Base.getReg(); |
| 76 | unsigned OffReg = Offset.getReg(); |
| 77 | unsigned OffImm = MI->getOperand(NumOps-2).getImm(); |
| 78 | ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); |
| 79 | switch (AddrMode) { |
| 80 | default: |
| 81 | assert(false && "Unknown indexed op!"); |
| 82 | return NULL; |
| 83 | case ARMII::AddrMode2: { |
| 84 | bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; |
| 85 | unsigned Amt = ARM_AM::getAM2Offset(OffImm); |
| 86 | if (OffReg == 0) { |
Evan Cheng | e7cbe41 | 2009-07-08 21:03:57 +0000 | [diff] [blame] | 87 | if (ARM_AM::getSOImmVal(Amt) == -1) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 88 | // Can't encode it in a so_imm operand. This transformation will |
| 89 | // add more than 1 instruction. Abandon! |
| 90 | return NULL; |
| 91 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 92 | get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) |
Evan Cheng | e7cbe41 | 2009-07-08 21:03:57 +0000 | [diff] [blame] | 93 | .addReg(BaseReg).addImm(Amt) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 94 | .addImm(Pred).addReg(0).addReg(0); |
| 95 | } else if (Amt != 0) { |
| 96 | ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); |
| 97 | unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); |
| 98 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 99 | get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 100 | .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc) |
| 101 | .addImm(Pred).addReg(0).addReg(0); |
| 102 | } else |
| 103 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 104 | get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 105 | .addReg(BaseReg).addReg(OffReg) |
| 106 | .addImm(Pred).addReg(0).addReg(0); |
| 107 | break; |
| 108 | } |
| 109 | case ARMII::AddrMode3 : { |
| 110 | bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; |
| 111 | unsigned Amt = ARM_AM::getAM3Offset(OffImm); |
| 112 | if (OffReg == 0) |
| 113 | // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand. |
| 114 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 115 | get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 116 | .addReg(BaseReg).addImm(Amt) |
| 117 | .addImm(Pred).addReg(0).addReg(0); |
| 118 | else |
| 119 | UpdateMI = BuildMI(MF, MI->getDebugLoc(), |
Evan Cheng | 78703dd | 2009-07-27 18:44:00 +0000 | [diff] [blame] | 120 | get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 121 | .addReg(BaseReg).addReg(OffReg) |
| 122 | .addImm(Pred).addReg(0).addReg(0); |
| 123 | break; |
| 124 | } |
| 125 | } |
| 126 | |
| 127 | std::vector<MachineInstr*> NewMIs; |
| 128 | if (isPre) { |
| 129 | if (isLoad) |
| 130 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 131 | get(MemOpc), MI->getOperand(0).getReg()) |
| 132 | .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); |
| 133 | else |
| 134 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 135 | get(MemOpc)).addReg(MI->getOperand(1).getReg()) |
| 136 | .addReg(WBReg).addReg(0).addImm(0).addImm(Pred); |
| 137 | NewMIs.push_back(MemMI); |
| 138 | NewMIs.push_back(UpdateMI); |
| 139 | } else { |
| 140 | if (isLoad) |
| 141 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 142 | get(MemOpc), MI->getOperand(0).getReg()) |
| 143 | .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); |
| 144 | else |
| 145 | MemMI = BuildMI(MF, MI->getDebugLoc(), |
| 146 | get(MemOpc)).addReg(MI->getOperand(1).getReg()) |
| 147 | .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred); |
| 148 | if (WB.isDead()) |
| 149 | UpdateMI->getOperand(0).setIsDead(); |
| 150 | NewMIs.push_back(UpdateMI); |
| 151 | NewMIs.push_back(MemMI); |
| 152 | } |
| 153 | |
| 154 | // Transfer LiveVariables states, kill / dead info. |
| 155 | if (LV) { |
| 156 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 157 | MachineOperand &MO = MI->getOperand(i); |
| 158 | if (MO.isReg() && MO.getReg() && |
| 159 | TargetRegisterInfo::isVirtualRegister(MO.getReg())) { |
| 160 | unsigned Reg = MO.getReg(); |
| 161 | |
| 162 | LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); |
| 163 | if (MO.isDef()) { |
| 164 | MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI; |
| 165 | if (MO.isDead()) |
| 166 | LV->addVirtualRegisterDead(Reg, NewMI); |
| 167 | } |
| 168 | if (MO.isUse() && MO.isKill()) { |
| 169 | for (unsigned j = 0; j < 2; ++j) { |
| 170 | // Look at the two new MI's in reverse order. |
| 171 | MachineInstr *NewMI = NewMIs[j]; |
| 172 | if (!NewMI->readsRegister(Reg)) |
| 173 | continue; |
| 174 | LV->addVirtualRegisterKilled(Reg, NewMI); |
| 175 | if (VI.removeKill(MI)) |
| 176 | VI.Kills.push_back(NewMI); |
| 177 | break; |
| 178 | } |
| 179 | } |
| 180 | } |
| 181 | } |
| 182 | } |
| 183 | |
| 184 | MFI->insert(MBBI, NewMIs[1]); |
| 185 | MFI->insert(MBBI, NewMIs[0]); |
| 186 | return NewMIs[0]; |
| 187 | } |
| 188 | |
| 189 | // Branch analysis. |
| 190 | bool |
| 191 | ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, |
| 192 | MachineBasicBlock *&FBB, |
| 193 | SmallVectorImpl<MachineOperand> &Cond, |
| 194 | bool AllowModify) const { |
| 195 | // If the block has no terminators, it just falls into the block after it. |
| 196 | MachineBasicBlock::iterator I = MBB.end(); |
| 197 | if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) |
| 198 | return false; |
| 199 | |
| 200 | // Get the last instruction in the block. |
| 201 | MachineInstr *LastInst = I; |
| 202 | |
| 203 | // If there is only one terminator instruction, process it. |
| 204 | unsigned LastOpc = LastInst->getOpcode(); |
| 205 | if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 206 | if (isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 207 | TBB = LastInst->getOperand(0).getMBB(); |
| 208 | return false; |
| 209 | } |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 210 | if (isCondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 211 | // Block ends with fall-through condbranch. |
| 212 | TBB = LastInst->getOperand(0).getMBB(); |
| 213 | Cond.push_back(LastInst->getOperand(1)); |
| 214 | Cond.push_back(LastInst->getOperand(2)); |
| 215 | return false; |
| 216 | } |
| 217 | return true; // Can't handle indirect branch. |
| 218 | } |
| 219 | |
| 220 | // Get the instruction before it if it is a terminator. |
| 221 | MachineInstr *SecondLastInst = I; |
| 222 | |
| 223 | // If there are three terminators, we don't know what sort of block this is. |
| 224 | if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I)) |
| 225 | return true; |
| 226 | |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 227 | // If the block ends with a B and a Bcc, handle it. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 228 | unsigned SecondLastOpc = SecondLastInst->getOpcode(); |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 229 | if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 230 | TBB = SecondLastInst->getOperand(0).getMBB(); |
| 231 | Cond.push_back(SecondLastInst->getOperand(1)); |
| 232 | Cond.push_back(SecondLastInst->getOperand(2)); |
| 233 | FBB = LastInst->getOperand(0).getMBB(); |
| 234 | return false; |
| 235 | } |
| 236 | |
| 237 | // If the block ends with two unconditional branches, handle it. The second |
| 238 | // one is not executed, so remove it. |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 239 | if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 240 | TBB = SecondLastInst->getOperand(0).getMBB(); |
| 241 | I = LastInst; |
| 242 | if (AllowModify) |
| 243 | I->eraseFromParent(); |
| 244 | return false; |
| 245 | } |
| 246 | |
| 247 | // ...likewise if it ends with a branch table followed by an unconditional |
| 248 | // branch. The branch folder can create these, and we must get rid of them for |
| 249 | // correctness of Thumb constant islands. |
Evan Cheng | 83e0e36 | 2009-07-27 18:25:24 +0000 | [diff] [blame] | 250 | if (isJumpTableBranchOpcode(SecondLastOpc) && |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 251 | isUncondBranchOpcode(LastOpc)) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 252 | I = LastInst; |
| 253 | if (AllowModify) |
| 254 | I->eraseFromParent(); |
| 255 | return true; |
| 256 | } |
| 257 | |
| 258 | // Otherwise, can't handle this. |
| 259 | return true; |
| 260 | } |
| 261 | |
| 262 | |
| 263 | unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 264 | MachineBasicBlock::iterator I = MBB.end(); |
| 265 | if (I == MBB.begin()) return 0; |
| 266 | --I; |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 267 | if (!isUncondBranchOpcode(I->getOpcode()) && |
| 268 | !isCondBranchOpcode(I->getOpcode())) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 269 | return 0; |
| 270 | |
| 271 | // Remove the branch. |
| 272 | I->eraseFromParent(); |
| 273 | |
| 274 | I = MBB.end(); |
| 275 | |
| 276 | if (I == MBB.begin()) return 1; |
| 277 | --I; |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 278 | if (!isCondBranchOpcode(I->getOpcode())) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 279 | return 1; |
| 280 | |
| 281 | // Remove the branch. |
| 282 | I->eraseFromParent(); |
| 283 | return 2; |
| 284 | } |
| 285 | |
| 286 | unsigned |
| 287 | ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 288 | MachineBasicBlock *FBB, |
| 289 | const SmallVectorImpl<MachineOperand> &Cond) const { |
| 290 | // FIXME this should probably have a DebugLoc argument |
| 291 | DebugLoc dl = DebugLoc::getUnknownLoc(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 292 | |
| 293 | ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>(); |
| 294 | int BOpc = !AFI->isThumbFunction() |
| 295 | ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB); |
| 296 | int BccOpc = !AFI->isThumbFunction() |
| 297 | ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 298 | |
| 299 | // Shouldn't be a fall through. |
| 300 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
| 301 | assert((Cond.size() == 2 || Cond.size() == 0) && |
| 302 | "ARM branch conditions have two components!"); |
| 303 | |
| 304 | if (FBB == 0) { |
| 305 | if (Cond.empty()) // Unconditional branch? |
| 306 | BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB); |
| 307 | else |
| 308 | BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) |
| 309 | .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); |
| 310 | return 1; |
| 311 | } |
| 312 | |
| 313 | // Two-way conditional branch. |
| 314 | BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB) |
| 315 | .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()); |
| 316 | BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB); |
| 317 | return 2; |
| 318 | } |
| 319 | |
| 320 | bool ARMBaseInstrInfo:: |
| 321 | ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { |
| 322 | ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm(); |
| 323 | Cond[0].setImm(ARMCC::getOppositeCondition(CC)); |
| 324 | return false; |
| 325 | } |
| 326 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 327 | bool ARMBaseInstrInfo:: |
| 328 | PredicateInstruction(MachineInstr *MI, |
| 329 | const SmallVectorImpl<MachineOperand> &Pred) const { |
| 330 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 331 | if (isUncondBranchOpcode(Opc)) { |
| 332 | MI->setDesc(get(getMatchingCondBranchOpcode(Opc))); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 333 | MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm())); |
| 334 | MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false)); |
| 335 | return true; |
| 336 | } |
| 337 | |
| 338 | int PIdx = MI->findFirstPredOperandIdx(); |
| 339 | if (PIdx != -1) { |
| 340 | MachineOperand &PMO = MI->getOperand(PIdx); |
| 341 | PMO.setImm(Pred[0].getImm()); |
| 342 | MI->getOperand(PIdx+1).setReg(Pred[1].getReg()); |
| 343 | return true; |
| 344 | } |
| 345 | return false; |
| 346 | } |
| 347 | |
| 348 | bool ARMBaseInstrInfo:: |
| 349 | SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, |
| 350 | const SmallVectorImpl<MachineOperand> &Pred2) const { |
| 351 | if (Pred1.size() > 2 || Pred2.size() > 2) |
| 352 | return false; |
| 353 | |
| 354 | ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm(); |
| 355 | ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm(); |
| 356 | if (CC1 == CC2) |
| 357 | return true; |
| 358 | |
| 359 | switch (CC1) { |
| 360 | default: |
| 361 | return false; |
| 362 | case ARMCC::AL: |
| 363 | return true; |
| 364 | case ARMCC::HS: |
| 365 | return CC2 == ARMCC::HI; |
| 366 | case ARMCC::LS: |
| 367 | return CC2 == ARMCC::LO || CC2 == ARMCC::EQ; |
| 368 | case ARMCC::GE: |
| 369 | return CC2 == ARMCC::GT; |
| 370 | case ARMCC::LE: |
| 371 | return CC2 == ARMCC::LT; |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, |
| 376 | std::vector<MachineOperand> &Pred) const { |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame^] | 377 | // FIXME: This confuses implicit_def with optional CPSR def. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 378 | const TargetInstrDesc &TID = MI->getDesc(); |
| 379 | if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) |
| 380 | return false; |
| 381 | |
| 382 | bool Found = false; |
| 383 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { |
| 384 | const MachineOperand &MO = MI->getOperand(i); |
| 385 | if (MO.isReg() && MO.getReg() == ARM::CPSR) { |
| 386 | Pred.push_back(MO); |
| 387 | Found = true; |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | return Found; |
| 392 | } |
| 393 | |
| 394 | |
| 395 | /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing |
| 396 | static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, |
| 397 | unsigned JTI) DISABLE_INLINE; |
| 398 | static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT, |
| 399 | unsigned JTI) { |
| 400 | return JT[JTI].MBBs.size(); |
| 401 | } |
| 402 | |
| 403 | /// GetInstSize - Return the size of the specified MachineInstr. |
| 404 | /// |
| 405 | unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { |
| 406 | const MachineBasicBlock &MBB = *MI->getParent(); |
| 407 | const MachineFunction *MF = MBB.getParent(); |
| 408 | const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo(); |
| 409 | |
| 410 | // Basic size info comes from the TSFlags field. |
| 411 | const TargetInstrDesc &TID = MI->getDesc(); |
| 412 | unsigned TSFlags = TID.TSFlags; |
| 413 | |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 414 | unsigned Opc = MI->getOpcode(); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 415 | switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { |
| 416 | default: { |
| 417 | // If this machine instr is an inline asm, measure it. |
| 418 | if (MI->getOpcode() == ARM::INLINEASM) |
Chris Lattner | d90183d | 2009-08-02 05:20:37 +0000 | [diff] [blame] | 419 | return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *TAI); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 420 | if (MI->isLabel()) |
| 421 | return 0; |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 422 | switch (Opc) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 423 | default: |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 424 | llvm_unreachable("Unknown or unset size field for instr!"); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 425 | case TargetInstrInfo::IMPLICIT_DEF: |
| 426 | case TargetInstrInfo::DECLARE: |
| 427 | case TargetInstrInfo::DBG_LABEL: |
| 428 | case TargetInstrInfo::EH_LABEL: |
| 429 | return 0; |
| 430 | } |
| 431 | break; |
| 432 | } |
Evan Cheng | 7894762 | 2009-07-24 18:20:44 +0000 | [diff] [blame] | 433 | case ARMII::Size8Bytes: return 8; // ARM instruction x 2. |
| 434 | case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. |
| 435 | case ARMII::Size2Bytes: return 2; // Thumb1 instruction. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 436 | case ARMII::SizeSpecial: { |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 437 | switch (Opc) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 438 | case ARM::CONSTPOOL_ENTRY: |
| 439 | // If this machine instr is a constant pool entry, its size is recorded as |
| 440 | // operand #2. |
| 441 | return MI->getOperand(2).getImm(); |
Evan Cheng | 7894762 | 2009-07-24 18:20:44 +0000 | [diff] [blame] | 442 | case ARM::Int_eh_sjlj_setjmp: |
| 443 | return 12; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 444 | case ARM::BR_JTr: |
| 445 | case ARM::BR_JTm: |
| 446 | case ARM::BR_JTadd: |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 447 | case ARM::tBR_JTr: |
Evan Cheng | d26b14c | 2009-07-31 18:28:05 +0000 | [diff] [blame] | 448 | case ARM::t2BR_JT: |
| 449 | case ARM::t2TBB: |
| 450 | case ARM::t2TBH: { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 451 | // These are jumptable branches, i.e. a branch followed by an inlined |
Evan Cheng | d26b14c | 2009-07-31 18:28:05 +0000 | [diff] [blame] | 452 | // jumptable. The size is 4 + 4 * number of entries. For TBB, each |
| 453 | // entry is one byte; TBH two byte each. |
Evan Cheng | a0ee862 | 2009-07-31 22:22:22 +0000 | [diff] [blame] | 454 | unsigned EntrySize = (Opc == ARM::t2TBB) |
| 455 | ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 456 | unsigned NumOps = TID.getNumOperands(); |
| 457 | MachineOperand JTOP = |
| 458 | MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); |
| 459 | unsigned JTI = JTOP.getIndex(); |
| 460 | const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); |
| 461 | const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); |
| 462 | assert(JTI < JT.size()); |
| 463 | // Thumb instructions are 2 byte aligned, but JT entries are 4 byte |
| 464 | // 4 aligned. The assembler / linker may add 2 byte padding just before |
| 465 | // the JT entries. The size does not include this padding; the |
| 466 | // constant islands pass does separate bookkeeping for it. |
| 467 | // FIXME: If we know the size of the function is less than (1 << 16) *2 |
| 468 | // bytes, we can use 16-bit entries instead. Then there won't be an |
| 469 | // alignment issue. |
Evan Cheng | 25f7cfc | 2009-08-01 06:13:52 +0000 | [diff] [blame] | 470 | unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT) ? 2 : 4; |
| 471 | unsigned NumEntries = getNumJTEntries(JT, JTI); |
| 472 | if (Opc == ARM::t2TBB && (NumEntries & 1)) |
| 473 | // Make sure the instruction that follows TBB is 2-byte aligned. |
| 474 | // FIXME: Constant island pass should insert an "ALIGN" instruction |
| 475 | // instead. |
| 476 | ++NumEntries; |
| 477 | return NumEntries * EntrySize + InstSize; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 478 | } |
| 479 | default: |
| 480 | // Otherwise, pseudo-instruction sizes are zero. |
| 481 | return 0; |
| 482 | } |
| 483 | } |
| 484 | } |
| 485 | return 0; // Not reached |
| 486 | } |
| 487 | |
| 488 | /// Return true if the instruction is a register to register move and |
| 489 | /// leave the source and dest operands in the passed parameters. |
| 490 | /// |
| 491 | bool |
| 492 | ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI, |
| 493 | unsigned &SrcReg, unsigned &DstReg, |
| 494 | unsigned& SrcSubIdx, unsigned& DstSubIdx) const { |
| 495 | SrcSubIdx = DstSubIdx = 0; // No sub-registers. |
| 496 | |
Evan Cheng | 68e3c6a | 2009-07-27 00:05:15 +0000 | [diff] [blame] | 497 | switch (MI.getOpcode()) { |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 498 | default: break; |
Evan Cheng | 68e3c6a | 2009-07-27 00:05:15 +0000 | [diff] [blame] | 499 | case ARM::FCPYS: |
| 500 | case ARM::FCPYD: |
| 501 | case ARM::VMOVD: |
| 502 | case ARM::VMOVQ: { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 503 | SrcReg = MI.getOperand(1).getReg(); |
| 504 | DstReg = MI.getOperand(0).getReg(); |
| 505 | return true; |
| 506 | } |
Evan Cheng | 68e3c6a | 2009-07-27 00:05:15 +0000 | [diff] [blame] | 507 | case ARM::MOVr: |
| 508 | case ARM::tMOVr: |
| 509 | case ARM::tMOVgpr2tgpr: |
| 510 | case ARM::tMOVtgpr2gpr: |
| 511 | case ARM::tMOVgpr2gpr: |
| 512 | case ARM::t2MOVr: { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 513 | assert(MI.getDesc().getNumOperands() >= 2 && |
| 514 | MI.getOperand(0).isReg() && |
| 515 | MI.getOperand(1).isReg() && |
| 516 | "Invalid ARM MOV instruction"); |
| 517 | SrcReg = MI.getOperand(1).getReg(); |
| 518 | DstReg = MI.getOperand(0).getReg(); |
| 519 | return true; |
| 520 | } |
Evan Cheng | 68e3c6a | 2009-07-27 00:05:15 +0000 | [diff] [blame] | 521 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 522 | |
| 523 | return false; |
| 524 | } |
| 525 | |
| 526 | unsigned |
| 527 | ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, |
| 528 | int &FrameIndex) const { |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 529 | switch (MI->getOpcode()) { |
| 530 | default: break; |
| 531 | case ARM::LDR: |
| 532 | case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 533 | if (MI->getOperand(1).isFI() && |
| 534 | MI->getOperand(2).isReg() && |
| 535 | MI->getOperand(3).isImm() && |
| 536 | MI->getOperand(2).getReg() == 0 && |
| 537 | MI->getOperand(3).getImm() == 0) { |
| 538 | FrameIndex = MI->getOperand(1).getIndex(); |
| 539 | return MI->getOperand(0).getReg(); |
| 540 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 541 | break; |
| 542 | case ARM::t2LDRi12: |
| 543 | case ARM::tRestore: |
David Goodwin | 5ff58b5 | 2009-07-24 00:16:18 +0000 | [diff] [blame] | 544 | if (MI->getOperand(1).isFI() && |
| 545 | MI->getOperand(2).isImm() && |
| 546 | MI->getOperand(2).getImm() == 0) { |
| 547 | FrameIndex = MI->getOperand(1).getIndex(); |
| 548 | return MI->getOperand(0).getReg(); |
| 549 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 550 | break; |
| 551 | case ARM::FLDD: |
| 552 | case ARM::FLDS: |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 553 | if (MI->getOperand(1).isFI() && |
| 554 | MI->getOperand(2).isImm() && |
| 555 | MI->getOperand(2).getImm() == 0) { |
| 556 | FrameIndex = MI->getOperand(1).getIndex(); |
| 557 | return MI->getOperand(0).getReg(); |
| 558 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 559 | break; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | unsigned |
| 566 | ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, |
| 567 | int &FrameIndex) const { |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 568 | switch (MI->getOpcode()) { |
| 569 | default: break; |
| 570 | case ARM::STR: |
| 571 | case ARM::t2STRs: // FIXME: don't use t2STRs to access frame. |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 572 | if (MI->getOperand(1).isFI() && |
| 573 | MI->getOperand(2).isReg() && |
| 574 | MI->getOperand(3).isImm() && |
| 575 | MI->getOperand(2).getReg() == 0 && |
| 576 | MI->getOperand(3).getImm() == 0) { |
| 577 | FrameIndex = MI->getOperand(1).getIndex(); |
| 578 | return MI->getOperand(0).getReg(); |
| 579 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 580 | break; |
| 581 | case ARM::t2STRi12: |
| 582 | case ARM::tSpill: |
David Goodwin | 5ff58b5 | 2009-07-24 00:16:18 +0000 | [diff] [blame] | 583 | if (MI->getOperand(1).isFI() && |
| 584 | MI->getOperand(2).isImm() && |
| 585 | MI->getOperand(2).getImm() == 0) { |
| 586 | FrameIndex = MI->getOperand(1).getIndex(); |
| 587 | return MI->getOperand(0).getReg(); |
| 588 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 589 | break; |
| 590 | case ARM::FSTD: |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 591 | case ARM::FSTS: |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 592 | if (MI->getOperand(1).isFI() && |
| 593 | MI->getOperand(2).isImm() && |
| 594 | MI->getOperand(2).getImm() == 0) { |
| 595 | FrameIndex = MI->getOperand(1).getIndex(); |
| 596 | return MI->getOperand(0).getReg(); |
| 597 | } |
Evan Cheng | dced03f | 2009-07-27 00:24:36 +0000 | [diff] [blame] | 598 | break; |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 599 | } |
| 600 | |
| 601 | return 0; |
| 602 | } |
| 603 | |
| 604 | bool |
| 605 | ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB, |
| 606 | MachineBasicBlock::iterator I, |
| 607 | unsigned DestReg, unsigned SrcReg, |
| 608 | const TargetRegisterClass *DestRC, |
| 609 | const TargetRegisterClass *SrcRC) const { |
| 610 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 611 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 612 | |
| 613 | if (DestRC != SrcRC) { |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 614 | if (((DestRC == ARM::DPRRegisterClass) && |
| 615 | (SrcRC == ARM::DPR_VFP2RegisterClass)) || |
| 616 | ((SrcRC == ARM::DPRRegisterClass) && |
| 617 | (DestRC == ARM::DPR_VFP2RegisterClass))) { |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 618 | // Allow copy between DPR and DPR_VFP2. |
| 619 | } else { |
| 620 | return false; |
| 621 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 622 | } |
| 623 | |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 624 | if (DestRC == ARM::GPRRegisterClass) { |
Evan Cheng | 08b93c6 | 2009-07-27 00:33:08 +0000 | [diff] [blame] | 625 | AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), |
Evan Cheng | dd6f632 | 2009-07-11 06:37:27 +0000 | [diff] [blame] | 626 | DestReg).addReg(SrcReg))); |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 627 | } else if (DestRC == ARM::SPRRegisterClass) { |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 628 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 629 | .addReg(SrcReg)); |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 630 | } else if ((DestRC == ARM::DPRRegisterClass) || |
| 631 | (DestRC == ARM::DPR_VFP2RegisterClass)) { |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 632 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 633 | .addReg(SrcReg)); |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 634 | } else if (DestRC == ARM::QPRRegisterClass) { |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 635 | BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg); |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 636 | } else { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 637 | return false; |
David Goodwin | 7bfdca0 | 2009-08-05 21:02:22 +0000 | [diff] [blame] | 638 | } |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 639 | |
| 640 | return true; |
| 641 | } |
| 642 | |
| 643 | void ARMBaseInstrInfo:: |
| 644 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 645 | unsigned SrcReg, bool isKill, int FI, |
| 646 | const TargetRegisterClass *RC) const { |
| 647 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 648 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 649 | |
| 650 | if (RC == ARM::GPRRegisterClass) { |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 651 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 652 | .addReg(SrcReg, getKillRegState(isKill)) |
| 653 | .addFrameIndex(FI).addReg(0).addImm(0)); |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 654 | } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 655 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 656 | .addReg(SrcReg, getKillRegState(isKill)) |
| 657 | .addFrameIndex(FI).addImm(0)); |
| 658 | } else { |
| 659 | assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 660 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 661 | .addReg(SrcReg, getKillRegState(isKill)) |
| 662 | .addFrameIndex(FI).addImm(0)); |
| 663 | } |
| 664 | } |
| 665 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 666 | void ARMBaseInstrInfo:: |
| 667 | loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, |
| 668 | unsigned DestReg, int FI, |
| 669 | const TargetRegisterClass *RC) const { |
| 670 | DebugLoc DL = DebugLoc::getUnknownLoc(); |
| 671 | if (I != MBB.end()) DL = I->getDebugLoc(); |
| 672 | |
| 673 | if (RC == ARM::GPRRegisterClass) { |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 674 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 675 | .addFrameIndex(FI).addReg(0).addImm(0)); |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 676 | } else if (RC == ARM::DPRRegisterClass || RC == ARM::DPR_VFP2RegisterClass) { |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 677 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 678 | .addFrameIndex(FI).addImm(0)); |
| 679 | } else { |
| 680 | assert(RC == ARM::SPRRegisterClass && "Unknown regclass!"); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 681 | AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 682 | .addFrameIndex(FI).addImm(0)); |
| 683 | } |
| 684 | } |
| 685 | |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 686 | MachineInstr *ARMBaseInstrInfo:: |
| 687 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, |
| 688 | const SmallVectorImpl<unsigned> &Ops, int FI) const { |
| 689 | if (Ops.size() != 1) return NULL; |
| 690 | |
| 691 | unsigned OpNum = Ops[0]; |
| 692 | unsigned Opc = MI->getOpcode(); |
| 693 | MachineInstr *NewMI = NULL; |
Evan Cheng | 8619864 | 2009-08-07 00:34:42 +0000 | [diff] [blame] | 694 | if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { // FIXME: tMOVgpr2gpr etc.? |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 695 | // If it is updating CPSR, then it cannot be folded. |
Evan Cheng | 1f5c988 | 2009-07-27 04:18:04 +0000 | [diff] [blame] | 696 | if (MI->getOperand(4).getReg() != ARM::CPSR || MI->getOperand(4).isDead()) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 697 | unsigned Pred = MI->getOperand(2).getImm(); |
| 698 | unsigned PredReg = MI->getOperand(3).getReg(); |
| 699 | if (OpNum == 0) { // move -> store |
| 700 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 701 | bool isKill = MI->getOperand(1).isKill(); |
| 702 | bool isUndef = MI->getOperand(1).isUndef(); |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 703 | if (Opc == ARM::MOVr) |
| 704 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) |
| 705 | .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 706 | .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); |
| 707 | else // ARM::t2MOVr |
| 708 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12)) |
| 709 | .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 710 | .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 711 | } else { // move -> load |
| 712 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 713 | bool isDead = MI->getOperand(0).isDead(); |
| 714 | bool isUndef = MI->getOperand(0).isUndef(); |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 715 | if (Opc == ARM::MOVr) |
| 716 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) |
| 717 | .addReg(DstReg, |
| 718 | RegState::Define | |
| 719 | getDeadRegState(isDead) | |
| 720 | getUndefRegState(isUndef)) |
| 721 | .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); |
| 722 | else // ARM::t2MOVr |
| 723 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12)) |
| 724 | .addReg(DstReg, |
| 725 | RegState::Define | |
| 726 | getDeadRegState(isDead) | |
| 727 | getUndefRegState(isUndef)) |
| 728 | .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 729 | } |
| 730 | } |
| 731 | } |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 732 | else if (Opc == ARM::FCPYS) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 733 | unsigned Pred = MI->getOperand(2).getImm(); |
| 734 | unsigned PredReg = MI->getOperand(3).getReg(); |
| 735 | if (OpNum == 0) { // move -> store |
| 736 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 737 | bool isKill = MI->getOperand(1).isKill(); |
| 738 | bool isUndef = MI->getOperand(1).isUndef(); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 739 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 740 | .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 741 | .addFrameIndex(FI) |
| 742 | .addImm(0).addImm(Pred).addReg(PredReg); |
| 743 | } else { // move -> load |
| 744 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 745 | bool isDead = MI->getOperand(0).isDead(); |
| 746 | bool isUndef = MI->getOperand(0).isUndef(); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 747 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 748 | .addReg(DstReg, |
| 749 | RegState::Define | |
| 750 | getDeadRegState(isDead) | |
| 751 | getUndefRegState(isUndef)) |
| 752 | .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); |
| 753 | } |
| 754 | } |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 755 | else if (Opc == ARM::FCPYD) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 756 | unsigned Pred = MI->getOperand(2).getImm(); |
| 757 | unsigned PredReg = MI->getOperand(3).getReg(); |
| 758 | if (OpNum == 0) { // move -> store |
| 759 | unsigned SrcReg = MI->getOperand(1).getReg(); |
| 760 | bool isKill = MI->getOperand(1).isKill(); |
| 761 | bool isUndef = MI->getOperand(1).isUndef(); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 762 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 763 | .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) |
| 764 | .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); |
| 765 | } else { // move -> load |
| 766 | unsigned DstReg = MI->getOperand(0).getReg(); |
| 767 | bool isDead = MI->getOperand(0).isDead(); |
| 768 | bool isUndef = MI->getOperand(0).isUndef(); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 769 | NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 770 | .addReg(DstReg, |
| 771 | RegState::Define | |
| 772 | getDeadRegState(isDead) | |
| 773 | getUndefRegState(isUndef)) |
| 774 | .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); |
| 775 | } |
| 776 | } |
| 777 | |
| 778 | return NewMI; |
| 779 | } |
| 780 | |
| 781 | MachineInstr* |
| 782 | ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, |
| 783 | MachineInstr* MI, |
| 784 | const SmallVectorImpl<unsigned> &Ops, |
| 785 | MachineInstr* LoadMI) const { |
Evan Cheng | 1f5c988 | 2009-07-27 04:18:04 +0000 | [diff] [blame] | 786 | // FIXME |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 787 | return 0; |
| 788 | } |
| 789 | |
| 790 | bool |
| 791 | ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, |
| 792 | const SmallVectorImpl<unsigned> &Ops) const { |
| 793 | if (Ops.size() != 1) return false; |
| 794 | |
| 795 | unsigned Opc = MI->getOpcode(); |
Evan Cheng | 5732ca0 | 2009-07-27 03:14:20 +0000 | [diff] [blame] | 796 | if (Opc == ARM::MOVr || Opc == ARM::t2MOVr) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 797 | // If it is updating CPSR, then it cannot be folded. |
Evan Cheng | 1f5c988 | 2009-07-27 04:18:04 +0000 | [diff] [blame] | 798 | return MI->getOperand(4).getReg() != ARM::CPSR ||MI->getOperand(4).isDead(); |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 799 | } else if (Opc == ARM::FCPYS || Opc == ARM::FCPYD) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 800 | return true; |
Evan Cheng | b74bb1a | 2009-07-24 00:53:56 +0000 | [diff] [blame] | 801 | } else if (Opc == ARM::VMOVD || Opc == ARM::VMOVQ) { |
David Goodwin | 334c264 | 2009-07-08 16:09:28 +0000 | [diff] [blame] | 802 | return false; // FIXME |
| 803 | } |
| 804 | |
| 805 | return false; |
| 806 | } |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 807 | |
Evan Cheng | 8fb9036 | 2009-08-08 03:20:32 +0000 | [diff] [blame^] | 808 | /// getInstrPredicate - If instruction is predicated, returns its predicate |
| 809 | /// condition, otherwise returns AL. It also returns the condition code |
| 810 | /// register by reference. |
| 811 | ARMCC::CondCodes llvm::getInstrPredicate(MachineInstr *MI, unsigned &PredReg) { |
| 812 | int PIdx = MI->findFirstPredOperandIdx(); |
| 813 | if (PIdx == -1) { |
| 814 | PredReg = 0; |
| 815 | return ARMCC::AL; |
| 816 | } |
| 817 | |
| 818 | PredReg = MI->getOperand(PIdx+1).getReg(); |
| 819 | return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm(); |
| 820 | } |
| 821 | |
| 822 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 823 | int llvm::getMatchingCondBranchOpcode(int Opc) { |
Evan Cheng | 5ca53a7 | 2009-07-27 18:20:05 +0000 | [diff] [blame] | 824 | if (Opc == ARM::B) |
| 825 | return ARM::Bcc; |
| 826 | else if (Opc == ARM::tB) |
| 827 | return ARM::tBcc; |
| 828 | else if (Opc == ARM::t2B) |
| 829 | return ARM::t2Bcc; |
| 830 | |
| 831 | llvm_unreachable("Unknown unconditional branch opcode!"); |
| 832 | return 0; |
| 833 | } |
| 834 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 835 | |
| 836 | void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB, |
| 837 | MachineBasicBlock::iterator &MBBI, DebugLoc dl, |
| 838 | unsigned DestReg, unsigned BaseReg, int NumBytes, |
| 839 | ARMCC::CondCodes Pred, unsigned PredReg, |
| 840 | const ARMBaseInstrInfo &TII) { |
| 841 | bool isSub = NumBytes < 0; |
| 842 | if (isSub) NumBytes = -NumBytes; |
| 843 | |
| 844 | while (NumBytes) { |
| 845 | unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes); |
| 846 | unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt); |
| 847 | assert(ThisVal && "Didn't extract field correctly"); |
| 848 | |
| 849 | // We will handle these bits from offset, clear them. |
| 850 | NumBytes &= ~ThisVal; |
| 851 | |
| 852 | assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?"); |
| 853 | |
| 854 | // Build the new ADD / SUB. |
| 855 | unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; |
| 856 | BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) |
| 857 | .addReg(BaseReg, RegState::Kill).addImm(ThisVal) |
| 858 | .addImm((unsigned)Pred).addReg(PredReg).addReg(0); |
| 859 | BaseReg = DestReg; |
| 860 | } |
| 861 | } |
| 862 | |
| 863 | int llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx, |
| 864 | unsigned FrameReg, int Offset, |
| 865 | const ARMBaseInstrInfo &TII) { |
| 866 | unsigned Opcode = MI.getOpcode(); |
| 867 | const TargetInstrDesc &Desc = MI.getDesc(); |
| 868 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 869 | bool isSub = false; |
| 870 | |
| 871 | // Memory operands in inline assembly always use AddrMode2. |
| 872 | if (Opcode == ARM::INLINEASM) |
| 873 | AddrMode = ARMII::AddrMode2; |
| 874 | |
| 875 | if (Opcode == ARM::ADDri) { |
| 876 | Offset += MI.getOperand(FrameRegIdx+1).getImm(); |
| 877 | if (Offset == 0) { |
| 878 | // Turn it into a move. |
| 879 | MI.setDesc(TII.get(ARM::MOVr)); |
| 880 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 881 | MI.RemoveOperand(FrameRegIdx+1); |
| 882 | return 0; |
| 883 | } else if (Offset < 0) { |
| 884 | Offset = -Offset; |
| 885 | isSub = true; |
| 886 | MI.setDesc(TII.get(ARM::SUBri)); |
| 887 | } |
| 888 | |
| 889 | // Common case: small offset, fits into instruction. |
| 890 | if (ARM_AM::getSOImmVal(Offset) != -1) { |
| 891 | // Replace the FrameIndex with sp / fp |
| 892 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 893 | MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); |
| 894 | return 0; |
| 895 | } |
| 896 | |
| 897 | // Otherwise, pull as much of the immedidate into this ADDri/SUBri |
| 898 | // as possible. |
| 899 | unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset); |
| 900 | unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt); |
| 901 | |
| 902 | // We will handle these bits from offset, clear them. |
| 903 | Offset &= ~ThisImmVal; |
| 904 | |
| 905 | // Get the properly encoded SOImmVal field. |
| 906 | assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 && |
| 907 | "Bit extraction didn't work?"); |
| 908 | MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal); |
| 909 | } else { |
| 910 | unsigned ImmIdx = 0; |
| 911 | int InstrOffs = 0; |
| 912 | unsigned NumBits = 0; |
| 913 | unsigned Scale = 1; |
| 914 | switch (AddrMode) { |
| 915 | case ARMII::AddrMode2: { |
| 916 | ImmIdx = FrameRegIdx+2; |
| 917 | InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm()); |
| 918 | if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 919 | InstrOffs *= -1; |
| 920 | NumBits = 12; |
| 921 | break; |
| 922 | } |
| 923 | case ARMII::AddrMode3: { |
| 924 | ImmIdx = FrameRegIdx+2; |
| 925 | InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm()); |
| 926 | if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 927 | InstrOffs *= -1; |
| 928 | NumBits = 8; |
| 929 | break; |
| 930 | } |
| 931 | case ARMII::AddrMode5: { |
| 932 | ImmIdx = FrameRegIdx+1; |
| 933 | InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm()); |
| 934 | if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 935 | InstrOffs *= -1; |
| 936 | NumBits = 8; |
| 937 | Scale = 4; |
| 938 | break; |
| 939 | } |
| 940 | default: |
| 941 | llvm_unreachable("Unsupported addressing mode!"); |
| 942 | break; |
| 943 | } |
| 944 | |
| 945 | Offset += InstrOffs * Scale; |
| 946 | assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!"); |
| 947 | if (Offset < 0) { |
| 948 | Offset = -Offset; |
| 949 | isSub = true; |
| 950 | } |
| 951 | |
| 952 | // Attempt to fold address comp. if opcode has offset bits |
| 953 | if (NumBits > 0) { |
| 954 | // Common case: small offset, fits into instruction. |
| 955 | MachineOperand &ImmOp = MI.getOperand(ImmIdx); |
| 956 | int ImmedOffset = Offset / Scale; |
| 957 | unsigned Mask = (1 << NumBits) - 1; |
| 958 | if ((unsigned)Offset <= Mask * Scale) { |
| 959 | // Replace the FrameIndex with sp |
| 960 | MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); |
| 961 | if (isSub) |
| 962 | ImmedOffset |= 1 << NumBits; |
| 963 | ImmOp.ChangeToImmediate(ImmedOffset); |
| 964 | return 0; |
| 965 | } |
| 966 | |
| 967 | // Otherwise, it didn't fit. Pull in what we can to simplify the immed. |
| 968 | ImmedOffset = ImmedOffset & Mask; |
| 969 | if (isSub) |
| 970 | ImmedOffset |= 1 << NumBits; |
| 971 | ImmOp.ChangeToImmediate(ImmedOffset); |
| 972 | Offset &= ~(Mask*Scale); |
| 973 | } |
| 974 | } |
| 975 | |
| 976 | return (isSub) ? -Offset : Offset; |
| 977 | } |