| David Greene | d1834cd | 2009-06-08 22:20:58 +0000 | [diff] [blame] | 1 | // RUN: tblgen %s | grep {\\\[(set} | count 2 |
| 2 | // RUN: tblgen %s | grep {\\\[\\\]} | count 2 |
| David Greene | f2db6e2 | 2009-06-08 20:23:18 +0000 | [diff] [blame] | 3 | |
| 4 | class ValueType<int size, int value> { |
| 5 | int Size = size; |
| 6 | int Value = value; |
| 7 | } |
| 8 | |
| 9 | def f32 : ValueType<32, 1>; // 2 x i64 vector value |
| 10 | |
| 11 | class Intrinsic<string name> { |
| 12 | string Name = name; |
| 13 | } |
| 14 | |
| 15 | class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, |
| 16 | list<dag> pattern> { |
| 17 | bits<8> Opcode = opcode; |
| 18 | dag OutOperands = oopnds; |
| 19 | dag InOperands = iopnds; |
| 20 | string AssemblyString = asmstr; |
| 21 | list<dag> Pattern = pattern; |
| 22 | } |
| 23 | |
| 24 | def ops; |
| 25 | def outs; |
| 26 | def ins; |
| 27 | |
| 28 | def set; |
| 29 | |
| 30 | // Define registers |
| 31 | class Register<string n> { |
| 32 | string Name = n; |
| 33 | } |
| 34 | |
| 35 | class RegisterClass<list<ValueType> regTypes, list<Register> regList> { |
| 36 | list<ValueType> RegTypes = regTypes; |
| 37 | list<Register> MemberList = regList; |
| 38 | } |
| 39 | |
| 40 | def XMM0: Register<"xmm0">; |
| 41 | def XMM1: Register<"xmm1">; |
| 42 | def XMM2: Register<"xmm2">; |
| 43 | def XMM3: Register<"xmm3">; |
| 44 | def XMM4: Register<"xmm4">; |
| 45 | def XMM5: Register<"xmm5">; |
| 46 | def XMM6: Register<"xmm6">; |
| 47 | def XMM7: Register<"xmm7">; |
| 48 | def XMM8: Register<"xmm8">; |
| 49 | def XMM9: Register<"xmm9">; |
| 50 | def XMM10: Register<"xmm10">; |
| 51 | def XMM11: Register<"xmm11">; |
| 52 | def XMM12: Register<"xmm12">; |
| 53 | def XMM13: Register<"xmm13">; |
| 54 | def XMM14: Register<"xmm14">; |
| 55 | def XMM15: Register<"xmm15">; |
| 56 | |
| 57 | def FR32 : RegisterClass<[f32], |
| 58 | [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, |
| 59 | XMM8, XMM9, XMM10, XMM11, |
| 60 | XMM12, XMM13, XMM14, XMM15]>; |
| 61 | |
| 62 | class SDNode {} |
| 63 | def not : SDNode; |
| 64 | |
| 65 | multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { |
| 66 | def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), |
| 67 | !strconcat(asmstr, "\t$dst, $src"), |
| 68 | !if(!null(patterns),[]<dag>,patterns[0])>; |
| 69 | def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), |
| 70 | !strconcat(asmstr, "\t$dst, $src"), |
| 71 | !if(!null(patterns),[]<dag>,!if(!null(!cdr(patterns)),patterns[0],patterns[1]))>; |
| 72 | } |
| 73 | |
| 74 | multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { |
| 75 | def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), |
| 76 | !strconcat(asmstr, "\t$dst, $src"), |
| 77 | !if(!null(patterns),[]<dag>,patterns[0])>; |
| 78 | def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), |
| 79 | !strconcat(asmstr, "\t$dst, $src"), |
| 80 | !if(!null(patterns),[]<dag>,!if(!null(!cdr(patterns)),patterns[0],patterns[1]))>; |
| 81 | } |
| 82 | |
| 83 | multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> : |
| 84 | scalar<opcode, asmstr, patterns>, |
| 85 | vscalar<opcode, asmstr, patterns>; |
| 86 | |
| 87 | defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>; |