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Jia Liuc5707112012-02-17 08:55:11 +00001//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +00009//
Akira Hatanakaa3defb02011-09-29 23:52:13 +000010// Simple pass to fills delay slots with useful instructions.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000011//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000012//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000013
14#define DEBUG_TYPE "delay-slot-filler"
15
16#include "Mips.h"
17#include "MipsTargetMachine.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +000018#include "llvm/ADT/SmallSet.h"
19#include "llvm/ADT/Statistic.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000020#include "llvm/CodeGen/MachineFunctionPass.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000022#include "llvm/Support/CommandLine.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000023#include "llvm/Target/TargetInstrInfo.h"
Chandler Carruthd04a8d42012-12-03 16:50:05 +000024#include "llvm/Target/TargetMachine.h"
Akira Hatanakaa3defb02011-09-29 23:52:13 +000025#include "llvm/Target/TargetRegisterInfo.h"
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000026
27using namespace llvm;
28
29STATISTIC(FilledSlots, "Number of delay slots filled");
Akira Hatanaka98f4d4d2011-10-05 01:19:13 +000030STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
Akira Hatanaka176965f2011-10-05 02:22:49 +000031 " are not NOP.");
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000032
Akira Hatanaka6522a9e2012-08-22 02:51:28 +000033static cl::opt<bool> DisableDelaySlotFiller(
34 "disable-mips-delay-filler",
Akira Hatanakaa3defb02011-09-29 23:52:13 +000035 cl::init(false),
Akira Hatanaka6522a9e2012-08-22 02:51:28 +000036 cl::desc("Disable the delay slot filler, which attempts to fill the Mips"
37 "delay slots with useful instructions."),
Akira Hatanakaa3defb02011-09-29 23:52:13 +000038 cl::Hidden);
39
Akira Hatanakaf9c3f3b2012-05-14 23:59:17 +000040// This option can be used to silence complaints by machine verifier passes.
41static cl::opt<bool> SkipDelaySlotFiller(
42 "skip-mips-delay-filler",
43 cl::init(false),
44 cl::desc("Skip MIPS' delay slot filling pass."),
45 cl::Hidden);
46
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000047namespace {
Akira Hatanaka5dd41c92013-02-07 21:32:32 +000048 class Filler : public MachineFunctionPass {
49 public:
Bruno Cardoso Lopes90c59542010-12-09 17:31:11 +000050 Filler(TargetMachine &tm)
Owen Anderson90c579d2010-08-06 18:33:48 +000051 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000052
53 virtual const char *getPassName() const {
54 return "Mips Delay Slot Filler";
55 }
56
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000057 bool runOnMachineFunction(MachineFunction &F) {
Akira Hatanakaf9c3f3b2012-05-14 23:59:17 +000058 if (SkipDelaySlotFiller)
59 return false;
60
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +000061 bool Changed = false;
62 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
63 FI != FE; ++FI)
64 Changed |= runOnMachineBasicBlock(*FI);
65 return Changed;
66 }
67
Akira Hatanaka5dd41c92013-02-07 21:32:32 +000068 private:
Akira Hatanakaeba97c52013-02-14 23:11:24 +000069 typedef MachineBasicBlock::iterator Iter;
70 typedef MachineBasicBlock::reverse_iterator ReverseIter;
Akira Hatanaka5dd41c92013-02-07 21:32:32 +000071
72 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
73
Akira Hatanakaa3defb02011-09-29 23:52:13 +000074 bool isDelayFiller(MachineBasicBlock &MBB,
Akira Hatanakaeba97c52013-02-14 23:11:24 +000075 Iter candidate);
Akira Hatanakaa3defb02011-09-29 23:52:13 +000076
Akira Hatanakaeba97c52013-02-14 23:11:24 +000077 void insertCallUses(Iter MI,
Akira Hatanaka864f6602012-06-14 21:10:56 +000078 SmallSet<unsigned, 32> &RegDefs,
79 SmallSet<unsigned, 32> &RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +000080
Akira Hatanakaeba97c52013-02-14 23:11:24 +000081 void insertDefsUses(Iter MI,
Akira Hatanaka864f6602012-06-14 21:10:56 +000082 SmallSet<unsigned, 32> &RegDefs,
83 SmallSet<unsigned, 32> &RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +000084
Akira Hatanaka864f6602012-06-14 21:10:56 +000085 bool IsRegInSet(SmallSet<unsigned, 32> &RegSet,
Akira Hatanakaa3defb02011-09-29 23:52:13 +000086 unsigned Reg);
87
Akira Hatanakaeba97c52013-02-14 23:11:24 +000088 bool delayHasHazard(Iter candidate,
Akira Hatanakaa3defb02011-09-29 23:52:13 +000089 bool &sawLoad, bool &sawStore,
90 SmallSet<unsigned, 32> &RegDefs,
91 SmallSet<unsigned, 32> &RegUses);
92
Akira Hatanaka6f818ab2011-10-05 01:23:39 +000093 bool
Akira Hatanakaeba97c52013-02-14 23:11:24 +000094 findDelayInstr(MachineBasicBlock &MBB, Iter slot,
95 Iter &Filler);
96
97 bool terminateSearch(const MachineInstr &Candidate) const;
Akira Hatanakaa3defb02011-09-29 23:52:13 +000098
Akira Hatanaka5dd41c92013-02-07 21:32:32 +000099 TargetMachine &TM;
100 const TargetInstrInfo *TII;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000101
Akira Hatanaka5dd41c92013-02-07 21:32:32 +0000102 static char ID;
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000103 };
104 char Filler::ID = 0;
105} // end of anonymous namespace
106
107/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000108/// We assume there is only one delay slot per delayed instruction.
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000109bool Filler::
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000110runOnMachineBasicBlock(MachineBasicBlock &MBB) {
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000111 bool Changed = false;
Akira Hatanaka53120e02011-10-05 01:30:09 +0000112
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000113 for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
Akira Hatanaka5dd41c92013-02-07 21:32:32 +0000114 if (!I->hasDelaySlot())
115 continue;
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000116
Akira Hatanaka5dd41c92013-02-07 21:32:32 +0000117 ++FilledSlots;
118 Changed = true;
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000119 Iter D;
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000120
Akira Hatanaka5dd41c92013-02-07 21:32:32 +0000121 // Delay slot filling is disabled at -O0.
122 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
123 findDelayInstr(MBB, I, D)) {
124 MBB.splice(llvm::next(I), &MBB, D);
125 ++UsefulSlots;
126 } else
127 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
Akira Hatanaka15841392012-06-13 23:25:52 +0000128
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000129 // Bundle the delay slot filler to the instruction with the delay slot.
130 MIBundleBuilder(MBB, I, llvm::next(llvm::next(I)));
Akira Hatanaka5dd41c92013-02-07 21:32:32 +0000131 }
132
Bruno Cardoso Lopes9684a692007-08-18 01:50:47 +0000133 return Changed;
134}
135
136/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
137/// slots in Mips MachineFunctions
138FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
139 return new Filler(tm);
140}
141
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000142bool Filler::findDelayInstr(MachineBasicBlock &MBB,
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000143 Iter slot,
144 Iter &Filler) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000145 SmallSet<unsigned, 32> RegDefs;
146 SmallSet<unsigned, 32> RegUses;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000147
Akira Hatanaka0f0c59a02011-10-05 02:04:17 +0000148 insertDefsUses(slot, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000149
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000150 bool sawLoad = false;
151 bool sawStore = false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000152
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000153 for (ReverseIter I(slot); I != MBB.rend(); ++I) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000154 // skip debug value
155 if (I->isDebugValue())
156 continue;
157
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000158 if (terminateSearch(*I))
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000159 break;
160
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000161 // Convert to forward iterator.
162 Iter FI(llvm::next(I).base());
163
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000164 if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
165 insertDefsUses(FI, RegDefs, RegUses);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000166 continue;
167 }
168
Akira Hatanaka7d8e04d2011-10-05 01:57:46 +0000169 Filler = FI;
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000170 return true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000171 }
Akira Hatanaka6f818ab2011-10-05 01:23:39 +0000172
173 return false;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000174}
175
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000176bool Filler::delayHasHazard(Iter candidate,
Akira Hatanaka82099682011-12-19 19:52:25 +0000177 bool &sawLoad, bool &sawStore,
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000178 SmallSet<unsigned, 32> &RegDefs,
179 SmallSet<unsigned, 32> &RegUses) {
180 if (candidate->isImplicitDef() || candidate->isKill())
181 return true;
182
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000183 // Loads or stores cannot be moved past a store to the delay slot
Jia Liubb481f82012-02-28 07:46:26 +0000184 // and stores cannot be moved past a load.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000185 if (candidate->mayLoad()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000186 if (sawStore)
187 return true;
Akira Hatanakacfc3fb52011-10-05 01:09:37 +0000188 sawLoad = true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000189 }
190
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000191 if (candidate->mayStore()) {
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000192 if (sawStore)
193 return true;
194 sawStore = true;
195 if (sawLoad)
196 return true;
197 }
198
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000199 assert((!candidate->isCall() && !candidate->isReturn()) &&
Akira Hatanaka42be2802011-10-05 18:17:49 +0000200 "Cannot put calls or returns in delay slot.");
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000201
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000202 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
203 const MachineOperand &MO = candidate->getOperand(i);
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000204 unsigned Reg;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000205
Akira Hatanaka0c419a72011-10-05 02:18:58 +0000206 if (!MO.isReg() || !(Reg = MO.getReg()))
207 continue; // skip
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000208
209 if (MO.isDef()) {
210 // check whether Reg is defined or used before delay slot.
211 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
212 return true;
213 }
214 if (MO.isUse()) {
215 // check whether Reg is defined before delay slot.
216 if (IsRegInSet(RegDefs, Reg))
217 return true;
218 }
219 }
220 return false;
221}
222
Akira Hatanakaa032dbd2012-11-16 02:39:34 +0000223// Helper function for getting a MachineOperand's register number and adding it
224// to RegDefs or RegUses.
225static void insertDefUse(const MachineOperand &MO,
226 SmallSet<unsigned, 32> &RegDefs,
227 SmallSet<unsigned, 32> &RegUses,
228 unsigned ExcludedReg = 0) {
229 unsigned Reg;
230
231 if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
232 return;
233
234 if (MO.isDef())
235 RegDefs.insert(Reg);
236 else if (MO.isUse())
237 RegUses.insert(Reg);
238}
239
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000240// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000241void Filler::insertDefsUses(Iter MI,
Akira Hatanaka864f6602012-06-14 21:10:56 +0000242 SmallSet<unsigned, 32> &RegDefs,
243 SmallSet<unsigned, 32> &RegUses) {
Akira Hatanakaa032dbd2012-11-16 02:39:34 +0000244 unsigned I, E = MI->getDesc().getNumOperands();
Jia Liubb481f82012-02-28 07:46:26 +0000245
Akira Hatanakaa032dbd2012-11-16 02:39:34 +0000246 for (I = 0; I != E; ++I)
247 insertDefUse(MI->getOperand(I), RegDefs, RegUses);
248
249 // If MI is a call, add RA to RegDefs to prevent users of RA from going into
250 // delay slot.
251 if (MI->isCall()) {
Akira Hatanaka2f523382011-10-05 18:11:44 +0000252 RegDefs.insert(Mips::RA);
Akira Hatanakaa032dbd2012-11-16 02:39:34 +0000253 return;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000254 }
Akira Hatanakaa032dbd2012-11-16 02:39:34 +0000255
256 // Return if MI is a return.
257 if (MI->isReturn())
258 return;
259
260 // Examine the implicit operands. Exclude register AT which is in the list of
261 // clobbered registers of branch instructions.
262 E = MI->getNumOperands();
263 for (; I != E; ++I)
264 insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000265}
266
267//returns true if the Reg or its alias is in the RegSet.
Akira Hatanaka864f6602012-06-14 21:10:56 +0000268bool Filler::IsRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
Jakob Stoklund Olesenf152fe82012-06-01 20:36:54 +0000269 // Check Reg and all aliased Registers.
270 for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
271 AI.isValid(); ++AI)
272 if (RegSet.count(*AI))
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000273 return true;
Akira Hatanakaa3defb02011-09-29 23:52:13 +0000274 return false;
275}
Akira Hatanakaeba97c52013-02-14 23:11:24 +0000276
277bool Filler::terminateSearch(const MachineInstr &Candidate) const {
278 return (Candidate.isTerminator() || Candidate.isCall() ||
279 Candidate.isLabel() || Candidate.isInlineAsm() ||
280 Candidate.hasUnmodeledSideEffects());
281}