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Misha Brukman5dfe3a92004-06-21 16:55:25 +00001//===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Misha Brukman98649d12004-06-24 21:54:47 +000010#define DEBUG_TYPE "isel"
Misha Brukman5dfe3a92004-06-21 16:55:25 +000011#include "PowerPC.h"
12#include "PowerPCInstrBuilder.h"
13#include "PowerPCInstrInfo.h"
14#include "llvm/Constants.h"
15#include "llvm/DerivedTypes.h"
16#include "llvm/Function.h"
17#include "llvm/Instructions.h"
Misha Brukman5dfe3a92004-06-21 16:55:25 +000018#include "llvm/Pass.h"
Misha Brukman8c9f5202004-06-21 18:30:31 +000019#include "llvm/CodeGen/IntrinsicLowering.h"
Misha Brukman5dfe3a92004-06-21 16:55:25 +000020#include "llvm/CodeGen/MachineConstantPool.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/MRegisterInfo.h"
25#include "llvm/Target/TargetMachine.h"
26#include "llvm/Support/GetElementPtrTypeIterator.h"
27#include "llvm/Support/InstVisitor.h"
Misha Brukman98649d12004-06-24 21:54:47 +000028#include "Support/Debug.h"
29#include <vector>
Misha Brukman5dfe3a92004-06-21 16:55:25 +000030using namespace llvm;
31
32namespace {
Misha Brukman422791f2004-06-21 17:41:12 +000033 /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
34 /// PPC Representation.
Misha Brukman5dfe3a92004-06-21 16:55:25 +000035 ///
36 enum TypeClass {
37 cByte, cShort, cInt, cFP, cLong
38 };
39}
40
41/// getClass - Turn a primitive type into a "class" number which is based on the
42/// size of the type, and whether or not it is floating point.
43///
44static inline TypeClass getClass(const Type *Ty) {
Misha Brukman358829f2004-06-21 17:25:55 +000045 switch (Ty->getTypeID()) {
Misha Brukman5dfe3a92004-06-21 16:55:25 +000046 case Type::SByteTyID:
47 case Type::UByteTyID: return cByte; // Byte operands are class #0
48 case Type::ShortTyID:
49 case Type::UShortTyID: return cShort; // Short operands are class #1
50 case Type::IntTyID:
51 case Type::UIntTyID:
52 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
53
54 case Type::FloatTyID:
55 case Type::DoubleTyID: return cFP; // Floating Point is #3
56
57 case Type::LongTyID:
58 case Type::ULongTyID: return cLong; // Longs are class #4
59 default:
60 assert(0 && "Invalid type to getClass!");
61 return cByte; // not reached
62 }
63}
64
65// getClassB - Just like getClass, but treat boolean values as ints.
66static inline TypeClass getClassB(const Type *Ty) {
67 if (Ty == Type::BoolTy) return cInt;
68 return getClass(Ty);
69}
70
71namespace {
72 struct ISel : public FunctionPass, InstVisitor<ISel> {
73 TargetMachine &TM;
74 MachineFunction *F; // The function we are compiling into
75 MachineBasicBlock *BB; // The current MBB we are compiling
76 int VarArgsFrameIndex; // FrameIndex for start of varargs area
77 int ReturnAddressIndex; // FrameIndex for the return address
78
79 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
80
81 // MBBMap - Mapping between LLVM BB -> Machine BB
82 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
83
84 // AllocaMap - Mapping from fixed sized alloca instructions to the
85 // FrameIndex for the alloca.
86 std::map<AllocaInst*, unsigned> AllocaMap;
87
88 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
89
90 /// runOnFunction - Top level implementation of instruction selection for
91 /// the entire function.
92 ///
93 bool runOnFunction(Function &Fn) {
94 // First pass over the function, lower any unknown intrinsic functions
95 // with the IntrinsicLowering class.
96 LowerUnknownIntrinsicFunctionCalls(Fn);
97
98 F = &MachineFunction::construct(&Fn, TM);
99
100 // Create all of the machine basic blocks for the function...
101 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
102 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
103
104 BB = &F->front();
105
106 // Set up a frame object for the return address. This is used by the
107 // llvm.returnaddress & llvm.frameaddress intrinisics.
108 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
109
110 // Copy incoming arguments off of the stack...
111 LoadArgumentsToVirtualRegs(Fn);
112
113 // Instruction select everything except PHI nodes
114 visit(Fn);
115
116 // Select the PHI nodes
117 SelectPHINodes();
118
119 RegMap.clear();
120 MBBMap.clear();
121 AllocaMap.clear();
122 F = 0;
123 // We always build a machine code representation for the function
124 return true;
125 }
126
127 virtual const char *getPassName() const {
128 return "PowerPC Simple Instruction Selection";
129 }
130
131 /// visitBasicBlock - This method is called when we are visiting a new basic
132 /// block. This simply creates a new MachineBasicBlock to emit code into
133 /// and adds it to the current MachineFunction. Subsequent visit* for
134 /// instructions will be invoked for all instructions in the basic block.
135 ///
136 void visitBasicBlock(BasicBlock &LLVM_BB) {
137 BB = MBBMap[&LLVM_BB];
138 }
139
140 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
141 /// function, lowering any calls to unknown intrinsic functions into the
142 /// equivalent LLVM code.
143 ///
144 void LowerUnknownIntrinsicFunctionCalls(Function &F);
145
146 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
147 /// from the stack into virtual registers.
148 ///
149 void LoadArgumentsToVirtualRegs(Function &F);
150
151 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
152 /// because we have to generate our sources into the source basic blocks,
153 /// not the current one.
154 ///
155 void SelectPHINodes();
156
157 // Visitation methods for various instructions. These methods simply emit
158 // fixed PowerPC code for each instruction.
159
160 // Control flow operators
161 void visitReturnInst(ReturnInst &RI);
162 void visitBranchInst(BranchInst &BI);
163
164 struct ValueRecord {
165 Value *Val;
166 unsigned Reg;
167 const Type *Ty;
168 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
169 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
170 };
171 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
172 const std::vector<ValueRecord> &Args);
173 void visitCallInst(CallInst &I);
174 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
175
176 // Arithmetic operators
177 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
178 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
179 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
180 void visitMul(BinaryOperator &B);
181
182 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
183 void visitRem(BinaryOperator &B) { visitDivRem(B); }
184 void visitDivRem(BinaryOperator &B);
185
186 // Bitwise operators
187 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
188 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
189 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
190
191 // Comparison operators...
192 void visitSetCondInst(SetCondInst &I);
193 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
194 MachineBasicBlock *MBB,
195 MachineBasicBlock::iterator MBBI);
196 void visitSelectInst(SelectInst &SI);
197
198
199 // Memory Instructions
200 void visitLoadInst(LoadInst &I);
201 void visitStoreInst(StoreInst &I);
202 void visitGetElementPtrInst(GetElementPtrInst &I);
203 void visitAllocaInst(AllocaInst &I);
204 void visitMallocInst(MallocInst &I);
205 void visitFreeInst(FreeInst &I);
206
207 // Other operators
208 void visitShiftInst(ShiftInst &I);
209 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
210 void visitCastInst(CastInst &I);
211 void visitVANextInst(VANextInst &I);
212 void visitVAArgInst(VAArgInst &I);
213
214 void visitInstruction(Instruction &I) {
215 std::cerr << "Cannot instruction select: " << I;
216 abort();
217 }
218
219 /// promote32 - Make a value 32-bits wide, and put it somewhere.
220 ///
221 void promote32(unsigned targetReg, const ValueRecord &VR);
222
223 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
224 /// constant expression GEP support.
225 ///
226 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
227 Value *Src, User::op_iterator IdxBegin,
228 User::op_iterator IdxEnd, unsigned TargetReg);
229
230 /// emitCastOperation - Common code shared between visitCastInst and
231 /// constant expression cast support.
232 ///
233 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
234 Value *Src, const Type *DestTy, unsigned TargetReg);
235
236 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
237 /// and constant expression support.
238 ///
239 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
240 MachineBasicBlock::iterator IP,
241 Value *Op0, Value *Op1,
242 unsigned OperatorClass, unsigned TargetReg);
243
244 /// emitBinaryFPOperation - This method handles emission of floating point
245 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
246 void emitBinaryFPOperation(MachineBasicBlock *BB,
247 MachineBasicBlock::iterator IP,
248 Value *Op0, Value *Op1,
249 unsigned OperatorClass, unsigned TargetReg);
250
251 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
252 Value *Op0, Value *Op1, unsigned TargetReg);
253
254 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
255 unsigned DestReg, const Type *DestTy,
256 unsigned Op0Reg, unsigned Op1Reg);
257 void doMultiplyConst(MachineBasicBlock *MBB,
258 MachineBasicBlock::iterator MBBI,
259 unsigned DestReg, const Type *DestTy,
260 unsigned Op0Reg, unsigned Op1Val);
261
262 void emitDivRemOperation(MachineBasicBlock *BB,
263 MachineBasicBlock::iterator IP,
264 Value *Op0, Value *Op1, bool isDiv,
265 unsigned TargetReg);
266
267 /// emitSetCCOperation - Common code shared between visitSetCondInst and
268 /// constant expression support.
269 ///
270 void emitSetCCOperation(MachineBasicBlock *BB,
271 MachineBasicBlock::iterator IP,
272 Value *Op0, Value *Op1, unsigned Opcode,
273 unsigned TargetReg);
274
275 /// emitShiftOperation - Common code shared between visitShiftInst and
276 /// constant expression support.
277 ///
278 void emitShiftOperation(MachineBasicBlock *MBB,
279 MachineBasicBlock::iterator IP,
280 Value *Op, Value *ShiftAmount, bool isLeftShift,
281 const Type *ResultTy, unsigned DestReg);
282
283 /// emitSelectOperation - Common code shared between visitSelectInst and the
284 /// constant expression support.
285 void emitSelectOperation(MachineBasicBlock *MBB,
286 MachineBasicBlock::iterator IP,
287 Value *Cond, Value *TrueVal, Value *FalseVal,
288 unsigned DestReg);
289
290 /// copyConstantToRegister - Output the instructions required to put the
291 /// specified constant into the specified register.
292 ///
293 void copyConstantToRegister(MachineBasicBlock *MBB,
294 MachineBasicBlock::iterator MBBI,
295 Constant *C, unsigned Reg);
296
297 void emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
298 unsigned LHS, unsigned RHS);
299
300 /// makeAnotherReg - This method returns the next register number we haven't
301 /// yet used.
302 ///
303 /// Long values are handled somewhat specially. They are always allocated
304 /// as pairs of 32 bit integer values. The register number returned is the
305 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
306 /// of the long value.
307 ///
308 unsigned makeAnotherReg(const Type *Ty) {
309 assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) &&
310 "Current target doesn't have PPC reg info??");
311 const PowerPCRegisterInfo *MRI =
312 static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo());
313 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
314 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
315 // Create the lower part
316 F->getSSARegMap()->createVirtualRegister(RC);
317 // Create the upper part.
318 return F->getSSARegMap()->createVirtualRegister(RC)-1;
319 }
320
321 // Add the mapping of regnumber => reg class to MachineFunction
322 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
323 return F->getSSARegMap()->createVirtualRegister(RC);
324 }
325
326 /// getReg - This method turns an LLVM value into a register number.
327 ///
328 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
329 unsigned getReg(Value *V) {
330 // Just append to the end of the current bb.
331 MachineBasicBlock::iterator It = BB->end();
332 return getReg(V, BB, It);
333 }
334 unsigned getReg(Value *V, MachineBasicBlock *MBB,
335 MachineBasicBlock::iterator IPt);
336
337 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
338 /// that is to be statically allocated with the initial stack frame
339 /// adjustment.
340 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
341 };
342}
343
344/// dyn_castFixedAlloca - If the specified value is a fixed size alloca
345/// instruction in the entry block, return it. Otherwise, return a null
346/// pointer.
347static AllocaInst *dyn_castFixedAlloca(Value *V) {
348 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
349 BasicBlock *BB = AI->getParent();
350 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
351 return AI;
352 }
353 return 0;
354}
355
356/// getReg - This method turns an LLVM value into a register number.
357///
358unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
359 MachineBasicBlock::iterator IPt) {
360 // If this operand is a constant, emit the code to copy the constant into
361 // the register here...
362 //
363 if (Constant *C = dyn_cast<Constant>(V)) {
364 unsigned Reg = makeAnotherReg(V->getType());
365 copyConstantToRegister(MBB, IPt, C, Reg);
366 return Reg;
367 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
368 unsigned Reg1 = makeAnotherReg(V->getType());
Misha Brukman422791f2004-06-21 17:41:12 +0000369 unsigned Reg2 = makeAnotherReg(V->getType());
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000370 // Move the address of the global into the register
371 BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(PPC32::R0).addGlobalAddress(GV);
372 BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1).addGlobalAddress(GV);
373 return Reg2;
374 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
375 // Do not emit noop casts at all.
376 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
377 return getReg(CI->getOperand(0), MBB, IPt);
378 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
379 unsigned Reg = makeAnotherReg(V->getType());
380 unsigned FI = getFixedSizedAllocaFI(AI);
381 addFrameReference(BuildMI(*MBB, IPt, PPC32::ADDI, 2, Reg), FI, 0, false);
382 return Reg;
383 }
384
385 unsigned &Reg = RegMap[V];
386 if (Reg == 0) {
387 Reg = makeAnotherReg(V->getType());
388 RegMap[V] = Reg;
389 }
390
391 return Reg;
392}
393
394/// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
395/// that is to be statically allocated with the initial stack frame
396/// adjustment.
397unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
398 // Already computed this?
399 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
400 if (I != AllocaMap.end() && I->first == AI) return I->second;
401
402 const Type *Ty = AI->getAllocatedType();
403 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
404 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
405 TySize *= CUI->getValue(); // Get total allocated size...
406 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
407
408 // Create a new stack object using the frame manager...
409 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
410 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
411 return FrameIdx;
412}
413
414
415/// copyConstantToRegister - Output the instructions required to put the
416/// specified constant into the specified register.
417///
418void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
419 MachineBasicBlock::iterator IP,
420 Constant *C, unsigned R) {
421 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
422 unsigned Class = 0;
423 switch (CE->getOpcode()) {
424 case Instruction::GetElementPtr:
425 emitGEPOperation(MBB, IP, CE->getOperand(0),
426 CE->op_begin()+1, CE->op_end(), R);
427 return;
428 case Instruction::Cast:
429 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
430 return;
431
432 case Instruction::Xor: ++Class; // FALL THROUGH
433 case Instruction::Or: ++Class; // FALL THROUGH
434 case Instruction::And: ++Class; // FALL THROUGH
435 case Instruction::Sub: ++Class; // FALL THROUGH
436 case Instruction::Add:
437 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
438 Class, R);
439 return;
440
441 case Instruction::Mul:
442 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
443 return;
444
445 case Instruction::Div:
446 case Instruction::Rem:
447 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
448 CE->getOpcode() == Instruction::Div, R);
449 return;
450
451 case Instruction::SetNE:
452 case Instruction::SetEQ:
453 case Instruction::SetLT:
454 case Instruction::SetGT:
455 case Instruction::SetLE:
456 case Instruction::SetGE:
457 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
458 CE->getOpcode(), R);
459 return;
460
461 case Instruction::Shl:
462 case Instruction::Shr:
463 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
464 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
465 return;
466
467 case Instruction::Select:
468 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
469 CE->getOperand(2), R);
470 return;
471
472 default:
473 std::cerr << "Offending expr: " << C << "\n";
474 assert(0 && "Constant expression not yet handled!\n");
475 }
476 }
477
478 if (C->getType()->isIntegral()) {
479 unsigned Class = getClassB(C->getType());
480
481 if (Class == cLong) {
482 // Copy the value into the register pair.
483 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
Misha Brukman422791f2004-06-21 17:41:12 +0000484 unsigned hiTmp = makeAnotherReg(Type::IntTy);
485 unsigned loTmp = makeAnotherReg(Type::IntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000486 BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0).addImm(Val >> 48);
487 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp).addImm((Val >> 32) & 0xFFFF);
488 BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0).addImm((Val >> 16) & 0xFFFF);
489 BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
490 return;
491 }
492
493 assert(Class <= cInt && "Type not handled yet!");
494
495 if (C->getType() == Type::BoolTy) {
496 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(C == ConstantBool::True);
497 } else if (Class == cByte || Class == cShort) {
498 ConstantInt *CI = cast<ConstantInt>(C);
499 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
500 } else {
501 ConstantInt *CI = cast<ConstantInt>(C);
502 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
503 if (TheVal < 32768 && TheVal >= -32768) {
Misha Brukman422791f2004-06-21 17:41:12 +0000504 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
505 } else {
506 unsigned TmpReg = makeAnotherReg(Type::IntTy);
507 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0).addImm(CI->getRawValue() >> 16);
508 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg).addImm(CI->getRawValue() & 0xFFFF);
509 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000510 }
511 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
512 // We need to spill the constant to memory...
513 MachineConstantPool *CP = F->getConstantPool();
514 unsigned CPI = CP->getConstantPoolIndex(CFP);
515 const Type *Ty = CFP->getType();
516
517 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
518 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
519 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 2, R), CPI);
520 } else if (isa<ConstantPointerNull>(C)) {
521 // Copy zero (null pointer) to the register.
522 BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
523 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000524 BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0)
525 .addGlobalAddress(CPR->getValue());
526 BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0)
527 .addGlobalAddress(CPR->getValue());
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000528 } else {
529 std::cerr << "Offending constant: " << C << "\n";
530 assert(0 && "Type not handled yet!");
531 }
532}
533
534/// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
535/// the stack into virtual registers.
536///
537/// FIXME: When we can calculate which args are coming in via registers
538/// source them from there instead.
539void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
540 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
541 unsigned GPR_remaining = 8;
542 unsigned FPR_remaining = 13;
543 unsigned GPR_idx = 3;
544 unsigned FPR_idx = 1;
Misha Brukman422791f2004-06-21 17:41:12 +0000545
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000546 MachineFrameInfo *MFI = F->getFrameInfo();
547
548 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
549 bool ArgLive = !I->use_empty();
550 unsigned Reg = ArgLive ? getReg(*I) : 0;
551 int FI; // Frame object index
552
553 switch (getClassB(I->getType())) {
554 case cByte:
555 if (ArgLive) {
556 FI = MFI->CreateFixedObject(1, ArgOffset);
Misha Brukman422791f2004-06-21 17:41:12 +0000557 if (GPR_remaining > 0) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000558 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
559 .addReg(PPC32::R0+GPR_idx);
Misha Brukman422791f2004-06-21 17:41:12 +0000560 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +0000561 addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
Misha Brukman422791f2004-06-21 17:41:12 +0000562 }
563 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000564 break;
565 case cShort:
566 if (ArgLive) {
567 FI = MFI->CreateFixedObject(2, ArgOffset);
Misha Brukman422791f2004-06-21 17:41:12 +0000568 if (GPR_remaining > 0) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000569 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
570 .addReg(PPC32::R0+GPR_idx);
Misha Brukman422791f2004-06-21 17:41:12 +0000571 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +0000572 addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
Misha Brukman422791f2004-06-21 17:41:12 +0000573 }
574 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000575 break;
576 case cInt:
577 if (ArgLive) {
578 FI = MFI->CreateFixedObject(4, ArgOffset);
Misha Brukman422791f2004-06-21 17:41:12 +0000579 if (GPR_remaining > 0) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000580 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
581 .addReg(PPC32::R0+GPR_idx);
Misha Brukman422791f2004-06-21 17:41:12 +0000582 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +0000583 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
Misha Brukman422791f2004-06-21 17:41:12 +0000584 }
585 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000586 break;
587 case cLong:
588 if (ArgLive) {
589 FI = MFI->CreateFixedObject(8, ArgOffset);
Misha Brukman422791f2004-06-21 17:41:12 +0000590 if (GPR_remaining > 1) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000591 BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx)
592 .addReg(PPC32::R0+GPR_idx);
593 BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(PPC32::R0+GPR_idx+1)
594 .addReg(PPC32::R0+GPR_idx+1);
Misha Brukman422791f2004-06-21 17:41:12 +0000595 } else {
596 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
597 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
598 }
599 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000600 ArgOffset += 4; // longs require 4 additional bytes
Misha Brukman422791f2004-06-21 17:41:12 +0000601 if (GPR_remaining > 1) {
602 GPR_remaining--; // uses up 2 GPRs
603 GPR_idx++;
604 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000605 break;
606 case cFP:
607 if (ArgLive) {
608 unsigned Opcode;
609 if (I->getType() == Type::FloatTy) {
610 Opcode = PPC32::LFS;
611 FI = MFI->CreateFixedObject(4, ArgOffset);
612 } else {
613 Opcode = PPC32::LFD;
614 FI = MFI->CreateFixedObject(8, ArgOffset);
615 }
Misha Brukman422791f2004-06-21 17:41:12 +0000616 if (FPR_remaining > 0) {
617 BuildMI(BB, PPC32::FMR, 1, Reg).addReg(PPC32::F0+FPR_idx);
618 FPR_remaining--;
619 FPR_idx++;
620 } else {
621 addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
622 }
623 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000624 if (I->getType() == Type::DoubleTy) {
625 ArgOffset += 4; // doubles require 4 additional bytes
Misha Brukman422791f2004-06-21 17:41:12 +0000626 if (GPR_remaining > 0) {
627 GPR_remaining--; // uses up 2 GPRs
628 GPR_idx++;
629 }
630 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000631 break;
632 default:
633 assert(0 && "Unhandled argument type!");
634 }
635 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
Misha Brukman422791f2004-06-21 17:41:12 +0000636 if (GPR_remaining > 0) {
637 GPR_remaining--; // uses up 2 GPRs
638 GPR_idx++;
639 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000640 }
641
642 // If the function takes variable number of arguments, add a frame offset for
643 // the start of the first vararg value... this is used to expand
644 // llvm.va_start.
645 if (Fn.getFunctionType()->isVarArg())
646 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
647}
648
649
650/// SelectPHINodes - Insert machine code to generate phis. This is tricky
651/// because we have to generate our sources into the source basic blocks, not
652/// the current one.
653///
654void ISel::SelectPHINodes() {
655 const TargetInstrInfo &TII = *TM.getInstrInfo();
656 const Function &LF = *F->getFunction(); // The LLVM function...
657 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
658 const BasicBlock *BB = I;
659 MachineBasicBlock &MBB = *MBBMap[I];
660
661 // Loop over all of the PHI nodes in the LLVM basic block...
662 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
663 for (BasicBlock::const_iterator I = BB->begin();
664 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
665
666 // Create a new machine instr PHI node, and insert it.
667 unsigned PHIReg = getReg(*PN);
668 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
669 PPC32::PHI, PN->getNumOperands(), PHIReg);
670
671 MachineInstr *LongPhiMI = 0;
672 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
673 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
674 PPC32::PHI, PN->getNumOperands(), PHIReg+1);
675
676 // PHIValues - Map of blocks to incoming virtual registers. We use this
677 // so that we only initialize one incoming value for a particular block,
678 // even if the block has multiple entries in the PHI node.
679 //
680 std::map<MachineBasicBlock*, unsigned> PHIValues;
681
682 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
683 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
684 unsigned ValReg;
685 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
686 PHIValues.lower_bound(PredMBB);
687
688 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
689 // We already inserted an initialization of the register for this
690 // predecessor. Recycle it.
691 ValReg = EntryIt->second;
692
693 } else {
694 // Get the incoming value into a virtual register.
695 //
696 Value *Val = PN->getIncomingValue(i);
697
698 // If this is a constant or GlobalValue, we may have to insert code
699 // into the basic block to compute it into a virtual register.
700 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
701 isa<GlobalValue>(Val)) {
702 // Simple constants get emitted at the end of the basic block,
703 // before any terminator instructions. We "know" that the code to
704 // move a constant into a register will never clobber any flags.
705 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
706 } else {
707 // Because we don't want to clobber any values which might be in
708 // physical registers with the computation of this constant (which
709 // might be arbitrarily complex if it is a constant expression),
710 // just insert the computation at the top of the basic block.
711 MachineBasicBlock::iterator PI = PredMBB->begin();
712
713 // Skip over any PHI nodes though!
714 while (PI != PredMBB->end() && PI->getOpcode() == PPC32::PHI)
715 ++PI;
716
717 ValReg = getReg(Val, PredMBB, PI);
718 }
719
720 // Remember that we inserted a value for this PHI for this predecessor
721 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
722 }
723
724 PhiMI->addRegOperand(ValReg);
725 PhiMI->addMachineBasicBlockOperand(PredMBB);
726 if (LongPhiMI) {
727 LongPhiMI->addRegOperand(ValReg+1);
728 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
729 }
730 }
731
732 // Now that we emitted all of the incoming values for the PHI node, make
733 // sure to reposition the InsertPoint after the PHI that we just added.
734 // This is needed because we might have inserted a constant into this
735 // block, right after the PHI's which is before the old insert point!
736 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
737 ++PHIInsertPoint;
738 }
739 }
740}
741
742
743// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
744// it into the conditional branch or select instruction which is the only user
745// of the cc instruction. This is the case if the conditional branch is the
746// only user of the setcc, and if the setcc is in the same basic block as the
747// conditional branch. We also don't handle long arguments below, so we reject
748// them here as well.
749//
750static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
751 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
752 if (SCI->hasOneUse()) {
753 Instruction *User = cast<Instruction>(SCI->use_back());
754 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
755 SCI->getParent() == User->getParent() &&
756 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
757 SCI->getOpcode() == Instruction::SetEQ ||
758 SCI->getOpcode() == Instruction::SetNE))
759 return SCI;
760 }
761 return 0;
762}
763
764// Return a fixed numbering for setcc instructions which does not depend on the
765// order of the opcodes.
766//
767static unsigned getSetCCNumber(unsigned Opcode) {
768 switch(Opcode) {
769 default: assert(0 && "Unknown setcc instruction!");
770 case Instruction::SetEQ: return 0;
771 case Instruction::SetNE: return 1;
772 case Instruction::SetLT: return 2;
773 case Instruction::SetGE: return 3;
774 case Instruction::SetGT: return 4;
775 case Instruction::SetLE: return 5;
776 }
777}
778
779/// emitUCOM - emits an unordered FP compare.
780void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
781 unsigned LHS, unsigned RHS) {
Misha Brukman422791f2004-06-21 17:41:12 +0000782 BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000783}
784
785// EmitComparison - This function emits a comparison of the two operands,
786// returning the extended setcc code to use.
787unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
788 MachineBasicBlock *MBB,
789 MachineBasicBlock::iterator IP) {
790 // The arguments are already supposed to be of the same type.
791 const Type *CompTy = Op0->getType();
792 unsigned Class = getClassB(CompTy);
793 unsigned Op0r = getReg(Op0, MBB, IP);
794
795 // Special case handling of: cmp R, i
796 if (isa<ConstantPointerNull>(Op1)) {
797 BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
798 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
799 if (Class == cByte || Class == cShort || Class == cInt) {
800 unsigned Op1v = CI->getRawValue();
801
802 // Mask off any upper bits of the constant, if there are any...
803 Op1v &= (1ULL << (8 << Class)) - 1;
804
Misha Brukman422791f2004-06-21 17:41:12 +0000805 // Compare immediate or promote to reg?
806 if (Op1v <= 32767) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000807 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
808 PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
Misha Brukman422791f2004-06-21 17:41:12 +0000809 } else {
810 unsigned Op1r = getReg(Op1, MBB, IP);
Misha Brukman2fec9902004-06-21 20:22:03 +0000811 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3,
812 PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
Misha Brukman422791f2004-06-21 17:41:12 +0000813 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000814 return OpNum;
815 } else {
816 assert(Class == cLong && "Unknown integer class!");
817 unsigned LowCst = CI->getRawValue();
818 unsigned HiCst = CI->getRawValue() >> 32;
819 if (OpNum < 2) { // seteq, setne
820 unsigned LoTmp = Op0r;
821 if (LowCst != 0) {
Misha Brukman422791f2004-06-21 17:41:12 +0000822 unsigned LoLow = makeAnotherReg(Type::IntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000823 unsigned LoTmp = makeAnotherReg(Type::IntTy);
824 BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
Misha Brukman2fec9902004-06-21 20:22:03 +0000825 BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
826 .addImm(LowCst >> 16);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000827 }
828 unsigned HiTmp = Op0r+1;
829 if (HiCst != 0) {
Misha Brukman422791f2004-06-21 17:41:12 +0000830 unsigned HiLow = makeAnotherReg(Type::IntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000831 unsigned HiTmp = makeAnotherReg(Type::IntTy);
832 BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
Misha Brukman2fec9902004-06-21 20:22:03 +0000833 BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
834 .addImm(HiCst >> 16);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000835 }
836 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
837 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
838 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
839 return OpNum;
840 } else {
841 // Emit a sequence of code which compares the high and low parts once
842 // each, then uses a conditional move to handle the overflow case. For
843 // example, a setlt for long would generate code like this:
844 //
845 // AL = lo(op1) < lo(op2) // Always unsigned comparison
846 // BL = hi(op1) < hi(op2) // Signedness depends on operands
847 // dest = hi(op1) == hi(op2) ? BL : AL;
848 //
849
850 // FIXME: Not Yet Implemented
Misha Brukman422791f2004-06-21 17:41:12 +0000851 return OpNum;
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000852 }
853 }
854 }
855
856 unsigned Op1r = getReg(Op1, MBB, IP);
857 switch (Class) {
858 default: assert(0 && "Unknown type class!");
859 case cByte:
860 case cShort:
861 case cInt:
Misha Brukman2fec9902004-06-21 20:22:03 +0000862 BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2,
863 PPC32::CR0).addReg(Op0r).addReg(Op1r);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000864 break;
865 case cFP:
866 emitUCOM(MBB, IP, Op0r, Op1r);
867 break;
868
869 case cLong:
870 if (OpNum < 2) { // seteq, setne
871 unsigned LoTmp = makeAnotherReg(Type::IntTy);
872 unsigned HiTmp = makeAnotherReg(Type::IntTy);
873 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
874 BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
875 BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
876 BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
877 //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
878 break; // Allow the sete or setne to be generated from flags set by OR
879 } else {
880 // Emit a sequence of code which compares the high and low parts once
881 // each, then uses a conditional move to handle the overflow case. For
882 // example, a setlt for long would generate code like this:
883 //
884 // AL = lo(op1) < lo(op2) // Signedness depends on operands
885 // BL = hi(op1) < hi(op2) // Always unsigned comparison
886 // dest = hi(op1) == hi(op2) ? BL : AL;
887 //
888
889 // FIXME: Not Yet Implemented
890 return OpNum;
891 }
892 }
893 return OpNum;
894}
895
896/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
897/// register, then move it to wherever the result should be.
898///
899void ISel::visitSetCondInst(SetCondInst &I) {
900 if (canFoldSetCCIntoBranchOrSelect(&I))
901 return; // Fold this into a branch or select.
902
903 unsigned DestReg = getReg(I);
904 MachineBasicBlock::iterator MII = BB->end();
Misha Brukman2fec9902004-06-21 20:22:03 +0000905 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
906 DestReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000907}
908
909/// emitSetCCOperation - Common code shared between visitSetCondInst and
910/// constant expression support.
911///
912/// FIXME: this is wrong. we should figure out a way to guarantee
913/// TargetReg is a CR and then make it a no-op
914void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
915 MachineBasicBlock::iterator IP,
916 Value *Op0, Value *Op1, unsigned Opcode,
917 unsigned TargetReg) {
918 unsigned OpNum = getSetCCNumber(Opcode);
919 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
920
921 // The value is already in CR0 at this point, do nothing.
922}
923
924
925void ISel::visitSelectInst(SelectInst &SI) {
926 unsigned DestReg = getReg(SI);
927 MachineBasicBlock::iterator MII = BB->end();
Misha Brukman2fec9902004-06-21 20:22:03 +0000928 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
929 SI.getFalseValue(), DestReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000930}
931
932/// emitSelect - Common code shared between visitSelectInst and the constant
933/// expression support.
934/// FIXME: this is most likely broken in one or more ways. Namely, PowerPC has
935/// no select instruction. FSEL only works for comparisons against zero.
936void ISel::emitSelectOperation(MachineBasicBlock *MBB,
937 MachineBasicBlock::iterator IP,
938 Value *Cond, Value *TrueVal, Value *FalseVal,
939 unsigned DestReg) {
940 unsigned SelectClass = getClassB(TrueVal->getType());
941
942 unsigned TrueReg = getReg(TrueVal, MBB, IP);
943 unsigned FalseReg = getReg(FalseVal, MBB, IP);
944
945 if (TrueReg == FalseReg) {
Misha Brukman422791f2004-06-21 17:41:12 +0000946 if (SelectClass == cFP) {
Misha Brukman2fec9902004-06-21 20:22:03 +0000947 BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
Misha Brukman422791f2004-06-21 17:41:12 +0000948 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +0000949 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
Misha Brukman422791f2004-06-21 17:41:12 +0000950 }
951
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000952 if (SelectClass == cLong)
Misha Brukman2fec9902004-06-21 20:22:03 +0000953 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1)
954 .addReg(TrueReg+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000955 return;
956 }
957
958 unsigned CondReg = getReg(Cond, MBB, IP);
959 unsigned numZeros = makeAnotherReg(Type::IntTy);
960 unsigned falseHi = makeAnotherReg(Type::IntTy);
961 unsigned falseAll = makeAnotherReg(Type::IntTy);
962 unsigned trueAll = makeAnotherReg(Type::IntTy);
963 unsigned Temp1 = makeAnotherReg(Type::IntTy);
964 unsigned Temp2 = makeAnotherReg(Type::IntTy);
965
966 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
Misha Brukman2fec9902004-06-21 20:22:03 +0000967 BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26)
968 .addImm(0).addImm(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000969 BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
970 BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
971 BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
972 BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
973 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
974
975 if (SelectClass == cLong) {
Misha Brukman422791f2004-06-21 17:41:12 +0000976 unsigned Temp3 = makeAnotherReg(Type::IntTy);
977 unsigned Temp4 = makeAnotherReg(Type::IntTy);
978 BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
979 BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
980 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000981 }
982
983 return;
984}
985
986
987
988/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
989/// operand, in the specified target register.
990///
991void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
992 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
993
994 Value *Val = VR.Val;
995 const Type *Ty = VR.Ty;
996 if (Val) {
997 if (Constant *C = dyn_cast<Constant>(Val)) {
998 Val = ConstantExpr::getCast(C, Type::IntTy);
999 Ty = Type::IntTy;
1000 }
1001
Misha Brukman2fec9902004-06-21 20:22:03 +00001002 // If this is a simple constant, just emit a load directly to avoid the copy
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001003 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1004 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
1005
1006 if (TheVal < 32768 && TheVal >= -32768) {
Misha Brukman422791f2004-06-21 17:41:12 +00001007 BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
1008 } else {
1009 unsigned TmpReg = makeAnotherReg(Type::IntTy);
Misha Brukman2fec9902004-06-21 20:22:03 +00001010 BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0)
1011 .addImm(TheVal >> 16);
1012 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
1013 .addImm(TheVal & 0xFFFF);
Misha Brukman422791f2004-06-21 17:41:12 +00001014 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001015 return;
1016 }
1017 }
1018
1019 // Make sure we have the register number for this value...
1020 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1021
1022 switch (getClassB(Ty)) {
1023 case cByte:
1024 // Extend value into target register (8->32)
1025 if (isUnsigned)
Misha Brukman2fec9902004-06-21 20:22:03 +00001026 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1027 .addZImm(24).addZImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001028 else
1029 BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
1030 break;
1031 case cShort:
1032 // Extend value into target register (16->32)
1033 if (isUnsigned)
Misha Brukman2fec9902004-06-21 20:22:03 +00001034 BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
1035 .addZImm(16).addZImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001036 else
1037 BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
1038 break;
1039 case cInt:
1040 // Move value into target register (32->32)
1041 BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
1042 break;
1043 default:
1044 assert(0 && "Unpromotable operand class in promote32");
1045 }
1046}
1047
Misha Brukman2fec9902004-06-21 20:22:03 +00001048/// visitReturnInst - implemented with BLR
1049///
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001050void ISel::visitReturnInst(ReturnInst &I) {
1051 Value *RetVal = I.getOperand(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001052 switch (getClassB(RetVal->getType())) {
1053 case cByte: // integral return values: extend or move into r3 and return
1054 case cShort:
1055 case cInt:
1056 promote32(PPC32::R3, ValueRecord(RetVal));
1057 break;
1058 case cFP: { // Floats & Doubles: Return in f1
1059 unsigned RetReg = getReg(RetVal);
1060 BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
1061 break;
1062 }
1063 case cLong: {
1064 unsigned RetReg = getReg(RetVal);
1065 BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
1066 BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
1067 break;
1068 }
1069 default:
1070 visitInstruction(I);
1071 }
1072 BuildMI(BB, PPC32::BLR, 1).addImm(0);
1073}
1074
1075// getBlockAfter - Return the basic block which occurs lexically after the
1076// specified one.
1077static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1078 Function::iterator I = BB; ++I; // Get iterator to next block
1079 return I != BB->getParent()->end() ? &*I : 0;
1080}
1081
1082/// visitBranchInst - Handle conditional and unconditional branches here. Note
1083/// that since code layout is frozen at this point, that if we are trying to
1084/// jump to a block that is the immediate successor of the current block, we can
1085/// just make a fall-through (but we don't currently).
1086///
1087void ISel::visitBranchInst(BranchInst &BI) {
Misha Brukman2fec9902004-06-21 20:22:03 +00001088 // Update machine-CFG edges
1089 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1090 if (BI.isConditional())
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001091 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
Misha Brukman2fec9902004-06-21 20:22:03 +00001092
1093 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1094
1095 if (!BI.isConditional()) { // Unconditional branch?
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001096 if (BI.getSuccessor(0) != NextBB)
1097 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1098 return;
Misha Brukman2fec9902004-06-21 20:22:03 +00001099 }
1100
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001101 // See if we can fold the setcc into the branch itself...
1102 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
1103 if (SCI == 0) {
1104 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1105 // computed some other way...
1106 unsigned condReg = getReg(BI.getCondition());
Misha Brukman2fec9902004-06-21 20:22:03 +00001107 BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg)
1108 .addImm(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001109 if (BI.getSuccessor(1) == NextBB) {
1110 if (BI.getSuccessor(0) != NextBB)
Misha Brukman2fec9902004-06-21 20:22:03 +00001111 BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2)
1112 .addMBB(MBBMap[BI.getSuccessor(0)]);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001113 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00001114 BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2)
1115 .addMBB(MBBMap[BI.getSuccessor(1)]);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001116
1117 if (BI.getSuccessor(0) != NextBB)
1118 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
1119 }
1120 return;
1121 }
1122
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001123 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1124 MachineBasicBlock::iterator MII = BB->end();
1125 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
1126
1127 const Type *CompTy = SCI->getOperand(0)->getType();
1128 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1129
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001130 static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
1131 unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
1132 unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
1133 unsigned BIval = BITab[0];
1134
1135 if (BI.getSuccessor(0) != NextBB) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001136 BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval)
1137 .addMBB(MBBMap[BI.getSuccessor(0)]);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001138 if (BI.getSuccessor(1) != NextBB)
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001139 BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001140 } else {
1141 // Change to the inverse condition...
1142 if (BI.getSuccessor(1) != NextBB) {
Misha Brukman2fec9902004-06-21 20:22:03 +00001143 BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval)
1144 .addMBB(MBBMap[BI.getSuccessor(1)]);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001145 }
1146 }
1147}
1148
1149
1150/// doCall - This emits an abstract call instruction, setting up the arguments
1151/// and the return value as appropriate. For the actual function call itself,
1152/// it inserts the specified CallMI instruction into the stream.
1153///
1154/// FIXME: See Documentation at the following URL for "correct" behavior
1155/// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
1156void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
1157 const std::vector<ValueRecord> &Args) {
1158 // Count how many bytes are to be pushed on the stack...
1159 unsigned NumBytes = 0;
1160
1161 if (!Args.empty()) {
1162 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1163 switch (getClassB(Args[i].Ty)) {
1164 case cByte: case cShort: case cInt:
1165 NumBytes += 4; break;
1166 case cLong:
1167 NumBytes += 8; break;
1168 case cFP:
1169 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1170 break;
1171 default: assert(0 && "Unknown class!");
1172 }
1173
1174 // Adjust the stack pointer for the new arguments...
1175 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
1176
1177 // Arguments go on the stack in reverse order, as specified by the ABI.
1178 unsigned ArgOffset = 0;
Misha Brukman422791f2004-06-21 17:41:12 +00001179 unsigned GPR_remaining = 8;
1180 unsigned FPR_remaining = 13;
1181 unsigned GPR_idx = 3;
1182 unsigned FPR_idx = 1;
1183
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001184 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1185 unsigned ArgReg;
1186 switch (getClassB(Args[i].Ty)) {
1187 case cByte:
1188 case cShort:
1189 // Promote arg to 32 bits wide into a temporary register...
1190 ArgReg = makeAnotherReg(Type::UIntTy);
1191 promote32(ArgReg, Args[i]);
Misha Brukman422791f2004-06-21 17:41:12 +00001192
1193 // Reg or stack?
1194 if (GPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001195 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
1196 .addReg(ArgReg);
Misha Brukman422791f2004-06-21 17:41:12 +00001197 } else {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001198 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1199 .addReg(PPC32::R1);
Misha Brukman422791f2004-06-21 17:41:12 +00001200 }
1201 break;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001202 case cInt:
1203 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1204
Misha Brukman422791f2004-06-21 17:41:12 +00001205 // Reg or stack?
1206 if (GPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001207 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
1208 .addReg(ArgReg);
Misha Brukman422791f2004-06-21 17:41:12 +00001209 } else {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001210 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1211 .addReg(PPC32::R1);
Misha Brukman422791f2004-06-21 17:41:12 +00001212 }
1213 break;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001214 case cLong:
Misha Brukman422791f2004-06-21 17:41:12 +00001215 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001216
Misha Brukman422791f2004-06-21 17:41:12 +00001217 // Reg or stack?
1218 if (GPR_remaining > 1) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001219 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg)
1220 .addReg(ArgReg);
1221 BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx + 1).addReg(ArgReg+1)
1222 .addReg(ArgReg+1);
Misha Brukman422791f2004-06-21 17:41:12 +00001223 } else {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001224 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
1225 .addReg(PPC32::R1);
1226 BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4)
1227 .addReg(PPC32::R1);
Misha Brukman422791f2004-06-21 17:41:12 +00001228 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001229
1230 ArgOffset += 4; // 8 byte entry, not 4.
Misha Brukman422791f2004-06-21 17:41:12 +00001231 if (GPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001232 GPR_remaining -= 1; // uses up 2 GPRs
1233 GPR_idx += 1;
Misha Brukman422791f2004-06-21 17:41:12 +00001234 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001235 break;
1236 case cFP:
1237 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1238 if (Args[i].Ty == Type::FloatTy) {
Misha Brukman1916bf92004-06-24 21:56:15 +00001239 // Reg or stack?
1240 if (FPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001241 BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
1242 FPR_remaining--;
1243 FPR_idx++;
Misha Brukman1916bf92004-06-24 21:56:15 +00001244 } else {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001245 BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
1246 .addReg(PPC32::R1);
Misha Brukman1916bf92004-06-24 21:56:15 +00001247 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001248 } else {
1249 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
Misha Brukman1916bf92004-06-24 21:56:15 +00001250 // Reg or stack?
1251 if (FPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001252 BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
1253 FPR_remaining--;
1254 FPR_idx++;
Misha Brukman1916bf92004-06-24 21:56:15 +00001255 } else {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001256 BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
1257 .addReg(PPC32::R1);
Misha Brukman1916bf92004-06-24 21:56:15 +00001258 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001259
Misha Brukman1916bf92004-06-24 21:56:15 +00001260 ArgOffset += 4; // 8 byte entry, not 4.
1261 if (GPR_remaining > 0) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001262 GPR_remaining--; // uses up 2 GPRs
1263 GPR_idx++;
Misha Brukman1916bf92004-06-24 21:56:15 +00001264 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001265 }
1266 break;
1267
1268 default: assert(0 && "Unknown class!");
1269 }
1270 ArgOffset += 4;
Misha Brukman422791f2004-06-21 17:41:12 +00001271 if (GPR_remaining > 0) {
1272 GPR_remaining--; // uses up 2 GPRs
1273 GPR_idx++;
1274 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001275 }
1276 } else {
1277 BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
1278 }
1279
1280 BB->push_back(CallMI);
1281
1282 BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
1283
1284 // If there is a return value, scavenge the result from the location the call
1285 // leaves it in...
1286 //
1287 if (Ret.Ty != Type::VoidTy) {
1288 unsigned DestClass = getClassB(Ret.Ty);
1289 switch (DestClass) {
1290 case cByte:
1291 case cShort:
1292 case cInt:
1293 // Integral results are in r3
Misha Brukman422791f2004-06-21 17:41:12 +00001294 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
Misha Brukmane327e492004-06-24 23:53:24 +00001295 break;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001296 case cFP: // Floating-point return values live in f1
1297 BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
1298 break;
1299 case cLong: // Long values are in r3:r4
Misha Brukman422791f2004-06-21 17:41:12 +00001300 BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
1301 BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001302 break;
1303 default: assert(0 && "Unknown class!");
1304 }
1305 }
1306}
1307
1308
1309/// visitCallInst - Push args on stack and do a procedure call instruction.
1310void ISel::visitCallInst(CallInst &CI) {
1311 MachineInstr *TheCall;
1312 if (Function *F = CI.getCalledFunction()) {
1313 // Is it an intrinsic function call?
1314 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
1315 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1316 return;
1317 }
1318
1319 // Emit a CALL instruction with PC-relative displacement.
1320 TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
1321 } else { // Emit an indirect call through the CTR
1322 unsigned Reg = getReg(CI.getCalledValue());
1323 BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
1324 TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
1325 }
1326
1327 std::vector<ValueRecord> Args;
1328 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
1329 Args.push_back(ValueRecord(CI.getOperand(i)));
1330
1331 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1332 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
1333}
1334
1335
1336/// dyncastIsNan - Return the operand of an isnan operation if this is an isnan.
1337///
1338static Value *dyncastIsNan(Value *V) {
1339 if (CallInst *CI = dyn_cast<CallInst>(V))
1340 if (Function *F = CI->getCalledFunction())
Misha Brukmana2916ce2004-06-21 17:58:36 +00001341 if (F->getIntrinsicID() == Intrinsic::isunordered)
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001342 return CI->getOperand(1);
1343 return 0;
1344}
1345
1346/// isOnlyUsedByUnorderedComparisons - Return true if this value is only used by
1347/// or's whos operands are all calls to the isnan predicate.
1348static bool isOnlyUsedByUnorderedComparisons(Value *V) {
1349 assert(dyncastIsNan(V) && "The value isn't an isnan call!");
1350
1351 // Check all uses, which will be or's of isnans if this predicate is true.
1352 for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI != E;++UI){
1353 Instruction *I = cast<Instruction>(*UI);
1354 if (I->getOpcode() != Instruction::Or) return false;
1355 if (I->getOperand(0) != V && !dyncastIsNan(I->getOperand(0))) return false;
1356 if (I->getOperand(1) != V && !dyncastIsNan(I->getOperand(1))) return false;
1357 }
1358
1359 return true;
1360}
1361
1362/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1363/// function, lowering any calls to unknown intrinsic functions into the
1364/// equivalent LLVM code.
1365///
1366void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1367 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1368 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1369 if (CallInst *CI = dyn_cast<CallInst>(I++))
1370 if (Function *F = CI->getCalledFunction())
1371 switch (F->getIntrinsicID()) {
1372 case Intrinsic::not_intrinsic:
1373 case Intrinsic::vastart:
1374 case Intrinsic::vacopy:
1375 case Intrinsic::vaend:
1376 case Intrinsic::returnaddress:
1377 case Intrinsic::frameaddress:
Misha Brukmana2916ce2004-06-21 17:58:36 +00001378 // FIXME: should lower this ourselves
1379 // case Intrinsic::isunordered:
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001380 // We directly implement these intrinsics
1381 break;
1382 case Intrinsic::readio: {
1383 // On PPC, memory operations are in-order. Lower this intrinsic
1384 // into a volatile load.
1385 Instruction *Before = CI->getPrev();
1386 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1387 CI->replaceAllUsesWith(LI);
1388 BB->getInstList().erase(CI);
1389 break;
1390 }
1391 case Intrinsic::writeio: {
1392 // On PPC, memory operations are in-order. Lower this intrinsic
1393 // into a volatile store.
1394 Instruction *Before = CI->getPrev();
1395 StoreInst *LI = new StoreInst(CI->getOperand(1),
1396 CI->getOperand(2), true, CI);
1397 CI->replaceAllUsesWith(LI);
1398 BB->getInstList().erase(CI);
1399 break;
1400 }
1401 default:
1402 // All other intrinsic calls we must lower.
1403 Instruction *Before = CI->getPrev();
1404 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1405 if (Before) { // Move iterator to instruction after call
1406 I = Before; ++I;
1407 } else {
1408 I = BB->begin();
1409 }
1410 }
1411}
1412
1413void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1414 unsigned TmpReg1, TmpReg2, TmpReg3;
1415 switch (ID) {
1416 case Intrinsic::vastart:
1417 // Get the address of the first vararg value...
1418 TmpReg1 = getReg(CI);
1419 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
1420 return;
1421
1422 case Intrinsic::vacopy:
1423 TmpReg1 = getReg(CI);
1424 TmpReg2 = getReg(CI.getOperand(1));
1425 BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(TmpReg2).addReg(TmpReg2);
1426 return;
1427 case Intrinsic::vaend: return;
1428
1429 case Intrinsic::returnaddress:
1430 case Intrinsic::frameaddress:
1431 TmpReg1 = getReg(CI);
1432 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1433 if (ID == Intrinsic::returnaddress) {
1434 // Just load the return address
1435 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
1436 ReturnAddressIndex);
1437 } else {
1438 addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
1439 ReturnAddressIndex, -4, false);
1440 }
1441 } else {
1442 // Values other than zero are not implemented yet.
1443 BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
1444 }
1445 return;
1446
Misha Brukmana2916ce2004-06-21 17:58:36 +00001447#if 0
1448 // This may be useful for supporting isunordered
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001449 case Intrinsic::isnan:
1450 // If this is only used by 'isunordered' style comparisons, don't emit it.
1451 if (isOnlyUsedByUnorderedComparisons(&CI)) return;
1452 TmpReg1 = getReg(CI.getOperand(1));
1453 emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
Misha Brukman422791f2004-06-21 17:41:12 +00001454 TmpReg2 = makeAnotherReg(Type::IntTy);
1455 BuildMI(BB, PPC32::MFCR, TmpReg2);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001456 TmpReg3 = getReg(CI);
1457 BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
1458 return;
Misha Brukmana2916ce2004-06-21 17:58:36 +00001459#endif
1460
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001461 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
1462 }
1463}
1464
1465/// visitSimpleBinary - Implement simple binary operators for integral types...
1466/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1467/// Xor.
1468///
1469void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1470 unsigned DestReg = getReg(B);
1471 MachineBasicBlock::iterator MI = BB->end();
1472 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
1473 unsigned Class = getClassB(B.getType());
1474
1475 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
1476}
1477
1478/// emitBinaryFPOperation - This method handles emission of floating point
1479/// Add (0), Sub (1), Mul (2), and Div (3) operations.
1480void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
1481 MachineBasicBlock::iterator IP,
1482 Value *Op0, Value *Op1,
1483 unsigned OperatorClass, unsigned DestReg) {
1484
1485 // Special case: op Reg, <const fp>
1486 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001487 // Create a constant pool entry for this constant.
1488 MachineConstantPool *CP = F->getConstantPool();
1489 unsigned CPI = CP->getConstantPoolIndex(Op1C);
1490 const Type *Ty = Op1->getType();
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001491
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001492 static const unsigned OpcodeTab[][4] = {
1493 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1494 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1495 };
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001496
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001497 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1498 unsigned TempReg = makeAnotherReg(Ty);
1499 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1500 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001501
Misha Brukmanfadb82f2004-06-24 22:00:15 +00001502 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1503 unsigned Op0r = getReg(Op0, BB, IP);
1504 BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
1505 return;
1506 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001507
1508 // Special case: R1 = op <const fp>, R2
1509 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
1510 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
1511 // -0.0 - X === -X
1512 unsigned op1Reg = getReg(Op1, BB, IP);
1513 BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
1514 return;
1515 } else {
1516 // R1 = op CST, R2 --> R1 = opr R2, CST
1517
1518 // Create a constant pool entry for this constant.
1519 MachineConstantPool *CP = F->getConstantPool();
1520 unsigned CPI = CP->getConstantPoolIndex(CFP);
1521 const Type *Ty = CFP->getType();
1522
1523 static const unsigned OpcodeTab[][4] = {
1524 { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
1525 { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
1526 };
1527
1528 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
Misha Brukman422791f2004-06-21 17:41:12 +00001529 unsigned TempReg = makeAnotherReg(Ty);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001530 unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
1531 addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
1532
1533 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
1534 unsigned Op1r = getReg(Op1, BB, IP);
Misha Brukman422791f2004-06-21 17:41:12 +00001535 BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001536 return;
1537 }
1538
1539 // General case.
1540 static const unsigned OpcodeTab[4] = {
1541 PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
1542 };
1543
1544 unsigned Opcode = OpcodeTab[OperatorClass];
1545 unsigned Op0r = getReg(Op0, BB, IP);
1546 unsigned Op1r = getReg(Op1, BB, IP);
1547 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1548}
1549
1550/// emitSimpleBinaryOperation - Implement simple binary operators for integral
1551/// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
1552/// Or, 4 for Xor.
1553///
1554/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
1555/// and constant expression support.
1556///
1557void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
1558 MachineBasicBlock::iterator IP,
1559 Value *Op0, Value *Op1,
1560 unsigned OperatorClass, unsigned DestReg) {
1561 unsigned Class = getClassB(Op0->getType());
1562
Misha Brukman422791f2004-06-21 17:41:12 +00001563 // Arithmetic and Bitwise operators
1564 static const unsigned OpcodeTab[5] = {
1565 PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
1566 };
1567 // Otherwise, code generate the full operation with a constant.
1568 static const unsigned BottomTab[] = {
1569 PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
1570 };
1571 static const unsigned TopTab[] = {
1572 PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
1573 };
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001574
1575 if (Class == cFP) {
1576 assert(OperatorClass < 2 && "No logical ops for FP!");
1577 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
1578 return;
1579 }
1580
1581 if (Op0->getType() == Type::BoolTy) {
1582 if (OperatorClass == 3)
1583 // If this is an or of two isnan's, emit an FP comparison directly instead
1584 // of or'ing two isnan's together.
1585 if (Value *LHS = dyncastIsNan(Op0))
1586 if (Value *RHS = dyncastIsNan(Op1)) {
1587 unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
Misha Brukman422791f2004-06-21 17:41:12 +00001588 unsigned TmpReg = makeAnotherReg(Type::IntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001589 emitUCOM(MBB, IP, Op0Reg, Op1Reg);
Misha Brukman422791f2004-06-21 17:41:12 +00001590 BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
Misha Brukman2fec9902004-06-21 20:22:03 +00001591 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
1592 .addImm(31).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001593 return;
1594 }
1595 }
1596
1597 // sub 0, X -> neg X
1598 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
1599 if (OperatorClass == 1 && CI->isNullValue()) {
1600 unsigned op1Reg = getReg(Op1, MBB, IP);
1601 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
1602
1603 if (Class == cLong) {
Misha Brukman422791f2004-06-21 17:41:12 +00001604 unsigned zeroes = makeAnotherReg(Type::IntTy);
1605 unsigned overflow = makeAnotherReg(Type::IntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001606 unsigned T = makeAnotherReg(Type::IntTy);
Misha Brukman422791f2004-06-21 17:41:12 +00001607 BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
Misha Brukman2fec9902004-06-21 20:22:03 +00001608 BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27)
1609 .addImm(5).addImm(31);
Misha Brukman422791f2004-06-21 17:41:12 +00001610 BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
1611 BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001612 }
1613 return;
1614 }
1615
1616 // Special case: op Reg, <const int>
1617 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1618 unsigned Op0r = getReg(Op0, MBB, IP);
1619
1620 // xor X, -1 -> not X
1621 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
1622 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1623 if (Class == cLong) // Invert the top part too
Misha Brukman2fec9902004-06-21 20:22:03 +00001624 BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1)
1625 .addReg(Op0r+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001626 return;
1627 }
1628
1629 unsigned Opcode = OpcodeTab[OperatorClass];
1630 unsigned Op1r = getReg(Op1, MBB, IP);
1631
1632 if (Class != cLong) {
1633 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1634 return;
1635 }
1636
1637 // If the constant is zero in the low 32-bits, just copy the low part
1638 // across and apply the normal 32-bit operation to the high parts. There
1639 // will be no carry or borrow into the top.
1640 if (cast<ConstantInt>(Op1C)->getRawValue() == 0) {
1641 if (OperatorClass != 2) // All but and...
1642 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
1643 else
1644 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
Misha Brukman422791f2004-06-21 17:41:12 +00001645 BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001646 return;
1647 }
1648
1649 // If this is a long value and the high or low bits have a special
1650 // property, emit some special cases.
1651 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
1652
1653 // If this is a logical operation and the top 32-bits are zero, just
1654 // operate on the lower 32.
1655 if (Op1h == 0 && OperatorClass > 1) {
1656 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
1657 if (OperatorClass != 2) // All but and
Misha Brukman2fec9902004-06-21 20:22:03 +00001658 BuildMI(*MBB, IP, PPC32::OR, 2,DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001659 else
Misha Brukman2fec9902004-06-21 20:22:03 +00001660 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg+1).addReg(PPC32::R0).addImm(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001661 return;
1662 }
1663
1664 // TODO: We could handle lots of other special cases here, such as AND'ing
1665 // with 0xFFFFFFFF00000000 -> noop, etc.
1666
Misha Brukman2fec9902004-06-21 20:22:03 +00001667 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1668 .addImm(Op1r);
1669 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1670 .addImm(Op1r+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001671 return;
1672 }
1673
1674 unsigned Op0r = getReg(Op0, MBB, IP);
1675 unsigned Op1r = getReg(Op1, MBB, IP);
1676
1677 if (Class != cLong) {
Misha Brukman422791f2004-06-21 17:41:12 +00001678 unsigned Opcode = OpcodeTab[OperatorClass];
1679 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001680 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00001681 BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
1682 .addImm(Op1r);
1683 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
1684 .addImm(Op1r+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001685 }
1686 return;
1687}
1688
1689/// doMultiply - Emit appropriate instructions to multiply together the
1690/// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
1691/// result should be given as DestTy.
1692///
1693void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
1694 unsigned DestReg, const Type *DestTy,
1695 unsigned op0Reg, unsigned op1Reg) {
1696 unsigned Class = getClass(DestTy);
1697 switch (Class) {
1698 case cLong:
Misha Brukman2fec9902004-06-21 20:22:03 +00001699 BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1)
1700 .addReg(op1Reg+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001701 case cInt:
1702 case cShort:
1703 case cByte:
1704 BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
1705 return;
1706 default:
Misha Brukman422791f2004-06-21 17:41:12 +00001707 assert(0 && "doMultiply cannot operate on unknown type!");
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001708 }
1709}
1710
1711// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
1712// returns zero when the input is not exactly a power of two.
1713static unsigned ExactLog2(unsigned Val) {
1714 if (Val == 0 || (Val & (Val-1))) return 0;
1715 unsigned Count = 0;
1716 while (Val != 1) {
1717 Val >>= 1;
1718 ++Count;
1719 }
1720 return Count+1;
1721}
1722
1723
1724/// doMultiplyConst - This function is specialized to efficiently codegen an 8,
1725/// 16, or 32-bit integer multiply by a constant.
Misha Brukman2fec9902004-06-21 20:22:03 +00001726///
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001727void ISel::doMultiplyConst(MachineBasicBlock *MBB,
1728 MachineBasicBlock::iterator IP,
1729 unsigned DestReg, const Type *DestTy,
1730 unsigned op0Reg, unsigned ConstRHS) {
1731 unsigned Class = getClass(DestTy);
1732 // Handle special cases here.
1733 switch (ConstRHS) {
1734 case 0:
1735 BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1736 return;
1737 case 1:
1738 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
1739 return;
1740 case 2:
1741 BuildMI(*MBB, IP, PPC32::ADD, 2,DestReg).addReg(op0Reg).addReg(op0Reg);
1742 return;
1743 }
1744
1745 // If the element size is exactly a power of 2, use a shift to get it.
1746 if (unsigned Shift = ExactLog2(ConstRHS)) {
1747 switch (Class) {
1748 default: assert(0 && "Unknown class for this function!");
1749 case cByte:
1750 case cShort:
1751 case cInt:
Misha Brukman2fec9902004-06-21 20:22:03 +00001752 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg)
1753 .addImm(Shift-1).addImm(0).addImm(31-Shift-1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001754 return;
1755 }
1756 }
1757
1758 // Most general case, emit a normal multiply...
1759 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
1760 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
Misha Brukman2fec9902004-06-21 20:22:03 +00001761 BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0)
1762 .addImm(ConstRHS >> 16);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001763 BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
1764
1765 // Emit a MUL to multiply the register holding the index by
1766 // elementSize, putting the result in OffsetReg.
1767 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
1768}
1769
1770void ISel::visitMul(BinaryOperator &I) {
1771 unsigned ResultReg = getReg(I);
1772
1773 Value *Op0 = I.getOperand(0);
1774 Value *Op1 = I.getOperand(1);
1775
1776 MachineBasicBlock::iterator IP = BB->end();
1777 emitMultiply(BB, IP, Op0, Op1, ResultReg);
1778}
1779
1780void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
1781 Value *Op0, Value *Op1, unsigned DestReg) {
1782 MachineBasicBlock &BB = *MBB;
1783 TypeClass Class = getClass(Op0->getType());
1784
1785 // Simple scalar multiply?
1786 unsigned Op0Reg = getReg(Op0, &BB, IP);
1787 switch (Class) {
1788 case cByte:
1789 case cShort:
1790 case cInt:
1791 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1792 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
1793 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
1794 } else {
1795 unsigned Op1Reg = getReg(Op1, &BB, IP);
1796 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
1797 }
1798 return;
1799 case cFP:
1800 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
1801 return;
1802 case cLong:
1803 break;
1804 }
1805
1806 // Long value. We have to do things the hard way...
1807 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
1808 unsigned CLow = CI->getRawValue();
1809 unsigned CHi = CI->getRawValue() >> 32;
1810
1811 if (CLow == 0) {
1812 // If the low part of the constant is all zeros, things are simple.
1813 BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
1814 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
1815 return;
1816 }
1817
1818 // Multiply the two low parts
1819 unsigned OverflowReg = 0;
1820 if (CLow == 1) {
1821 BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
1822 } else {
Misha Brukman422791f2004-06-21 17:41:12 +00001823 unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001824 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
1825 OverflowReg = makeAnotherReg(Type::UIntTy);
Misha Brukman2fec9902004-06-21 20:22:03 +00001826 BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0)
1827 .addImm(CLow >> 16);
Misha Brukman422791f2004-06-21 17:41:12 +00001828 BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
1829 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
Misha Brukman2fec9902004-06-21 20:22:03 +00001830 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg)
1831 .addReg(Op1RegL);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001832 }
1833
1834 unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
1835 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
1836
1837 unsigned AHBLplusOverflowReg;
1838 if (OverflowReg) {
1839 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1840 BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
1841 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1842 } else {
1843 AHBLplusOverflowReg = AHBLReg;
1844 }
1845
1846 if (CHi == 0) {
Misha Brukman2fec9902004-06-21 20:22:03 +00001847 BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
1848 .addReg(AHBLplusOverflowReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001849 } else {
1850 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1851 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
1852
1853 BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1854 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1855 }
1856 return;
1857 }
1858
1859 // General 64x64 multiply
1860
1861 unsigned Op1Reg = getReg(Op1, &BB, IP);
1862
1863 // Multiply the two low parts... capturing carry into EDX
1864 BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL
1865
1866 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
1867 BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL >> 32
1868
1869 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
1870 BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
1871
1872 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
1873 BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
1874 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
1875
1876 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
1877 BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
1878
1879 BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
1880 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
1881}
1882
1883
1884/// visitDivRem - Handle division and remainder instructions... these
1885/// instruction both require the same instructions to be generated, they just
1886/// select the result from a different register. Note that both of these
1887/// instructions work differently for signed and unsigned operands.
1888///
1889void ISel::visitDivRem(BinaryOperator &I) {
1890 unsigned ResultReg = getReg(I);
1891 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
1892
1893 MachineBasicBlock::iterator IP = BB->end();
Misha Brukman2fec9902004-06-21 20:22:03 +00001894 emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
1895 ResultReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001896}
1897
1898void ISel::emitDivRemOperation(MachineBasicBlock *BB,
1899 MachineBasicBlock::iterator IP,
1900 Value *Op0, Value *Op1, bool isDiv,
1901 unsigned ResultReg) {
1902 const Type *Ty = Op0->getType();
1903 unsigned Class = getClass(Ty);
1904 switch (Class) {
1905 case cFP: // Floating point divide
1906 if (isDiv) {
1907 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
1908 return;
1909 } else { // Floating point remainder...
1910 unsigned Op0Reg = getReg(Op0, BB, IP);
1911 unsigned Op1Reg = getReg(Op1, BB, IP);
1912 MachineInstr *TheCall =
1913 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
1914 std::vector<ValueRecord> Args;
1915 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
1916 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
1917 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
1918 }
1919 return;
1920 case cLong: {
1921 static const char *FnName[] =
1922 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
1923 unsigned Op0Reg = getReg(Op0, BB, IP);
1924 unsigned Op1Reg = getReg(Op1, BB, IP);
1925 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
1926 MachineInstr *TheCall =
1927 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol(FnName[NameIdx], true);
1928
1929 std::vector<ValueRecord> Args;
1930 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
1931 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
1932 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
1933 return;
1934 }
1935 case cByte: case cShort: case cInt:
1936 break; // Small integrals, handled below...
1937 default: assert(0 && "Unknown class!");
1938 }
1939
1940 // Special case signed division by power of 2.
1941 if (isDiv)
1942 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
1943 assert(Class != cLong && "This doesn't handle 64-bit divides!");
1944 int V = CI->getValue();
1945
1946 if (V == 1) { // X /s 1 => X
1947 unsigned Op0Reg = getReg(Op0, BB, IP);
1948 BuildMI(*BB, IP, PPC32::OR, 2, ResultReg).addReg(Op0Reg).addReg(Op0Reg);
1949 return;
1950 }
1951
1952 if (V == -1) { // X /s -1 => -X
1953 unsigned Op0Reg = getReg(Op0, BB, IP);
1954 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(Op0Reg);
1955 return;
1956 }
1957
1958 bool isNeg = false;
1959 if (V < 0) { // Not a positive power of 2?
1960 V = -V;
1961 isNeg = true; // Maybe it's a negative power of 2.
1962 }
1963 if (unsigned Log = ExactLog2(V)) {
1964 --Log;
1965 unsigned Op0Reg = getReg(Op0, BB, IP);
1966 unsigned TmpReg = makeAnotherReg(Op0->getType());
1967 if (Log != 1)
Misha Brukman2fec9902004-06-21 20:22:03 +00001968 BuildMI(*BB, IP, PPC32::SRAWI,2, TmpReg).addReg(Op0Reg).addImm(Log-1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001969 else
1970 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
1971
1972 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
Misha Brukman2fec9902004-06-21 20:22:03 +00001973 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log)
1974 .addImm(32-Log).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001975
1976 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
1977 BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
1978
1979 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
1980 BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
1981
1982 if (isNeg)
1983 BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
1984 return;
1985 }
1986 }
1987
1988 unsigned Op0Reg = getReg(Op0, BB, IP);
1989 unsigned Op1Reg = getReg(Op1, BB, IP);
1990
1991 if (isDiv) {
Misha Brukman422791f2004-06-21 17:41:12 +00001992 if (Ty->isSigned()) {
Misha Brukman2fec9902004-06-21 20:22:03 +00001993 BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
Misha Brukman422791f2004-06-21 17:41:12 +00001994 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00001995 BuildMI(*BB, IP,PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
Misha Brukman422791f2004-06-21 17:41:12 +00001996 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00001997 } else { // Remainder
Misha Brukman422791f2004-06-21 17:41:12 +00001998 unsigned TmpReg1 = makeAnotherReg(Op0->getType());
1999 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2000
2001 if (Ty->isSigned()) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002002 BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
Misha Brukman422791f2004-06-21 17:41:12 +00002003 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002004 BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
Misha Brukman422791f2004-06-21 17:41:12 +00002005 }
2006 BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
2007 BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002008 }
2009}
2010
2011
2012/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2013/// for constant immediate shift values, and for constant immediate
2014/// shift values equal to 1. Even the general case is sort of special,
2015/// because the shift amount has to be in CL, not just any old register.
2016///
2017void ISel::visitShiftInst(ShiftInst &I) {
2018 MachineBasicBlock::iterator IP = BB->end ();
Misha Brukman2fec9902004-06-21 20:22:03 +00002019 emitShiftOperation(BB, IP, I.getOperand (0), I.getOperand (1),
2020 I.getOpcode () == Instruction::Shl, I.getType (),
2021 getReg (I));
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002022}
2023
2024/// emitShiftOperation - Common code shared between visitShiftInst and
2025/// constant expression support.
Misha Brukman2fec9902004-06-21 20:22:03 +00002026///
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002027void ISel::emitShiftOperation(MachineBasicBlock *MBB,
2028 MachineBasicBlock::iterator IP,
2029 Value *Op, Value *ShiftAmount, bool isLeftShift,
2030 const Type *ResultTy, unsigned DestReg) {
2031 unsigned SrcReg = getReg (Op, MBB, IP);
2032 bool isSigned = ResultTy->isSigned ();
2033 unsigned Class = getClass (ResultTy);
2034
2035 // Longs, as usual, are handled specially...
2036 if (Class == cLong) {
2037 // If we have a constant shift, we can generate much more efficient code
2038 // than otherwise...
2039 //
2040 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2041 unsigned Amount = CUI->getValue();
2042 if (Amount < 32) {
2043 if (isLeftShift) {
Misha Brukman422791f2004-06-21 17:41:12 +00002044 // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
Misha Brukman2fec9902004-06-21 20:22:03 +00002045 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2046 .addImm(Amount).addImm(0).addImm(31-Amount);
2047 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
2048 .addImm(Amount).addImm(32-Amount).addImm(31);
2049 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2050 .addImm(Amount).addImm(0).addImm(31-Amount);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002051 } else {
Misha Brukman422791f2004-06-21 17:41:12 +00002052 // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
Misha Brukman2fec9902004-06-21 20:22:03 +00002053 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2054 .addImm(32-Amount).addImm(Amount).addImm(31);
2055 BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
2056 .addImm(32-Amount).addImm(0).addImm(Amount-1);
2057 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
2058 .addImm(32-Amount).addImm(Amount).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002059 }
2060 } else { // Shifting more than 32 bits
2061 Amount -= 32;
2062 if (isLeftShift) {
2063 if (Amount != 0) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002064 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg)
2065 .addImm(Amount).addImm(0).addImm(31-Amount);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002066 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002067 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg)
2068 .addReg(SrcReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002069 }
Misha Brukman2fec9902004-06-21 20:22:03 +00002070 BuildMI(*MBB, IP, PPC32::ADDI, 2,DestReg).addReg(PPC32::R0).addImm(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002071 } else {
2072 if (Amount != 0) {
Misha Brukman422791f2004-06-21 17:41:12 +00002073 if (isSigned)
Misha Brukmanfadb82f2004-06-24 22:00:15 +00002074 BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1)
2075 .addImm(Amount);
Misha Brukman422791f2004-06-21 17:41:12 +00002076 else
Misha Brukmanfadb82f2004-06-24 22:00:15 +00002077 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1)
2078 .addImm(32-Amount).addImm(Amount).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002079 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002080 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1)
2081 .addReg(SrcReg+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002082 }
Misha Brukman2fec9902004-06-21 20:22:03 +00002083 BuildMI(*MBB, IP,PPC32::ADDI,2,DestReg+1).addReg(PPC32::R0).addImm(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002084 }
2085 }
2086 } else {
2087 unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
2088 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
Misha Brukman422791f2004-06-21 17:41:12 +00002089 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2090 unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
2091 unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
2092 unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
2093 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2094
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002095 if (isLeftShift) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002096 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2097 .addImm(32);
2098 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1)
2099 .addReg(ShiftAmountReg);
2100 BuildMI(*MBB, IP, PPC32::SRW, 2,TmpReg3).addReg(SrcReg).addReg(TmpReg1);
2101 BuildMI(*MBB, IP, PPC32::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
2102 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2103 .addImm(-32);
2104 BuildMI(*MBB, IP, PPC32::SLW, 2,TmpReg6).addReg(SrcReg).addReg(TmpReg5);
2105 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4)
2106 .addReg(TmpReg6);
2107 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2108 .addReg(ShiftAmountReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002109 } else {
2110 if (isSigned) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002111 // FIXME: Unimplmented
2112 // Page C-3 of the PowerPC 32bit Programming Environments Manual
Misha Brukman422791f2004-06-21 17:41:12 +00002113 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002114 BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
2115 .addImm(32);
2116 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg)
2117 .addReg(ShiftAmountReg);
2118 BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1)
2119 .addReg(TmpReg1);
2120 BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2)
2121 .addReg(TmpReg3);
2122 BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
2123 .addImm(-32);
2124 BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1)
2125 .addReg(TmpReg5);
2126 BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4)
2127 .addReg(TmpReg6);
2128 BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1)
2129 .addReg(ShiftAmountReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002130 }
2131 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002132 }
2133 return;
2134 }
2135
2136 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
2137 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2138 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
2139 unsigned Amount = CUI->getValue();
2140
Misha Brukman422791f2004-06-21 17:41:12 +00002141 if (isLeftShift) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002142 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2143 .addImm(Amount).addImm(0).addImm(31-Amount);
Misha Brukman422791f2004-06-21 17:41:12 +00002144 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002145 if (isSigned) {
2146 BuildMI(*MBB, IP, PPC32::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
2147 } else {
2148 BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
2149 .addImm(32-Amount).addImm(Amount).addImm(31);
2150 }
Misha Brukman422791f2004-06-21 17:41:12 +00002151 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002152 } else { // The shift amount is non-constant.
2153 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
2154
Misha Brukman422791f2004-06-21 17:41:12 +00002155 if (isLeftShift) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002156 BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
2157 .addReg(ShiftAmountReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002158 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002159 BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg)
2160 .addReg(SrcReg).addReg(ShiftAmountReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002161 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002162 }
2163}
2164
2165
2166/// visitLoadInst - Implement LLVM load instructions
2167///
2168void ISel::visitLoadInst(LoadInst &I) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002169 static const unsigned Opcodes[] = {
2170 PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS
2171 };
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002172 unsigned Class = getClassB(I.getType());
2173 unsigned Opcode = Opcodes[Class];
2174 if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
2175
2176 unsigned DestReg = getReg(I);
2177
2178 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
Misha Brukman422791f2004-06-21 17:41:12 +00002179 unsigned FI = getFixedSizedAllocaFI(AI);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002180 if (Class == cLong) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002181 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
2182 addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002183 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002184 addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
Misha Brukman422791f2004-06-21 17:41:12 +00002185 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002186 } else {
Misha Brukman422791f2004-06-21 17:41:12 +00002187 unsigned SrcAddrReg = getReg(I.getOperand(0));
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002188
2189 if (Class == cLong) {
2190 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2191 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(SrcAddrReg);
2192 } else {
2193 BuildMI(BB, Opcode, 2, DestReg).addImm(0).addReg(SrcAddrReg);
2194 }
2195 }
2196}
2197
2198/// visitStoreInst - Implement LLVM store instructions
2199///
2200void ISel::visitStoreInst(StoreInst &I) {
2201 unsigned ValReg = getReg(I.getOperand(0));
2202 unsigned AddressReg = getReg(I.getOperand(1));
2203
2204 const Type *ValTy = I.getOperand(0)->getType();
2205 unsigned Class = getClassB(ValTy);
2206
2207 if (Class == cLong) {
Misha Brukman422791f2004-06-21 17:41:12 +00002208 BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
Misha Brukman2fec9902004-06-21 20:22:03 +00002209 BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002210 return;
2211 }
2212
2213 static const unsigned Opcodes[] = {
2214 PPC32::STB, PPC32::STH, PPC32::STW, PPC32::STFS
2215 };
2216 unsigned Opcode = Opcodes[Class];
2217 if (ValTy == Type::DoubleTy) Opcode = PPC32::STFD;
2218 BuildMI(BB, Opcode, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
2219}
2220
2221
2222/// visitCastInst - Here we have various kinds of copying with or without sign
2223/// extension going on.
2224///
2225void ISel::visitCastInst(CastInst &CI) {
2226 Value *Op = CI.getOperand(0);
2227
2228 unsigned SrcClass = getClassB(Op->getType());
2229 unsigned DestClass = getClassB(CI.getType());
2230 // Noop casts are not emitted: getReg will return the source operand as the
2231 // register to use for any uses of the noop cast.
2232 if (DestClass == SrcClass)
2233 return;
2234
2235 // If this is a cast from a 32-bit integer to a Long type, and the only uses
2236 // of the case are GEP instructions, then the cast does not need to be
2237 // generated explicitly, it will be folded into the GEP.
2238 if (DestClass == cLong && SrcClass == cInt) {
2239 bool AllUsesAreGEPs = true;
2240 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
2241 if (!isa<GetElementPtrInst>(*I)) {
2242 AllUsesAreGEPs = false;
2243 break;
2244 }
2245
2246 // No need to codegen this cast if all users are getelementptr instrs...
2247 if (AllUsesAreGEPs) return;
2248 }
2249
2250 unsigned DestReg = getReg(CI);
2251 MachineBasicBlock::iterator MI = BB->end();
2252 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
2253}
2254
2255/// emitCastOperation - Common code shared between visitCastInst and constant
2256/// expression cast support.
2257///
2258void ISel::emitCastOperation(MachineBasicBlock *BB,
2259 MachineBasicBlock::iterator IP,
2260 Value *Src, const Type *DestTy,
2261 unsigned DestReg) {
2262 const Type *SrcTy = Src->getType();
2263 unsigned SrcClass = getClassB(SrcTy);
2264 unsigned DestClass = getClassB(DestTy);
2265 unsigned SrcReg = getReg(Src, BB, IP);
2266
2267 // Implement casts to bool by using compare on the operand followed by set if
2268 // not zero on the result.
2269 if (DestTy == Type::BoolTy) {
2270 switch (SrcClass) {
2271 case cByte:
Misha Brukman422791f2004-06-21 17:41:12 +00002272 case cShort:
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002273 case cInt: {
2274 unsigned TmpReg = makeAnotherReg(Type::IntTy);
Misha Brukman422791f2004-06-21 17:41:12 +00002275 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
2276 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002277 break;
2278 }
2279 case cLong: {
2280 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2281 unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
2282 BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
Misha Brukman422791f2004-06-21 17:41:12 +00002283 BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
2284 BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002285 break;
2286 }
2287 case cFP:
2288 // FIXME
Misha Brukman422791f2004-06-21 17:41:12 +00002289 // Load -0.0
2290 // Compare
2291 // move to CR1
2292 // Negate -0.0
2293 // Compare
2294 // CROR
2295 // MFCR
2296 // Left-align
2297 // SRA ?
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002298 break;
2299 }
2300 return;
2301 }
2302
2303 // Implement casts between values of the same type class (as determined by
2304 // getClass) by using a register-to-register move.
2305 if (SrcClass == DestClass) {
Misha Brukman422791f2004-06-21 17:41:12 +00002306 if (SrcClass <= cInt) {
2307 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2308 } else if (SrcClass == cFP && SrcTy == DestTy) {
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002309 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2310 } else if (SrcClass == cFP) {
2311 if (SrcTy == Type::FloatTy) { // float -> double
2312 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
2313 BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
2314 } else { // double -> float
2315 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
2316 "Unknown cFP member!");
Misha Brukman422791f2004-06-21 17:41:12 +00002317 BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002318 }
2319 } else if (SrcClass == cLong) {
Misha Brukman422791f2004-06-21 17:41:12 +00002320 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
Misha Brukman2fec9902004-06-21 20:22:03 +00002321 BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1)
2322 .addReg(SrcReg+1);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002323 } else {
2324 assert(0 && "Cannot handle this type of cast instruction!");
2325 abort();
2326 }
2327 return;
2328 }
2329
2330 // Handle cast of SMALLER int to LARGER int using a move with sign extension
2331 // or zero extension, depending on whether the source type was signed.
2332 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
2333 SrcClass < DestClass) {
2334 bool isLong = DestClass == cLong;
2335 if (isLong) DestClass = cInt;
2336
2337 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
2338 if (SrcClass < cInt) {
2339 if (isUnsigned) {
Misha Brukman422791f2004-06-21 17:41:12 +00002340 unsigned shift = (SrcClass == cByte) ? 24 : 16;
Misha Brukman2fec9902004-06-21 20:22:03 +00002341 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2342 .addImm(shift).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002343 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002344 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH,
2345 1, DestReg).addReg(SrcReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002346 }
2347 } else {
2348 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2349 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002350
2351 if (isLong) { // Handle upper 32 bits as appropriate...
2352 if (isUnsigned) // Zero out top bits...
2353 BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
2354 else // Sign extend bottom half...
2355 BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
2356 }
2357 return;
2358 }
2359
2360 // Special case long -> int ...
2361 if (SrcClass == cLong && DestClass == cInt) {
2362 BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
2363 return;
2364 }
2365
2366 // Handle cast of LARGER int to SMALLER int with a clear or sign extend
2367 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
2368 && SrcClass > DestClass) {
2369 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
Misha Brukman422791f2004-06-21 17:41:12 +00002370 if (isUnsigned) {
2371 unsigned shift = (SrcClass == cByte) ? 24 : 16;
Misha Brukman2fec9902004-06-21 20:22:03 +00002372 BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
2373 .addImm(shift).addImm(31);
Misha Brukman422791f2004-06-21 17:41:12 +00002374 } else {
Misha Brukman2fec9902004-06-21 20:22:03 +00002375 BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1,
2376 DestReg).addReg(SrcReg);
Misha Brukman422791f2004-06-21 17:41:12 +00002377 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002378 return;
2379 }
2380
2381 // Handle casts from integer to floating point now...
2382 if (DestClass == cFP) {
2383
Misha Brukman422791f2004-06-21 17:41:12 +00002384 // Emit a library call for long to float conversion
2385 if (SrcClass == cLong) {
2386 std::vector<ValueRecord> Args;
2387 Args.push_back(ValueRecord(SrcReg, SrcTy));
Misha Brukman2fec9902004-06-21 20:22:03 +00002388 MachineInstr *TheCall =
2389 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__floatdidf", true);
Misha Brukman422791f2004-06-21 17:41:12 +00002390 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2391 return;
2392 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002393
2394 unsigned TmpReg = makeAnotherReg(Type::IntTy);
Misha Brukman358829f2004-06-21 17:25:55 +00002395 switch (SrcTy->getTypeID()) {
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002396 case Type::BoolTyID:
2397 case Type::SByteTyID:
2398 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2399 break;
2400 case Type::UByteTyID:
Misha Brukman2fec9902004-06-21 20:22:03 +00002401 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2402 .addImm(24).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002403 break;
2404 case Type::ShortTyID:
2405 BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
2406 break;
2407 case Type::UShortTyID:
Misha Brukman2fec9902004-06-21 20:22:03 +00002408 BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0)
2409 .addImm(16).addImm(31);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002410 break;
Misha Brukman422791f2004-06-21 17:41:12 +00002411 case Type::IntTyID:
2412 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2413 break;
2414 case Type::UIntTyID:
2415 BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
2416 break;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002417 default: // No promotion needed...
2418 break;
2419 }
2420
2421 SrcReg = TmpReg;
Misha Brukman422791f2004-06-21 17:41:12 +00002422
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002423 // Spill the integer to memory and reload it from there.
Misha Brukman422791f2004-06-21 17:41:12 +00002424 // Also spill room for a special conversion constant
2425 int ConstantFrameIndex =
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002426 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2427 int ValueFrameIdx =
2428 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2429
Misha Brukman422791f2004-06-21 17:41:12 +00002430 unsigned constantHi = makeAnotherReg(Type::IntTy);
2431 unsigned constantLo = makeAnotherReg(Type::IntTy);
2432 unsigned ConstF = makeAnotherReg(Type::DoubleTy);
2433 unsigned TempF = makeAnotherReg(Type::DoubleTy);
2434
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002435 if (!SrcTy->isSigned()) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002436 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2437 .addImm(0x4330);
Misha Brukman422791f2004-06-21 17:41:12 +00002438 BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
Misha Brukman2fec9902004-06-21 20:22:03 +00002439 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2440 ConstantFrameIndex);
2441 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2442 ConstantFrameIndex, 4);
2443 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2444 ValueFrameIdx);
2445 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg),
2446 ValueFrameIdx, 4);
2447 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2448 ConstantFrameIndex);
Misha Brukman422791f2004-06-21 17:41:12 +00002449 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
2450 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
2451 } else {
2452 unsigned TempLo = makeAnotherReg(Type::IntTy);
Misha Brukman2fec9902004-06-21 20:22:03 +00002453 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0)
2454 .addImm(0x4330);
2455 BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0)
2456 .addImm(0x8000);
2457 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2458 ConstantFrameIndex);
2459 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
2460 ConstantFrameIndex, 4);
2461 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
2462 ValueFrameIdx);
Misha Brukman422791f2004-06-21 17:41:12 +00002463 BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
Misha Brukman2fec9902004-06-21 20:22:03 +00002464 addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo),
2465 ValueFrameIdx, 4);
2466 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
2467 ConstantFrameIndex);
Misha Brukman422791f2004-06-21 17:41:12 +00002468 addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
Misha Brukman2fec9902004-06-21 20:22:03 +00002469 BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF ).addReg(ConstF);
Misha Brukman422791f2004-06-21 17:41:12 +00002470 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002471 return;
2472 }
2473
2474 // Handle casts from floating point to integer now...
2475 if (SrcClass == cFP) {
2476
Misha Brukman422791f2004-06-21 17:41:12 +00002477 // emit library call
2478 if (DestClass == cLong) {
2479 std::vector<ValueRecord> Args;
2480 Args.push_back(ValueRecord(SrcReg, SrcTy));
Misha Brukman2fec9902004-06-21 20:22:03 +00002481 MachineInstr *TheCall =
2482 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__fixdfdi", true);
Misha Brukman422791f2004-06-21 17:41:12 +00002483 doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
2484 return;
2485 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002486
2487 int ValueFrameIdx =
2488 F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
2489
Misha Brukman422791f2004-06-21 17:41:12 +00002490 // load into 32 bit value, and then truncate as necessary
2491 // FIXME: This is wrong for unsigned dest types
2492 //if (DestTy->isSigned()) {
2493 unsigned TempReg = makeAnotherReg(Type::DoubleTy);
2494 BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
Misha Brukman2fec9902004-06-21 20:22:03 +00002495 addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3)
2496 .addReg(TempReg), ValueFrameIdx);
2497 addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg),
2498 ValueFrameIdx+4);
Misha Brukman422791f2004-06-21 17:41:12 +00002499 //} else {
2500 //}
2501
2502 // FIXME: Truncate return value
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002503 return;
2504 }
2505
2506 // Anything we haven't handled already, we can't (yet) handle at all.
2507 assert(0 && "Unhandled cast instruction!");
2508 abort();
2509}
2510
2511/// visitVANextInst - Implement the va_next instruction...
2512///
2513void ISel::visitVANextInst(VANextInst &I) {
2514 unsigned VAList = getReg(I.getOperand(0));
2515 unsigned DestReg = getReg(I);
2516
2517 unsigned Size;
Misha Brukman358829f2004-06-21 17:25:55 +00002518 switch (I.getArgType()->getTypeID()) {
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002519 default:
2520 std::cerr << I;
2521 assert(0 && "Error: bad type for va_next instruction!");
2522 return;
2523 case Type::PointerTyID:
2524 case Type::UIntTyID:
2525 case Type::IntTyID:
2526 Size = 4;
2527 break;
2528 case Type::ULongTyID:
2529 case Type::LongTyID:
2530 case Type::DoubleTyID:
2531 Size = 8;
2532 break;
2533 }
2534
2535 // Increment the VAList pointer...
2536 BuildMI(BB, PPC32::ADDI, 2, DestReg).addReg(VAList).addImm(Size);
2537}
2538
2539void ISel::visitVAArgInst(VAArgInst &I) {
2540 unsigned VAList = getReg(I.getOperand(0));
2541 unsigned DestReg = getReg(I);
2542
Misha Brukman358829f2004-06-21 17:25:55 +00002543 switch (I.getType()->getTypeID()) {
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002544 default:
2545 std::cerr << I;
2546 assert(0 && "Error: bad type for va_next instruction!");
2547 return;
2548 case Type::PointerTyID:
2549 case Type::UIntTyID:
2550 case Type::IntTyID:
2551 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2552 break;
2553 case Type::ULongTyID:
2554 case Type::LongTyID:
2555 BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(VAList);
2556 BuildMI(BB, PPC32::LWZ, 2, DestReg+1).addImm(4).addReg(VAList);
2557 break;
2558 case Type::DoubleTyID:
2559 BuildMI(BB, PPC32::LFD, 2, DestReg).addImm(0).addReg(VAList);
2560 break;
2561 }
2562}
2563
2564/// visitGetElementPtrInst - instruction-select GEP instructions
2565///
2566void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
2567 unsigned outputReg = getReg(I);
Misha Brukman2fec9902004-06-21 20:22:03 +00002568 emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
2569 outputReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002570}
2571
2572void ISel::emitGEPOperation(MachineBasicBlock *MBB,
2573 MachineBasicBlock::iterator IP,
2574 Value *Src, User::op_iterator IdxBegin,
2575 User::op_iterator IdxEnd, unsigned TargetReg) {
2576 const TargetData &TD = TM.getTargetData();
2577 if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
2578 Src = CPR->getValue();
2579
2580 std::vector<Value*> GEPOps;
2581 GEPOps.resize(IdxEnd-IdxBegin+1);
2582 GEPOps[0] = Src;
2583 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
2584
2585 std::vector<const Type*> GEPTypes;
2586 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
2587 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
2588
2589 // Keep emitting instructions until we consume the entire GEP instruction.
Misha Brukman98649d12004-06-24 21:54:47 +00002590 while (!GEPTypes.empty()) {
Misha Brukman2fec9902004-06-21 20:22:03 +00002591 // It's an array or pointer access: [ArraySize x ElementType].
2592 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
2593 Value *idx = GEPOps.back();
2594 GEPOps.pop_back(); // Consume a GEP operand
2595 GEPTypes.pop_back();
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002596
Misha Brukman2fec9902004-06-21 20:22:03 +00002597 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
2598 // operand on X86. Handle this case directly now...
2599 if (CastInst *CI = dyn_cast<CastInst>(idx))
2600 if (CI->getOperand(0)->getType() == Type::IntTy ||
2601 CI->getOperand(0)->getType() == Type::UIntTy)
2602 idx = CI->getOperand(0);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002603
Misha Brukman2fec9902004-06-21 20:22:03 +00002604 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
2605 // must find the size of the pointed-to type (Not coincidentally, the next
2606 // type is the type of the elements in the array).
2607 const Type *ElTy = SqTy->getElementType();
2608 unsigned elementSize = TD.getTypeSize(ElTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002609
Misha Brukman2fec9902004-06-21 20:22:03 +00002610 if (elementSize == 1) {
2611 // If the element size is 1, we don't have to multiply, just add
2612 unsigned idxReg = getReg(idx, MBB, IP);
2613 unsigned Reg = makeAnotherReg(Type::UIntTy);
2614 BuildMI(*MBB, IP, PPC32::ADD, 2,TargetReg).addReg(Reg).addReg(idxReg);
2615 --IP; // Insert the next instruction before this one.
2616 TargetReg = Reg; // Codegen the rest of the GEP into this
2617 } else {
2618 unsigned idxReg = getReg(idx, MBB, IP);
2619 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002620
Misha Brukman2fec9902004-06-21 20:22:03 +00002621 // Make sure we can back the iterator up to point to the first
2622 // instruction emitted.
2623 MachineBasicBlock::iterator BeforeIt = IP;
2624 if (IP == MBB->begin())
2625 BeforeIt = MBB->end();
2626 else
2627 --BeforeIt;
2628 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002629
Misha Brukman2fec9902004-06-21 20:22:03 +00002630 // Emit an ADD to add OffsetReg to the basePtr.
2631 unsigned Reg = makeAnotherReg(Type::UIntTy);
2632 BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002633
Misha Brukman2fec9902004-06-21 20:22:03 +00002634 // Step to the first instruction of the multiply.
2635 if (BeforeIt == MBB->end())
2636 IP = MBB->begin();
2637 else
2638 IP = ++BeforeIt;
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002639
Misha Brukman2fec9902004-06-21 20:22:03 +00002640 TargetReg = Reg; // Codegen the rest of the GEP into this
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002641 }
Misha Brukman2fec9902004-06-21 20:22:03 +00002642 }
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002643}
2644
2645/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
2646/// frame manager, otherwise do it the hard way.
2647///
2648void ISel::visitAllocaInst(AllocaInst &I) {
2649 // If this is a fixed size alloca in the entry block for the function, we
2650 // statically stack allocate the space, so we don't need to do anything here.
2651 //
2652 if (dyn_castFixedAlloca(&I)) return;
2653
2654 // Find the data size of the alloca inst's getAllocatedType.
2655 const Type *Ty = I.getAllocatedType();
2656 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
2657
2658 // Create a register to hold the temporary result of multiplying the type size
2659 // constant by the variable amount.
2660 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
2661 unsigned SrcReg1 = getReg(I.getArraySize());
2662
2663 // TotalSizeReg = mul <numelements>, <TypeSize>
2664 MachineBasicBlock::iterator MBBI = BB->end();
2665 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
2666
2667 // AddedSize = add <TotalSizeReg>, 15
2668 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
2669 BuildMI(BB, PPC32::ADD, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
2670
2671 // AlignedSize = and <AddedSize>, ~15
2672 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
Misha Brukman2fec9902004-06-21 20:22:03 +00002673 BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
2674 .addImm(0).addImm(27);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002675
2676 // Subtract size from stack pointer, thereby allocating some space.
2677 BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
2678
2679 // Put a pointer to the space into the result register, by copying
2680 // the stack pointer.
2681 BuildMI(BB, PPC32::OR, 2, getReg(I)).addReg(PPC32::R1).addReg(PPC32::R1);
2682
2683 // Inform the Frame Information that we have just allocated a variable-sized
2684 // object.
2685 F->getFrameInfo()->CreateVariableSizedObject();
2686}
2687
2688/// visitMallocInst - Malloc instructions are code generated into direct calls
2689/// to the library malloc.
2690///
2691void ISel::visitMallocInst(MallocInst &I) {
2692 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
2693 unsigned Arg;
2694
2695 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
2696 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
2697 } else {
2698 Arg = makeAnotherReg(Type::UIntTy);
2699 unsigned Op0Reg = getReg(I.getOperand(0));
2700 MachineBasicBlock::iterator MBBI = BB->end();
2701 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
2702 }
2703
2704 std::vector<ValueRecord> Args;
2705 Args.push_back(ValueRecord(Arg, Type::UIntTy));
Misha Brukman2fec9902004-06-21 20:22:03 +00002706 MachineInstr *TheCall =
2707 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("malloc", true);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002708 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
2709}
2710
2711
2712/// visitFreeInst - Free instructions are code gen'd to call the free libc
2713/// function.
2714///
2715void ISel::visitFreeInst(FreeInst &I) {
2716 std::vector<ValueRecord> Args;
2717 Args.push_back(ValueRecord(I.getOperand(0)));
Misha Brukman2fec9902004-06-21 20:22:03 +00002718 MachineInstr *TheCall =
2719 BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("free", true);
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002720 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
2721}
2722
2723/// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
2724/// into a machine code representation is a very simple peep-hole fashion. The
2725/// generated code sucks but the implementation is nice and simple.
2726///
2727FunctionPass *llvm::createPPCSimpleInstructionSelector(TargetMachine &TM) {
2728 return new ISel(TM);
2729}