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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
65 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000066 grow();
67}
68
Chris Lattner8c4d88d2004-09-30 01:54:45 +000069void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000070 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
71 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000072}
73
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000077 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000078 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
79 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
80 RC->getAlignment());
81 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 ++NumSpills;
83 return frameIndex;
84}
85
86void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
87 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000088 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000090 assert((frameIndex >= 0 ||
91 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
92 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000093 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000094}
95
Evan Cheng2638e1a2007-03-20 08:13:50 +000096int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
97 assert(MRegisterInfo::isVirtualRegister(virtReg));
98 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
99 "attempt to assign re-mat id to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +0000100 const MachineInstr *DefMI = getReMaterializedMI(virtReg);
101 int FrameIdx;
102 if (TII.isLoadFromStackSlot((MachineInstr*)DefMI, FrameIdx)) {
103 // Load from stack slot is re-materialize as reload from the stack slot!
104 Virt2StackSlotMap[virtReg] = FrameIdx;
105 return FrameIdx;
106 }
Evan Cheng2638e1a2007-03-20 08:13:50 +0000107 Virt2StackSlotMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000108 return ReMatId++;
109}
110
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000112 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000113 // Move previous memory references folded to new instruction.
114 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000115 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000116 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
117 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000118 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000119 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000120
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000121 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000122 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
123 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000124 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000125 // Folded a two-address operand.
126 MRInfo = isModRef;
127 } else if (OldMI->getOperand(OpNo).isDef()) {
128 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000129 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000130 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000131 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000132
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000133 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000134 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000135}
136
Chris Lattner7f690e62004-09-30 02:15:18 +0000137void VirtRegMap::print(std::ostream &OS) const {
138 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000139
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000141 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000142 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
143 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
144 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000145
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146 }
147
148 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000149 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
150 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
151 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
152 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000153}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000154
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000155void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000156 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000157}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000158
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000159
160//===----------------------------------------------------------------------===//
161// Simple Spiller Implementation
162//===----------------------------------------------------------------------===//
163
164Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000165
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000166namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000167 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000168 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000170}
171
Chris Lattner35f27052006-05-01 21:16:03 +0000172bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000173 DOUT << "********** REWRITE MACHINE CODE **********\n";
174 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000175 const TargetMachine &TM = MF.getTarget();
176 const MRegisterInfo &MRI = *TM.getRegisterInfo();
177 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000178
Chris Lattner4ea1b822004-09-30 02:33:48 +0000179 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
180 // each vreg once (in the case where a spilled vreg is used by multiple
181 // operands). This is always smaller than the number of operands to the
182 // current machine instr, so it should be small.
183 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000184
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000185 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
186 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000187 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000188 MachineBasicBlock &MBB = *MBBI;
189 for (MachineBasicBlock::iterator MII = MBB.begin(),
190 E = MBB.end(); MII != E; ++MII) {
191 MachineInstr &MI = *MII;
192 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000193 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000194 if (MO.isRegister() && MO.getReg())
195 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
196 unsigned VirtReg = MO.getReg();
197 unsigned PhysReg = VRM.getPhys(VirtReg);
198 if (VRM.hasStackSlot(VirtReg)) {
199 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000200 const TargetRegisterClass* RC =
201 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000202
Chris Lattner886dd912005-04-04 21:35:34 +0000203 if (MO.isUse() &&
204 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
205 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000206 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000207 LoadedRegs.push_back(VirtReg);
208 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000209 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000210 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000211
Chris Lattner886dd912005-04-04 21:35:34 +0000212 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000213 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000214 ++NumStores;
215 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000216 }
Chris Lattner886dd912005-04-04 21:35:34 +0000217 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000218 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000219 } else {
220 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000222 }
Chris Lattner886dd912005-04-04 21:35:34 +0000223
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000224 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000225 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000226 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000227 }
228 return true;
229}
230
231//===----------------------------------------------------------------------===//
232// Local Spiller Implementation
233//===----------------------------------------------------------------------===//
234
235namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000236 /// LocalSpiller - This spiller does a simple pass over the machine basic
237 /// block to attempt to keep spills in registers as much as possible for
238 /// blocks that have low register pressure (the vreg may be spilled due to
239 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000240 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000241 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000242 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000243 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000244 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000245 MRI = MF.getTarget().getRegisterInfo();
246 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000247 DOUT << "\n**** Local spiller rewriting function '"
248 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000249
Evan Cheng2638e1a2007-03-20 08:13:50 +0000250 std::vector<MachineInstr *> ReMatedMIs;
Chris Lattner7fb64342004-10-01 19:04:51 +0000251 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
252 MBB != E; ++MBB)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000253 RewriteMBB(*MBB, VRM, ReMatedMIs);
254 for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i)
255 delete ReMatedMIs[i];
Chris Lattner7fb64342004-10-01 19:04:51 +0000256 return true;
257 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000258 private:
Evan Cheng2638e1a2007-03-20 08:13:50 +0000259 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
260 std::vector<MachineInstr*> &ReMatedMIs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000261 };
262}
263
Chris Lattner66cf80f2006-02-03 23:13:58 +0000264/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
265/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000266///
267/// Note that not all physregs are created equal here. In particular, some
268/// physregs are reloads that we are allowed to clobber or ignore at any time.
269/// Other physregs are values that the register allocated program is using that
270/// we cannot CHANGE, but we can read if we like. We keep track of this on a
271/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
272/// entries. The predicate 'canClobberPhysReg()' checks this bit and
273/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000274namespace {
275class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000276 const MRegisterInfo *MRI;
277 const TargetInstrInfo *TII;
278
279 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
280 // register values that are still available, due to being loaded or stored to,
Evan Cheng6b448092007-03-02 08:52:00 +0000281 // but not invalidated yet. It also tracks the instructions that defined
Evan Chengde4e9422007-02-25 09:51:27 +0000282 // or used the register.
Evan Cheng6b448092007-03-02 08:52:00 +0000283 typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo;
Evan Cheng91e23902007-02-23 01:13:26 +0000284 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000285
286 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
287 // which stack slot values are currently held by a physreg. This is used to
288 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
289 std::multimap<unsigned, int> PhysRegsAvailable;
290
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000291 void disallowClobberPhysRegOnly(unsigned PhysReg);
292
Chris Lattner66cf80f2006-02-03 23:13:58 +0000293 void ClobberPhysRegOnly(unsigned PhysReg);
294public:
295 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
296 : MRI(mri), TII(tii) {
297 }
298
Evan Cheng91e23902007-02-23 01:13:26 +0000299 const MRegisterInfo *getRegInfo() const { return MRI; }
300
Chris Lattner66cf80f2006-02-03 23:13:58 +0000301 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000302 /// physical register, return that PhysReg, otherwise return 0. It also
303 /// returns by reference the instruction that either defines or last uses
304 /// the register.
305 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
306 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
307 if (I != SpillSlotsAvailable.end()) {
Evan Cheng6b448092007-03-02 08:52:00 +0000308 if (!I->second.second.empty())
309 SSMI = I->second.second.back();
Evan Cheng91e23902007-02-23 01:13:26 +0000310 return I->second.first >> 1; // Remove the CanClobber bit.
311 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000312 return 0;
313 }
Evan Chengde4e9422007-02-25 09:51:27 +0000314
Evan Cheng6b448092007-03-02 08:52:00 +0000315 /// addLastUse - Add the last use information of all stack slots whose
Evan Chengde4e9422007-02-25 09:51:27 +0000316 /// values are available in the specific register.
Evan Cheng6b448092007-03-02 08:52:00 +0000317 void addLastUse(unsigned PhysReg, MachineInstr *Use) {
Evan Chengde4e9422007-02-25 09:51:27 +0000318 std::multimap<unsigned, int>::iterator I =
319 PhysRegsAvailable.lower_bound(PhysReg);
320 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
321 int Slot = I->second;
322 I++;
323
324 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
325 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
326 unsigned Val = II->second.first;
327 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
Evan Cheng7cb33c82007-03-30 20:21:35 +0000328 // This can be true if there are multiple uses of the same register.
329 if (II->second.second.back() != Use)
330 II->second.second.push_back(Use);
Evan Cheng6b448092007-03-02 08:52:00 +0000331 }
332 }
333
334 /// removeLastUse - Remove the last use information of all stack slots whose
335 /// values are available in the specific register.
336 void removeLastUse(unsigned PhysReg, MachineInstr *Use) {
337 std::multimap<unsigned, int>::iterator I =
338 PhysRegsAvailable.lower_bound(PhysReg);
339 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
340 int Slot = I->second;
341 I++;
342
343 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
344 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
345 unsigned Val = II->second.first;
346 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
347 if (II->second.second.back() == Use)
348 II->second.second.pop_back();
Evan Chengde4e9422007-02-25 09:51:27 +0000349 }
350 }
Chris Lattner540fec62006-02-25 01:51:33 +0000351
Chris Lattner66cf80f2006-02-03 23:13:58 +0000352 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000353 /// specified physreg. If CanClobber is true, the physreg can be modified at
354 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000355 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
356 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000357 // If this stack slot is thought to be available in some other physreg,
358 // remove its record.
359 ModifyStackSlot(Slot);
360
Chris Lattner66cf80f2006-02-03 23:13:58 +0000361 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng6b448092007-03-02 08:52:00 +0000362 std::vector<MachineInstr*> DefUses;
363 DefUses.push_back(MI);
Evan Cheng91e23902007-02-23 01:13:26 +0000364 SpillSlotsAvailable[Slot] =
Evan Cheng6b448092007-03-02 08:52:00 +0000365 std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000366
Evan Cheng2638e1a2007-03-20 08:13:50 +0000367 if (Slot > VirtRegMap::MAX_STACK_SLOT)
368 DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1;
369 else
370 DOUT << "Remembering SS#" << Slot;
371 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000372 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000373
Chris Lattner593c9582006-02-03 23:28:46 +0000374 /// canClobberPhysReg - Return true if the spiller is allowed to change the
375 /// value of the specified stackslot register if it desires. The specified
376 /// stack slot must be available in a physreg for this query to make sense.
377 bool canClobberPhysReg(int Slot) const {
378 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000379 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000380 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000381
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000382 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
383 /// stackslot register. The register is still available but is no longer
384 /// allowed to be modifed.
385 void disallowClobberPhysReg(unsigned PhysReg);
386
Chris Lattner66cf80f2006-02-03 23:13:58 +0000387 /// ClobberPhysReg - This is called when the specified physreg changes
388 /// value. We use this to invalidate any info about stuff we thing lives in
389 /// it and any of its aliases.
390 void ClobberPhysReg(unsigned PhysReg);
391
392 /// ModifyStackSlot - This method is called when the value in a stack slot
393 /// changes. This removes information about which register the previous value
394 /// for this slot lives in (as the previous value is dead now).
395 void ModifyStackSlot(int Slot);
396};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000397}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000398
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000399/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
400/// stackslot register. The register is still available but is no longer
401/// allowed to be modifed.
402void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
403 std::multimap<unsigned, int>::iterator I =
404 PhysRegsAvailable.lower_bound(PhysReg);
405 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
406 int Slot = I->second;
407 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000408 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000409 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000410 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000411 DOUT << "PhysReg " << MRI->getName(PhysReg)
412 << " copied, it is available for use but can no longer be modified\n";
413 }
414}
415
416/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
417/// stackslot register and its aliases. The register and its aliases may
418/// still available but is no longer allowed to be modifed.
419void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
420 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
421 disallowClobberPhysRegOnly(*AS);
422 disallowClobberPhysRegOnly(PhysReg);
423}
424
Chris Lattner66cf80f2006-02-03 23:13:58 +0000425/// ClobberPhysRegOnly - This is called when the specified physreg changes
426/// value. We use this to invalidate any info about stuff we thing lives in it.
427void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
428 std::multimap<unsigned, int>::iterator I =
429 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000430 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000431 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000432 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000433 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000434 "Bidirectional map mismatch!");
435 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000436 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000437 << " clobbered, invalidating ";
438 if (Slot > VirtRegMap::MAX_STACK_SLOT)
439 DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
440 else
441 DOUT << "SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000442 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000443}
444
Chris Lattner66cf80f2006-02-03 23:13:58 +0000445/// ClobberPhysReg - This is called when the specified physreg changes
446/// value. We use this to invalidate any info about stuff we thing lives in
447/// it and any of its aliases.
448void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000449 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000450 ClobberPhysRegOnly(*AS);
451 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000452}
453
Chris Lattner07cf1412006-02-03 00:36:31 +0000454/// ModifyStackSlot - This method is called when the value in a stack slot
455/// changes. This removes information about which register the previous value
456/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000457void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000458 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000459 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000460 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000461 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000462
463 // This register may hold the value of multiple stack slots, only remove this
464 // stack slot from the set of values the register contains.
465 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
466 for (; ; ++I) {
467 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
468 "Map inverse broken!");
469 if (I->second == Slot) break;
470 }
471 PhysRegsAvailable.erase(I);
472}
473
474
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000475
Chris Lattner7fb64342004-10-01 19:04:51 +0000476// ReusedOp - For each reused operand, we keep track of a bit of information, in
477// case we need to rollback upon processing a new operand. See comments below.
478namespace {
479 struct ReusedOp {
480 // The MachineInstr operand that reused an available value.
481 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000482
Chris Lattner7fb64342004-10-01 19:04:51 +0000483 // StackSlot - The spill slot of the value being reused.
484 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000485
Chris Lattner7fb64342004-10-01 19:04:51 +0000486 // PhysRegReused - The physical register the value was available in.
487 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000488
Chris Lattner7fb64342004-10-01 19:04:51 +0000489 // AssignedPhysReg - The physreg that was assigned for use by the reload.
490 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000491
492 // VirtReg - The virtual register itself.
493 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000494
Chris Lattner8a61a752005-10-06 17:19:06 +0000495 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
496 unsigned vreg)
497 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
498 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000499 };
Chris Lattner540fec62006-02-25 01:51:33 +0000500
501 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
502 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000503 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000504 MachineInstr &MI;
505 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000506 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000507 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000508 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000509 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000510 }
Chris Lattner540fec62006-02-25 01:51:33 +0000511
512 bool hasReuses() const {
513 return !Reuses.empty();
514 }
515
516 /// addReuse - If we choose to reuse a virtual register that is already
517 /// available instead of reloading it, remember that we did so.
518 void addReuse(unsigned OpNo, unsigned StackSlot,
519 unsigned PhysRegReused, unsigned AssignedPhysReg,
520 unsigned VirtReg) {
521 // If the reload is to the assigned register anyway, no undo will be
522 // required.
523 if (PhysRegReused == AssignedPhysReg) return;
524
525 // Otherwise, remember this.
526 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
527 AssignedPhysReg, VirtReg));
528 }
Evan Chenge077ef62006-11-04 00:21:55 +0000529
530 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000531 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000532 }
533
534 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000535 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000536 }
Chris Lattner540fec62006-02-25 01:51:33 +0000537
538 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
539 /// is some other operand that is using the specified register, either pick
540 /// a new register to use, or evict the previous reload and use this reg.
541 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
542 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000543 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000544 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000545 if (Reuses.empty()) return PhysReg; // This is most often empty.
546
547 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
548 ReusedOp &Op = Reuses[ro];
549 // If we find some other reuse that was supposed to use this register
550 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000551 // register. That is, unless its reload register has already been
552 // considered and subsequently rejected because it has also been reused
553 // by another operand.
554 if (Op.PhysRegReused == PhysReg &&
555 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000556 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000557 unsigned NewReg = Op.AssignedPhysReg;
558 Rejected.insert(PhysReg);
559 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000560 } else {
561 // Otherwise, we might also have a problem if a previously reused
562 // value aliases the new register. If so, codegen the previous reload
563 // and use this one.
564 unsigned PRRU = Op.PhysRegReused;
565 const MRegisterInfo *MRI = Spills.getRegInfo();
566 if (MRI->areAliases(PRRU, PhysReg)) {
567 // Okay, we found out that an alias of a reused register
568 // was used. This isn't good because it means we have
569 // to undo a previous reuse.
570 MachineBasicBlock *MBB = MI->getParent();
571 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000572 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
573
574 // Copy Op out of the vector and remove it, we're going to insert an
575 // explicit load for it.
576 ReusedOp NewOp = Op;
577 Reuses.erase(Reuses.begin()+ro);
578
579 // Ok, we're going to try to reload the assigned physreg into the
580 // slot that we were supposed to in the first place. However, that
581 // register could hold a reuse. Check to see if it conflicts or
582 // would prefer us to use a different register.
583 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000584 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000585
586 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
587 NewOp.StackSlot, AliasRC);
588 Spills.ClobberPhysReg(NewPhysReg);
589 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000590
591 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000592 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000593
Chris Lattnere53f4a02006-05-04 17:52:23 +0000594 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000595
Evan Cheng91e23902007-02-23 01:13:26 +0000596 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000597 ++NumLoads;
598 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000599 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000600
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000601 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000602 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000603
604 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000605 return PhysReg;
606 }
607 }
608 }
609 return PhysReg;
610 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000611
612 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
613 /// 'Rejected' set to remember which registers have been considered and
614 /// rejected for the reload. This avoids infinite looping in case like
615 /// this:
616 /// t1 := op t2, t3
617 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
618 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
619 /// t1 <- desires r1
620 /// sees r1 is taken by t2, tries t2's reload register r0
621 /// sees r0 is taken by t3, tries t3's reload register r1
622 /// sees r1 is taken by t2, tries t2's reload register r0 ...
623 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
624 AvailableSpills &Spills,
625 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000626 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000627 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
628 }
Chris Lattner540fec62006-02-25 01:51:33 +0000629 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000630}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000631
Chris Lattner7fb64342004-10-01 19:04:51 +0000632
633/// rewriteMBB - Keep track of which spills are available even after the
634/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000635void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
636 std::vector<MachineInstr*> &ReMatedMIs) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000637 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000638
Chris Lattner66cf80f2006-02-03 23:13:58 +0000639 // Spills - Keep track of which spilled values are available in physregs so
640 // that we can choose to reuse the physregs instead of emitting reloads.
641 AvailableSpills Spills(MRI, TII);
642
Chris Lattner52b25db2004-10-01 19:47:12 +0000643 // MaybeDeadStores - When we need to write a value back into a stack slot,
644 // keep track of the inserted store. If the stack slot value is never read
645 // (because the value was used from some available register, for example), and
646 // subsequently stored to, the original store is dead. This map keeps track
647 // of inserted stores that are not used. If we see a subsequent store to the
648 // same stack slot, the original store is deleted.
649 std::map<int, MachineInstr*> MaybeDeadStores;
650
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000651 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
652
Chris Lattner7fb64342004-10-01 19:04:51 +0000653 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
654 MII != E; ) {
655 MachineInstr &MI = *MII;
656 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
657
Chris Lattner540fec62006-02-25 01:51:33 +0000658 /// ReusedOperands - Keep track of operand reuse in case we need to undo
659 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000660 ReuseInfo ReusedOperands(MI, MRI);
661
662 // Loop over all of the implicit defs, clearing them from our available
663 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000664 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng2638e1a2007-03-20 08:13:50 +0000665
666 // If this instruction is being rematerialized, just remove it!
Evan Cheng91935142007-04-04 07:40:01 +0000667 int FrameIdx;
668 if ((TID->Flags & M_REMATERIALIZIBLE) ||
669 TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000670 bool Remove = true;
671 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
672 MachineOperand &MO = MI.getOperand(i);
673 if (!MO.isRegister() || MO.getReg() == 0)
674 continue; // Ignore non-register operands.
675 if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) {
676 Remove = false;
677 break;
678 }
679 }
680 if (Remove) {
681 VRM.RemoveFromFoldedVirtMap(&MI);
682 ReMatedMIs.push_back(MI.removeFromParent());
683 MII = NextMII;
684 continue;
685 }
686 }
687
Evan Cheng86facc22006-12-15 06:41:01 +0000688 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000689 if (ImpDef) {
690 for ( ; *ImpDef; ++ImpDef) {
691 PhysRegsUsed[*ImpDef] = true;
692 ReusedOperands.markClobbered(*ImpDef);
693 Spills.ClobberPhysReg(*ImpDef);
694 }
695 }
696
Chris Lattner7fb64342004-10-01 19:04:51 +0000697 // Process all of the spilled uses and all non spilled reg references.
698 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
699 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000700 if (!MO.isRegister() || MO.getReg() == 0)
701 continue; // Ignore non-register operands.
702
703 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
704 // Ignore physregs for spilling, but remember that it is used by this
705 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000706 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000707 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000708 continue;
709 }
710
711 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
712 "Not a virtual or a physical register?");
713
714 unsigned VirtReg = MO.getReg();
715 if (!VRM.hasStackSlot(VirtReg)) {
716 // This virtual register was assigned a physreg!
717 unsigned Phys = VRM.getPhys(VirtReg);
718 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000719 if (MO.isDef())
720 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000721 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000722 continue;
723 }
724
725 // This virtual register is now known to be a spilled value.
726 if (!MO.isUse())
727 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000728
Evan Cheng2638e1a2007-03-20 08:13:50 +0000729 bool doReMat = VRM.isReMaterialized(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000730 int StackSlot = VRM.getStackSlot(VirtReg);
731 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000732
Chris Lattner50ea01e2005-09-09 20:29:51 +0000733 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000734 MachineInstr *SSMI = NULL;
735 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000736 // This spilled operand might be part of a two-address operand. If this
737 // is the case, then changing it will necessarily require changing the
738 // def part of the instruction as well. However, in some cases, we
739 // aren't allowed to modify the reused register. If none of these cases
740 // apply, reuse it.
741 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000742 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000743 if (ti != -1 &&
744 MI.getOperand(ti).isReg() &&
745 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000746 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000747 // long as we are allowed to clobber the value and there isn't an
748 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000749 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
750 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000751 }
752
753 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000754 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000755 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
756 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
757 else
758 DOUT << "Reusing SS#" << StackSlot;
759 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000760 << MRI->getName(PhysReg) << " for vreg"
761 << VirtReg <<" instead of reloading into physreg "
762 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000763 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000764
Evan Cheng91e23902007-02-23 01:13:26 +0000765 // Extend the live range of the MI that last kill the register if
766 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000767 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000768 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000769 int UIdx = SSMI->findRegisterUseOperand(PhysReg, true);
770 if (UIdx != -1) {
771 MachineOperand &MOK = SSMI->getOperand(UIdx);
772 WasKill = MOK.isKill();
773 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000774 }
Evan Cheng6b448092007-03-02 08:52:00 +0000775 }
776 if (ti == -1) {
777 // Unless it's the use of a two-address code, transfer the kill
778 // of the reused register to this use.
Evan Chenga7288df2007-03-03 06:32:37 +0000779 if (WasKill)
780 MI.getOperand(i).setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000781 Spills.addLastUse(PhysReg, &MI);
Evan Cheng50d25d72007-02-23 21:47:50 +0000782 }
Evan Cheng91e23902007-02-23 01:13:26 +0000783
Chris Lattneraddc55a2006-04-28 01:46:50 +0000784 // The only technical detail we have is that we don't know that
785 // PhysReg won't be clobbered by a reloaded stack slot that occurs
786 // later in the instruction. In particular, consider 'op V1, V2'.
787 // If V1 is available in physreg R0, we would choose to reuse it
788 // here, instead of reloading it into the register the allocator
789 // indicated (say R1). However, V2 might have to be reloaded
790 // later, and it might indicate that it needs to live in R0. When
791 // this occurs, we need to have information available that
792 // indicates it is safe to use R1 for the reload instead of R0.
793 //
794 // To further complicate matters, we might conflict with an alias,
795 // or R0 and R1 might not be compatible with each other. In this
796 // case, we actually insert a reload for V1 in R1, ensuring that
797 // we can get at R0 or its alias.
798 ReusedOperands.addReuse(i, StackSlot, PhysReg,
799 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000800 if (ti != -1)
801 // Only mark it clobbered if this is a use&def operand.
802 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000803 ++NumReused;
804 continue;
805 }
806
807 // Otherwise we have a situation where we have a two-address instruction
808 // whose mod/ref operand needs to be reloaded. This reload is already
809 // available in some register "PhysReg", but if we used PhysReg as the
810 // operand to our 2-addr instruction, the instruction would modify
811 // PhysReg. This isn't cool if something later uses PhysReg and expects
812 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000813 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000814 // To avoid this problem, and to avoid doing a load right after a store,
815 // we emit a copy from PhysReg into the designated register for this
816 // operand.
817 unsigned DesignatedReg = VRM.getPhys(VirtReg);
818 assert(DesignatedReg && "Must map virtreg to physreg!");
819
820 // Note that, if we reused a register for a previous operand, the
821 // register we want to reload into might not actually be
822 // available. If this occurs, use the register indicated by the
823 // reuser.
824 if (ReusedOperands.hasReuses())
825 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
826 Spills, MaybeDeadStores);
827
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000828 // If the mapped designated register is actually the physreg we have
829 // incoming, we don't need to inserted a dead copy.
830 if (DesignatedReg == PhysReg) {
831 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000832 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
833 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
834 else
835 DOUT << "Reusing SS#" << StackSlot;
836 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000837 << VirtReg
838 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000839 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000840 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000841 ++NumReused;
842 continue;
843 }
844
Chris Lattneraddc55a2006-04-28 01:46:50 +0000845 const TargetRegisterClass* RC =
846 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
847
848 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000849 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000850 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000851
852 // Extend the live range of the MI that last kill the register if
853 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000854 bool WasKill = false;
Evan Chengde4e9422007-02-25 09:51:27 +0000855 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000856 int UIdx = SSMI->findRegisterUseOperand(PhysReg, true);
857 if (UIdx != -1) {
858 MachineOperand &MOK = SSMI->getOperand(UIdx);
859 WasKill = MOK.isKill();
860 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000861 }
Evan Chengde4e9422007-02-25 09:51:27 +0000862 }
Evan Cheng6b448092007-03-02 08:52:00 +0000863 MachineInstr *CopyMI = prior(MII);
Evan Chenga7288df2007-03-03 06:32:37 +0000864 if (WasKill) {
865 // Transfer kill to the next use.
Evan Chengad7ccf32007-03-26 22:40:42 +0000866 int UIdx = CopyMI->findRegisterUseOperand(PhysReg);
867 assert(UIdx != -1);
868 MachineOperand &MOU = CopyMI->getOperand(UIdx);
869 MOU.setIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000870 }
871 Spills.addLastUse(PhysReg, CopyMI);
Evan Chengde4e9422007-02-25 09:51:27 +0000872
Chris Lattneraddc55a2006-04-28 01:46:50 +0000873 // This invalidates DesignatedReg.
874 Spills.ClobberPhysReg(DesignatedReg);
875
Evan Cheng91e23902007-02-23 01:13:26 +0000876 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000877 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000878 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000879 ++NumReused;
880 continue;
881 }
882
883 // Otherwise, reload it and remember that we have it.
884 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000885 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000886 const TargetRegisterClass* RC =
887 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000888
Chris Lattner50ea01e2005-09-09 20:29:51 +0000889 // Note that, if we reused a register for a previous operand, the
890 // register we want to reload into might not actually be
891 // available. If this occurs, use the register indicated by the
892 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000893 if (ReusedOperands.hasReuses())
894 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
895 Spills, MaybeDeadStores);
896
Chris Lattner50ea01e2005-09-09 20:29:51 +0000897 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000898 ReusedOperands.markClobbered(PhysReg);
Evan Cheng91935142007-04-04 07:40:01 +0000899 if (doReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000900 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000901 ++NumReMats;
902 } else {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000903 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000904 ++NumLoads;
905 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000906 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000907 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000908
909 // Any stores to this stack slot are not dead anymore.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000910 if (!doReMat)
911 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000912 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000913 // Assumes this is the last use. IsKill will be unset if reg is reused
914 // unless it's a two-address operand.
915 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
916 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000917 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000918 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000919 }
920
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000921 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000922
Chris Lattner7fb64342004-10-01 19:04:51 +0000923 // If we have folded references to memory operands, make sure we clear all
924 // physical registers that may contain the value of the spilled virtual
925 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000926 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
927 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000928 DOUT << "Folded vreg: " << I->second.first << " MR: "
929 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000930 unsigned VirtReg = I->second.first;
931 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000932 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000934 continue;
935 }
936 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000937 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000938
939 // If this folded instruction is just a use, check to see if it's a
940 // straight load from the virt reg slot.
941 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
942 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000943 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000944 if (FrameIdx == SS) {
945 // If this spill slot is available, turn it into a copy (or nothing)
946 // instead of leaving it as a load!
Evan Chengde4e9422007-02-25 09:51:27 +0000947 MachineInstr *SSMI = NULL;
948 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000949 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000950 MachineFunction &MF = *MBB.getParent();
951 if (DestReg != InReg) {
952 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
953 MF.getSSARegMap()->getRegClass(VirtReg));
954 // Revisit the copy so we make sure to notice the effects of the
955 // operation on the destreg (either needing to RA it if it's
956 // virtual or needing to clobber any values if it's physical).
957 NextMII = &MI;
958 --NextMII; // backtrack to the copy.
Evan Chengde4e9422007-02-25 09:51:27 +0000959 } else
960 DOUT << "Removing now-noop copy: " << MI;
961
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000962 // Either way, the live range of the last kill of InReg has been
963 // extended. Remove its kill.
Evan Chenga7288df2007-03-03 06:32:37 +0000964 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000965 if (SSMI) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000966 int UIdx = SSMI->findRegisterUseOperand(InReg, true);
967 if (UIdx != -1) {
968 MachineOperand &MOK = SSMI->getOperand(UIdx);
969 WasKill = MOK.isKill();
970 MOK.unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000971 }
Evan Cheng6b448092007-03-02 08:52:00 +0000972 }
973 if (NextMII != MBB.end()) {
Evan Chengad7ccf32007-03-26 22:40:42 +0000974 // If NextMII uses InReg and the use is not a two address
975 // operand, mark it killed.
976 int UIdx = NextMII->findRegisterUseOperand(InReg);
977 if (UIdx != -1) {
978 MachineOperand &MOU = NextMII->getOperand(UIdx);
979 if (WasKill) {
980 const TargetInstrDescriptor *NTID =
981 NextMII->getInstrDescriptor();
Evan Cheng018d6e12007-03-27 00:48:28 +0000982 if (UIdx >= NTID->numOperands ||
983 NTID->getOperandConstraint(UIdx, TOI::TIED_TO) == -1)
Evan Chengad7ccf32007-03-26 22:40:42 +0000984 MOU.setIsKill();
985 }
Evan Cheng6b448092007-03-02 08:52:00 +0000986 Spills.addLastUse(InReg, &(*NextMII));
Evan Chengde4e9422007-02-25 09:51:27 +0000987 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000988 }
Evan Chengde4e9422007-02-25 09:51:27 +0000989
Chris Lattner6ec36262006-10-12 17:45:38 +0000990 VRM.RemoveFromFoldedVirtMap(&MI);
991 MBB.erase(&MI);
992 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000993 }
Chris Lattnercea86882005-09-19 06:56:21 +0000994 }
995 }
996 }
997
998 // If this reference is not a use, any previous store is now dead.
999 // Otherwise, the store to this stack slot is not dead anymore.
1000 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
1001 if (MDSI != MaybeDeadStores.end()) {
1002 if (MR & VirtRegMap::isRef) // Previous store is not dead.
1003 MaybeDeadStores.erase(MDSI);
1004 else {
1005 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +00001006 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001007 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +00001008 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +00001009 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +00001010 MaybeDeadStores.erase(MDSI);
1011 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +00001012 }
1013 }
1014
1015 // If the spill slot value is available, and this is a new definition of
1016 // the value, the value is not available anymore.
1017 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +00001018 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001019 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +00001020
1021 // If this is *just* a mod of the value, check to see if this is just a
1022 // store to the spill slot (i.e. the spill got merged into the copy). If
1023 // so, realize that the vreg is available now, and add the store to the
1024 // MaybeDeadStore info.
1025 int StackSlot;
1026 if (!(MR & VirtRegMap::isRef)) {
1027 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1028 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1029 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001030 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001031 // this as a potentially dead store in case there is a subsequent
1032 // store into the stack slot without a read from it.
1033 MaybeDeadStores[StackSlot] = &MI;
1034
Chris Lattnercd816392006-02-02 23:29:36 +00001035 // If the stack slot value was previously available in some other
1036 // register, change it now. Otherwise, make the register available,
1037 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001038 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001039 }
1040 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001041 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001042 }
1043
Chris Lattner7fb64342004-10-01 19:04:51 +00001044 // Process all of the spilled defs.
1045 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1046 MachineOperand &MO = MI.getOperand(i);
1047 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1048 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001049
Chris Lattner7fb64342004-10-01 19:04:51 +00001050 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001051 // Check to see if this is a noop copy. If so, eliminate the
1052 // instruction before considering the dest reg to be changed.
1053 unsigned Src, Dst;
1054 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1055 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001056 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng6b448092007-03-02 08:52:00 +00001057 Spills.removeLastUse(Src, &MI);
Chris Lattner29268692006-09-05 02:12:02 +00001058 MBB.erase(&MI);
1059 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001060 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001061 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001062 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001063
1064 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001065 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001066 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001067
1068 // Check to see if this instruction is a load from a stack slot into
1069 // a register. If so, this provides the stack slot value in the reg.
1070 int FrameIdx;
1071 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1072 assert(DestReg == VirtReg && "Unknown load situation!");
1073
1074 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001075 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001076 goto ProcessNextInst;
1077 }
1078
Chris Lattner29268692006-09-05 02:12:02 +00001079 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001080 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001081
Chris Lattner84e752a2006-02-03 03:06:49 +00001082 // The only vregs left are stack slot definitions.
1083 int StackSlot = VRM.getStackSlot(VirtReg);
1084 const TargetRegisterClass *RC =
1085 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001086
Chris Lattner29268692006-09-05 02:12:02 +00001087 // If this def is part of a two-address operand, make sure to execute
1088 // the store from the correct physical register.
1089 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001090 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001091 if (TiedOp != -1)
1092 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001093 else {
Chris Lattner29268692006-09-05 02:12:02 +00001094 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001095 if (ReusedOperands.isClobbered(PhysReg)) {
1096 // Another def has taken the assigned physreg. It must have been a
1097 // use&def which got it due to reuse. Undo the reuse!
1098 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1099 Spills, MaybeDeadStores);
1100 }
1101 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001102
Chris Lattner84e752a2006-02-03 03:06:49 +00001103 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +00001104 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001105 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001106 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001107 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001108
Chris Lattner84e752a2006-02-03 03:06:49 +00001109 // If there is a dead store to this stack slot, nuke it now.
1110 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1111 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001112 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001113 ++NumDSE;
1114 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001115 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001116 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001117 LastStore = next(MII);
1118
1119 // If the stack slot value was previously available in some other
1120 // register, change it now. Otherwise, make the register available,
1121 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001122 Spills.ModifyStackSlot(StackSlot);
1123 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001124 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001125 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001126
1127 // Check to see if this is a noop copy. If so, eliminate the
1128 // instruction before considering the dest reg to be changed.
1129 {
1130 unsigned Src, Dst;
1131 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1132 ++NumDCE;
1133 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng7cb33c82007-03-30 20:21:35 +00001134 Spills.removeLastUse(Src, &MI);
Evan Chengf50d09a2007-02-08 06:04:54 +00001135 MBB.erase(&MI);
1136 VRM.RemoveFromFoldedVirtMap(&MI);
1137 goto ProcessNextInst;
1138 }
1139 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001140 }
1141 }
Chris Lattnercea86882005-09-19 06:56:21 +00001142 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +00001143 MII = NextMII;
1144 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001145}
1146
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001147
1148
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001149llvm::Spiller* llvm::createSpiller() {
1150 switch (SpillerOpt) {
1151 default: assert(0 && "Unreachable!");
1152 case local:
1153 return new LocalSpiller();
1154 case simple:
1155 return new SimpleSpiller();
1156 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001157}