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Misha Brukman91b5ca82004-07-26 18:45:48 +00001//===-- X86ISelSimple.cpp - A simple instruction selector for x86 ---------===//
John Criswellb576c942003-10-20 19:43:21 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
Chris Lattner72614082002-10-25 22:55:53 +00009//
Chris Lattner3e130a22003-01-13 00:32:26 +000010// This file defines a simple peephole instruction selector for the x86 target
Chris Lattner72614082002-10-25 22:55:53 +000011//
12//===----------------------------------------------------------------------===//
13
14#include "X86.h"
Chris Lattner6fc3c522002-11-17 21:11:55 +000015#include "X86InstrBuilder.h"
Misha Brukmanc8893fc2003-10-23 16:22:08 +000016#include "X86InstrInfo.h"
17#include "llvm/Constants.h"
18#include "llvm/DerivedTypes.h"
Chris Lattner72614082002-10-25 22:55:53 +000019#include "llvm/Function.h"
Chris Lattner67580ed2003-05-13 20:21:19 +000020#include "llvm/Instructions.h"
Misha Brukmanc8893fc2003-10-23 16:22:08 +000021#include "llvm/Pass.h"
Chris Lattner30483732004-06-20 07:49:54 +000022#include "llvm/CodeGen/IntrinsicLowering.h"
Misha Brukmanc8893fc2003-10-23 16:22:08 +000023#include "llvm/CodeGen/MachineConstantPool.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner341a9372002-10-29 17:43:55 +000025#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner94af4142002-12-25 05:13:53 +000026#include "llvm/CodeGen/SSARegMap.h"
Misha Brukmand2cc0172002-11-20 00:58:23 +000027#include "llvm/Target/MRegisterInfo.h"
Misha Brukmanc8893fc2003-10-23 16:22:08 +000028#include "llvm/Target/TargetMachine.h"
Chris Lattner3f1e8e72004-02-22 07:04:00 +000029#include "llvm/Support/GetElementPtrTypeIterator.h"
Chris Lattner67580ed2003-05-13 20:21:19 +000030#include "llvm/Support/InstVisitor.h"
Chris Lattner986618e2004-02-22 19:47:26 +000031#include "Support/Statistic.h"
Chris Lattner44827152003-12-28 09:47:19 +000032using namespace llvm;
Brian Gaeked0fde302003-11-11 22:41:34 +000033
Chris Lattner986618e2004-02-22 19:47:26 +000034namespace {
35 Statistic<>
36 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
Chris Lattner427aeb42004-04-11 19:21:59 +000037
38 /// TypeClass - Used by the X86 backend to group LLVM types by their basic X86
39 /// Representation.
40 ///
41 enum TypeClass {
42 cByte, cShort, cInt, cFP, cLong
43 };
44}
45
46/// getClass - Turn a primitive type into a "class" number which is based on the
47/// size of the type, and whether or not it is floating point.
48///
49static inline TypeClass getClass(const Type *Ty) {
Chris Lattnerf70c22b2004-06-17 18:19:28 +000050 switch (Ty->getTypeID()) {
Chris Lattner427aeb42004-04-11 19:21:59 +000051 case Type::SByteTyID:
52 case Type::UByteTyID: return cByte; // Byte operands are class #0
53 case Type::ShortTyID:
54 case Type::UShortTyID: return cShort; // Short operands are class #1
55 case Type::IntTyID:
56 case Type::UIntTyID:
57 case Type::PointerTyID: return cInt; // Int's and pointers are class #2
58
59 case Type::FloatTyID:
60 case Type::DoubleTyID: return cFP; // Floating Point is #3
61
62 case Type::LongTyID:
63 case Type::ULongTyID: return cLong; // Longs are class #4
64 default:
65 assert(0 && "Invalid type to getClass!");
66 return cByte; // not reached
67 }
68}
69
70// getClassB - Just like getClass, but treat boolean values as bytes.
71static inline TypeClass getClassB(const Type *Ty) {
72 if (Ty == Type::BoolTy) return cByte;
73 return getClass(Ty);
Chris Lattner986618e2004-02-22 19:47:26 +000074}
Chris Lattnercf93cdd2004-01-30 22:13:44 +000075
Chris Lattner72614082002-10-25 22:55:53 +000076namespace {
Chris Lattnerb4f68ed2002-10-29 22:37:54 +000077 struct ISel : public FunctionPass, InstVisitor<ISel> {
78 TargetMachine &TM;
Chris Lattnereca195e2003-05-08 19:44:13 +000079 MachineFunction *F; // The function we are compiling into
80 MachineBasicBlock *BB; // The current MBB we are compiling
81 int VarArgsFrameIndex; // FrameIndex for start of varargs area
Chris Lattner0e5b79c2004-02-15 01:04:03 +000082 int ReturnAddressIndex; // FrameIndex for the return address
Chris Lattner72614082002-10-25 22:55:53 +000083
Chris Lattner72614082002-10-25 22:55:53 +000084 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
85
Chris Lattner333b2fa2002-12-13 10:09:43 +000086 // MBBMap - Mapping between LLVM BB -> Machine BB
87 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
88
Chris Lattnercb2fd552004-05-13 07:40:27 +000089 // AllocaMap - Mapping from fixed sized alloca instructions to the
90 // FrameIndex for the alloca.
91 std::map<AllocaInst*, unsigned> AllocaMap;
92
Chris Lattnerf70e0c22003-12-28 21:23:38 +000093 ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
Chris Lattner72614082002-10-25 22:55:53 +000094
95 /// runOnFunction - Top level implementation of instruction selection for
96 /// the entire function.
97 ///
Chris Lattnerb4f68ed2002-10-29 22:37:54 +000098 bool runOnFunction(Function &Fn) {
Chris Lattner44827152003-12-28 09:47:19 +000099 // First pass over the function, lower any unknown intrinsic functions
100 // with the IntrinsicLowering class.
101 LowerUnknownIntrinsicFunctionCalls(Fn);
102
Chris Lattner36b36032002-10-29 23:40:58 +0000103 F = &MachineFunction::construct(&Fn, TM);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000104
Chris Lattner065faeb2002-12-28 20:24:02 +0000105 // Create all of the machine basic blocks for the function...
Chris Lattner333b2fa2002-12-13 10:09:43 +0000106 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
107 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
108
Chris Lattner14aa7fe2002-12-16 22:54:46 +0000109 BB = &F->front();
Chris Lattnerdbd73722003-05-06 21:32:22 +0000110
Chris Lattner0e5b79c2004-02-15 01:04:03 +0000111 // Set up a frame object for the return address. This is used by the
112 // llvm.returnaddress & llvm.frameaddress intrinisics.
113 ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
114
Chris Lattnerdbd73722003-05-06 21:32:22 +0000115 // Copy incoming arguments off of the stack...
Chris Lattner065faeb2002-12-28 20:24:02 +0000116 LoadArgumentsToVirtualRegs(Fn);
Chris Lattner14aa7fe2002-12-16 22:54:46 +0000117
Chris Lattner333b2fa2002-12-13 10:09:43 +0000118 // Instruction select everything except PHI nodes
Chris Lattnerb4f68ed2002-10-29 22:37:54 +0000119 visit(Fn);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000120
121 // Select the PHI nodes
122 SelectPHINodes();
123
Chris Lattner986618e2004-02-22 19:47:26 +0000124 // Insert the FP_REG_KILL instructions into blocks that need them.
125 InsertFPRegKills();
126
Chris Lattner72614082002-10-25 22:55:53 +0000127 RegMap.clear();
Chris Lattner333b2fa2002-12-13 10:09:43 +0000128 MBBMap.clear();
Chris Lattnercb2fd552004-05-13 07:40:27 +0000129 AllocaMap.clear();
Chris Lattnerb4f68ed2002-10-29 22:37:54 +0000130 F = 0;
Chris Lattner2a865b02003-07-26 23:05:37 +0000131 // We always build a machine code representation for the function
132 return true;
Chris Lattner72614082002-10-25 22:55:53 +0000133 }
134
Chris Lattnerf0eb7be2002-12-15 21:13:40 +0000135 virtual const char *getPassName() const {
136 return "X86 Simple Instruction Selection";
137 }
138
Chris Lattner72614082002-10-25 22:55:53 +0000139 /// visitBasicBlock - This method is called when we are visiting a new basic
Chris Lattner33f53b52002-10-29 20:48:56 +0000140 /// block. This simply creates a new MachineBasicBlock to emit code into
141 /// and adds it to the current MachineFunction. Subsequent visit* for
142 /// instructions will be invoked for all instructions in the basic block.
Chris Lattner72614082002-10-25 22:55:53 +0000143 ///
144 void visitBasicBlock(BasicBlock &LLVM_BB) {
Chris Lattner333b2fa2002-12-13 10:09:43 +0000145 BB = MBBMap[&LLVM_BB];
Chris Lattner72614082002-10-25 22:55:53 +0000146 }
147
Chris Lattner44827152003-12-28 09:47:19 +0000148 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
149 /// function, lowering any calls to unknown intrinsic functions into the
150 /// equivalent LLVM code.
Misha Brukman538607f2004-03-01 23:53:11 +0000151 ///
Chris Lattner44827152003-12-28 09:47:19 +0000152 void LowerUnknownIntrinsicFunctionCalls(Function &F);
153
Chris Lattner065faeb2002-12-28 20:24:02 +0000154 /// LoadArgumentsToVirtualRegs - Load all of the arguments to this function
155 /// from the stack into virtual registers.
156 ///
157 void LoadArgumentsToVirtualRegs(Function &F);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000158
159 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
160 /// because we have to generate our sources into the source basic blocks,
161 /// not the current one.
162 ///
163 void SelectPHINodes();
164
Chris Lattner986618e2004-02-22 19:47:26 +0000165 /// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks
166 /// that need them. This only occurs due to the floating point stackifier
167 /// not being aggressive enough to handle arbitrary global stackification.
168 ///
169 void InsertFPRegKills();
170
Chris Lattner72614082002-10-25 22:55:53 +0000171 // Visitation methods for various instructions. These methods simply emit
172 // fixed X86 code for each instruction.
173 //
Brian Gaekefa8d5712002-11-22 11:07:01 +0000174
175 // Control flow operators
Chris Lattner72614082002-10-25 22:55:53 +0000176 void visitReturnInst(ReturnInst &RI);
Chris Lattner2df035b2002-11-02 19:27:56 +0000177 void visitBranchInst(BranchInst &BI);
Chris Lattner3e130a22003-01-13 00:32:26 +0000178
179 struct ValueRecord {
Chris Lattner5e2cb8b2003-08-04 02:12:48 +0000180 Value *Val;
Chris Lattner3e130a22003-01-13 00:32:26 +0000181 unsigned Reg;
182 const Type *Ty;
Chris Lattner5e2cb8b2003-08-04 02:12:48 +0000183 ValueRecord(unsigned R, const Type *T) : Val(0), Reg(R), Ty(T) {}
184 ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
Chris Lattner3e130a22003-01-13 00:32:26 +0000185 };
186 void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
Misha Brukmanc8893fc2003-10-23 16:22:08 +0000187 const std::vector<ValueRecord> &Args);
Brian Gaekefa8d5712002-11-22 11:07:01 +0000188 void visitCallInst(CallInst &I);
Brian Gaeked0fde302003-11-11 22:41:34 +0000189 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
Chris Lattnere2954c82002-11-02 20:04:26 +0000190
191 // Arithmetic operators
Chris Lattnerf01729e2002-11-02 20:54:46 +0000192 void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass);
Chris Lattner68aad932002-11-02 20:13:22 +0000193 void visitAdd(BinaryOperator &B) { visitSimpleBinary(B, 0); }
194 void visitSub(BinaryOperator &B) { visitSimpleBinary(B, 1); }
Chris Lattnerca9671d2002-11-02 20:28:58 +0000195 void visitMul(BinaryOperator &B);
Chris Lattnere2954c82002-11-02 20:04:26 +0000196
Chris Lattnerf01729e2002-11-02 20:54:46 +0000197 void visitDiv(BinaryOperator &B) { visitDivRem(B); }
198 void visitRem(BinaryOperator &B) { visitDivRem(B); }
199 void visitDivRem(BinaryOperator &B);
200
Chris Lattnere2954c82002-11-02 20:04:26 +0000201 // Bitwise operators
Chris Lattner68aad932002-11-02 20:13:22 +0000202 void visitAnd(BinaryOperator &B) { visitSimpleBinary(B, 2); }
203 void visitOr (BinaryOperator &B) { visitSimpleBinary(B, 3); }
204 void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
Chris Lattnere2954c82002-11-02 20:04:26 +0000205
Chris Lattner6d40c192003-01-16 16:43:00 +0000206 // Comparison operators...
207 void visitSetCondInst(SetCondInst &I);
Chris Lattnerb2acc512003-10-19 21:09:10 +0000208 unsigned EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
209 MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000210 MachineBasicBlock::iterator MBBI);
Chris Lattner12d96a02004-03-30 21:22:00 +0000211 void visitSelectInst(SelectInst &SI);
212
Chris Lattnerb2acc512003-10-19 21:09:10 +0000213
Chris Lattner6fc3c522002-11-17 21:11:55 +0000214 // Memory Instructions
215 void visitLoadInst(LoadInst &I);
216 void visitStoreInst(StoreInst &I);
Brian Gaeke20244b72002-12-12 15:33:40 +0000217 void visitGetElementPtrInst(GetElementPtrInst &I);
Brian Gaeke20244b72002-12-12 15:33:40 +0000218 void visitAllocaInst(AllocaInst &I);
Chris Lattner3e130a22003-01-13 00:32:26 +0000219 void visitMallocInst(MallocInst &I);
220 void visitFreeInst(FreeInst &I);
Brian Gaeke20244b72002-12-12 15:33:40 +0000221
Chris Lattnere2954c82002-11-02 20:04:26 +0000222 // Other operators
Brian Gaekea1719c92002-10-31 23:03:59 +0000223 void visitShiftInst(ShiftInst &I);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000224 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
Brian Gaekefa8d5712002-11-22 11:07:01 +0000225 void visitCastInst(CastInst &I);
Chris Lattner73815062003-10-18 05:56:40 +0000226 void visitVANextInst(VANextInst &I);
227 void visitVAArgInst(VAArgInst &I);
Chris Lattner72614082002-10-25 22:55:53 +0000228
229 void visitInstruction(Instruction &I) {
230 std::cerr << "Cannot instruction select: " << I;
231 abort();
232 }
233
Brian Gaeke95780cc2002-12-13 07:56:18 +0000234 /// promote32 - Make a value 32-bits wide, and put it somewhere.
Chris Lattner3e130a22003-01-13 00:32:26 +0000235 ///
236 void promote32(unsigned targetReg, const ValueRecord &VR);
237
Chris Lattner721d2d42004-03-08 01:18:36 +0000238 /// getAddressingMode - Get the addressing mode to use to address the
239 /// specified value. The returned value should be used with addFullAddress.
240 void getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
241 unsigned &IndexReg, unsigned &Disp);
242
243
244 /// getGEPIndex - This is used to fold GEP instructions into X86 addressing
245 /// expressions.
Chris Lattnerb6bac512004-02-25 06:13:04 +0000246 void getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
247 std::vector<Value*> &GEPOps,
248 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
249 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
250
251 /// isGEPFoldable - Return true if the specified GEP can be completely
252 /// folded into the addressing mode of a load/store or lea instruction.
253 bool isGEPFoldable(MachineBasicBlock *MBB,
254 Value *Src, User::op_iterator IdxBegin,
255 User::op_iterator IdxEnd, unsigned &BaseReg,
256 unsigned &Scale, unsigned &IndexReg, unsigned &Disp);
257
Chris Lattner3e130a22003-01-13 00:32:26 +0000258 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
259 /// constant expression GEP support.
260 ///
Chris Lattner827832c2004-02-22 17:05:38 +0000261 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
Chris Lattner333b2fa2002-12-13 10:09:43 +0000262 Value *Src, User::op_iterator IdxBegin,
Chris Lattnerc0812d82002-12-13 06:56:29 +0000263 User::op_iterator IdxEnd, unsigned TargetReg);
264
Chris Lattner548f61d2003-04-23 17:22:12 +0000265 /// emitCastOperation - Common code shared between visitCastInst and
266 /// constant expression cast support.
Misha Brukman538607f2004-03-01 23:53:11 +0000267 ///
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000268 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
Chris Lattner548f61d2003-04-23 17:22:12 +0000269 Value *Src, const Type *DestTy, unsigned TargetReg);
270
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000271 /// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
272 /// and constant expression support.
Misha Brukman538607f2004-03-01 23:53:11 +0000273 ///
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000274 void emitSimpleBinaryOperation(MachineBasicBlock *BB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000275 MachineBasicBlock::iterator IP,
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000276 Value *Op0, Value *Op1,
277 unsigned OperatorClass, unsigned TargetReg);
278
Chris Lattner6621ed92004-04-11 21:23:56 +0000279 /// emitBinaryFPOperation - This method handles emission of floating point
280 /// Add (0), Sub (1), Mul (2), and Div (3) operations.
281 void emitBinaryFPOperation(MachineBasicBlock *BB,
282 MachineBasicBlock::iterator IP,
283 Value *Op0, Value *Op1,
284 unsigned OperatorClass, unsigned TargetReg);
285
Chris Lattner462fa822004-04-11 20:56:28 +0000286 void emitMultiply(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
287 Value *Op0, Value *Op1, unsigned TargetReg);
288
289 void doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
290 unsigned DestReg, const Type *DestTy,
291 unsigned Op0Reg, unsigned Op1Reg);
292 void doMultiplyConst(MachineBasicBlock *MBB,
293 MachineBasicBlock::iterator MBBI,
294 unsigned DestReg, const Type *DestTy,
295 unsigned Op0Reg, unsigned Op1Val);
296
Chris Lattnercadff442003-10-23 17:21:43 +0000297 void emitDivRemOperation(MachineBasicBlock *BB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000298 MachineBasicBlock::iterator IP,
Chris Lattner462fa822004-04-11 20:56:28 +0000299 Value *Op0, Value *Op1, bool isDiv,
300 unsigned TargetReg);
Chris Lattnercadff442003-10-23 17:21:43 +0000301
Chris Lattner58c41fe2003-08-24 19:19:47 +0000302 /// emitSetCCOperation - Common code shared between visitSetCondInst and
303 /// constant expression support.
Misha Brukman538607f2004-03-01 23:53:11 +0000304 ///
Chris Lattner58c41fe2003-08-24 19:19:47 +0000305 void emitSetCCOperation(MachineBasicBlock *BB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000306 MachineBasicBlock::iterator IP,
Chris Lattner58c41fe2003-08-24 19:19:47 +0000307 Value *Op0, Value *Op1, unsigned Opcode,
308 unsigned TargetReg);
Brian Gaeke2dd3e1b2003-11-22 05:18:35 +0000309
310 /// emitShiftOperation - Common code shared between visitShiftInst and
311 /// constant expression support.
Misha Brukman538607f2004-03-01 23:53:11 +0000312 ///
Brian Gaekedfcc9cf2003-11-22 06:49:41 +0000313 void emitShiftOperation(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000314 MachineBasicBlock::iterator IP,
Brian Gaekedfcc9cf2003-11-22 06:49:41 +0000315 Value *Op, Value *ShiftAmount, bool isLeftShift,
316 const Type *ResultTy, unsigned DestReg);
317
Chris Lattner12d96a02004-03-30 21:22:00 +0000318 /// emitSelectOperation - Common code shared between visitSelectInst and the
319 /// constant expression support.
320 void emitSelectOperation(MachineBasicBlock *MBB,
321 MachineBasicBlock::iterator IP,
322 Value *Cond, Value *TrueVal, Value *FalseVal,
323 unsigned DestReg);
Chris Lattner58c41fe2003-08-24 19:19:47 +0000324
Chris Lattnerc5291f52002-10-27 21:16:59 +0000325 /// copyConstantToRegister - Output the instructions required to put the
326 /// specified constant into the specified register.
327 ///
Chris Lattner8a307e82002-12-16 19:32:50 +0000328 void copyConstantToRegister(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000329 MachineBasicBlock::iterator MBBI,
Chris Lattner8a307e82002-12-16 19:32:50 +0000330 Constant *C, unsigned Reg);
Chris Lattnerc5291f52002-10-27 21:16:59 +0000331
Chris Lattner01cdb1b2004-06-11 05:33:49 +0000332 void emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
333 unsigned LHS, unsigned RHS);
334
Chris Lattner3e130a22003-01-13 00:32:26 +0000335 /// makeAnotherReg - This method returns the next register number we haven't
336 /// yet used.
337 ///
338 /// Long values are handled somewhat specially. They are always allocated
339 /// as pairs of 32 bit integer values. The register number returned is the
340 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
341 /// of the long value.
342 ///
Chris Lattnerc0812d82002-12-13 06:56:29 +0000343 unsigned makeAnotherReg(const Type *Ty) {
Chris Lattner7db1fa92003-07-30 05:33:48 +0000344 assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
345 "Current target doesn't have X86 reg info??");
346 const X86RegisterInfo *MRI =
347 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
Chris Lattner3e130a22003-01-13 00:32:26 +0000348 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
Misha Brukmanc8893fc2003-10-23 16:22:08 +0000349 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
350 // Create the lower part
351 F->getSSARegMap()->createVirtualRegister(RC);
352 // Create the upper part.
353 return F->getSSARegMap()->createVirtualRegister(RC)-1;
Chris Lattner3e130a22003-01-13 00:32:26 +0000354 }
355
Chris Lattnerc0812d82002-12-13 06:56:29 +0000356 // Add the mapping of regnumber => reg class to MachineFunction
Chris Lattner7db1fa92003-07-30 05:33:48 +0000357 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
Chris Lattner3e130a22003-01-13 00:32:26 +0000358 return F->getSSARegMap()->createVirtualRegister(RC);
Brian Gaeke20244b72002-12-12 15:33:40 +0000359 }
360
Chris Lattnercb2fd552004-05-13 07:40:27 +0000361 /// getReg - This method turns an LLVM value into a register number.
Chris Lattner72614082002-10-25 22:55:53 +0000362 ///
363 unsigned getReg(Value &V) { return getReg(&V); } // Allow references
Chris Lattnerf08ad9f2002-12-13 10:50:40 +0000364 unsigned getReg(Value *V) {
365 // Just append to the end of the current bb.
366 MachineBasicBlock::iterator It = BB->end();
367 return getReg(V, BB, It);
368 }
Brian Gaeke71794c02002-12-13 11:22:48 +0000369 unsigned getReg(Value *V, MachineBasicBlock *MBB,
Chris Lattnercb2fd552004-05-13 07:40:27 +0000370 MachineBasicBlock::iterator IPt);
Chris Lattner427aeb42004-04-11 19:21:59 +0000371
Chris Lattnercb2fd552004-05-13 07:40:27 +0000372 /// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
373 /// that is to be statically allocated with the initial stack frame
374 /// adjustment.
375 unsigned getFixedSizedAllocaFI(AllocaInst *AI);
Chris Lattner72614082002-10-25 22:55:53 +0000376 };
377}
378
Chris Lattnercb2fd552004-05-13 07:40:27 +0000379/// dyn_castFixedAlloca - If the specified value is a fixed size alloca
380/// instruction in the entry block, return it. Otherwise, return a null
381/// pointer.
382static AllocaInst *dyn_castFixedAlloca(Value *V) {
383 if (AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
384 BasicBlock *BB = AI->getParent();
385 if (isa<ConstantUInt>(AI->getArraySize()) && BB ==&BB->getParent()->front())
386 return AI;
387 }
388 return 0;
389}
390
391/// getReg - This method turns an LLVM value into a register number.
392///
393unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
394 MachineBasicBlock::iterator IPt) {
395 // If this operand is a constant, emit the code to copy the constant into
396 // the register here...
Chris Lattnercb2fd552004-05-13 07:40:27 +0000397 if (Constant *C = dyn_cast<Constant>(V)) {
398 unsigned Reg = makeAnotherReg(V->getType());
399 copyConstantToRegister(MBB, IPt, C, Reg);
400 return Reg;
Chris Lattnercb2fd552004-05-13 07:40:27 +0000401 } else if (CastInst *CI = dyn_cast<CastInst>(V)) {
Chris Lattner8b486a12004-06-29 00:14:38 +0000402 // Do not emit noop casts at all, unless it's a double -> float cast.
403 if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()) &&
404 (CI->getType() != Type::FloatTy ||
405 CI->getOperand(0)->getType() != Type::DoubleTy))
Chris Lattnercb2fd552004-05-13 07:40:27 +0000406 return getReg(CI->getOperand(0), MBB, IPt);
407 } else if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
408 // If the alloca address couldn't be folded into the instruction addressing,
409 // emit an explicit LEA as appropriate.
410 unsigned Reg = makeAnotherReg(V->getType());
411 unsigned FI = getFixedSizedAllocaFI(AI);
412 addFrameReference(BuildMI(*MBB, IPt, X86::LEA32r, 4, Reg), FI);
413 return Reg;
414 }
415
416 unsigned &Reg = RegMap[V];
417 if (Reg == 0) {
418 Reg = makeAnotherReg(V->getType());
419 RegMap[V] = Reg;
420 }
421
422 return Reg;
423}
424
425/// getFixedSizedAllocaFI - Return the frame index for a fixed sized alloca
426/// that is to be statically allocated with the initial stack frame
427/// adjustment.
428unsigned ISel::getFixedSizedAllocaFI(AllocaInst *AI) {
429 // Already computed this?
430 std::map<AllocaInst*, unsigned>::iterator I = AllocaMap.lower_bound(AI);
431 if (I != AllocaMap.end() && I->first == AI) return I->second;
432
433 const Type *Ty = AI->getAllocatedType();
434 ConstantUInt *CUI = cast<ConstantUInt>(AI->getArraySize());
435 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
436 TySize *= CUI->getValue(); // Get total allocated size...
437 unsigned Alignment = TM.getTargetData().getTypeAlignment(Ty);
438
439 // Create a new stack object using the frame manager...
440 int FrameIdx = F->getFrameInfo()->CreateStackObject(TySize, Alignment);
441 AllocaMap.insert(I, std::make_pair(AI, FrameIdx));
442 return FrameIdx;
443}
444
445
Chris Lattnerc5291f52002-10-27 21:16:59 +0000446/// copyConstantToRegister - Output the instructions required to put the
447/// specified constant into the specified register.
448///
Chris Lattner8a307e82002-12-16 19:32:50 +0000449void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000450 MachineBasicBlock::iterator IP,
Chris Lattner8a307e82002-12-16 19:32:50 +0000451 Constant *C, unsigned R) {
Chris Lattnerc0812d82002-12-13 06:56:29 +0000452 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000453 unsigned Class = 0;
454 switch (CE->getOpcode()) {
455 case Instruction::GetElementPtr:
Brian Gaeke68b1edc2002-12-16 04:23:29 +0000456 emitGEPOperation(MBB, IP, CE->getOperand(0),
Chris Lattner333b2fa2002-12-13 10:09:43 +0000457 CE->op_begin()+1, CE->op_end(), R);
Chris Lattnerc0812d82002-12-13 06:56:29 +0000458 return;
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000459 case Instruction::Cast:
Chris Lattner548f61d2003-04-23 17:22:12 +0000460 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
Chris Lattner4b12cde2003-04-21 21:33:44 +0000461 return;
Chris Lattnerc0812d82002-12-13 06:56:29 +0000462
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000463 case Instruction::Xor: ++Class; // FALL THROUGH
464 case Instruction::Or: ++Class; // FALL THROUGH
465 case Instruction::And: ++Class; // FALL THROUGH
466 case Instruction::Sub: ++Class; // FALL THROUGH
467 case Instruction::Add:
468 emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
469 Class, R);
470 return;
471
Chris Lattner462fa822004-04-11 20:56:28 +0000472 case Instruction::Mul:
473 emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
Chris Lattnercadff442003-10-23 17:21:43 +0000474 return;
Chris Lattner462fa822004-04-11 20:56:28 +0000475
Chris Lattnercadff442003-10-23 17:21:43 +0000476 case Instruction::Div:
Chris Lattner462fa822004-04-11 20:56:28 +0000477 case Instruction::Rem:
478 emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
479 CE->getOpcode() == Instruction::Div, R);
Chris Lattnercadff442003-10-23 17:21:43 +0000480 return;
Chris Lattnercadff442003-10-23 17:21:43 +0000481
Chris Lattner58c41fe2003-08-24 19:19:47 +0000482 case Instruction::SetNE:
483 case Instruction::SetEQ:
484 case Instruction::SetLT:
485 case Instruction::SetGT:
486 case Instruction::SetLE:
487 case Instruction::SetGE:
488 emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
489 CE->getOpcode(), R);
490 return;
491
Brian Gaeke2dd3e1b2003-11-22 05:18:35 +0000492 case Instruction::Shl:
493 case Instruction::Shr:
494 emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
Brian Gaekedfcc9cf2003-11-22 06:49:41 +0000495 CE->getOpcode() == Instruction::Shl, CE->getType(), R);
496 return;
Brian Gaeke2dd3e1b2003-11-22 05:18:35 +0000497
Chris Lattner12d96a02004-03-30 21:22:00 +0000498 case Instruction::Select:
499 emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
500 CE->getOperand(2), R);
501 return;
502
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000503 default:
Chris Lattner76e2df22004-07-15 02:14:30 +0000504 std::cerr << "Offending expr: " << *C << "\n";
Chris Lattnerb2acc512003-10-19 21:09:10 +0000505 assert(0 && "Constant expression not yet handled!\n");
Chris Lattnerb515f6d2003-05-08 20:49:25 +0000506 }
Brian Gaeke20244b72002-12-12 15:33:40 +0000507 }
Chris Lattnerc5291f52002-10-27 21:16:59 +0000508
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000509 if (C->getType()->isIntegral()) {
Chris Lattner6b993cc2002-12-15 08:02:15 +0000510 unsigned Class = getClassB(C->getType());
Chris Lattner3e130a22003-01-13 00:32:26 +0000511
512 if (Class == cLong) {
513 // Copy the value into the register pair.
Chris Lattnerc07736a2003-07-23 15:22:26 +0000514 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000515 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(Val & 0xFFFFFFFF);
516 BuildMI(*MBB, IP, X86::MOV32ri, 1, R+1).addImm(Val >> 32);
Chris Lattner3e130a22003-01-13 00:32:26 +0000517 return;
518 }
519
Chris Lattner94af4142002-12-25 05:13:53 +0000520 assert(Class <= cInt && "Type not handled yet!");
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000521
522 static const unsigned IntegralOpcodeTab[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000523 X86::MOV8ri, X86::MOV16ri, X86::MOV32ri
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000524 };
525
Chris Lattner6b993cc2002-12-15 08:02:15 +0000526 if (C->getType() == Type::BoolTy) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000527 BuildMI(*MBB, IP, X86::MOV8ri, 1, R).addImm(C == ConstantBool::True);
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000528 } else {
Chris Lattnerc07736a2003-07-23 15:22:26 +0000529 ConstantInt *CI = cast<ConstantInt>(C);
Chris Lattneree352852004-02-29 07:22:16 +0000530 BuildMI(*MBB, IP, IntegralOpcodeTab[Class],1,R).addImm(CI->getRawValue());
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000531 }
Chris Lattner94af4142002-12-25 05:13:53 +0000532 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
Chris Lattneraf703622004-02-02 18:56:30 +0000533 if (CFP->isExactlyValue(+0.0))
Chris Lattneree352852004-02-29 07:22:16 +0000534 BuildMI(*MBB, IP, X86::FLD0, 0, R);
Chris Lattneraf703622004-02-02 18:56:30 +0000535 else if (CFP->isExactlyValue(+1.0))
Chris Lattneree352852004-02-29 07:22:16 +0000536 BuildMI(*MBB, IP, X86::FLD1, 0, R);
Chris Lattner94af4142002-12-25 05:13:53 +0000537 else {
Chris Lattner3e130a22003-01-13 00:32:26 +0000538 // Otherwise we need to spill the constant to memory...
539 MachineConstantPool *CP = F->getConstantPool();
540 unsigned CPI = CP->getConstantPoolIndex(CFP);
Chris Lattner6c09db22003-10-20 04:11:23 +0000541 const Type *Ty = CFP->getType();
542
543 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000544 unsigned LoadOpcode = Ty == Type::FloatTy ? X86::FLD32m : X86::FLD64m;
Chris Lattneree352852004-02-29 07:22:16 +0000545 addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 4, R), CPI);
Chris Lattner94af4142002-12-25 05:13:53 +0000546 }
547
Chris Lattnerf08ad9f2002-12-13 10:50:40 +0000548 } else if (isa<ConstantPointerNull>(C)) {
Brian Gaeke20244b72002-12-12 15:33:40 +0000549 // Copy zero (null pointer) to the register.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000550 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addImm(0);
Reid Spencer8863f182004-07-18 00:38:32 +0000551 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
552 BuildMI(*MBB, IP, X86::MOV32ri, 1, R).addGlobalAddress(GV);
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000553 } else {
Chris Lattner76e2df22004-07-15 02:14:30 +0000554 std::cerr << "Offending constant: " << *C << "\n";
Chris Lattnerb1761fc2002-11-02 01:15:18 +0000555 assert(0 && "Type not handled yet!");
Chris Lattnerc5291f52002-10-27 21:16:59 +0000556 }
557}
558
Chris Lattner065faeb2002-12-28 20:24:02 +0000559/// LoadArgumentsToVirtualRegs - Load all of the arguments to this function from
560/// the stack into virtual registers.
561///
562void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
563 // Emit instructions to load the arguments... On entry to a function on the
564 // X86, the stack frame looks like this:
565 //
566 // [ESP] -- return address
Chris Lattner3e130a22003-01-13 00:32:26 +0000567 // [ESP + 4] -- first argument (leftmost lexically)
568 // [ESP + 8] -- second argument, if first argument is four bytes in size
Chris Lattner065faeb2002-12-28 20:24:02 +0000569 // ...
570 //
Chris Lattnerf158da22003-01-16 02:20:12 +0000571 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
Chris Lattneraa09b752002-12-28 21:08:28 +0000572 MachineFrameInfo *MFI = F->getFrameInfo();
Chris Lattner065faeb2002-12-28 20:24:02 +0000573
574 for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
Chris Lattner427aeb42004-04-11 19:21:59 +0000575 bool ArgLive = !I->use_empty();
576 unsigned Reg = ArgLive ? getReg(*I) : 0;
Chris Lattner065faeb2002-12-28 20:24:02 +0000577 int FI; // Frame object index
Chris Lattner427aeb42004-04-11 19:21:59 +0000578
Chris Lattner065faeb2002-12-28 20:24:02 +0000579 switch (getClassB(I->getType())) {
580 case cByte:
Chris Lattner427aeb42004-04-11 19:21:59 +0000581 if (ArgLive) {
582 FI = MFI->CreateFixedObject(1, ArgOffset);
583 addFrameReference(BuildMI(BB, X86::MOV8rm, 4, Reg), FI);
584 }
Chris Lattner065faeb2002-12-28 20:24:02 +0000585 break;
586 case cShort:
Chris Lattner427aeb42004-04-11 19:21:59 +0000587 if (ArgLive) {
588 FI = MFI->CreateFixedObject(2, ArgOffset);
589 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, Reg), FI);
590 }
Chris Lattner065faeb2002-12-28 20:24:02 +0000591 break;
592 case cInt:
Chris Lattner427aeb42004-04-11 19:21:59 +0000593 if (ArgLive) {
594 FI = MFI->CreateFixedObject(4, ArgOffset);
595 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
596 }
Chris Lattner065faeb2002-12-28 20:24:02 +0000597 break;
Chris Lattner3e130a22003-01-13 00:32:26 +0000598 case cLong:
Chris Lattner427aeb42004-04-11 19:21:59 +0000599 if (ArgLive) {
600 FI = MFI->CreateFixedObject(8, ArgOffset);
601 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg), FI);
602 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, Reg+1), FI, 4);
603 }
Chris Lattner3e130a22003-01-13 00:32:26 +0000604 ArgOffset += 4; // longs require 4 additional bytes
605 break;
Chris Lattner065faeb2002-12-28 20:24:02 +0000606 case cFP:
Chris Lattner427aeb42004-04-11 19:21:59 +0000607 if (ArgLive) {
608 unsigned Opcode;
609 if (I->getType() == Type::FloatTy) {
610 Opcode = X86::FLD32m;
611 FI = MFI->CreateFixedObject(4, ArgOffset);
612 } else {
613 Opcode = X86::FLD64m;
614 FI = MFI->CreateFixedObject(8, ArgOffset);
615 }
616 addFrameReference(BuildMI(BB, Opcode, 4, Reg), FI);
Chris Lattner065faeb2002-12-28 20:24:02 +0000617 }
Chris Lattner427aeb42004-04-11 19:21:59 +0000618 if (I->getType() == Type::DoubleTy)
619 ArgOffset += 4; // doubles require 4 additional bytes
Chris Lattner065faeb2002-12-28 20:24:02 +0000620 break;
621 default:
622 assert(0 && "Unhandled argument type!");
623 }
Chris Lattner3e130a22003-01-13 00:32:26 +0000624 ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
Chris Lattner065faeb2002-12-28 20:24:02 +0000625 }
Chris Lattnereca195e2003-05-08 19:44:13 +0000626
627 // If the function takes variable number of arguments, add a frame offset for
628 // the start of the first vararg value... this is used to expand
629 // llvm.va_start.
630 if (Fn.getFunctionType()->isVarArg())
631 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
Chris Lattner065faeb2002-12-28 20:24:02 +0000632}
633
634
Chris Lattner333b2fa2002-12-13 10:09:43 +0000635/// SelectPHINodes - Insert machine code to generate phis. This is tricky
636/// because we have to generate our sources into the source basic blocks, not
637/// the current one.
638///
639void ISel::SelectPHINodes() {
Chris Lattnerd029cd22004-06-02 05:55:25 +0000640 const TargetInstrInfo &TII = *TM.getInstrInfo();
Chris Lattner333b2fa2002-12-13 10:09:43 +0000641 const Function &LF = *F->getFunction(); // The LLVM function...
642 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
643 const BasicBlock *BB = I;
Chris Lattner168aa902004-02-29 07:10:16 +0000644 MachineBasicBlock &MBB = *MBBMap[I];
Chris Lattner333b2fa2002-12-13 10:09:43 +0000645
646 // Loop over all of the PHI nodes in the LLVM basic block...
Chris Lattner168aa902004-02-29 07:10:16 +0000647 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
Chris Lattner333b2fa2002-12-13 10:09:43 +0000648 for (BasicBlock::const_iterator I = BB->begin();
Chris Lattnera81fc682003-10-19 00:26:11 +0000649 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
Chris Lattner3e130a22003-01-13 00:32:26 +0000650
Chris Lattner333b2fa2002-12-13 10:09:43 +0000651 // Create a new machine instr PHI node, and insert it.
Chris Lattner3e130a22003-01-13 00:32:26 +0000652 unsigned PHIReg = getReg(*PN);
Chris Lattner168aa902004-02-29 07:10:16 +0000653 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
654 X86::PHI, PN->getNumOperands(), PHIReg);
Chris Lattner3e130a22003-01-13 00:32:26 +0000655
656 MachineInstr *LongPhiMI = 0;
Chris Lattner168aa902004-02-29 07:10:16 +0000657 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
658 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
659 X86::PHI, PN->getNumOperands(), PHIReg+1);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000660
Chris Lattnera6e73f12003-05-12 14:22:21 +0000661 // PHIValues - Map of blocks to incoming virtual registers. We use this
662 // so that we only initialize one incoming value for a particular block,
663 // even if the block has multiple entries in the PHI node.
664 //
665 std::map<MachineBasicBlock*, unsigned> PHIValues;
666
Chris Lattner333b2fa2002-12-13 10:09:43 +0000667 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
668 MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
Chris Lattnera6e73f12003-05-12 14:22:21 +0000669 unsigned ValReg;
670 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
671 PHIValues.lower_bound(PredMBB);
Chris Lattner333b2fa2002-12-13 10:09:43 +0000672
Chris Lattnera6e73f12003-05-12 14:22:21 +0000673 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
674 // We already inserted an initialization of the register for this
675 // predecessor. Recycle it.
676 ValReg = EntryIt->second;
677
678 } else {
Chris Lattnera81fc682003-10-19 00:26:11 +0000679 // Get the incoming value into a virtual register.
Chris Lattnera6e73f12003-05-12 14:22:21 +0000680 //
Chris Lattnera81fc682003-10-19 00:26:11 +0000681 Value *Val = PN->getIncomingValue(i);
682
683 // If this is a constant or GlobalValue, we may have to insert code
684 // into the basic block to compute it into a virtual register.
Reid Spencer8863f182004-07-18 00:38:32 +0000685 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val))) {
Chris Lattnercb2fd552004-05-13 07:40:27 +0000686 // Simple constants get emitted at the end of the basic block,
687 // before any terminator instructions. We "know" that the code to
688 // move a constant into a register will never clobber any flags.
689 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
Chris Lattnera81fc682003-10-19 00:26:11 +0000690 } else {
Chris Lattnercb2fd552004-05-13 07:40:27 +0000691 // Because we don't want to clobber any values which might be in
692 // physical registers with the computation of this constant (which
693 // might be arbitrarily complex if it is a constant expression),
694 // just insert the computation at the top of the basic block.
695 MachineBasicBlock::iterator PI = PredMBB->begin();
696
697 // Skip over any PHI nodes though!
698 while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
699 ++PI;
700
701 ValReg = getReg(Val, PredMBB, PI);
Chris Lattnera81fc682003-10-19 00:26:11 +0000702 }
Chris Lattnera6e73f12003-05-12 14:22:21 +0000703
704 // Remember that we inserted a value for this PHI for this predecessor
705 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
706 }
707
Misha Brukmanc8893fc2003-10-23 16:22:08 +0000708 PhiMI->addRegOperand(ValReg);
Chris Lattner3e130a22003-01-13 00:32:26 +0000709 PhiMI->addMachineBasicBlockOperand(PredMBB);
Misha Brukmanc8893fc2003-10-23 16:22:08 +0000710 if (LongPhiMI) {
711 LongPhiMI->addRegOperand(ValReg+1);
712 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
713 }
Chris Lattner333b2fa2002-12-13 10:09:43 +0000714 }
Chris Lattner168aa902004-02-29 07:10:16 +0000715
716 // Now that we emitted all of the incoming values for the PHI node, make
717 // sure to reposition the InsertPoint after the PHI that we just added.
718 // This is needed because we might have inserted a constant into this
719 // block, right after the PHI's which is before the old insert point!
720 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
721 ++PHIInsertPoint;
Chris Lattner333b2fa2002-12-13 10:09:43 +0000722 }
723 }
724}
725
Chris Lattner986618e2004-02-22 19:47:26 +0000726/// RequiresFPRegKill - The floating point stackifier pass cannot insert
727/// compensation code on critical edges. As such, it requires that we kill all
728/// FP registers on the exit from any blocks that either ARE critical edges, or
729/// branch to a block that has incoming critical edges.
730///
731/// Note that this kill instruction will eventually be eliminated when
732/// restrictions in the stackifier are relaxed.
733///
Brian Gaeke1afe7732004-04-28 04:45:55 +0000734static bool RequiresFPRegKill(const MachineBasicBlock *MBB) {
Chris Lattner986618e2004-02-22 19:47:26 +0000735#if 0
Brian Gaeke1afe7732004-04-28 04:45:55 +0000736 const BasicBlock *BB = MBB->getBasicBlock ();
Chris Lattner986618e2004-02-22 19:47:26 +0000737 for (succ_const_iterator SI = succ_begin(BB), E = succ_end(BB); SI!=E; ++SI) {
738 const BasicBlock *Succ = *SI;
739 pred_const_iterator PI = pred_begin(Succ), PE = pred_end(Succ);
740 ++PI; // Block have at least one predecessory
741 if (PI != PE) { // If it has exactly one, this isn't crit edge
742 // If this block has more than one predecessor, check all of the
743 // predecessors to see if they have multiple successors. If so, then the
744 // block we are analyzing needs an FPRegKill.
745 for (PI = pred_begin(Succ); PI != PE; ++PI) {
746 const BasicBlock *Pred = *PI;
747 succ_const_iterator SI2 = succ_begin(Pred);
748 ++SI2; // There must be at least one successor of this block.
749 if (SI2 != succ_end(Pred))
750 return true; // Yes, we must insert the kill on this edge.
751 }
752 }
753 }
754 // If we got this far, there is no need to insert the kill instruction.
755 return false;
756#else
757 return true;
758#endif
759}
760
761// InsertFPRegKills - Insert FP_REG_KILL instructions into basic blocks that
762// need them. This only occurs due to the floating point stackifier not being
763// aggressive enough to handle arbitrary global stackification.
764//
765// Currently we insert an FP_REG_KILL instruction into each block that uses or
766// defines a floating point virtual register.
767//
768// When the global register allocators (like linear scan) finally update live
769// variable analysis, we can keep floating point values in registers across
770// portions of the CFG that do not involve critical edges. This will be a big
771// win, but we are waiting on the global allocators before we can do this.
772//
773// With a bit of work, the floating point stackifier pass can be enhanced to
774// break critical edges as needed (to make a place to put compensation code),
775// but this will require some infrastructure improvements as well.
776//
777void ISel::InsertFPRegKills() {
778 SSARegMap &RegMap = *F->getSSARegMap();
Chris Lattner986618e2004-02-22 19:47:26 +0000779
780 for (MachineFunction::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) {
Chris Lattner986618e2004-02-22 19:47:26 +0000781 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I!=E; ++I)
Alkis Evlogimenos71e353e2004-02-26 22:00:20 +0000782 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
783 MachineOperand& MO = I->getOperand(i);
784 if (MO.isRegister() && MO.getReg()) {
785 unsigned Reg = MO.getReg();
Chris Lattner986618e2004-02-22 19:47:26 +0000786 if (MRegisterInfo::isVirtualRegister(Reg))
Chris Lattner65cf42d2004-02-23 07:29:45 +0000787 if (RegMap.getRegClass(Reg)->getSize() == 10)
788 goto UsesFPReg;
Chris Lattner986618e2004-02-22 19:47:26 +0000789 }
Alkis Evlogimenos71e353e2004-02-26 22:00:20 +0000790 }
Chris Lattner65cf42d2004-02-23 07:29:45 +0000791 // If we haven't found an FP register use or def in this basic block, check
792 // to see if any of our successors has an FP PHI node, which will cause a
793 // copy to be inserted into this block.
Brian Gaeke235aa5e2004-04-28 04:34:16 +0000794 for (MachineBasicBlock::const_succ_iterator SI = BB->succ_begin(),
795 SE = BB->succ_end(); SI != SE; ++SI) {
796 MachineBasicBlock *SBB = *SI;
Chris Lattnerfbc39d52004-02-23 07:42:19 +0000797 for (MachineBasicBlock::iterator I = SBB->begin();
798 I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
799 if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
800 goto UsesFPReg;
Chris Lattner986618e2004-02-22 19:47:26 +0000801 }
Chris Lattnerfbc39d52004-02-23 07:42:19 +0000802 }
Chris Lattner65cf42d2004-02-23 07:29:45 +0000803 continue;
804 UsesFPReg:
805 // Okay, this block uses an FP register. If the block has successors (ie,
806 // it's not an unwind/return), insert the FP_REG_KILL instruction.
Brian Gaeke1afe7732004-04-28 04:45:55 +0000807 if (BB->succ_size () && RequiresFPRegKill(BB)) {
Chris Lattneree352852004-02-29 07:22:16 +0000808 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
Chris Lattner65cf42d2004-02-23 07:29:45 +0000809 ++NumFPKill;
Chris Lattner986618e2004-02-22 19:47:26 +0000810 }
811 }
812}
813
814
Chris Lattner9f1b5312004-05-13 15:12:43 +0000815void ISel::getAddressingMode(Value *Addr, unsigned &BaseReg, unsigned &Scale,
816 unsigned &IndexReg, unsigned &Disp) {
817 BaseReg = 0; Scale = 1; IndexReg = 0; Disp = 0;
818 if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Addr)) {
819 if (isGEPFoldable(BB, GEP->getOperand(0), GEP->op_begin()+1, GEP->op_end(),
820 BaseReg, Scale, IndexReg, Disp))
821 return;
822 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
823 if (CE->getOpcode() == Instruction::GetElementPtr)
824 if (isGEPFoldable(BB, CE->getOperand(0), CE->op_begin()+1, CE->op_end(),
825 BaseReg, Scale, IndexReg, Disp))
826 return;
827 }
828
829 // If it's not foldable, reset addr mode.
830 BaseReg = getReg(Addr);
831 Scale = 1; IndexReg = 0; Disp = 0;
832}
833
Chris Lattner307ecba2004-03-30 22:39:09 +0000834// canFoldSetCCIntoBranchOrSelect - Return the setcc instruction if we can fold
835// it into the conditional branch or select instruction which is the only user
836// of the cc instruction. This is the case if the conditional branch is the
Chris Lattnera6f9fe62004-06-18 00:29:22 +0000837// only user of the setcc. We also don't handle long arguments below, so we
838// reject them here as well.
Chris Lattner6d40c192003-01-16 16:43:00 +0000839//
Chris Lattner307ecba2004-03-30 22:39:09 +0000840static SetCondInst *canFoldSetCCIntoBranchOrSelect(Value *V) {
Chris Lattner6d40c192003-01-16 16:43:00 +0000841 if (SetCondInst *SCI = dyn_cast<SetCondInst>(V))
Chris Lattner307ecba2004-03-30 22:39:09 +0000842 if (SCI->hasOneUse()) {
843 Instruction *User = cast<Instruction>(SCI->use_back());
844 if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
Chris Lattner48c937e2004-04-06 17:34:50 +0000845 (getClassB(SCI->getOperand(0)->getType()) != cLong ||
846 SCI->getOpcode() == Instruction::SetEQ ||
847 SCI->getOpcode() == Instruction::SetNE))
Chris Lattner6d40c192003-01-16 16:43:00 +0000848 return SCI;
849 }
850 return 0;
851}
Chris Lattner333b2fa2002-12-13 10:09:43 +0000852
Chris Lattner6d40c192003-01-16 16:43:00 +0000853// Return a fixed numbering for setcc instructions which does not depend on the
854// order of the opcodes.
855//
856static unsigned getSetCCNumber(unsigned Opcode) {
857 switch(Opcode) {
858 default: assert(0 && "Unknown setcc instruction!");
859 case Instruction::SetEQ: return 0;
860 case Instruction::SetNE: return 1;
861 case Instruction::SetLT: return 2;
Chris Lattner55f6fab2003-01-16 18:07:23 +0000862 case Instruction::SetGE: return 3;
863 case Instruction::SetGT: return 4;
864 case Instruction::SetLE: return 5;
Chris Lattner6d40c192003-01-16 16:43:00 +0000865 }
866}
Chris Lattner06925362002-11-17 21:56:38 +0000867
Chris Lattner6d40c192003-01-16 16:43:00 +0000868// LLVM -> X86 signed X86 unsigned
869// ----- ---------- ------------
870// seteq -> sete sete
871// setne -> setne setne
872// setlt -> setl setb
Chris Lattner55f6fab2003-01-16 18:07:23 +0000873// setge -> setge setae
Chris Lattner6d40c192003-01-16 16:43:00 +0000874// setgt -> setg seta
875// setle -> setle setbe
Chris Lattnerb2acc512003-10-19 21:09:10 +0000876// ----
877// sets // Used by comparison with 0 optimization
878// setns
879static const unsigned SetCCOpcodeTab[2][8] = {
880 { X86::SETEr, X86::SETNEr, X86::SETBr, X86::SETAEr, X86::SETAr, X86::SETBEr,
881 0, 0 },
882 { X86::SETEr, X86::SETNEr, X86::SETLr, X86::SETGEr, X86::SETGr, X86::SETLEr,
883 X86::SETSr, X86::SETNSr },
Chris Lattner6d40c192003-01-16 16:43:00 +0000884};
885
Chris Lattner01cdb1b2004-06-11 05:33:49 +0000886/// emitUCOMr - In the future when we support processors before the P6, this
887/// wraps the logic for emitting an FUCOMr vs FUCOMIr.
888void ISel::emitUCOMr(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
889 unsigned LHS, unsigned RHS) {
890 if (0) { // for processors prior to the P6
891 BuildMI(*MBB, IP, X86::FUCOMr, 2).addReg(LHS).addReg(RHS);
892 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
893 BuildMI(*MBB, IP, X86::SAHF, 1);
894 } else {
895 BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(LHS).addReg(RHS);
896 }
897}
898
Chris Lattnerb2acc512003-10-19 21:09:10 +0000899// EmitComparison - This function emits a comparison of the two operands,
900// returning the extended setcc code to use.
901unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
902 MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +0000903 MachineBasicBlock::iterator IP) {
Brian Gaeke1749d632002-11-07 17:59:21 +0000904 // The arguments are already supposed to be of the same type.
Chris Lattner6d40c192003-01-16 16:43:00 +0000905 const Type *CompTy = Op0->getType();
Chris Lattner3e130a22003-01-13 00:32:26 +0000906 unsigned Class = getClassB(CompTy);
Chris Lattner58c41fe2003-08-24 19:19:47 +0000907 unsigned Op0r = getReg(Op0, MBB, IP);
Chris Lattner333864d2003-06-05 19:30:30 +0000908
909 // Special case handling of: cmp R, i
Chris Lattner260195d2004-05-07 19:55:55 +0000910 if (isa<ConstantPointerNull>(Op1)) {
911 if (OpNum < 2) // seteq/setne -> test
912 BuildMI(*MBB, IP, X86::TEST32rr, 2).addReg(Op0r).addReg(Op0r);
913 else
914 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(0);
915 return OpNum;
916
917 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
Chris Lattnere80e6372004-04-06 16:02:27 +0000918 if (Class == cByte || Class == cShort || Class == cInt) {
919 unsigned Op1v = CI->getRawValue();
Chris Lattnerc07736a2003-07-23 15:22:26 +0000920
Chris Lattner333864d2003-06-05 19:30:30 +0000921 // Mask off any upper bits of the constant, if there are any...
922 Op1v &= (1ULL << (8 << Class)) - 1;
923
Chris Lattnerb2acc512003-10-19 21:09:10 +0000924 // If this is a comparison against zero, emit more efficient code. We
925 // can't handle unsigned comparisons against zero unless they are == or
926 // !=. These should have been strength reduced already anyway.
927 if (Op1v == 0 && (CompTy->isSigned() || OpNum < 2)) {
928 static const unsigned TESTTab[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000929 X86::TEST8rr, X86::TEST16rr, X86::TEST32rr
Chris Lattnerb2acc512003-10-19 21:09:10 +0000930 };
Chris Lattneree352852004-02-29 07:22:16 +0000931 BuildMI(*MBB, IP, TESTTab[Class], 2).addReg(Op0r).addReg(Op0r);
Chris Lattnerb2acc512003-10-19 21:09:10 +0000932
933 if (OpNum == 2) return 6; // Map jl -> js
934 if (OpNum == 3) return 7; // Map jg -> jns
935 return OpNum;
Chris Lattner333864d2003-06-05 19:30:30 +0000936 }
Chris Lattnerb2acc512003-10-19 21:09:10 +0000937
938 static const unsigned CMPTab[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000939 X86::CMP8ri, X86::CMP16ri, X86::CMP32ri
Chris Lattnerb2acc512003-10-19 21:09:10 +0000940 };
941
Chris Lattneree352852004-02-29 07:22:16 +0000942 BuildMI(*MBB, IP, CMPTab[Class], 2).addReg(Op0r).addImm(Op1v);
Chris Lattnerb2acc512003-10-19 21:09:10 +0000943 return OpNum;
Chris Lattnere80e6372004-04-06 16:02:27 +0000944 } else {
945 assert(Class == cLong && "Unknown integer class!");
946 unsigned LowCst = CI->getRawValue();
947 unsigned HiCst = CI->getRawValue() >> 32;
948 if (OpNum < 2) { // seteq, setne
949 unsigned LoTmp = Op0r;
950 if (LowCst != 0) {
951 LoTmp = makeAnotherReg(Type::IntTy);
952 BuildMI(*MBB, IP, X86::XOR32ri, 2, LoTmp).addReg(Op0r).addImm(LowCst);
953 }
954 unsigned HiTmp = Op0r+1;
955 if (HiCst != 0) {
956 HiTmp = makeAnotherReg(Type::IntTy);
Chris Lattner48c937e2004-04-06 17:34:50 +0000957 BuildMI(*MBB, IP, X86::XOR32ri, 2,HiTmp).addReg(Op0r+1).addImm(HiCst);
Chris Lattnere80e6372004-04-06 16:02:27 +0000958 }
959 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
960 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
961 return OpNum;
Chris Lattner48c937e2004-04-06 17:34:50 +0000962 } else {
963 // Emit a sequence of code which compares the high and low parts once
964 // each, then uses a conditional move to handle the overflow case. For
965 // example, a setlt for long would generate code like this:
966 //
Chris Lattner9984fd02004-05-09 23:16:33 +0000967 // AL = lo(op1) < lo(op2) // Always unsigned comparison
968 // BL = hi(op1) < hi(op2) // Signedness depends on operands
969 // dest = hi(op1) == hi(op2) ? BL : AL;
Chris Lattner48c937e2004-04-06 17:34:50 +0000970 //
971
972 // FIXME: This would be much better if we had hierarchical register
973 // classes! Until then, hardcode registers so that we can deal with
974 // their aliases (because we don't have conditional byte moves).
975 //
976 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r).addImm(LowCst);
977 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
978 BuildMI(*MBB, IP, X86::CMP32ri, 2).addReg(Op0r+1).addImm(HiCst);
979 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0,X86::BL);
980 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
981 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
982 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
983 .addReg(X86::AX);
984 // NOTE: visitSetCondInst knows that the value is dumped into the BL
985 // register at this point for long values...
986 return OpNum;
Chris Lattnere80e6372004-04-06 16:02:27 +0000987 }
Chris Lattner333864d2003-06-05 19:30:30 +0000988 }
Chris Lattnere80e6372004-04-06 16:02:27 +0000989 }
Chris Lattner333864d2003-06-05 19:30:30 +0000990
Chris Lattner9f08a922004-02-03 18:54:04 +0000991 // Special case handling of comparison against +/- 0.0
992 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op1))
993 if (CFP->isExactlyValue(+0.0) || CFP->isExactlyValue(-0.0)) {
Chris Lattneree352852004-02-29 07:22:16 +0000994 BuildMI(*MBB, IP, X86::FTST, 1).addReg(Op0r);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +0000995 BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
Chris Lattneree352852004-02-29 07:22:16 +0000996 BuildMI(*MBB, IP, X86::SAHF, 1);
Chris Lattner9f08a922004-02-03 18:54:04 +0000997 return OpNum;
998 }
999
Chris Lattner58c41fe2003-08-24 19:19:47 +00001000 unsigned Op1r = getReg(Op1, MBB, IP);
Chris Lattner3e130a22003-01-13 00:32:26 +00001001 switch (Class) {
1002 default: assert(0 && "Unknown type class!");
1003 // Emit: cmp <var1>, <var2> (do the comparison). We can
1004 // compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
1005 // 32-bit.
1006 case cByte:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001007 BuildMI(*MBB, IP, X86::CMP8rr, 2).addReg(Op0r).addReg(Op1r);
Chris Lattner3e130a22003-01-13 00:32:26 +00001008 break;
1009 case cShort:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001010 BuildMI(*MBB, IP, X86::CMP16rr, 2).addReg(Op0r).addReg(Op1r);
Chris Lattner3e130a22003-01-13 00:32:26 +00001011 break;
1012 case cInt:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001013 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
Chris Lattner3e130a22003-01-13 00:32:26 +00001014 break;
1015 case cFP:
Chris Lattner01cdb1b2004-06-11 05:33:49 +00001016 emitUCOMr(MBB, IP, Op0r, Op1r);
Chris Lattner3e130a22003-01-13 00:32:26 +00001017 break;
1018
1019 case cLong:
1020 if (OpNum < 2) { // seteq, setne
1021 unsigned LoTmp = makeAnotherReg(Type::IntTy);
1022 unsigned HiTmp = makeAnotherReg(Type::IntTy);
1023 unsigned FinalTmp = makeAnotherReg(Type::IntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001024 BuildMI(*MBB, IP, X86::XOR32rr, 2, LoTmp).addReg(Op0r).addReg(Op1r);
1025 BuildMI(*MBB, IP, X86::XOR32rr, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
1026 BuildMI(*MBB, IP, X86::OR32rr, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
Chris Lattner3e130a22003-01-13 00:32:26 +00001027 break; // Allow the sete or setne to be generated from flags set by OR
1028 } else {
1029 // Emit a sequence of code which compares the high and low parts once
1030 // each, then uses a conditional move to handle the overflow case. For
1031 // example, a setlt for long would generate code like this:
1032 //
1033 // AL = lo(op1) < lo(op2) // Signedness depends on operands
1034 // BL = hi(op1) < hi(op2) // Always unsigned comparison
Chris Lattner9984fd02004-05-09 23:16:33 +00001035 // dest = hi(op1) == hi(op2) ? BL : AL;
Chris Lattner3e130a22003-01-13 00:32:26 +00001036 //
1037
Chris Lattner6d40c192003-01-16 16:43:00 +00001038 // FIXME: This would be much better if we had hierarchical register
Chris Lattner3e130a22003-01-13 00:32:26 +00001039 // classes! Until then, hardcode registers so that we can deal with their
1040 // aliases (because we don't have conditional byte moves).
1041 //
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001042 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
Chris Lattneree352852004-02-29 07:22:16 +00001043 BuildMI(*MBB, IP, SetCCOpcodeTab[0][OpNum], 0, X86::AL);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001044 BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r+1).addReg(Op1r+1);
Chris Lattneree352852004-02-29 07:22:16 +00001045 BuildMI(*MBB, IP, SetCCOpcodeTab[CompTy->isSigned()][OpNum], 0, X86::BL);
1046 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::BH);
1047 BuildMI(*MBB, IP, X86::IMPLICIT_DEF, 0, X86::AH);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001048 BuildMI(*MBB, IP, X86::CMOVE16rr, 2, X86::BX).addReg(X86::BX)
Chris Lattneree352852004-02-29 07:22:16 +00001049 .addReg(X86::AX);
Chris Lattner6d40c192003-01-16 16:43:00 +00001050 // NOTE: visitSetCondInst knows that the value is dumped into the BL
1051 // register at this point for long values...
Chris Lattnerb2acc512003-10-19 21:09:10 +00001052 return OpNum;
Chris Lattner3e130a22003-01-13 00:32:26 +00001053 }
1054 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00001055 return OpNum;
Chris Lattner6d40c192003-01-16 16:43:00 +00001056}
Chris Lattner3e130a22003-01-13 00:32:26 +00001057
Chris Lattner6d40c192003-01-16 16:43:00 +00001058/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
1059/// register, then move it to wherever the result should be.
1060///
1061void ISel::visitSetCondInst(SetCondInst &I) {
Chris Lattner307ecba2004-03-30 22:39:09 +00001062 if (canFoldSetCCIntoBranchOrSelect(&I))
1063 return; // Fold this into a branch or select.
Chris Lattner6d40c192003-01-16 16:43:00 +00001064
Chris Lattner6d40c192003-01-16 16:43:00 +00001065 unsigned DestReg = getReg(I);
Chris Lattner58c41fe2003-08-24 19:19:47 +00001066 MachineBasicBlock::iterator MII = BB->end();
1067 emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),
1068 DestReg);
1069}
Chris Lattner6d40c192003-01-16 16:43:00 +00001070
Chris Lattner58c41fe2003-08-24 19:19:47 +00001071/// emitSetCCOperation - Common code shared between visitSetCondInst and
1072/// constant expression support.
Misha Brukman538607f2004-03-01 23:53:11 +00001073///
Chris Lattner58c41fe2003-08-24 19:19:47 +00001074void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00001075 MachineBasicBlock::iterator IP,
Chris Lattner58c41fe2003-08-24 19:19:47 +00001076 Value *Op0, Value *Op1, unsigned Opcode,
1077 unsigned TargetReg) {
1078 unsigned OpNum = getSetCCNumber(Opcode);
Chris Lattnerb2acc512003-10-19 21:09:10 +00001079 OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
Chris Lattner58c41fe2003-08-24 19:19:47 +00001080
Chris Lattnerb2acc512003-10-19 21:09:10 +00001081 const Type *CompTy = Op0->getType();
1082 unsigned CompClass = getClassB(CompTy);
1083 bool isSigned = CompTy->isSigned() && CompClass != cFP;
1084
1085 if (CompClass != cLong || OpNum < 2) {
Chris Lattner6d40c192003-01-16 16:43:00 +00001086 // Handle normal comparisons with a setcc instruction...
Chris Lattneree352852004-02-29 07:22:16 +00001087 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, TargetReg);
Chris Lattner6d40c192003-01-16 16:43:00 +00001088 } else {
1089 // Handle long comparisons by copying the value which is already in BL into
1090 // the register we want...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001091 BuildMI(*MBB, IP, X86::MOV8rr, 1, TargetReg).addReg(X86::BL);
Chris Lattner6d40c192003-01-16 16:43:00 +00001092 }
Brian Gaeke1749d632002-11-07 17:59:21 +00001093}
Chris Lattner51b49a92002-11-02 19:45:49 +00001094
Chris Lattner12d96a02004-03-30 21:22:00 +00001095void ISel::visitSelectInst(SelectInst &SI) {
1096 unsigned DestReg = getReg(SI);
1097 MachineBasicBlock::iterator MII = BB->end();
1098 emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
1099 SI.getFalseValue(), DestReg);
1100}
1101
1102/// emitSelect - Common code shared between visitSelectInst and the constant
1103/// expression support.
1104void ISel::emitSelectOperation(MachineBasicBlock *MBB,
1105 MachineBasicBlock::iterator IP,
1106 Value *Cond, Value *TrueVal, Value *FalseVal,
1107 unsigned DestReg) {
1108 unsigned SelectClass = getClassB(TrueVal->getType());
1109
1110 // We don't support 8-bit conditional moves. If we have incoming constants,
1111 // transform them into 16-bit constants to avoid having a run-time conversion.
1112 if (SelectClass == cByte) {
1113 if (Constant *T = dyn_cast<Constant>(TrueVal))
1114 TrueVal = ConstantExpr::getCast(T, Type::ShortTy);
1115 if (Constant *F = dyn_cast<Constant>(FalseVal))
1116 FalseVal = ConstantExpr::getCast(F, Type::ShortTy);
1117 }
1118
Chris Lattner82c5a992004-04-13 21:56:09 +00001119 unsigned TrueReg = getReg(TrueVal, MBB, IP);
1120 unsigned FalseReg = getReg(FalseVal, MBB, IP);
1121 if (TrueReg == FalseReg) {
1122 static const unsigned Opcode[] = {
1123 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
1124 };
1125 BuildMI(*MBB, IP, Opcode[SelectClass], 1, DestReg).addReg(TrueReg);
1126 if (SelectClass == cLong)
1127 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(TrueReg+1);
1128 return;
1129 }
1130
Chris Lattner307ecba2004-03-30 22:39:09 +00001131 unsigned Opcode;
1132 if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
1133 // We successfully folded the setcc into the select instruction.
1134
1135 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
1136 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
1137 IP);
1138
1139 const Type *CompTy = SCI->getOperand(0)->getType();
1140 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
1141
1142 // LLVM -> X86 signed X86 unsigned
1143 // ----- ---------- ------------
1144 // seteq -> cmovNE cmovNE
1145 // setne -> cmovE cmovE
1146 // setlt -> cmovGE cmovAE
1147 // setge -> cmovL cmovB
1148 // setgt -> cmovLE cmovBE
1149 // setle -> cmovG cmovA
1150 // ----
1151 // cmovNS // Used by comparison with 0 optimization
1152 // cmovS
1153
1154 switch (SelectClass) {
Chris Lattner352eb482004-03-31 22:03:35 +00001155 default: assert(0 && "Unknown value class!");
1156 case cFP: {
1157 // Annoyingly, we don't have a full set of floating point conditional
1158 // moves. :(
1159 static const unsigned OpcodeTab[2][8] = {
1160 { X86::FCMOVNE, X86::FCMOVE, X86::FCMOVAE, X86::FCMOVB,
1161 X86::FCMOVBE, X86::FCMOVA, 0, 0 },
1162 { X86::FCMOVNE, X86::FCMOVE, 0, 0, 0, 0, 0, 0 },
1163 };
1164 Opcode = OpcodeTab[isSigned][OpNum];
1165
1166 // If opcode == 0, we hit a case that we don't support. Output a setcc
1167 // and compare the result against zero.
1168 if (Opcode == 0) {
1169 unsigned CompClass = getClassB(CompTy);
1170 unsigned CondReg;
1171 if (CompClass != cLong || OpNum < 2) {
1172 CondReg = makeAnotherReg(Type::BoolTy);
1173 // Handle normal comparisons with a setcc instruction...
1174 BuildMI(*MBB, IP, SetCCOpcodeTab[isSigned][OpNum], 0, CondReg);
1175 } else {
1176 // Long comparisons end up in the BL register.
1177 CondReg = X86::BL;
1178 }
1179
Chris Lattner68626c22004-03-31 22:22:36 +00001180 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
Chris Lattner352eb482004-03-31 22:03:35 +00001181 Opcode = X86::FCMOVE;
1182 }
1183 break;
1184 }
Chris Lattner307ecba2004-03-30 22:39:09 +00001185 case cByte:
1186 case cShort: {
1187 static const unsigned OpcodeTab[2][8] = {
1188 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVAE16rr, X86::CMOVB16rr,
1189 X86::CMOVBE16rr, X86::CMOVA16rr, 0, 0 },
1190 { X86::CMOVNE16rr, X86::CMOVE16rr, X86::CMOVGE16rr, X86::CMOVL16rr,
1191 X86::CMOVLE16rr, X86::CMOVG16rr, X86::CMOVNS16rr, X86::CMOVS16rr },
1192 };
1193 Opcode = OpcodeTab[isSigned][OpNum];
1194 break;
1195 }
1196 case cInt:
1197 case cLong: {
1198 static const unsigned OpcodeTab[2][8] = {
1199 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVAE32rr, X86::CMOVB32rr,
1200 X86::CMOVBE32rr, X86::CMOVA32rr, 0, 0 },
1201 { X86::CMOVNE32rr, X86::CMOVE32rr, X86::CMOVGE32rr, X86::CMOVL32rr,
1202 X86::CMOVLE32rr, X86::CMOVG32rr, X86::CMOVNS32rr, X86::CMOVS32rr },
1203 };
1204 Opcode = OpcodeTab[isSigned][OpNum];
1205 break;
1206 }
1207 }
1208 } else {
1209 // Get the value being branched on, and use it to set the condition codes.
1210 unsigned CondReg = getReg(Cond, MBB, IP);
Chris Lattner68626c22004-03-31 22:22:36 +00001211 BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
Chris Lattner307ecba2004-03-30 22:39:09 +00001212 switch (SelectClass) {
Chris Lattner352eb482004-03-31 22:03:35 +00001213 default: assert(0 && "Unknown value class!");
1214 case cFP: Opcode = X86::FCMOVE; break;
Chris Lattner307ecba2004-03-30 22:39:09 +00001215 case cByte:
Chris Lattner352eb482004-03-31 22:03:35 +00001216 case cShort: Opcode = X86::CMOVE16rr; break;
Chris Lattner307ecba2004-03-30 22:39:09 +00001217 case cInt:
Chris Lattner352eb482004-03-31 22:03:35 +00001218 case cLong: Opcode = X86::CMOVE32rr; break;
Chris Lattner307ecba2004-03-30 22:39:09 +00001219 }
1220 }
Chris Lattner12d96a02004-03-30 21:22:00 +00001221
Chris Lattner12d96a02004-03-30 21:22:00 +00001222 unsigned RealDestReg = DestReg;
Chris Lattner12d96a02004-03-30 21:22:00 +00001223
Chris Lattner12d96a02004-03-30 21:22:00 +00001224
1225 // Annoyingly enough, X86 doesn't HAVE 8-bit conditional moves. Because of
1226 // this, we have to promote the incoming values to 16 bits, perform a 16-bit
1227 // cmove, then truncate the result.
1228 if (SelectClass == cByte) {
1229 DestReg = makeAnotherReg(Type::ShortTy);
1230 if (getClassB(TrueVal->getType()) == cByte) {
1231 // Promote the true value, by storing it into AL, and reading from AX.
1232 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::AL).addReg(TrueReg);
1233 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::AH).addImm(0);
1234 TrueReg = makeAnotherReg(Type::ShortTy);
1235 BuildMI(*MBB, IP, X86::MOV16rr, 1, TrueReg).addReg(X86::AX);
1236 }
1237 if (getClassB(FalseVal->getType()) == cByte) {
1238 // Promote the true value, by storing it into CL, and reading from CX.
1239 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(FalseReg);
1240 BuildMI(*MBB, IP, X86::MOV8ri, 1, X86::CH).addImm(0);
1241 FalseReg = makeAnotherReg(Type::ShortTy);
1242 BuildMI(*MBB, IP, X86::MOV16rr, 1, FalseReg).addReg(X86::CX);
1243 }
1244 }
1245
1246 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(TrueReg).addReg(FalseReg);
1247
1248 switch (SelectClass) {
1249 case cByte:
1250 // We did the computation with 16-bit registers. Truncate back to our
1251 // result by copying into AX then copying out AL.
1252 BuildMI(*MBB, IP, X86::MOV16rr, 1, X86::AX).addReg(DestReg);
1253 BuildMI(*MBB, IP, X86::MOV8rr, 1, RealDestReg).addReg(X86::AL);
1254 break;
1255 case cLong:
1256 // Move the upper half of the value as well.
1257 BuildMI(*MBB, IP, Opcode, 2,DestReg+1).addReg(TrueReg+1).addReg(FalseReg+1);
1258 break;
1259 }
1260}
Chris Lattner58c41fe2003-08-24 19:19:47 +00001261
1262
1263
Brian Gaekec2505982002-11-30 11:57:28 +00001264/// promote32 - Emit instructions to turn a narrow operand into a 32-bit-wide
1265/// operand, in the specified target register.
Misha Brukman538607f2004-03-01 23:53:11 +00001266///
Chris Lattner3e130a22003-01-13 00:32:26 +00001267void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
Chris Lattner9984fd02004-05-09 23:16:33 +00001268 bool isUnsigned = VR.Ty->isUnsigned() || VR.Ty == Type::BoolTy;
Chris Lattner5e2cb8b2003-08-04 02:12:48 +00001269
Chris Lattner29bf0622004-04-06 01:21:00 +00001270 Value *Val = VR.Val;
1271 const Type *Ty = VR.Ty;
Chris Lattner502e36c2004-04-06 01:25:33 +00001272 if (Val) {
Chris Lattner29bf0622004-04-06 01:21:00 +00001273 if (Constant *C = dyn_cast<Constant>(Val)) {
1274 Val = ConstantExpr::getCast(C, Type::IntTy);
1275 Ty = Type::IntTy;
1276 }
Chris Lattner5e2cb8b2003-08-04 02:12:48 +00001277
Chris Lattner502e36c2004-04-06 01:25:33 +00001278 // If this is a simple constant, just emit a MOVri directly to avoid the
1279 // copy.
1280 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
1281 int TheVal = CI->getRawValue() & 0xFFFFFFFF;
Chris Lattner2b10b082004-05-12 16:35:04 +00001282 BuildMI(BB, X86::MOV32ri, 1, targetReg).addImm(TheVal);
Chris Lattner502e36c2004-04-06 01:25:33 +00001283 return;
1284 }
1285 }
1286
Chris Lattner29bf0622004-04-06 01:21:00 +00001287 // Make sure we have the register number for this value...
1288 unsigned Reg = Val ? getReg(Val) : VR.Reg;
1289
1290 switch (getClassB(Ty)) {
Chris Lattner94af4142002-12-25 05:13:53 +00001291 case cByte:
1292 // Extend value into target register (8->32)
1293 if (isUnsigned)
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001294 BuildMI(BB, X86::MOVZX32rr8, 1, targetReg).addReg(Reg);
Chris Lattner94af4142002-12-25 05:13:53 +00001295 else
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001296 BuildMI(BB, X86::MOVSX32rr8, 1, targetReg).addReg(Reg);
Chris Lattner94af4142002-12-25 05:13:53 +00001297 break;
1298 case cShort:
1299 // Extend value into target register (16->32)
1300 if (isUnsigned)
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001301 BuildMI(BB, X86::MOVZX32rr16, 1, targetReg).addReg(Reg);
Chris Lattner94af4142002-12-25 05:13:53 +00001302 else
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001303 BuildMI(BB, X86::MOVSX32rr16, 1, targetReg).addReg(Reg);
Chris Lattner94af4142002-12-25 05:13:53 +00001304 break;
1305 case cInt:
1306 // Move value into target register (32->32)
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001307 BuildMI(BB, X86::MOV32rr, 1, targetReg).addReg(Reg);
Chris Lattner94af4142002-12-25 05:13:53 +00001308 break;
1309 default:
1310 assert(0 && "Unpromotable operand class in promote32");
1311 }
Brian Gaekec2505982002-11-30 11:57:28 +00001312}
Chris Lattnerc5291f52002-10-27 21:16:59 +00001313
Chris Lattner72614082002-10-25 22:55:53 +00001314/// 'ret' instruction - Here we are interested in meeting the x86 ABI. As such,
1315/// we have the following possibilities:
1316///
1317/// ret void: No return value, simply emit a 'ret' instruction
1318/// ret sbyte, ubyte : Extend value into EAX and return
1319/// ret short, ushort: Extend value into EAX and return
1320/// ret int, uint : Move value into EAX and return
1321/// ret pointer : Move value into EAX and return
Chris Lattner06925362002-11-17 21:56:38 +00001322/// ret long, ulong : Move value into EAX/EDX and return
1323/// ret float/double : Top of FP stack
Chris Lattner72614082002-10-25 22:55:53 +00001324///
Chris Lattner3e130a22003-01-13 00:32:26 +00001325void ISel::visitReturnInst(ReturnInst &I) {
Chris Lattner94af4142002-12-25 05:13:53 +00001326 if (I.getNumOperands() == 0) {
1327 BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
1328 return;
1329 }
1330
1331 Value *RetVal = I.getOperand(0);
Chris Lattner3e130a22003-01-13 00:32:26 +00001332 switch (getClassB(RetVal->getType())) {
Chris Lattner94af4142002-12-25 05:13:53 +00001333 case cByte: // integral return values: extend or move into EAX and return
1334 case cShort:
1335 case cInt:
Chris Lattner29bf0622004-04-06 01:21:00 +00001336 promote32(X86::EAX, ValueRecord(RetVal));
Chris Lattnerdbd73722003-05-06 21:32:22 +00001337 // Declare that EAX is live on exit
Chris Lattnerc2489032003-05-07 19:21:28 +00001338 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::EAX).addReg(X86::ESP);
Chris Lattner94af4142002-12-25 05:13:53 +00001339 break;
Chris Lattner29bf0622004-04-06 01:21:00 +00001340 case cFP: { // Floats & Doubles: Return in ST(0)
1341 unsigned RetReg = getReg(RetVal);
Chris Lattner3e130a22003-01-13 00:32:26 +00001342 BuildMI(BB, X86::FpSETRESULT, 1).addReg(RetReg);
Chris Lattnerdbd73722003-05-06 21:32:22 +00001343 // Declare that top-of-stack is live on exit
Chris Lattnerc2489032003-05-07 19:21:28 +00001344 BuildMI(BB, X86::IMPLICIT_USE, 2).addReg(X86::ST0).addReg(X86::ESP);
Chris Lattner94af4142002-12-25 05:13:53 +00001345 break;
Chris Lattner29bf0622004-04-06 01:21:00 +00001346 }
1347 case cLong: {
1348 unsigned RetReg = getReg(RetVal);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001349 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(RetReg);
1350 BuildMI(BB, X86::MOV32rr, 1, X86::EDX).addReg(RetReg+1);
Chris Lattnerdbd73722003-05-06 21:32:22 +00001351 // Declare that EAX & EDX are live on exit
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001352 BuildMI(BB, X86::IMPLICIT_USE, 3).addReg(X86::EAX).addReg(X86::EDX)
1353 .addReg(X86::ESP);
Chris Lattner3e130a22003-01-13 00:32:26 +00001354 break;
Chris Lattner29bf0622004-04-06 01:21:00 +00001355 }
Chris Lattner94af4142002-12-25 05:13:53 +00001356 default:
Chris Lattner3e130a22003-01-13 00:32:26 +00001357 visitInstruction(I);
Chris Lattner94af4142002-12-25 05:13:53 +00001358 }
Chris Lattner43189d12002-11-17 20:07:45 +00001359 // Emit a 'ret' instruction
Chris Lattner94af4142002-12-25 05:13:53 +00001360 BuildMI(BB, X86::RET, 0);
Chris Lattner72614082002-10-25 22:55:53 +00001361}
1362
Chris Lattner55f6fab2003-01-16 18:07:23 +00001363// getBlockAfter - Return the basic block which occurs lexically after the
1364// specified one.
1365static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
1366 Function::iterator I = BB; ++I; // Get iterator to next block
1367 return I != BB->getParent()->end() ? &*I : 0;
1368}
1369
Chris Lattner51b49a92002-11-02 19:45:49 +00001370/// visitBranchInst - Handle conditional and unconditional branches here. Note
1371/// that since code layout is frozen at this point, that if we are trying to
1372/// jump to a block that is the immediate successor of the current block, we can
Chris Lattner6d40c192003-01-16 16:43:00 +00001373/// just make a fall-through (but we don't currently).
Chris Lattner51b49a92002-11-02 19:45:49 +00001374///
Chris Lattner94af4142002-12-25 05:13:53 +00001375void ISel::visitBranchInst(BranchInst &BI) {
Brian Gaekeea9ca672004-04-28 04:19:37 +00001376 // Update machine-CFG edges
1377 BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
1378 if (BI.isConditional())
1379 BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
1380
Chris Lattner55f6fab2003-01-16 18:07:23 +00001381 BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
1382
1383 if (!BI.isConditional()) { // Unconditional branch?
Chris Lattnercf93cdd2004-01-30 22:13:44 +00001384 if (BI.getSuccessor(0) != NextBB)
Brian Gaeke9f088e42004-05-14 06:54:56 +00001385 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
Chris Lattner6d40c192003-01-16 16:43:00 +00001386 return;
1387 }
1388
1389 // See if we can fold the setcc into the branch itself...
Chris Lattner307ecba2004-03-30 22:39:09 +00001390 SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
Chris Lattner6d40c192003-01-16 16:43:00 +00001391 if (SCI == 0) {
1392 // Nope, cannot fold setcc into this branch. Emit a branch on a condition
1393 // computed some other way...
Chris Lattner065faeb2002-12-28 20:24:02 +00001394 unsigned condReg = getReg(BI.getCondition());
Chris Lattner68626c22004-03-31 22:22:36 +00001395 BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001396 if (BI.getSuccessor(1) == NextBB) {
1397 if (BI.getSuccessor(0) != NextBB)
Brian Gaeke9f088e42004-05-14 06:54:56 +00001398 BuildMI(BB, X86::JNE, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001399 } else {
Brian Gaeke9f088e42004-05-14 06:54:56 +00001400 BuildMI(BB, X86::JE, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001401
1402 if (BI.getSuccessor(0) != NextBB)
Brian Gaeke9f088e42004-05-14 06:54:56 +00001403 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001404 }
Chris Lattner6d40c192003-01-16 16:43:00 +00001405 return;
Chris Lattner94af4142002-12-25 05:13:53 +00001406 }
Chris Lattner6d40c192003-01-16 16:43:00 +00001407
1408 unsigned OpNum = getSetCCNumber(SCI->getOpcode());
Chris Lattner58c41fe2003-08-24 19:19:47 +00001409 MachineBasicBlock::iterator MII = BB->end();
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001410 OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
Chris Lattnerb2acc512003-10-19 21:09:10 +00001411
1412 const Type *CompTy = SCI->getOperand(0)->getType();
1413 bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
Chris Lattner6d40c192003-01-16 16:43:00 +00001414
Chris Lattnerb2acc512003-10-19 21:09:10 +00001415
Chris Lattner6d40c192003-01-16 16:43:00 +00001416 // LLVM -> X86 signed X86 unsigned
1417 // ----- ---------- ------------
1418 // seteq -> je je
1419 // setne -> jne jne
1420 // setlt -> jl jb
Chris Lattner55f6fab2003-01-16 18:07:23 +00001421 // setge -> jge jae
Chris Lattner6d40c192003-01-16 16:43:00 +00001422 // setgt -> jg ja
1423 // setle -> jle jbe
Chris Lattnerb2acc512003-10-19 21:09:10 +00001424 // ----
1425 // js // Used by comparison with 0 optimization
1426 // jns
1427
1428 static const unsigned OpcodeTab[2][8] = {
1429 { X86::JE, X86::JNE, X86::JB, X86::JAE, X86::JA, X86::JBE, 0, 0 },
1430 { X86::JE, X86::JNE, X86::JL, X86::JGE, X86::JG, X86::JLE,
1431 X86::JS, X86::JNS },
Chris Lattner6d40c192003-01-16 16:43:00 +00001432 };
1433
Chris Lattner55f6fab2003-01-16 18:07:23 +00001434 if (BI.getSuccessor(0) != NextBB) {
Brian Gaeke9f088e42004-05-14 06:54:56 +00001435 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1436 .addMBB(MBBMap[BI.getSuccessor(0)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001437 if (BI.getSuccessor(1) != NextBB)
Brian Gaeke9f088e42004-05-14 06:54:56 +00001438 BuildMI(BB, X86::JMP, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001439 } else {
1440 // Change to the inverse condition...
1441 if (BI.getSuccessor(1) != NextBB) {
1442 OpNum ^= 1;
Brian Gaeke9f088e42004-05-14 06:54:56 +00001443 BuildMI(BB, OpcodeTab[isSigned][OpNum], 1)
1444 .addMBB(MBBMap[BI.getSuccessor(1)]);
Chris Lattner55f6fab2003-01-16 18:07:23 +00001445 }
1446 }
Chris Lattner2df035b2002-11-02 19:27:56 +00001447}
1448
Chris Lattner3e130a22003-01-13 00:32:26 +00001449
1450/// doCall - This emits an abstract call instruction, setting up the arguments
1451/// and the return value as appropriate. For the actual function call itself,
1452/// it inserts the specified CallMI instruction into the stream.
1453///
1454void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001455 const std::vector<ValueRecord> &Args) {
Chris Lattner3e130a22003-01-13 00:32:26 +00001456
Chris Lattner065faeb2002-12-28 20:24:02 +00001457 // Count how many bytes are to be pushed on the stack...
1458 unsigned NumBytes = 0;
Misha Brukman0d2cf3a2002-12-04 19:22:53 +00001459
Chris Lattner3e130a22003-01-13 00:32:26 +00001460 if (!Args.empty()) {
1461 for (unsigned i = 0, e = Args.size(); i != e; ++i)
1462 switch (getClassB(Args[i].Ty)) {
Chris Lattner065faeb2002-12-28 20:24:02 +00001463 case cByte: case cShort: case cInt:
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001464 NumBytes += 4; break;
Chris Lattner065faeb2002-12-28 20:24:02 +00001465 case cLong:
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001466 NumBytes += 8; break;
Chris Lattner065faeb2002-12-28 20:24:02 +00001467 case cFP:
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001468 NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
1469 break;
Chris Lattner065faeb2002-12-28 20:24:02 +00001470 default: assert(0 && "Unknown class!");
1471 }
1472
1473 // Adjust the stack pointer for the new arguments...
Chris Lattneree352852004-02-29 07:22:16 +00001474 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
Chris Lattner065faeb2002-12-28 20:24:02 +00001475
1476 // Arguments go on the stack in reverse order, as specified by the ABI.
1477 unsigned ArgOffset = 0;
Chris Lattner3e130a22003-01-13 00:32:26 +00001478 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
Chris Lattnerce6096f2004-03-01 02:34:08 +00001479 unsigned ArgReg;
Chris Lattner3e130a22003-01-13 00:32:26 +00001480 switch (getClassB(Args[i].Ty)) {
Chris Lattner065faeb2002-12-28 20:24:02 +00001481 case cByte:
Chris Lattner2b10b082004-05-12 16:35:04 +00001482 if (Args[i].Val && isa<ConstantBool>(Args[i].Val)) {
1483 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1484 .addImm(Args[i].Val == ConstantBool::True);
1485 break;
1486 }
1487 // FALL THROUGH
Chris Lattner21585222004-03-01 02:42:43 +00001488 case cShort:
1489 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1490 // Zero/Sign extend constant, then stuff into memory.
1491 ConstantInt *Val = cast<ConstantInt>(Args[i].Val);
1492 Val = cast<ConstantInt>(ConstantExpr::getCast(Val, Type::IntTy));
1493 addRegOffset(BuildMI(BB, X86::MOV32mi, 5), X86::ESP, ArgOffset)
1494 .addImm(Val->getRawValue() & 0xFFFFFFFF);
1495 } else {
1496 // Promote arg to 32 bits wide into a temporary register...
1497 ArgReg = makeAnotherReg(Type::UIntTy);
1498 promote32(ArgReg, Args[i]);
1499 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1500 X86::ESP, ArgOffset).addReg(ArgReg);
1501 }
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001502 break;
Chris Lattner065faeb2002-12-28 20:24:02 +00001503 case cInt:
Chris Lattner21585222004-03-01 02:42:43 +00001504 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1505 unsigned Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1506 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1507 X86::ESP, ArgOffset).addImm(Val);
Chris Lattnerb7cb9ff2004-05-13 15:26:48 +00001508 } else if (Args[i].Val && isa<ConstantPointerNull>(Args[i].Val)) {
1509 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1510 X86::ESP, ArgOffset).addImm(0);
Chris Lattner21585222004-03-01 02:42:43 +00001511 } else {
1512 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1513 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1514 X86::ESP, ArgOffset).addReg(ArgReg);
1515 }
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001516 break;
Chris Lattner3e130a22003-01-13 00:32:26 +00001517 case cLong:
Chris Lattner92900a62004-04-06 03:23:00 +00001518 if (Args[i].Val && isa<ConstantInt>(Args[i].Val)) {
1519 uint64_t Val = cast<ConstantInt>(Args[i].Val)->getRawValue();
1520 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1521 X86::ESP, ArgOffset).addImm(Val & ~0U);
1522 addRegOffset(BuildMI(BB, X86::MOV32mi, 5),
1523 X86::ESP, ArgOffset+4).addImm(Val >> 32ULL);
1524 } else {
1525 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
1526 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1527 X86::ESP, ArgOffset).addReg(ArgReg);
1528 addRegOffset(BuildMI(BB, X86::MOV32mr, 5),
1529 X86::ESP, ArgOffset+4).addReg(ArgReg+1);
1530 }
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001531 ArgOffset += 4; // 8 byte entry, not 4.
1532 break;
1533
Chris Lattner065faeb2002-12-28 20:24:02 +00001534 case cFP:
Chris Lattnerce6096f2004-03-01 02:34:08 +00001535 ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001536 if (Args[i].Ty == Type::FloatTy) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001537 addRegOffset(BuildMI(BB, X86::FST32m, 5),
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001538 X86::ESP, ArgOffset).addReg(ArgReg);
1539 } else {
1540 assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001541 addRegOffset(BuildMI(BB, X86::FST64m, 5),
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001542 X86::ESP, ArgOffset).addReg(ArgReg);
1543 ArgOffset += 4; // 8 byte entry, not 4.
1544 }
1545 break;
Chris Lattner065faeb2002-12-28 20:24:02 +00001546
Chris Lattner3e130a22003-01-13 00:32:26 +00001547 default: assert(0 && "Unknown class!");
Chris Lattner065faeb2002-12-28 20:24:02 +00001548 }
1549 ArgOffset += 4;
Chris Lattner94af4142002-12-25 05:13:53 +00001550 }
Chris Lattner3e130a22003-01-13 00:32:26 +00001551 } else {
Chris Lattneree352852004-02-29 07:22:16 +00001552 BuildMI(BB, X86::ADJCALLSTACKDOWN, 1).addImm(0);
Chris Lattner94af4142002-12-25 05:13:53 +00001553 }
Chris Lattner6e49a4b2002-12-13 14:13:27 +00001554
Chris Lattner3e130a22003-01-13 00:32:26 +00001555 BB->push_back(CallMI);
Misha Brukman0d2cf3a2002-12-04 19:22:53 +00001556
Chris Lattneree352852004-02-29 07:22:16 +00001557 BuildMI(BB, X86::ADJCALLSTACKUP, 1).addImm(NumBytes);
Chris Lattnera3243642002-12-04 23:45:28 +00001558
1559 // If there is a return value, scavenge the result from the location the call
1560 // leaves it in...
1561 //
Chris Lattner3e130a22003-01-13 00:32:26 +00001562 if (Ret.Ty != Type::VoidTy) {
1563 unsigned DestClass = getClassB(Ret.Ty);
1564 switch (DestClass) {
Brian Gaeke20244b72002-12-12 15:33:40 +00001565 case cByte:
1566 case cShort:
1567 case cInt: {
1568 // Integral results are in %eax, or the appropriate portion
1569 // thereof.
1570 static const unsigned regRegMove[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001571 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr
Brian Gaeke20244b72002-12-12 15:33:40 +00001572 };
1573 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX };
Chris Lattner3e130a22003-01-13 00:32:26 +00001574 BuildMI(BB, regRegMove[DestClass], 1, Ret.Reg).addReg(AReg[DestClass]);
Chris Lattner4fa1acc2002-12-04 23:50:28 +00001575 break;
Brian Gaeke20244b72002-12-12 15:33:40 +00001576 }
Chris Lattner94af4142002-12-25 05:13:53 +00001577 case cFP: // Floating-point return values live in %ST(0)
Chris Lattner3e130a22003-01-13 00:32:26 +00001578 BuildMI(BB, X86::FpGETRESULT, 1, Ret.Reg);
Brian Gaeke20244b72002-12-12 15:33:40 +00001579 break;
Chris Lattner3e130a22003-01-13 00:32:26 +00001580 case cLong: // Long values are left in EDX:EAX
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001581 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg).addReg(X86::EAX);
1582 BuildMI(BB, X86::MOV32rr, 1, Ret.Reg+1).addReg(X86::EDX);
Chris Lattner3e130a22003-01-13 00:32:26 +00001583 break;
1584 default: assert(0 && "Unknown class!");
Chris Lattner4fa1acc2002-12-04 23:50:28 +00001585 }
Chris Lattnera3243642002-12-04 23:45:28 +00001586 }
Brian Gaekefa8d5712002-11-22 11:07:01 +00001587}
Chris Lattner2df035b2002-11-02 19:27:56 +00001588
Chris Lattner3e130a22003-01-13 00:32:26 +00001589
1590/// visitCallInst - Push args on stack and do a procedure call instruction.
1591void ISel::visitCallInst(CallInst &CI) {
1592 MachineInstr *TheCall;
1593 if (Function *F = CI.getCalledFunction()) {
Chris Lattnereca195e2003-05-08 19:44:13 +00001594 // Is it an intrinsic function call?
Brian Gaeked0fde302003-11-11 22:41:34 +00001595 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
Chris Lattnereca195e2003-05-08 19:44:13 +00001596 visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
1597 return;
1598 }
1599
Chris Lattner3e130a22003-01-13 00:32:26 +00001600 // Emit a CALL instruction with PC-relative displacement.
1601 TheCall = BuildMI(X86::CALLpcrel32, 1).addGlobalAddress(F, true);
1602 } else { // Emit an indirect call...
1603 unsigned Reg = getReg(CI.getCalledValue());
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001604 TheCall = BuildMI(X86::CALL32r, 1).addReg(Reg);
Chris Lattner3e130a22003-01-13 00:32:26 +00001605 }
1606
1607 std::vector<ValueRecord> Args;
1608 for (unsigned i = 1, e = CI.getNumOperands(); i != e; ++i)
Chris Lattner5e2cb8b2003-08-04 02:12:48 +00001609 Args.push_back(ValueRecord(CI.getOperand(i)));
Chris Lattner3e130a22003-01-13 00:32:26 +00001610
1611 unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
1612 doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
Misha Brukmanc8893fc2003-10-23 16:22:08 +00001613}
Chris Lattner3e130a22003-01-13 00:32:26 +00001614
Chris Lattner44827152003-12-28 09:47:19 +00001615/// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1616/// function, lowering any calls to unknown intrinsic functions into the
1617/// equivalent LLVM code.
Misha Brukman538607f2004-03-01 23:53:11 +00001618///
Chris Lattner44827152003-12-28 09:47:19 +00001619void ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1620 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1621 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1622 if (CallInst *CI = dyn_cast<CallInst>(I++))
1623 if (Function *F = CI->getCalledFunction())
1624 switch (F->getIntrinsicID()) {
Chris Lattneraed386e2003-12-28 09:53:23 +00001625 case Intrinsic::not_intrinsic:
Chris Lattner317201d2004-03-13 00:24:00 +00001626 case Intrinsic::vastart:
1627 case Intrinsic::vacopy:
1628 case Intrinsic::vaend:
Chris Lattner0e5b79c2004-02-15 01:04:03 +00001629 case Intrinsic::returnaddress:
1630 case Intrinsic::frameaddress:
Chris Lattner915e5e52004-02-12 17:53:22 +00001631 case Intrinsic::memcpy:
Chris Lattner2a0f2242004-02-14 04:46:05 +00001632 case Intrinsic::memset:
Chris Lattnerdc572442004-06-15 21:36:44 +00001633 case Intrinsic::isunordered:
John Criswell4ffff9e2004-04-08 20:31:47 +00001634 case Intrinsic::readport:
1635 case Intrinsic::writeport:
Chris Lattner44827152003-12-28 09:47:19 +00001636 // We directly implement these intrinsics
1637 break;
John Criswelle5a4c152004-04-13 22:13:14 +00001638 case Intrinsic::readio: {
1639 // On X86, memory operations are in-order. Lower this intrinsic
1640 // into a volatile load.
1641 Instruction *Before = CI->getPrev();
Chris Lattnerb4fe76c2004-06-11 04:31:10 +00001642 LoadInst * LI = new LoadInst(CI->getOperand(1), "", true, CI);
1643 CI->replaceAllUsesWith(LI);
1644 BB->getInstList().erase(CI);
John Criswelle5a4c152004-04-13 22:13:14 +00001645 break;
1646 }
1647 case Intrinsic::writeio: {
1648 // On X86, memory operations are in-order. Lower this intrinsic
1649 // into a volatile store.
1650 Instruction *Before = CI->getPrev();
Chris Lattnerb4fe76c2004-06-11 04:31:10 +00001651 StoreInst *LI = new StoreInst(CI->getOperand(1),
1652 CI->getOperand(2), true, CI);
1653 CI->replaceAllUsesWith(LI);
1654 BB->getInstList().erase(CI);
John Criswelle5a4c152004-04-13 22:13:14 +00001655 break;
1656 }
Chris Lattner44827152003-12-28 09:47:19 +00001657 default:
1658 // All other intrinsic calls we must lower.
1659 Instruction *Before = CI->getPrev();
Chris Lattnerf70e0c22003-12-28 21:23:38 +00001660 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
Chris Lattner44827152003-12-28 09:47:19 +00001661 if (Before) { // Move iterator to instruction after call
Chris Lattnerb4fe76c2004-06-11 04:31:10 +00001662 I = Before; ++I;
Chris Lattner44827152003-12-28 09:47:19 +00001663 } else {
1664 I = BB->begin();
1665 }
1666 }
Chris Lattner44827152003-12-28 09:47:19 +00001667}
1668
Brian Gaeked0fde302003-11-11 22:41:34 +00001669void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
Chris Lattnereca195e2003-05-08 19:44:13 +00001670 unsigned TmpReg1, TmpReg2;
1671 switch (ID) {
Chris Lattner5634b9f2004-03-13 00:24:52 +00001672 case Intrinsic::vastart:
Chris Lattnereca195e2003-05-08 19:44:13 +00001673 // Get the address of the first vararg value...
Chris Lattner73815062003-10-18 05:56:40 +00001674 TmpReg1 = getReg(CI);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001675 addFrameReference(BuildMI(BB, X86::LEA32r, 5, TmpReg1), VarArgsFrameIndex);
Chris Lattnereca195e2003-05-08 19:44:13 +00001676 return;
1677
Chris Lattner5634b9f2004-03-13 00:24:52 +00001678 case Intrinsic::vacopy:
Chris Lattner73815062003-10-18 05:56:40 +00001679 TmpReg1 = getReg(CI);
1680 TmpReg2 = getReg(CI.getOperand(1));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001681 BuildMI(BB, X86::MOV32rr, 1, TmpReg1).addReg(TmpReg2);
Chris Lattnereca195e2003-05-08 19:44:13 +00001682 return;
Chris Lattner5634b9f2004-03-13 00:24:52 +00001683 case Intrinsic::vaend: return; // Noop on X86
Chris Lattnereca195e2003-05-08 19:44:13 +00001684
Chris Lattner0e5b79c2004-02-15 01:04:03 +00001685 case Intrinsic::returnaddress:
1686 case Intrinsic::frameaddress:
1687 TmpReg1 = getReg(CI);
1688 if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
1689 if (ID == Intrinsic::returnaddress) {
1690 // Just load the return address
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001691 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, TmpReg1),
Chris Lattner0e5b79c2004-02-15 01:04:03 +00001692 ReturnAddressIndex);
1693 } else {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001694 addFrameReference(BuildMI(BB, X86::LEA32r, 4, TmpReg1),
Chris Lattner0e5b79c2004-02-15 01:04:03 +00001695 ReturnAddressIndex, -4);
1696 }
1697 } else {
1698 // Values other than zero are not implemented yet.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001699 BuildMI(BB, X86::MOV32ri, 1, TmpReg1).addImm(0);
Chris Lattner0e5b79c2004-02-15 01:04:03 +00001700 }
1701 return;
1702
Chris Lattnerdc572442004-06-15 21:36:44 +00001703 case Intrinsic::isunordered:
1704 TmpReg1 = getReg(CI.getOperand(1));
1705 TmpReg2 = getReg(CI.getOperand(2));
1706 emitUCOMr(BB, BB->end(), TmpReg2, TmpReg1);
1707 TmpReg2 = getReg(CI);
1708 BuildMI(BB, X86::SETPr, 0, TmpReg2);
1709 return;
1710
Chris Lattner915e5e52004-02-12 17:53:22 +00001711 case Intrinsic::memcpy: {
1712 assert(CI.getNumOperands() == 5 && "Illegal llvm.memcpy call!");
1713 unsigned Align = 1;
1714 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1715 Align = AlignC->getRawValue();
1716 if (Align == 0) Align = 1;
1717 }
1718
1719 // Turn the byte code into # iterations
Chris Lattner915e5e52004-02-12 17:53:22 +00001720 unsigned CountReg;
Chris Lattner2a0f2242004-02-14 04:46:05 +00001721 unsigned Opcode;
Chris Lattner915e5e52004-02-12 17:53:22 +00001722 switch (Align & 3) {
1723 case 2: // WORD aligned
Chris Lattner07122832004-02-13 23:36:47 +00001724 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1725 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
1726 } else {
1727 CountReg = makeAnotherReg(Type::IntTy);
Chris Lattner8dd8d262004-02-26 01:20:02 +00001728 unsigned ByteReg = getReg(CI.getOperand(3));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001729 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
Chris Lattner07122832004-02-13 23:36:47 +00001730 }
Chris Lattner2a0f2242004-02-14 04:46:05 +00001731 Opcode = X86::REP_MOVSW;
Chris Lattner915e5e52004-02-12 17:53:22 +00001732 break;
1733 case 0: // DWORD aligned
Chris Lattner07122832004-02-13 23:36:47 +00001734 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
1735 CountReg = getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
1736 } else {
1737 CountReg = makeAnotherReg(Type::IntTy);
Chris Lattner8dd8d262004-02-26 01:20:02 +00001738 unsigned ByteReg = getReg(CI.getOperand(3));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001739 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
Chris Lattner07122832004-02-13 23:36:47 +00001740 }
Chris Lattner2a0f2242004-02-14 04:46:05 +00001741 Opcode = X86::REP_MOVSD;
Chris Lattner915e5e52004-02-12 17:53:22 +00001742 break;
Chris Lattner8dd8d262004-02-26 01:20:02 +00001743 default: // BYTE aligned
Chris Lattner07122832004-02-13 23:36:47 +00001744 CountReg = getReg(CI.getOperand(3));
Chris Lattner2a0f2242004-02-14 04:46:05 +00001745 Opcode = X86::REP_MOVSB;
Chris Lattner915e5e52004-02-12 17:53:22 +00001746 break;
1747 }
1748
1749 // No matter what the alignment is, we put the source in ESI, the
1750 // destination in EDI, and the count in ECX.
1751 TmpReg1 = getReg(CI.getOperand(1));
1752 TmpReg2 = getReg(CI.getOperand(2));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001753 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1754 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
1755 BuildMI(BB, X86::MOV32rr, 1, X86::ESI).addReg(TmpReg2);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001756 BuildMI(BB, Opcode, 0);
1757 return;
1758 }
1759 case Intrinsic::memset: {
1760 assert(CI.getNumOperands() == 5 && "Illegal llvm.memset call!");
1761 unsigned Align = 1;
1762 if (ConstantInt *AlignC = dyn_cast<ConstantInt>(CI.getOperand(4))) {
1763 Align = AlignC->getRawValue();
1764 if (Align == 0) Align = 1;
Chris Lattner915e5e52004-02-12 17:53:22 +00001765 }
1766
Chris Lattner2a0f2242004-02-14 04:46:05 +00001767 // Turn the byte code into # iterations
Chris Lattner2a0f2242004-02-14 04:46:05 +00001768 unsigned CountReg;
1769 unsigned Opcode;
1770 if (ConstantInt *ValC = dyn_cast<ConstantInt>(CI.getOperand(2))) {
1771 unsigned Val = ValC->getRawValue() & 255;
1772
1773 // If the value is a constant, then we can potentially use larger copies.
1774 switch (Align & 3) {
1775 case 2: // WORD aligned
1776 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
Chris Lattner300d0ed2004-02-14 06:00:36 +00001777 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/2));
Chris Lattner2a0f2242004-02-14 04:46:05 +00001778 } else {
1779 CountReg = makeAnotherReg(Type::IntTy);
Chris Lattner8dd8d262004-02-26 01:20:02 +00001780 unsigned ByteReg = getReg(CI.getOperand(3));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001781 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(1);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001782 }
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001783 BuildMI(BB, X86::MOV16ri, 1, X86::AX).addImm((Val << 8) | Val);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001784 Opcode = X86::REP_STOSW;
1785 break;
1786 case 0: // DWORD aligned
1787 if (ConstantInt *I = dyn_cast<ConstantInt>(CI.getOperand(3))) {
Chris Lattner300d0ed2004-02-14 06:00:36 +00001788 CountReg =getReg(ConstantUInt::get(Type::UIntTy, I->getRawValue()/4));
Chris Lattner2a0f2242004-02-14 04:46:05 +00001789 } else {
1790 CountReg = makeAnotherReg(Type::IntTy);
Chris Lattner8dd8d262004-02-26 01:20:02 +00001791 unsigned ByteReg = getReg(CI.getOperand(3));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001792 BuildMI(BB, X86::SHR32ri, 2, CountReg).addReg(ByteReg).addImm(2);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001793 }
1794 Val = (Val << 8) | Val;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001795 BuildMI(BB, X86::MOV32ri, 1, X86::EAX).addImm((Val << 16) | Val);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001796 Opcode = X86::REP_STOSD;
1797 break;
Chris Lattner8dd8d262004-02-26 01:20:02 +00001798 default: // BYTE aligned
Chris Lattner2a0f2242004-02-14 04:46:05 +00001799 CountReg = getReg(CI.getOperand(3));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001800 BuildMI(BB, X86::MOV8ri, 1, X86::AL).addImm(Val);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001801 Opcode = X86::REP_STOSB;
1802 break;
1803 }
1804 } else {
1805 // If it's not a constant value we are storing, just fall back. We could
1806 // try to be clever to form 16 bit and 32 bit values, but we don't yet.
1807 unsigned ValReg = getReg(CI.getOperand(2));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001808 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001809 CountReg = getReg(CI.getOperand(3));
1810 Opcode = X86::REP_STOSB;
1811 }
1812
1813 // No matter what the alignment is, we put the source in ESI, the
1814 // destination in EDI, and the count in ECX.
1815 TmpReg1 = getReg(CI.getOperand(1));
1816 //TmpReg2 = getReg(CI.getOperand(2));
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00001817 BuildMI(BB, X86::MOV32rr, 1, X86::ECX).addReg(CountReg);
1818 BuildMI(BB, X86::MOV32rr, 1, X86::EDI).addReg(TmpReg1);
Chris Lattner2a0f2242004-02-14 04:46:05 +00001819 BuildMI(BB, Opcode, 0);
Chris Lattner915e5e52004-02-12 17:53:22 +00001820 return;
1821 }
1822
Chris Lattner87e18de2004-04-13 17:20:37 +00001823 case Intrinsic::readport: {
1824 // First, determine that the size of the operand falls within the acceptable
1825 // range for this architecture.
John Criswell4ffff9e2004-04-08 20:31:47 +00001826 //
Chris Lattner87e18de2004-04-13 17:20:37 +00001827 if (getClassB(CI.getOperand(1)->getType()) != cShort) {
John Criswellca6ea0f2004-04-08 22:39:13 +00001828 std::cerr << "llvm.readport: Address size is not 16 bits\n";
Chris Lattner87e18de2004-04-13 17:20:37 +00001829 exit(1);
John Criswellca6ea0f2004-04-08 22:39:13 +00001830 }
John Criswell4ffff9e2004-04-08 20:31:47 +00001831
John Criswell4ffff9e2004-04-08 20:31:47 +00001832 // Now, move the I/O port address into the DX register and use the IN
1833 // instruction to get the input data.
1834 //
Chris Lattner87e18de2004-04-13 17:20:37 +00001835 unsigned Class = getClass(CI.getCalledFunction()->getReturnType());
1836 unsigned DestReg = getReg(CI);
John Criswell4ffff9e2004-04-08 20:31:47 +00001837
Chris Lattner87e18de2004-04-13 17:20:37 +00001838 // If the port is a single-byte constant, use the immediate form.
1839 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(1)))
1840 if ((C->getRawValue() & 255) == C->getRawValue()) {
1841 switch (Class) {
1842 case cByte:
1843 BuildMI(BB, X86::IN8ri, 1).addImm((unsigned char)C->getRawValue());
1844 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1845 return;
1846 case cShort:
1847 BuildMI(BB, X86::IN16ri, 1).addImm((unsigned char)C->getRawValue());
1848 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1849 return;
1850 case cInt:
1851 BuildMI(BB, X86::IN32ri, 1).addImm((unsigned char)C->getRawValue());
1852 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1853 return;
1854 }
1855 }
1856
1857 unsigned Reg = getReg(CI.getOperand(1));
1858 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1859 switch (Class) {
1860 case cByte:
1861 BuildMI(BB, X86::IN8rr, 0);
1862 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
1863 break;
1864 case cShort:
1865 BuildMI(BB, X86::IN16rr, 0);
1866 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::AX);
1867 break;
1868 case cInt:
1869 BuildMI(BB, X86::IN32rr, 0);
1870 BuildMI(BB, X86::MOV8rr, 1, DestReg).addReg(X86::EAX);
1871 break;
1872 default:
1873 std::cerr << "Cannot do input on this data type";
John Criswellca6ea0f2004-04-08 22:39:13 +00001874 exit (1);
1875 }
John Criswell4ffff9e2004-04-08 20:31:47 +00001876 return;
Chris Lattner87e18de2004-04-13 17:20:37 +00001877 }
John Criswell4ffff9e2004-04-08 20:31:47 +00001878
Chris Lattner87e18de2004-04-13 17:20:37 +00001879 case Intrinsic::writeport: {
1880 // First, determine that the size of the operand falls within the
1881 // acceptable range for this architecture.
1882 if (getClass(CI.getOperand(2)->getType()) != cShort) {
1883 std::cerr << "llvm.writeport: Address size is not 16 bits\n";
1884 exit(1);
1885 }
1886
1887 unsigned Class = getClassB(CI.getOperand(1)->getType());
1888 unsigned ValReg = getReg(CI.getOperand(1));
1889 switch (Class) {
1890 case cByte:
1891 BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(ValReg);
1892 break;
1893 case cShort:
1894 BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(ValReg);
1895 break;
1896 case cInt:
1897 BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(ValReg);
1898 break;
1899 default:
1900 std::cerr << "llvm.writeport: invalid data type for X86 target";
1901 exit(1);
1902 }
1903
1904
1905 // If the port is a single-byte constant, use the immediate form.
1906 if (ConstantInt *C = dyn_cast<ConstantInt>(CI.getOperand(2)))
1907 if ((C->getRawValue() & 255) == C->getRawValue()) {
1908 static const unsigned O[] = { X86::OUT8ir, X86::OUT16ir, X86::OUT32ir };
1909 BuildMI(BB, O[Class], 1).addImm((unsigned char)C->getRawValue());
1910 return;
1911 }
1912
1913 // Otherwise, move the I/O port address into the DX register and the value
1914 // to write into the AL/AX/EAX register.
1915 static const unsigned Opc[] = { X86::OUT8rr, X86::OUT16rr, X86::OUT32rr };
1916 unsigned Reg = getReg(CI.getOperand(2));
1917 BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(Reg);
1918 BuildMI(BB, Opc[Class], 0);
1919 return;
1920 }
1921
Chris Lattner44827152003-12-28 09:47:19 +00001922 default: assert(0 && "Error: unknown intrinsics should have been lowered!");
Chris Lattnereca195e2003-05-08 19:44:13 +00001923 }
1924}
1925
Chris Lattner7dee5da2004-03-08 01:58:35 +00001926static bool isSafeToFoldLoadIntoInstruction(LoadInst &LI, Instruction &User) {
1927 if (LI.getParent() != User.getParent())
1928 return false;
1929 BasicBlock::iterator It = &LI;
1930 // Check all of the instructions between the load and the user. We should
1931 // really use alias analysis here, but for now we just do something simple.
1932 for (++It; It != BasicBlock::iterator(&User); ++It) {
1933 switch (It->getOpcode()) {
Chris Lattner85c84e72004-03-18 06:29:54 +00001934 case Instruction::Free:
Chris Lattner7dee5da2004-03-08 01:58:35 +00001935 case Instruction::Store:
1936 case Instruction::Call:
1937 case Instruction::Invoke:
1938 return false;
Chris Lattner133dbb12004-04-12 03:02:48 +00001939 case Instruction::Load:
1940 if (cast<LoadInst>(It)->isVolatile() && LI.isVolatile())
1941 return false;
1942 break;
Chris Lattner7dee5da2004-03-08 01:58:35 +00001943 }
1944 }
1945 return true;
1946}
1947
Chris Lattnerb515f6d2003-05-08 20:49:25 +00001948/// visitSimpleBinary - Implement simple binary operators for integral types...
1949/// OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for Or, 4 for
1950/// Xor.
Misha Brukman538607f2004-03-01 23:53:11 +00001951///
Chris Lattnerb515f6d2003-05-08 20:49:25 +00001952void ISel::visitSimpleBinary(BinaryOperator &B, unsigned OperatorClass) {
1953 unsigned DestReg = getReg(B);
1954 MachineBasicBlock::iterator MI = BB->end();
Chris Lattner721d2d42004-03-08 01:18:36 +00001955 Value *Op0 = B.getOperand(0), *Op1 = B.getOperand(1);
Chris Lattnerc81e6ba2004-05-10 15:15:55 +00001956 unsigned Class = getClassB(B.getType());
Chris Lattner721d2d42004-03-08 01:18:36 +00001957
Chris Lattner7dee5da2004-03-08 01:58:35 +00001958 // Special case: op Reg, load [mem]
Chris Lattnerc81e6ba2004-05-10 15:15:55 +00001959 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1) && Class != cLong &&
Chris Lattnerccd97962004-06-17 22:15:25 +00001960 Op0->hasOneUse() &&
Chris Lattnerc81e6ba2004-05-10 15:15:55 +00001961 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B))
Chris Lattner7dee5da2004-03-08 01:58:35 +00001962 if (!B.swapOperands())
1963 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
1964
Chris Lattnerccd97962004-06-17 22:15:25 +00001965 if (isa<LoadInst>(Op1) && Class != cLong && Op1->hasOneUse() &&
Chris Lattner7dee5da2004-03-08 01:58:35 +00001966 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op1), B)) {
1967
Chris Lattner95157f72004-04-11 22:05:45 +00001968 unsigned Opcode;
1969 if (Class != cFP) {
1970 static const unsigned OpcodeTab[][3] = {
1971 // Arithmetic operators
1972 { X86::ADD8rm, X86::ADD16rm, X86::ADD32rm }, // ADD
1973 { X86::SUB8rm, X86::SUB16rm, X86::SUB32rm }, // SUB
1974
1975 // Bitwise operators
1976 { X86::AND8rm, X86::AND16rm, X86::AND32rm }, // AND
1977 { X86:: OR8rm, X86:: OR16rm, X86:: OR32rm }, // OR
1978 { X86::XOR8rm, X86::XOR16rm, X86::XOR32rm }, // XOR
1979 };
1980 Opcode = OpcodeTab[OperatorClass][Class];
1981 } else {
1982 static const unsigned OpcodeTab[][2] = {
1983 { X86::FADD32m, X86::FADD64m }, // ADD
1984 { X86::FSUB32m, X86::FSUB64m }, // SUB
1985 };
1986 const Type *Ty = Op0->getType();
1987 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
1988 Opcode = OpcodeTab[OperatorClass][Ty == Type::DoubleTy];
1989 }
Chris Lattner7dee5da2004-03-08 01:58:35 +00001990
Chris Lattner7dee5da2004-03-08 01:58:35 +00001991 unsigned Op0r = getReg(Op0);
Chris Lattner9f1b5312004-05-13 15:12:43 +00001992 if (AllocaInst *AI =
1993 dyn_castFixedAlloca(cast<LoadInst>(Op1)->getOperand(0))) {
1994 unsigned FI = getFixedSizedAllocaFI(AI);
1995 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r), FI);
1996
1997 } else {
1998 unsigned BaseReg, Scale, IndexReg, Disp;
1999 getAddressingMode(cast<LoadInst>(Op1)->getOperand(0), BaseReg,
2000 Scale, IndexReg, Disp);
2001
2002 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op0r),
2003 BaseReg, Scale, IndexReg, Disp);
2004 }
Chris Lattner7dee5da2004-03-08 01:58:35 +00002005 return;
2006 }
2007
Chris Lattner95157f72004-04-11 22:05:45 +00002008 // If this is a floating point subtract, check to see if we can fold the first
2009 // operand in.
2010 if (Class == cFP && OperatorClass == 1 &&
2011 isa<LoadInst>(Op0) &&
2012 isSafeToFoldLoadIntoInstruction(*cast<LoadInst>(Op0), B)) {
2013 const Type *Ty = Op0->getType();
2014 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2015 unsigned Opcode = Ty == Type::FloatTy ? X86::FSUBR32m : X86::FSUBR64m;
2016
Chris Lattner95157f72004-04-11 22:05:45 +00002017 unsigned Op1r = getReg(Op1);
Chris Lattner9f1b5312004-05-13 15:12:43 +00002018 if (AllocaInst *AI =
2019 dyn_castFixedAlloca(cast<LoadInst>(Op0)->getOperand(0))) {
2020 unsigned FI = getFixedSizedAllocaFI(AI);
2021 addFrameReference(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r), FI);
2022 } else {
2023 unsigned BaseReg, Scale, IndexReg, Disp;
2024 getAddressingMode(cast<LoadInst>(Op0)->getOperand(0), BaseReg,
2025 Scale, IndexReg, Disp);
2026
2027 addFullAddress(BuildMI(BB, Opcode, 5, DestReg).addReg(Op1r),
2028 BaseReg, Scale, IndexReg, Disp);
2029 }
Chris Lattner95157f72004-04-11 22:05:45 +00002030 return;
2031 }
2032
Chris Lattner721d2d42004-03-08 01:18:36 +00002033 emitSimpleBinaryOperation(BB, MI, Op0, Op1, OperatorClass, DestReg);
Chris Lattnerb515f6d2003-05-08 20:49:25 +00002034}
Chris Lattner3e130a22003-01-13 00:32:26 +00002035
Chris Lattner6621ed92004-04-11 21:23:56 +00002036
2037/// emitBinaryFPOperation - This method handles emission of floating point
2038/// Add (0), Sub (1), Mul (2), and Div (3) operations.
2039void ISel::emitBinaryFPOperation(MachineBasicBlock *BB,
2040 MachineBasicBlock::iterator IP,
2041 Value *Op0, Value *Op1,
2042 unsigned OperatorClass, unsigned DestReg) {
2043
2044 // Special case: op Reg, <const fp>
2045 if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1))
2046 if (!Op1C->isExactlyValue(+0.0) && !Op1C->isExactlyValue(+1.0)) {
2047 // Create a constant pool entry for this constant.
2048 MachineConstantPool *CP = F->getConstantPool();
2049 unsigned CPI = CP->getConstantPoolIndex(Op1C);
2050 const Type *Ty = Op1->getType();
2051
2052 static const unsigned OpcodeTab[][4] = {
2053 { X86::FADD32m, X86::FSUB32m, X86::FMUL32m, X86::FDIV32m }, // Float
2054 { X86::FADD64m, X86::FSUB64m, X86::FMUL64m, X86::FDIV64m }, // Double
2055 };
2056
2057 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
2058 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2059 unsigned Op0r = getReg(Op0, BB, IP);
2060 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2061 DestReg).addReg(Op0r), CPI);
2062 return;
2063 }
2064
Chris Lattner13c07fe2004-04-12 00:12:04 +00002065 // Special case: R1 = op <const fp>, R2
Chris Lattner6621ed92004-04-11 21:23:56 +00002066 if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
2067 if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
2068 // -0.0 - X === -X
2069 unsigned op1Reg = getReg(Op1, BB, IP);
2070 BuildMI(*BB, IP, X86::FCHS, 1, DestReg).addReg(op1Reg);
2071 return;
2072 } else if (!CFP->isExactlyValue(+0.0) && !CFP->isExactlyValue(+1.0)) {
Chris Lattner13c07fe2004-04-12 00:12:04 +00002073 // R1 = op CST, R2 --> R1 = opr R2, CST
Chris Lattner6621ed92004-04-11 21:23:56 +00002074
2075 // Create a constant pool entry for this constant.
2076 MachineConstantPool *CP = F->getConstantPool();
2077 unsigned CPI = CP->getConstantPoolIndex(CFP);
2078 const Type *Ty = CFP->getType();
2079
2080 static const unsigned OpcodeTab[][4] = {
2081 { X86::FADD32m, X86::FSUBR32m, X86::FMUL32m, X86::FDIVR32m }, // Float
2082 { X86::FADD64m, X86::FSUBR64m, X86::FMUL64m, X86::FDIVR64m }, // Double
2083 };
2084
2085 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2086 unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
2087 unsigned Op1r = getReg(Op1, BB, IP);
2088 addConstantPoolReference(BuildMI(*BB, IP, Opcode, 5,
2089 DestReg).addReg(Op1r), CPI);
2090 return;
2091 }
2092
2093 // General case.
2094 static const unsigned OpcodeTab[4] = {
2095 X86::FpADD, X86::FpSUB, X86::FpMUL, X86::FpDIV
2096 };
2097
2098 unsigned Opcode = OpcodeTab[OperatorClass];
2099 unsigned Op0r = getReg(Op0, BB, IP);
2100 unsigned Op1r = getReg(Op1, BB, IP);
2101 BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2102}
2103
Chris Lattnerb2acc512003-10-19 21:09:10 +00002104/// emitSimpleBinaryOperation - Implement simple binary operators for integral
2105/// types... OperatorClass is one of: 0 for Add, 1 for Sub, 2 for And, 3 for
2106/// Or, 4 for Xor.
Chris Lattner68aad932002-11-02 20:13:22 +00002107///
Chris Lattnerb515f6d2003-05-08 20:49:25 +00002108/// emitSimpleBinaryOperation - Common code shared between visitSimpleBinary
2109/// and constant expression support.
Chris Lattnerb2acc512003-10-19 21:09:10 +00002110///
2111void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00002112 MachineBasicBlock::iterator IP,
Chris Lattnerb515f6d2003-05-08 20:49:25 +00002113 Value *Op0, Value *Op1,
Chris Lattnerb2acc512003-10-19 21:09:10 +00002114 unsigned OperatorClass, unsigned DestReg) {
Chris Lattnerb515f6d2003-05-08 20:49:25 +00002115 unsigned Class = getClassB(Op0->getType());
Chris Lattnerb2acc512003-10-19 21:09:10 +00002116
Chris Lattner6621ed92004-04-11 21:23:56 +00002117 if (Class == cFP) {
2118 assert(OperatorClass < 2 && "No logical ops for FP!");
2119 emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
2120 return;
2121 }
2122
Chris Lattner48b0c972004-04-11 20:26:20 +00002123 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op0))
Chris Lattner667ea022004-06-18 00:50:37 +00002124 if (OperatorClass == 1) {
Chris Lattner48b0c972004-04-11 20:26:20 +00002125 static unsigned const NEGTab[] = {
2126 X86::NEG8r, X86::NEG16r, X86::NEG32r, 0, X86::NEG32r
2127 };
Chris Lattner667ea022004-06-18 00:50:37 +00002128
2129 // sub 0, X -> neg X
2130 if (CI->isNullValue()) {
2131 unsigned op1Reg = getReg(Op1, MBB, IP);
2132 BuildMI(*MBB, IP, NEGTab[Class], 1, DestReg).addReg(op1Reg);
Chris Lattner48b0c972004-04-11 20:26:20 +00002133
Chris Lattner667ea022004-06-18 00:50:37 +00002134 if (Class == cLong) {
2135 // We just emitted: Dl = neg Sl
2136 // Now emit : T = addc Sh, 0
2137 // : Dh = neg T
2138 unsigned T = makeAnotherReg(Type::IntTy);
2139 BuildMI(*MBB, IP, X86::ADC32ri, 2, T).addReg(op1Reg+1).addImm(0);
2140 BuildMI(*MBB, IP, X86::NEG32r, 1, DestReg+1).addReg(T);
2141 }
2142 return;
2143 } else if (Op1->hasOneUse() && Class != cLong) {
2144 // sub C, X -> tmp = neg X; DestReg = add tmp, C. This is better
2145 // than copying C into a temporary register, because of register
2146 // pressure (tmp and destreg can share a register.
2147 static unsigned const ADDRITab[] = {
2148 X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri
2149 };
2150 unsigned op1Reg = getReg(Op1, MBB, IP);
2151 unsigned Tmp = makeAnotherReg(Op0->getType());
2152 BuildMI(*MBB, IP, NEGTab[Class], 1, Tmp).addReg(op1Reg);
Chris Lattner30483732004-06-20 07:49:54 +00002153 BuildMI(*MBB, IP, ADDRITab[Class], 2,
2154 DestReg).addReg(Tmp).addImm(CI->getRawValue());
Chris Lattner667ea022004-06-18 00:50:37 +00002155 return;
Chris Lattnerb2acc512003-10-19 21:09:10 +00002156 }
Chris Lattner48b0c972004-04-11 20:26:20 +00002157 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00002158
Chris Lattner48b0c972004-04-11 20:26:20 +00002159 // Special case: op Reg, <const int>
2160 if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
Chris Lattner721d2d42004-03-08 01:18:36 +00002161 unsigned Op0r = getReg(Op0, MBB, IP);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002162
Chris Lattner721d2d42004-03-08 01:18:36 +00002163 // xor X, -1 -> not X
2164 if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002165 static unsigned const NOTTab[] = {
2166 X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
2167 };
Chris Lattner721d2d42004-03-08 01:18:36 +00002168 BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002169 if (Class == cLong) // Invert the top part too
2170 BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
Chris Lattner721d2d42004-03-08 01:18:36 +00002171 return;
2172 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00002173
Chris Lattner721d2d42004-03-08 01:18:36 +00002174 // add X, -1 -> dec X
Chris Lattner06521672004-04-06 03:36:57 +00002175 if (OperatorClass == 0 && Op1C->isAllOnesValue() && Class != cLong) {
2176 // Note that we can't use dec for 64-bit decrements, because it does not
2177 // set the carry flag!
2178 static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
Chris Lattner721d2d42004-03-08 01:18:36 +00002179 BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
2180 return;
2181 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00002182
Chris Lattner721d2d42004-03-08 01:18:36 +00002183 // add X, 1 -> inc X
Chris Lattner06521672004-04-06 03:36:57 +00002184 if (OperatorClass == 0 && Op1C->equalsInt(1) && Class != cLong) {
2185 // Note that we can't use inc for 64-bit increments, because it does not
2186 // set the carry flag!
2187 static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
Alkis Evlogimenosbee8a092004-04-02 18:11:32 +00002188 BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
Chris Lattner721d2d42004-03-08 01:18:36 +00002189 return;
2190 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00002191
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002192 static const unsigned OpcodeTab[][5] = {
Chris Lattner721d2d42004-03-08 01:18:36 +00002193 // Arithmetic operators
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002194 { X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
2195 { X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
Chris Lattnerb2acc512003-10-19 21:09:10 +00002196
Chris Lattner721d2d42004-03-08 01:18:36 +00002197 // Bitwise operators
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002198 { X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
2199 { X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
2200 { X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
Chris Lattner721d2d42004-03-08 01:18:36 +00002201 };
2202
Chris Lattner721d2d42004-03-08 01:18:36 +00002203 unsigned Opcode = OpcodeTab[OperatorClass][Class];
Chris Lattner33f7fa32004-04-06 03:15:53 +00002204 unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
Chris Lattner721d2d42004-03-08 01:18:36 +00002205
Chris Lattner33f7fa32004-04-06 03:15:53 +00002206 if (Class != cLong) {
2207 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2208 return;
Chris Lattner6621ed92004-04-11 21:23:56 +00002209 }
2210
2211 // If this is a long value and the high or low bits have a special
2212 // property, emit some special cases.
2213 unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
2214
2215 // If the constant is zero in the low 32-bits, just copy the low part
2216 // across and apply the normal 32-bit operation to the high parts. There
2217 // will be no carry or borrow into the top.
2218 if (Op1l == 0) {
2219 if (OperatorClass != 2) // All but and...
2220 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
2221 else
2222 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2223 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
2224 .addReg(Op0r+1).addImm(Op1h);
Chris Lattner33f7fa32004-04-06 03:15:53 +00002225 return;
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002226 }
Chris Lattner6621ed92004-04-11 21:23:56 +00002227
2228 // If this is a logical operation and the top 32-bits are zero, just
2229 // operate on the lower 32.
2230 if (Op1h == 0 && OperatorClass > 1) {
2231 BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
2232 .addReg(Op0r).addImm(Op1l);
2233 if (OperatorClass != 2) // All but and
2234 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
2235 else
2236 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
2237 return;
2238 }
2239
2240 // TODO: We could handle lots of other special cases here, such as AND'ing
2241 // with 0xFFFFFFFF00000000 -> noop, etc.
2242
2243 // Otherwise, code generate the full operation with a constant.
2244 static const unsigned TopTab[] = {
2245 X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
2246 };
2247
2248 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
2249 BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
2250 .addReg(Op0r+1).addImm(Op1h);
2251 return;
Chris Lattner721d2d42004-03-08 01:18:36 +00002252 }
2253
2254 // Finally, handle the general case now.
Chris Lattner7ba92302004-04-06 02:13:25 +00002255 static const unsigned OpcodeTab[][5] = {
Chris Lattner721d2d42004-03-08 01:18:36 +00002256 // Arithmetic operators
Chris Lattner6621ed92004-04-11 21:23:56 +00002257 { X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, 0, X86::ADD32rr }, // ADD
2258 { X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, 0, X86::SUB32rr }, // SUB
Chris Lattner721d2d42004-03-08 01:18:36 +00002259
Chris Lattnerb2acc512003-10-19 21:09:10 +00002260 // Bitwise operators
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002261 { X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
2262 { X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
2263 { X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
Chris Lattnerb2acc512003-10-19 21:09:10 +00002264 };
Chris Lattner721d2d42004-03-08 01:18:36 +00002265
Chris Lattnerb2acc512003-10-19 21:09:10 +00002266 unsigned Opcode = OpcodeTab[OperatorClass][Class];
Chris Lattner721d2d42004-03-08 01:18:36 +00002267 unsigned Op0r = getReg(Op0, MBB, IP);
2268 unsigned Op1r = getReg(Op1, MBB, IP);
2269 BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
2270
Chris Lattnerab1d0e02004-04-06 02:11:49 +00002271 if (Class == cLong) { // Handle the upper 32 bits of long values...
Chris Lattner721d2d42004-03-08 01:18:36 +00002272 static const unsigned TopTab[] = {
2273 X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
2274 };
2275 BuildMI(*MBB, IP, TopTab[OperatorClass], 2,
2276 DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
2277 }
Chris Lattnere2954c82002-11-02 20:04:26 +00002278}
2279
Chris Lattner3e130a22003-01-13 00:32:26 +00002280/// doMultiply - Emit appropriate instructions to multiply together the
2281/// registers op0Reg and op1Reg, and put the result in DestReg. The type of the
2282/// result should be given as DestTy.
2283///
Chris Lattnerbaa58a52004-02-23 03:10:10 +00002284void ISel::doMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI,
Chris Lattner3e130a22003-01-13 00:32:26 +00002285 unsigned DestReg, const Type *DestTy,
Chris Lattner8a307e82002-12-16 19:32:50 +00002286 unsigned op0Reg, unsigned op1Reg) {
Chris Lattner3e130a22003-01-13 00:32:26 +00002287 unsigned Class = getClass(DestTy);
Chris Lattner94af4142002-12-25 05:13:53 +00002288 switch (Class) {
Chris Lattner0f1c4612003-06-21 17:16:58 +00002289 case cInt:
2290 case cShort:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002291 BuildMI(*MBB, MBBI, Class == cInt ? X86::IMUL32rr:X86::IMUL16rr, 2, DestReg)
Chris Lattner0f1c4612003-06-21 17:16:58 +00002292 .addReg(op0Reg).addReg(op1Reg);
2293 return;
2294 case cByte:
2295 // Must use the MUL instruction, which forces use of AL...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002296 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, X86::AL).addReg(op0Reg);
2297 BuildMI(*MBB, MBBI, X86::MUL8r, 1).addReg(op1Reg);
2298 BuildMI(*MBB, MBBI, X86::MOV8rr, 1, DestReg).addReg(X86::AL);
Chris Lattner0f1c4612003-06-21 17:16:58 +00002299 return;
Chris Lattner94af4142002-12-25 05:13:53 +00002300 default:
Chris Lattner3e130a22003-01-13 00:32:26 +00002301 case cLong: assert(0 && "doMultiply cannot operate on LONG values!");
Chris Lattner94af4142002-12-25 05:13:53 +00002302 }
Brian Gaeke20244b72002-12-12 15:33:40 +00002303}
2304
Chris Lattnerb2acc512003-10-19 21:09:10 +00002305// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
2306// returns zero when the input is not exactly a power of two.
2307static unsigned ExactLog2(unsigned Val) {
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002308 if (Val == 0 || (Val & (Val-1))) return 0;
Chris Lattnerb2acc512003-10-19 21:09:10 +00002309 unsigned Count = 0;
2310 while (Val != 1) {
Chris Lattnerb2acc512003-10-19 21:09:10 +00002311 Val >>= 1;
2312 ++Count;
2313 }
2314 return Count+1;
2315}
2316
Chris Lattner462fa822004-04-11 20:56:28 +00002317
2318/// doMultiplyConst - This function is specialized to efficiently codegen an 8,
2319/// 16, or 32-bit integer multiply by a constant.
Chris Lattnerb2acc512003-10-19 21:09:10 +00002320void ISel::doMultiplyConst(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00002321 MachineBasicBlock::iterator IP,
Chris Lattnerb2acc512003-10-19 21:09:10 +00002322 unsigned DestReg, const Type *DestTy,
2323 unsigned op0Reg, unsigned ConstRHS) {
Chris Lattner6ab06d52004-04-06 04:55:43 +00002324 static const unsigned MOVrrTab[] = {X86::MOV8rr, X86::MOV16rr, X86::MOV32rr};
2325 static const unsigned MOVriTab[] = {X86::MOV8ri, X86::MOV16ri, X86::MOV32ri};
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002326 static const unsigned ADDrrTab[] = {X86::ADD8rr, X86::ADD16rr, X86::ADD32rr};
Chris Lattner596b97f2004-07-19 23:47:21 +00002327 static const unsigned NEGrTab[] = {X86::NEG8r , X86::NEG16r , X86::NEG32r };
Chris Lattner6ab06d52004-04-06 04:55:43 +00002328
Chris Lattnerb2acc512003-10-19 21:09:10 +00002329 unsigned Class = getClass(DestTy);
Chris Lattner596b97f2004-07-19 23:47:21 +00002330 unsigned TmpReg;
Chris Lattnerb2acc512003-10-19 21:09:10 +00002331
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002332 // Handle special cases here.
2333 switch (ConstRHS) {
Chris Lattner596b97f2004-07-19 23:47:21 +00002334 case -2:
2335 TmpReg = makeAnotherReg(DestTy);
2336 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2337 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(TmpReg).addReg(TmpReg);
2338 return;
2339 case -1:
2340 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(op0Reg);
2341 return;
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002342 case 0:
Chris Lattner6ab06d52004-04-06 04:55:43 +00002343 BuildMI(*MBB, IP, MOVriTab[Class], 1, DestReg).addImm(0);
2344 return;
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002345 case 1:
Chris Lattner6ab06d52004-04-06 04:55:43 +00002346 BuildMI(*MBB, IP, MOVrrTab[Class], 1, DestReg).addReg(op0Reg);
2347 return;
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002348 case 2:
2349 BuildMI(*MBB, IP, ADDrrTab[Class], 1,DestReg).addReg(op0Reg).addReg(op0Reg);
2350 return;
2351 case 3:
2352 case 5:
2353 case 9:
2354 if (Class == cInt) {
Chris Lattner47712882004-07-19 23:50:57 +00002355 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, DestReg),
Chris Lattner9eb9b8e2004-05-04 15:47:14 +00002356 op0Reg, ConstRHS-1, op0Reg, 0);
2357 return;
2358 }
Chris Lattner596b97f2004-07-19 23:47:21 +00002359 case -3:
2360 case -5:
2361 case -9:
2362 if (Class == cInt) {
2363 TmpReg = makeAnotherReg(DestTy);
2364 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TmpReg),
2365 op0Reg, -ConstRHS-1, op0Reg, 0);
2366 BuildMI(*MBB, IP, NEGrTab[Class], 1, DestReg).addReg(TmpReg);
2367 return;
2368 }
Chris Lattner6ab06d52004-04-06 04:55:43 +00002369 }
2370
Chris Lattnerb2acc512003-10-19 21:09:10 +00002371 // If the element size is exactly a power of 2, use a shift to get it.
2372 if (unsigned Shift = ExactLog2(ConstRHS)) {
2373 switch (Class) {
2374 default: assert(0 && "Unknown class for this function!");
2375 case cByte:
Chris Lattner596b97f2004-07-19 23:47:21 +00002376 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002377 return;
2378 case cShort:
Chris Lattner596b97f2004-07-19 23:47:21 +00002379 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002380 return;
2381 case cInt:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002382 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(op0Reg).addImm(Shift-1);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002383 return;
2384 }
2385 }
Chris Lattner596b97f2004-07-19 23:47:21 +00002386
2387 // If the element size is a negative power of 2, use a shift/neg to get it.
2388 if (unsigned Shift = ExactLog2(-ConstRHS)) {
2389 TmpReg = makeAnotherReg(DestTy);
2390 BuildMI(*MBB, IP, NEGrTab[Class], 1, TmpReg).addReg(op0Reg);
2391 switch (Class) {
2392 default: assert(0 && "Unknown class for this function!");
2393 case cByte:
2394 BuildMI(*MBB, IP, X86::SHL8ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2395 return;
2396 case cShort:
2397 BuildMI(*MBB, IP, X86::SHL16ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2398 return;
2399 case cInt:
2400 BuildMI(*MBB, IP, X86::SHL32ri,2, DestReg).addReg(TmpReg).addImm(Shift-1);
2401 return;
2402 }
2403 }
Chris Lattnerc01d1232003-10-20 03:42:58 +00002404
2405 if (Class == cShort) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002406 BuildMI(*MBB, IP, X86::IMUL16rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
Chris Lattnerc01d1232003-10-20 03:42:58 +00002407 return;
2408 } else if (Class == cInt) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002409 BuildMI(*MBB, IP, X86::IMUL32rri,2,DestReg).addReg(op0Reg).addImm(ConstRHS);
Chris Lattnerc01d1232003-10-20 03:42:58 +00002410 return;
2411 }
Chris Lattnerb2acc512003-10-19 21:09:10 +00002412
2413 // Most general case, emit a normal multiply...
Chris Lattner596b97f2004-07-19 23:47:21 +00002414 TmpReg = makeAnotherReg(DestTy);
Chris Lattneree352852004-02-29 07:22:16 +00002415 BuildMI(*MBB, IP, MOVriTab[Class], 1, TmpReg).addImm(ConstRHS);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002416
2417 // Emit a MUL to multiply the register holding the index by
2418 // elementSize, putting the result in OffsetReg.
2419 doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
2420}
2421
Chris Lattnerca9671d2002-11-02 20:28:58 +00002422/// visitMul - Multiplies are not simple binary operators because they must deal
2423/// with the EAX register explicitly.
2424///
2425void ISel::visitMul(BinaryOperator &I) {
Chris Lattner462fa822004-04-11 20:56:28 +00002426 unsigned ResultReg = getReg(I);
2427
Chris Lattner95157f72004-04-11 22:05:45 +00002428 Value *Op0 = I.getOperand(0);
2429 Value *Op1 = I.getOperand(1);
2430
2431 // Fold loads into floating point multiplies.
2432 if (getClass(Op0->getType()) == cFP) {
2433 if (isa<LoadInst>(Op0) && !isa<LoadInst>(Op1))
2434 if (!I.swapOperands())
2435 std::swap(Op0, Op1); // Make sure any loads are in the RHS.
2436 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2437 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2438 const Type *Ty = Op0->getType();
2439 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2440 unsigned Opcode = Ty == Type::FloatTy ? X86::FMUL32m : X86::FMUL64m;
2441
Chris Lattner95157f72004-04-11 22:05:45 +00002442 unsigned Op0r = getReg(Op0);
Chris Lattner9f1b5312004-05-13 15:12:43 +00002443 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2444 unsigned FI = getFixedSizedAllocaFI(AI);
2445 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2446 } else {
2447 unsigned BaseReg, Scale, IndexReg, Disp;
2448 getAddressingMode(LI->getOperand(0), BaseReg,
2449 Scale, IndexReg, Disp);
2450
2451 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
2452 BaseReg, Scale, IndexReg, Disp);
2453 }
Chris Lattner95157f72004-04-11 22:05:45 +00002454 return;
2455 }
2456 }
2457
Chris Lattner462fa822004-04-11 20:56:28 +00002458 MachineBasicBlock::iterator IP = BB->end();
Chris Lattner95157f72004-04-11 22:05:45 +00002459 emitMultiply(BB, IP, Op0, Op1, ResultReg);
Chris Lattner462fa822004-04-11 20:56:28 +00002460}
2461
2462void ISel::emitMultiply(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
2463 Value *Op0, Value *Op1, unsigned DestReg) {
2464 MachineBasicBlock &BB = *MBB;
2465 TypeClass Class = getClass(Op0->getType());
Chris Lattner3e130a22003-01-13 00:32:26 +00002466
2467 // Simple scalar multiply?
Chris Lattner8ebf1c32004-04-11 21:09:14 +00002468 unsigned Op0Reg = getReg(Op0, &BB, IP);
Chris Lattner462fa822004-04-11 20:56:28 +00002469 switch (Class) {
2470 case cByte:
2471 case cShort:
2472 case cInt:
2473 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
Chris Lattner462fa822004-04-11 20:56:28 +00002474 unsigned Val = (unsigned)CI->getRawValue(); // Isn't a 64-bit constant
2475 doMultiplyConst(&BB, IP, DestReg, Op0->getType(), Op0Reg, Val);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002476 } else {
Chris Lattner462fa822004-04-11 20:56:28 +00002477 unsigned Op1Reg = getReg(Op1, &BB, IP);
2478 doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
Chris Lattnerb2acc512003-10-19 21:09:10 +00002479 }
Chris Lattner462fa822004-04-11 20:56:28 +00002480 return;
2481 case cFP:
Chris Lattner6621ed92004-04-11 21:23:56 +00002482 emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
2483 return;
Chris Lattner462fa822004-04-11 20:56:28 +00002484 case cLong:
2485 break;
2486 }
Chris Lattner3e130a22003-01-13 00:32:26 +00002487
Chris Lattner462fa822004-04-11 20:56:28 +00002488 // Long value. We have to do things the hard way...
2489 if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
2490 unsigned CLow = CI->getRawValue();
2491 unsigned CHi = CI->getRawValue() >> 32;
2492
2493 if (CLow == 0) {
2494 // If the low part of the constant is all zeros, things are simple.
2495 BuildMI(BB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
2496 doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
2497 return;
2498 }
2499
2500 // Multiply the two low parts... capturing carry into EDX
2501 unsigned OverflowReg = 0;
2502 if (CLow == 1) {
2503 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0Reg);
Chris Lattner028adc42004-04-06 04:29:36 +00002504 } else {
Chris Lattner462fa822004-04-11 20:56:28 +00002505 unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
2506 OverflowReg = makeAnotherReg(Type::UIntTy);
2507 BuildMI(BB, IP, X86::MOV32ri, 1, Op1RegL).addImm(CLow);
2508 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2509 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1RegL); // AL*BL
Chris Lattner028adc42004-04-06 04:29:36 +00002510
Chris Lattner462fa822004-04-11 20:56:28 +00002511 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2512 BuildMI(BB, IP, X86::MOV32rr, 1,
2513 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2514 }
2515
2516 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2517 doMultiplyConst(&BB, IP, AHBLReg, Type::UIntTy, Op0Reg+1, CLow);
2518
2519 unsigned AHBLplusOverflowReg;
2520 if (OverflowReg) {
2521 AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2522 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
Chris Lattner028adc42004-04-06 04:29:36 +00002523 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
Chris Lattner462fa822004-04-11 20:56:28 +00002524 } else {
2525 AHBLplusOverflowReg = AHBLReg;
2526 }
2527
2528 if (CHi == 0) {
2529 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(AHBLplusOverflowReg);
2530 } else {
Chris Lattner028adc42004-04-06 04:29:36 +00002531 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
Chris Lattner462fa822004-04-11 20:56:28 +00002532 doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
Chris Lattner028adc42004-04-06 04:29:36 +00002533
Chris Lattner462fa822004-04-11 20:56:28 +00002534 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
Chris Lattner028adc42004-04-06 04:29:36 +00002535 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
2536 }
Chris Lattner462fa822004-04-11 20:56:28 +00002537 return;
Chris Lattner3e130a22003-01-13 00:32:26 +00002538 }
Chris Lattner462fa822004-04-11 20:56:28 +00002539
2540 // General 64x64 multiply
2541
2542 unsigned Op1Reg = getReg(Op1, &BB, IP);
2543 // Multiply the two low parts... capturing carry into EDX
2544 BuildMI(BB, IP, X86::MOV32rr, 1, X86::EAX).addReg(Op0Reg);
2545 BuildMI(BB, IP, X86::MUL32r, 1).addReg(Op1Reg); // AL*BL
2546
2547 unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
2548 BuildMI(BB, IP, X86::MOV32rr, 1, DestReg).addReg(X86::EAX); // AL*BL
2549 BuildMI(BB, IP, X86::MOV32rr, 1,
2550 OverflowReg).addReg(X86::EDX); // AL*BL >> 32
2551
2552 unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
2553 BuildMI(BB, IP, X86::IMUL32rr, 2,
2554 AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
2555
2556 unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
2557 BuildMI(BB, IP, X86::ADD32rr, 2, // AH*BL+(AL*BL >> 32)
2558 AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
2559
2560 unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
2561 BuildMI(BB, IP, X86::IMUL32rr, 2,
2562 ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
2563
2564 BuildMI(BB, IP, X86::ADD32rr, 2, // AL*BH + AH*BL + (AL*BL >> 32)
2565 DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
Chris Lattnerf01729e2002-11-02 20:54:46 +00002566}
Chris Lattnerca9671d2002-11-02 20:28:58 +00002567
Chris Lattner06925362002-11-17 21:56:38 +00002568
Chris Lattnerf01729e2002-11-02 20:54:46 +00002569/// visitDivRem - Handle division and remainder instructions... these
2570/// instruction both require the same instructions to be generated, they just
2571/// select the result from a different register. Note that both of these
2572/// instructions work differently for signed and unsigned operands.
2573///
2574void ISel::visitDivRem(BinaryOperator &I) {
Chris Lattnercadff442003-10-23 17:21:43 +00002575 unsigned ResultReg = getReg(I);
Chris Lattner95157f72004-04-11 22:05:45 +00002576 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
2577
2578 // Fold loads into floating point divides.
2579 if (getClass(Op0->getType()) == cFP) {
2580 if (LoadInst *LI = dyn_cast<LoadInst>(Op1))
2581 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2582 const Type *Ty = Op0->getType();
2583 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2584 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIV32m : X86::FDIV64m;
2585
Chris Lattner95157f72004-04-11 22:05:45 +00002586 unsigned Op0r = getReg(Op0);
Chris Lattner9f1b5312004-05-13 15:12:43 +00002587 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2588 unsigned FI = getFixedSizedAllocaFI(AI);
2589 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r), FI);
2590 } else {
2591 unsigned BaseReg, Scale, IndexReg, Disp;
2592 getAddressingMode(LI->getOperand(0), BaseReg,
2593 Scale, IndexReg, Disp);
2594
2595 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op0r),
2596 BaseReg, Scale, IndexReg, Disp);
2597 }
Chris Lattner95157f72004-04-11 22:05:45 +00002598 return;
2599 }
2600
2601 if (LoadInst *LI = dyn_cast<LoadInst>(Op0))
2602 if (isSafeToFoldLoadIntoInstruction(*LI, I)) {
2603 const Type *Ty = Op0->getType();
2604 assert(Ty == Type::FloatTy||Ty == Type::DoubleTy && "Unknown FP type!");
2605 unsigned Opcode = Ty == Type::FloatTy ? X86::FDIVR32m : X86::FDIVR64m;
2606
Chris Lattner95157f72004-04-11 22:05:45 +00002607 unsigned Op1r = getReg(Op1);
Chris Lattner9f1b5312004-05-13 15:12:43 +00002608 if (AllocaInst *AI = dyn_castFixedAlloca(LI->getOperand(0))) {
2609 unsigned FI = getFixedSizedAllocaFI(AI);
2610 addFrameReference(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r), FI);
2611 } else {
2612 unsigned BaseReg, Scale, IndexReg, Disp;
2613 getAddressingMode(LI->getOperand(0), BaseReg, Scale, IndexReg, Disp);
2614 addFullAddress(BuildMI(BB, Opcode, 5, ResultReg).addReg(Op1r),
2615 BaseReg, Scale, IndexReg, Disp);
2616 }
Chris Lattner95157f72004-04-11 22:05:45 +00002617 return;
2618 }
2619 }
2620
Chris Lattner94af4142002-12-25 05:13:53 +00002621
Chris Lattnercadff442003-10-23 17:21:43 +00002622 MachineBasicBlock::iterator IP = BB->end();
Chris Lattner95157f72004-04-11 22:05:45 +00002623 emitDivRemOperation(BB, IP, Op0, Op1,
Chris Lattner462fa822004-04-11 20:56:28 +00002624 I.getOpcode() == Instruction::Div, ResultReg);
Chris Lattnercadff442003-10-23 17:21:43 +00002625}
2626
2627void ISel::emitDivRemOperation(MachineBasicBlock *BB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00002628 MachineBasicBlock::iterator IP,
Chris Lattner462fa822004-04-11 20:56:28 +00002629 Value *Op0, Value *Op1, bool isDiv,
2630 unsigned ResultReg) {
Chris Lattner8ebf1c32004-04-11 21:09:14 +00002631 const Type *Ty = Op0->getType();
2632 unsigned Class = getClass(Ty);
Chris Lattner94af4142002-12-25 05:13:53 +00002633 switch (Class) {
Chris Lattner3e130a22003-01-13 00:32:26 +00002634 case cFP: // Floating point divide
Chris Lattnercadff442003-10-23 17:21:43 +00002635 if (isDiv) {
Chris Lattner6621ed92004-04-11 21:23:56 +00002636 emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
2637 return;
Chris Lattner5e2cb8b2003-08-04 02:12:48 +00002638 } else { // Floating point remainder...
Chris Lattner462fa822004-04-11 20:56:28 +00002639 unsigned Op0Reg = getReg(Op0, BB, IP);
2640 unsigned Op1Reg = getReg(Op1, BB, IP);
Chris Lattner3e130a22003-01-13 00:32:26 +00002641 MachineInstr *TheCall =
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002642 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true);
Chris Lattner3e130a22003-01-13 00:32:26 +00002643 std::vector<ValueRecord> Args;
Chris Lattnercadff442003-10-23 17:21:43 +00002644 Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
2645 Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
Chris Lattner3e130a22003-01-13 00:32:26 +00002646 doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
2647 }
Chris Lattner94af4142002-12-25 05:13:53 +00002648 return;
Chris Lattner3e130a22003-01-13 00:32:26 +00002649 case cLong: {
2650 static const char *FnName[] =
2651 { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
Chris Lattner462fa822004-04-11 20:56:28 +00002652 unsigned Op0Reg = getReg(Op0, BB, IP);
2653 unsigned Op1Reg = getReg(Op1, BB, IP);
Chris Lattner8ebf1c32004-04-11 21:09:14 +00002654 unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
Chris Lattner3e130a22003-01-13 00:32:26 +00002655 MachineInstr *TheCall =
2656 BuildMI(X86::CALLpcrel32, 1).addExternalSymbol(FnName[NameIdx], true);
2657
2658 std::vector<ValueRecord> Args;
Chris Lattnercadff442003-10-23 17:21:43 +00002659 Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
2660 Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
Chris Lattner3e130a22003-01-13 00:32:26 +00002661 doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
2662 return;
2663 }
2664 case cByte: case cShort: case cInt:
Misha Brukmancf00c4a2003-10-10 17:57:28 +00002665 break; // Small integrals, handled below...
Chris Lattner3e130a22003-01-13 00:32:26 +00002666 default: assert(0 && "Unknown class!");
Chris Lattner94af4142002-12-25 05:13:53 +00002667 }
Chris Lattnerf01729e2002-11-02 20:54:46 +00002668
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002669 static const unsigned MovOpcode[]={ X86::MOV8rr, X86::MOV16rr, X86::MOV32rr };
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002670 static const unsigned NEGOpcode[] = { X86::NEG8r, X86::NEG16r, X86::NEG32r };
2671 static const unsigned SAROpcode[]={ X86::SAR8ri, X86::SAR16ri, X86::SAR32ri };
2672 static const unsigned SHROpcode[]={ X86::SHR8ri, X86::SHR16ri, X86::SHR32ri };
2673 static const unsigned ADDOpcode[]={ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr };
2674
2675 // Special case signed division by power of 2.
2676 if (isDiv)
2677 if (ConstantSInt *CI = dyn_cast<ConstantSInt>(Op1)) {
2678 assert(Class != cLong && "This doesn't handle 64-bit divides!");
2679 int V = CI->getValue();
2680
2681 if (V == 1) { // X /s 1 => X
2682 unsigned Op0Reg = getReg(Op0, BB, IP);
2683 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2684 return;
2685 }
2686
2687 if (V == -1) { // X /s -1 => -X
2688 unsigned Op0Reg = getReg(Op0, BB, IP);
2689 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(Op0Reg);
2690 return;
2691 }
2692
2693 bool isNeg = false;
2694 if (V < 0) { // Not a positive power of 2?
2695 V = -V;
2696 isNeg = true; // Maybe it's a negative power of 2.
2697 }
2698 if (unsigned Log = ExactLog2(V)) {
2699 --Log;
2700 unsigned Op0Reg = getReg(Op0, BB, IP);
2701 unsigned TmpReg = makeAnotherReg(Op0->getType());
2702 if (Log != 1)
2703 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg)
2704 .addReg(Op0Reg).addImm(Log-1);
2705 else
2706 BuildMI(*BB, IP, MovOpcode[Class], 1, TmpReg).addReg(Op0Reg);
2707 unsigned TmpReg2 = makeAnotherReg(Op0->getType());
2708 BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
2709 .addReg(TmpReg).addImm(32-Log);
2710 unsigned TmpReg3 = makeAnotherReg(Op0->getType());
2711 BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
2712 .addReg(Op0Reg).addReg(TmpReg2);
2713
2714 unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
2715 BuildMI(*BB, IP, SAROpcode[Class], 2, TmpReg4)
2716 .addReg(Op0Reg).addImm(Log);
2717 if (isNeg)
2718 BuildMI(*BB, IP, NEGOpcode[Class], 1, ResultReg).addReg(TmpReg4);
2719 return;
2720 }
2721 }
2722
2723 static const unsigned Regs[] ={ X86::AL , X86::AX , X86::EAX };
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002724 static const unsigned ClrOpcode[]={ X86::MOV8ri, X86::MOV16ri, X86::MOV32ri };
Chris Lattnerf01729e2002-11-02 20:54:46 +00002725 static const unsigned ExtRegs[] ={ X86::AH , X86::DX , X86::EDX };
2726
2727 static const unsigned DivOpcode[][4] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002728 { X86::DIV8r , X86::DIV16r , X86::DIV32r , 0 }, // Unsigned division
2729 { X86::IDIV8r, X86::IDIV16r, X86::IDIV32r, 0 }, // Signed division
Chris Lattnerf01729e2002-11-02 20:54:46 +00002730 };
2731
Chris Lattnerf01729e2002-11-02 20:54:46 +00002732 unsigned Reg = Regs[Class];
2733 unsigned ExtReg = ExtRegs[Class];
Chris Lattnerf01729e2002-11-02 20:54:46 +00002734
2735 // Put the first operand into one of the A registers...
Chris Lattner462fa822004-04-11 20:56:28 +00002736 unsigned Op0Reg = getReg(Op0, BB, IP);
2737 unsigned Op1Reg = getReg(Op1, BB, IP);
Chris Lattneree352852004-02-29 07:22:16 +00002738 BuildMI(*BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg);
Chris Lattnerf01729e2002-11-02 20:54:46 +00002739
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002740 if (Ty->isSigned()) {
Chris Lattnerf01729e2002-11-02 20:54:46 +00002741 // Emit a sign extension instruction...
Chris Lattner462fa822004-04-11 20:56:28 +00002742 unsigned ShiftResult = makeAnotherReg(Op0->getType());
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002743 BuildMI(*BB, IP, SAROpcode[Class], 2,ShiftResult).addReg(Op0Reg).addImm(31);
Chris Lattneree352852004-02-29 07:22:16 +00002744 BuildMI(*BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult);
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002745
2746 // Emit the appropriate divide or remainder instruction...
2747 BuildMI(*BB, IP, DivOpcode[1][Class], 1).addReg(Op1Reg);
Chris Lattnerf01729e2002-11-02 20:54:46 +00002748 } else {
Alkis Evlogimenosf998a7e2004-01-12 07:22:45 +00002749 // If unsigned, emit a zeroing instruction... (reg = 0)
Chris Lattneree352852004-02-29 07:22:16 +00002750 BuildMI(*BB, IP, ClrOpcode[Class], 2, ExtReg).addImm(0);
Chris Lattnerf01729e2002-11-02 20:54:46 +00002751
Chris Lattnerc8af02c2004-05-04 19:33:58 +00002752 // Emit the appropriate divide or remainder instruction...
2753 BuildMI(*BB, IP, DivOpcode[0][Class], 1).addReg(Op1Reg);
2754 }
Chris Lattner06925362002-11-17 21:56:38 +00002755
Chris Lattnerf01729e2002-11-02 20:54:46 +00002756 // Figure out which register we want to pick the result out of...
Chris Lattnercadff442003-10-23 17:21:43 +00002757 unsigned DestReg = isDiv ? Reg : ExtReg;
Chris Lattnerf01729e2002-11-02 20:54:46 +00002758
Chris Lattnerf01729e2002-11-02 20:54:46 +00002759 // Put the result into the destination register...
Chris Lattneree352852004-02-29 07:22:16 +00002760 BuildMI(*BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg);
Chris Lattnerca9671d2002-11-02 20:28:58 +00002761}
Chris Lattnere2954c82002-11-02 20:04:26 +00002762
Chris Lattner06925362002-11-17 21:56:38 +00002763
Brian Gaekea1719c92002-10-31 23:03:59 +00002764/// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
2765/// for constant immediate shift values, and for constant immediate
2766/// shift values equal to 1. Even the general case is sort of special,
2767/// because the shift amount has to be in CL, not just any old register.
2768///
Chris Lattner3e130a22003-01-13 00:32:26 +00002769void ISel::visitShiftInst(ShiftInst &I) {
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002770 MachineBasicBlock::iterator IP = BB->end ();
2771 emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
2772 I.getOpcode () == Instruction::Shl, I.getType (),
2773 getReg (I));
2774}
2775
2776/// emitShiftOperation - Common code shared between visitShiftInst and
2777/// constant expression support.
2778void ISel::emitShiftOperation(MachineBasicBlock *MBB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00002779 MachineBasicBlock::iterator IP,
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002780 Value *Op, Value *ShiftAmount, bool isLeftShift,
2781 const Type *ResultTy, unsigned DestReg) {
2782 unsigned SrcReg = getReg (Op, MBB, IP);
2783 bool isSigned = ResultTy->isSigned ();
2784 unsigned Class = getClass (ResultTy);
Chris Lattner3e130a22003-01-13 00:32:26 +00002785
2786 static const unsigned ConstantOperand[][4] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002787 { X86::SHR8ri, X86::SHR16ri, X86::SHR32ri, X86::SHRD32rri8 }, // SHR
2788 { X86::SAR8ri, X86::SAR16ri, X86::SAR32ri, X86::SHRD32rri8 }, // SAR
2789 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SHL
2790 { X86::SHL8ri, X86::SHL16ri, X86::SHL32ri, X86::SHLD32rri8 }, // SAL = SHL
Chris Lattner3e130a22003-01-13 00:32:26 +00002791 };
Chris Lattnerb1761fc2002-11-02 01:15:18 +00002792
Chris Lattner3e130a22003-01-13 00:32:26 +00002793 static const unsigned NonConstantOperand[][4] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002794 { X86::SHR8rCL, X86::SHR16rCL, X86::SHR32rCL }, // SHR
2795 { X86::SAR8rCL, X86::SAR16rCL, X86::SAR32rCL }, // SAR
2796 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SHL
2797 { X86::SHL8rCL, X86::SHL16rCL, X86::SHL32rCL }, // SAL = SHL
Chris Lattner3e130a22003-01-13 00:32:26 +00002798 };
Chris Lattner796df732002-11-02 00:44:25 +00002799
Chris Lattner3e130a22003-01-13 00:32:26 +00002800 // Longs, as usual, are handled specially...
2801 if (Class == cLong) {
2802 // If we have a constant shift, we can generate much more efficient code
2803 // than otherwise...
2804 //
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002805 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
Chris Lattner3e130a22003-01-13 00:32:26 +00002806 unsigned Amount = CUI->getValue();
2807 if (Amount < 32) {
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002808 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
2809 if (isLeftShift) {
Chris Lattneree352852004-02-29 07:22:16 +00002810 BuildMI(*MBB, IP, Opc[3], 3,
2811 DestReg+1).addReg(SrcReg+1).addReg(SrcReg).addImm(Amount);
2812 BuildMI(*MBB, IP, Opc[2], 2, DestReg).addReg(SrcReg).addImm(Amount);
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002813 } else {
Chris Lattneree352852004-02-29 07:22:16 +00002814 BuildMI(*MBB, IP, Opc[3], 3,
2815 DestReg).addReg(SrcReg ).addReg(SrcReg+1).addImm(Amount);
2816 BuildMI(*MBB, IP, Opc[2],2,DestReg+1).addReg(SrcReg+1).addImm(Amount);
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002817 }
Chris Lattner3e130a22003-01-13 00:32:26 +00002818 } else { // Shifting more than 32 bits
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002819 Amount -= 32;
2820 if (isLeftShift) {
Chris Lattner722070e2004-04-06 03:42:38 +00002821 if (Amount != 0) {
2822 BuildMI(*MBB, IP, X86::SHL32ri, 2,
2823 DestReg + 1).addReg(SrcReg).addImm(Amount);
2824 } else {
2825 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg);
2826 }
2827 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002828 } else {
Chris Lattner722070e2004-04-06 03:42:38 +00002829 if (Amount != 0) {
2830 BuildMI(*MBB, IP, isSigned ? X86::SAR32ri : X86::SHR32ri, 2,
2831 DestReg).addReg(SrcReg+1).addImm(Amount);
2832 } else {
2833 BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg+1);
2834 }
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002835 BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
Misha Brukmanc8893fc2003-10-23 16:22:08 +00002836 }
Chris Lattner3e130a22003-01-13 00:32:26 +00002837 }
2838 } else {
Chris Lattner9171ef52003-06-01 01:56:54 +00002839 unsigned TmpReg = makeAnotherReg(Type::IntTy);
2840
2841 if (!isLeftShift && isSigned) {
2842 // If this is a SHR of a Long, then we need to do funny sign extension
2843 // stuff. TmpReg gets the value to use as the high-part if we are
2844 // shifting more than 32 bits.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002845 BuildMI(*MBB, IP, X86::SAR32ri, 2, TmpReg).addReg(SrcReg).addImm(31);
Chris Lattner9171ef52003-06-01 01:56:54 +00002846 } else {
2847 // Other shifts use a fixed zero value if the shift is more than 32
2848 // bits.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002849 BuildMI(*MBB, IP, X86::MOV32ri, 1, TmpReg).addImm(0);
Chris Lattner9171ef52003-06-01 01:56:54 +00002850 }
2851
2852 // Initialize CL with the shift amount...
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002853 unsigned ShiftAmountReg = getReg(ShiftAmount, MBB, IP);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002854 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
Chris Lattner9171ef52003-06-01 01:56:54 +00002855
2856 unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
2857 unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
2858 if (isLeftShift) {
2859 // TmpReg2 = shld inHi, inLo
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002860 BuildMI(*MBB, IP, X86::SHLD32rrCL,2,TmpReg2).addReg(SrcReg+1)
Chris Lattneree352852004-02-29 07:22:16 +00002861 .addReg(SrcReg);
Chris Lattner9171ef52003-06-01 01:56:54 +00002862 // TmpReg3 = shl inLo, CL
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002863 BuildMI(*MBB, IP, X86::SHL32rCL, 1, TmpReg3).addReg(SrcReg);
Chris Lattner9171ef52003-06-01 01:56:54 +00002864
2865 // Set the flags to indicate whether the shift was by more than 32 bits.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002866 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
Chris Lattner9171ef52003-06-01 01:56:54 +00002867
2868 // DestHi = (>32) ? TmpReg3 : TmpReg2;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002869 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
Chris Lattner9171ef52003-06-01 01:56:54 +00002870 DestReg+1).addReg(TmpReg2).addReg(TmpReg3);
2871 // DestLo = (>32) ? TmpReg : TmpReg3;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002872 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002873 DestReg).addReg(TmpReg3).addReg(TmpReg);
Chris Lattner9171ef52003-06-01 01:56:54 +00002874 } else {
2875 // TmpReg2 = shrd inLo, inHi
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002876 BuildMI(*MBB, IP, X86::SHRD32rrCL,2,TmpReg2).addReg(SrcReg)
Chris Lattneree352852004-02-29 07:22:16 +00002877 .addReg(SrcReg+1);
Chris Lattner9171ef52003-06-01 01:56:54 +00002878 // TmpReg3 = s[ah]r inHi, CL
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002879 BuildMI(*MBB, IP, isSigned ? X86::SAR32rCL : X86::SHR32rCL, 1, TmpReg3)
Chris Lattner9171ef52003-06-01 01:56:54 +00002880 .addReg(SrcReg+1);
2881
2882 // Set the flags to indicate whether the shift was by more than 32 bits.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002883 BuildMI(*MBB, IP, X86::TEST8ri, 2).addReg(X86::CL).addImm(32);
Chris Lattner9171ef52003-06-01 01:56:54 +00002884
2885 // DestLo = (>32) ? TmpReg3 : TmpReg2;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002886 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
Chris Lattner9171ef52003-06-01 01:56:54 +00002887 DestReg).addReg(TmpReg2).addReg(TmpReg3);
2888
2889 // DestHi = (>32) ? TmpReg : TmpReg3;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002890 BuildMI(*MBB, IP, X86::CMOVNE32rr, 2,
Chris Lattner9171ef52003-06-01 01:56:54 +00002891 DestReg+1).addReg(TmpReg3).addReg(TmpReg);
2892 }
Brian Gaekea1719c92002-10-31 23:03:59 +00002893 }
Chris Lattner3e130a22003-01-13 00:32:26 +00002894 return;
2895 }
Chris Lattnere9913f22002-11-02 01:41:55 +00002896
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002897 if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) {
Chris Lattner3e130a22003-01-13 00:32:26 +00002898 // The shift amount is constant, guaranteed to be a ubyte. Get its value.
2899 assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
Chris Lattnerb1761fc2002-11-02 01:15:18 +00002900
Chris Lattner3e130a22003-01-13 00:32:26 +00002901 const unsigned *Opc = ConstantOperand[isLeftShift*2+isSigned];
Chris Lattneree352852004-02-29 07:22:16 +00002902 BuildMI(*MBB, IP, Opc[Class], 2,
2903 DestReg).addReg(SrcReg).addImm(CUI->getValue());
Chris Lattner3e130a22003-01-13 00:32:26 +00002904 } else { // The shift amount is non-constant.
Brian Gaekedfcc9cf2003-11-22 06:49:41 +00002905 unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00002906 BuildMI(*MBB, IP, X86::MOV8rr, 1, X86::CL).addReg(ShiftAmountReg);
Chris Lattnerb1761fc2002-11-02 01:15:18 +00002907
Chris Lattner3e130a22003-01-13 00:32:26 +00002908 const unsigned *Opc = NonConstantOperand[isLeftShift*2+isSigned];
Chris Lattneree352852004-02-29 07:22:16 +00002909 BuildMI(*MBB, IP, Opc[Class], 1, DestReg).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00002910 }
2911}
Chris Lattnerb1761fc2002-11-02 01:15:18 +00002912
Chris Lattner3e130a22003-01-13 00:32:26 +00002913
Chris Lattner6fc3c522002-11-17 21:11:55 +00002914/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
Chris Lattnere8f0d922002-12-24 00:03:11 +00002915/// instruction. The load and store instructions are the only place where we
2916/// need to worry about the memory layout of the target machine.
Chris Lattner6fc3c522002-11-17 21:11:55 +00002917///
2918void ISel::visitLoadInst(LoadInst &I) {
Chris Lattner7dee5da2004-03-08 01:58:35 +00002919 // Check to see if this load instruction is going to be folded into a binary
2920 // instruction, like add. If so, we don't want to emit it. Wouldn't a real
2921 // pattern matching instruction selector be nice?
Chris Lattner95157f72004-04-11 22:05:45 +00002922 unsigned Class = getClassB(I.getType());
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002923 if (I.hasOneUse()) {
Chris Lattner7dee5da2004-03-08 01:58:35 +00002924 Instruction *User = cast<Instruction>(I.use_back());
2925 switch (User->getOpcode()) {
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002926 case Instruction::Cast:
2927 // If this is a cast from a signed-integer type to a floating point type,
2928 // fold the cast here.
John Criswell6b5bd582004-06-09 15:18:51 +00002929 if (getClassB(User->getType()) == cFP &&
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002930 (I.getType() == Type::ShortTy || I.getType() == Type::IntTy ||
2931 I.getType() == Type::LongTy)) {
2932 unsigned DestReg = getReg(User);
2933 static const unsigned Opcode[] = {
2934 0/*BYTE*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m
2935 };
Chris Lattner9f1b5312004-05-13 15:12:43 +00002936
2937 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
2938 unsigned FI = getFixedSizedAllocaFI(AI);
2939 addFrameReference(BuildMI(BB, Opcode[Class], 4, DestReg), FI);
2940 } else {
2941 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
2942 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
2943 addFullAddress(BuildMI(BB, Opcode[Class], 4, DestReg),
2944 BaseReg, Scale, IndexReg, Disp);
2945 }
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002946 return;
2947 } else {
2948 User = 0;
2949 }
2950 break;
Chris Lattner13c07fe2004-04-12 00:12:04 +00002951
Chris Lattner7dee5da2004-03-08 01:58:35 +00002952 case Instruction::Add:
2953 case Instruction::Sub:
2954 case Instruction::And:
2955 case Instruction::Or:
2956 case Instruction::Xor:
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002957 if (Class == cLong) User = 0;
Chris Lattner7dee5da2004-03-08 01:58:35 +00002958 break;
Chris Lattner95157f72004-04-11 22:05:45 +00002959 case Instruction::Mul:
2960 case Instruction::Div:
Chris Lattner13c07fe2004-04-12 00:12:04 +00002961 if (Class != cFP) User = 0;
Chris Lattnerfeac3e12004-04-11 23:21:26 +00002962 break; // Folding only implemented for floating point.
Chris Lattner95157f72004-04-11 22:05:45 +00002963 default: User = 0; break;
Chris Lattner7dee5da2004-03-08 01:58:35 +00002964 }
2965
2966 if (User) {
2967 // Okay, we found a user. If the load is the first operand and there is
2968 // no second operand load, reverse the operand ordering. Note that this
2969 // can fail for a subtract (ie, no change will be made).
Chris Lattner3dbb5042004-07-21 21:28:26 +00002970 bool Swapped = false;
Chris Lattner7dee5da2004-03-08 01:58:35 +00002971 if (!isa<LoadInst>(User->getOperand(1)))
Chris Lattner3dbb5042004-07-21 21:28:26 +00002972 Swapped = !cast<BinaryOperator>(User)->swapOperands();
Chris Lattner7dee5da2004-03-08 01:58:35 +00002973
2974 // Okay, now that everything is set up, if this load is used by the second
2975 // operand, and if there are no instructions that invalidate the load
2976 // before the binary operator, eliminate the load.
2977 if (User->getOperand(1) == &I &&
2978 isSafeToFoldLoadIntoInstruction(I, *User))
2979 return; // Eliminate the load!
Chris Lattner95157f72004-04-11 22:05:45 +00002980
2981 // If this is a floating point sub or div, we won't be able to swap the
2982 // operands, but we will still be able to eliminate the load.
2983 if (Class == cFP && User->getOperand(0) == &I &&
2984 !isa<LoadInst>(User->getOperand(1)) &&
2985 (User->getOpcode() == Instruction::Sub ||
2986 User->getOpcode() == Instruction::Div) &&
2987 isSafeToFoldLoadIntoInstruction(I, *User))
2988 return; // Eliminate the load!
Chris Lattner3dbb5042004-07-21 21:28:26 +00002989
2990 // If we swapped the operands to the instruction, but couldn't fold the
2991 // load anyway, swap them back. We don't want to break add X, int
2992 // folding.
2993 if (Swapped) cast<BinaryOperator>(User)->swapOperands();
Chris Lattner7dee5da2004-03-08 01:58:35 +00002994 }
2995 }
2996
Chris Lattner6ac1d712003-10-20 04:48:06 +00002997 static const unsigned Opcodes[] = {
Chris Lattner9f1b5312004-05-13 15:12:43 +00002998 X86::MOV8rm, X86::MOV16rm, X86::MOV32rm, X86::FLD32m, X86::MOV32rm
Chris Lattner3e130a22003-01-13 00:32:26 +00002999 };
Chris Lattner6ac1d712003-10-20 04:48:06 +00003000 unsigned Opcode = Opcodes[Class];
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003001 if (I.getType() == Type::DoubleTy) Opcode = X86::FLD64m;
Chris Lattner9f1b5312004-05-13 15:12:43 +00003002
3003 unsigned DestReg = getReg(I);
3004
3005 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
3006 unsigned FI = getFixedSizedAllocaFI(AI);
3007 if (Class == cLong) {
3008 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg), FI);
3009 addFrameReference(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), FI, 4);
3010 } else {
3011 addFrameReference(BuildMI(BB, Opcode, 4, DestReg), FI);
3012 }
3013 } else {
3014 unsigned BaseReg = 0, Scale = 1, IndexReg = 0, Disp = 0;
3015 getAddressingMode(I.getOperand(0), BaseReg, Scale, IndexReg, Disp);
3016
3017 if (Class == cLong) {
3018 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg),
3019 BaseReg, Scale, IndexReg, Disp);
3020 addFullAddress(BuildMI(BB, X86::MOV32rm, 4, DestReg+1),
3021 BaseReg, Scale, IndexReg, Disp+4);
3022 } else {
3023 addFullAddress(BuildMI(BB, Opcode, 4, DestReg),
3024 BaseReg, Scale, IndexReg, Disp);
3025 }
3026 }
Chris Lattner3e130a22003-01-13 00:32:26 +00003027}
3028
Chris Lattner6fc3c522002-11-17 21:11:55 +00003029/// visitStoreInst - Implement LLVM store instructions in terms of the x86 'mov'
3030/// instruction.
3031///
3032void ISel::visitStoreInst(StoreInst &I) {
Chris Lattner9f1b5312004-05-13 15:12:43 +00003033 unsigned BaseReg = ~0U, Scale = ~0U, IndexReg = ~0U, Disp = ~0U;
3034 unsigned AllocaFrameIdx = ~0U;
3035
3036 if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(1)))
3037 AllocaFrameIdx = getFixedSizedAllocaFI(AI);
3038 else
3039 getAddressingMode(I.getOperand(1), BaseReg, Scale, IndexReg, Disp);
Chris Lattnerb6bac512004-02-25 06:13:04 +00003040
Chris Lattner6c09db22003-10-20 04:11:23 +00003041 const Type *ValTy = I.getOperand(0)->getType();
3042 unsigned Class = getClassB(ValTy);
Chris Lattner6ac1d712003-10-20 04:48:06 +00003043
Chris Lattner5a830962004-02-25 02:56:58 +00003044 if (ConstantInt *CI = dyn_cast<ConstantInt>(I.getOperand(0))) {
3045 uint64_t Val = CI->getRawValue();
3046 if (Class == cLong) {
Chris Lattner9f1b5312004-05-13 15:12:43 +00003047 if (AllocaFrameIdx != ~0U) {
3048 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3049 AllocaFrameIdx).addImm(Val & ~0U);
3050 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3051 AllocaFrameIdx, 4).addImm(Val>>32);
3052 } else {
3053 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3054 BaseReg, Scale, IndexReg, Disp).addImm(Val & ~0U);
3055 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3056 BaseReg, Scale, IndexReg, Disp+4).addImm(Val>>32);
3057 }
Chris Lattner5a830962004-02-25 02:56:58 +00003058 } else {
3059 static const unsigned Opcodes[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003060 X86::MOV8mi, X86::MOV16mi, X86::MOV32mi
Chris Lattner5a830962004-02-25 02:56:58 +00003061 };
3062 unsigned Opcode = Opcodes[Class];
Chris Lattnerb7cb9ff2004-05-13 15:26:48 +00003063 if (AllocaFrameIdx != ~0U)
Chris Lattner9f1b5312004-05-13 15:12:43 +00003064 addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addImm(Val);
Chris Lattnerb7cb9ff2004-05-13 15:26:48 +00003065 else
Chris Lattner9f1b5312004-05-13 15:12:43 +00003066 addFullAddress(BuildMI(BB, Opcode, 5),
3067 BaseReg, Scale, IndexReg, Disp).addImm(Val);
Chris Lattner5a830962004-02-25 02:56:58 +00003068 }
Chris Lattnerb7cb9ff2004-05-13 15:26:48 +00003069 } else if (isa<ConstantPointerNull>(I.getOperand(0))) {
3070 if (AllocaFrameIdx != ~0U)
3071 addFrameReference(BuildMI(BB, X86::MOV32mi, 5), AllocaFrameIdx).addImm(0);
3072 else
3073 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3074 BaseReg, Scale, IndexReg, Disp).addImm(0);
3075
Chris Lattner5a830962004-02-25 02:56:58 +00003076 } else if (ConstantBool *CB = dyn_cast<ConstantBool>(I.getOperand(0))) {
Chris Lattner9f1b5312004-05-13 15:12:43 +00003077 if (AllocaFrameIdx != ~0U)
3078 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
3079 AllocaFrameIdx).addImm(CB->getValue());
3080 else
3081 addFullAddress(BuildMI(BB, X86::MOV8mi, 5),
3082 BaseReg, Scale, IndexReg, Disp).addImm(CB->getValue());
Chris Lattnere7a31c92004-05-07 21:18:15 +00003083 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) {
3084 // Store constant FP values with integer instructions to avoid having to
3085 // load the constants from the constant pool then do a store.
3086 if (CFP->getType() == Type::FloatTy) {
3087 union {
3088 unsigned I;
3089 float F;
3090 } V;
3091 V.F = CFP->getValue();
Chris Lattner9f1b5312004-05-13 15:12:43 +00003092 if (AllocaFrameIdx != ~0U)
3093 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3094 AllocaFrameIdx).addImm(V.I);
3095 else
3096 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3097 BaseReg, Scale, IndexReg, Disp).addImm(V.I);
Chris Lattner5a830962004-02-25 02:56:58 +00003098 } else {
Chris Lattnere7a31c92004-05-07 21:18:15 +00003099 union {
3100 uint64_t I;
3101 double F;
3102 } V;
3103 V.F = CFP->getValue();
Chris Lattner9f1b5312004-05-13 15:12:43 +00003104 if (AllocaFrameIdx != ~0U) {
3105 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3106 AllocaFrameIdx).addImm((unsigned)V.I);
3107 addFrameReference(BuildMI(BB, X86::MOV32mi, 5),
3108 AllocaFrameIdx, 4).addImm(unsigned(V.I >> 32));
3109 } else {
3110 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3111 BaseReg, Scale, IndexReg, Disp).addImm((unsigned)V.I);
3112 addFullAddress(BuildMI(BB, X86::MOV32mi, 5),
3113 BaseReg, Scale, IndexReg, Disp+4).addImm(
Chris Lattnere7a31c92004-05-07 21:18:15 +00003114 unsigned(V.I >> 32));
Chris Lattner9f1b5312004-05-13 15:12:43 +00003115 }
Chris Lattner5a830962004-02-25 02:56:58 +00003116 }
Chris Lattnere7a31c92004-05-07 21:18:15 +00003117
3118 } else if (Class == cLong) {
3119 unsigned ValReg = getReg(I.getOperand(0));
Chris Lattner9f1b5312004-05-13 15:12:43 +00003120 if (AllocaFrameIdx != ~0U) {
3121 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
3122 AllocaFrameIdx).addReg(ValReg);
3123 addFrameReference(BuildMI(BB, X86::MOV32mr, 5),
3124 AllocaFrameIdx, 4).addReg(ValReg+1);
3125 } else {
3126 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
3127 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
3128 addFullAddress(BuildMI(BB, X86::MOV32mr, 5),
3129 BaseReg, Scale, IndexReg, Disp+4).addReg(ValReg+1);
3130 }
Chris Lattnere7a31c92004-05-07 21:18:15 +00003131 } else {
3132 unsigned ValReg = getReg(I.getOperand(0));
3133 static const unsigned Opcodes[] = {
3134 X86::MOV8mr, X86::MOV16mr, X86::MOV32mr, X86::FST32m
3135 };
3136 unsigned Opcode = Opcodes[Class];
3137 if (ValTy == Type::DoubleTy) Opcode = X86::FST64m;
Chris Lattner9f1b5312004-05-13 15:12:43 +00003138
3139 if (AllocaFrameIdx != ~0U)
3140 addFrameReference(BuildMI(BB, Opcode, 5), AllocaFrameIdx).addReg(ValReg);
3141 else
3142 addFullAddress(BuildMI(BB, Opcode, 1+4),
3143 BaseReg, Scale, IndexReg, Disp).addReg(ValReg);
Chris Lattner94af4142002-12-25 05:13:53 +00003144 }
Chris Lattner6fc3c522002-11-17 21:11:55 +00003145}
3146
3147
Misha Brukman538607f2004-03-01 23:53:11 +00003148/// visitCastInst - Here we have various kinds of copying with or without sign
3149/// extension going on.
3150///
Chris Lattner3e130a22003-01-13 00:32:26 +00003151void ISel::visitCastInst(CastInst &CI) {
Chris Lattnerf5854472003-06-21 16:01:24 +00003152 Value *Op = CI.getOperand(0);
Chris Lattner427aeb42004-04-11 19:21:59 +00003153
Chris Lattner99382862004-04-12 00:23:04 +00003154 unsigned SrcClass = getClassB(Op->getType());
3155 unsigned DestClass = getClassB(CI.getType());
3156 // Noop casts are not emitted: getReg will return the source operand as the
3157 // register to use for any uses of the noop cast.
Chris Lattner8b486a12004-06-29 00:14:38 +00003158 if (DestClass == SrcClass) {
3159 // The only detail in this plan is that casts from double -> float are
3160 // truncating operations that we have to codegen through memory (despite
3161 // the fact that the source/dest registers are the same class).
3162 if (CI.getType() != Type::FloatTy || Op->getType() != Type::DoubleTy)
3163 return;
3164 }
Chris Lattner427aeb42004-04-11 19:21:59 +00003165
Chris Lattnerf5854472003-06-21 16:01:24 +00003166 // If this is a cast from a 32-bit integer to a Long type, and the only uses
3167 // of the case are GEP instructions, then the cast does not need to be
3168 // generated explicitly, it will be folded into the GEP.
Chris Lattner99382862004-04-12 00:23:04 +00003169 if (DestClass == cLong && SrcClass == cInt) {
Chris Lattnerf5854472003-06-21 16:01:24 +00003170 bool AllUsesAreGEPs = true;
3171 for (Value::use_iterator I = CI.use_begin(), E = CI.use_end(); I != E; ++I)
3172 if (!isa<GetElementPtrInst>(*I)) {
3173 AllUsesAreGEPs = false;
3174 break;
3175 }
3176
3177 // No need to codegen this cast if all users are getelementptr instrs...
3178 if (AllUsesAreGEPs) return;
3179 }
3180
Chris Lattner99382862004-04-12 00:23:04 +00003181 // If this cast converts a load from a short,int, or long integer to a FP
3182 // value, we will have folded this cast away.
3183 if (DestClass == cFP && isa<LoadInst>(Op) && Op->hasOneUse() &&
3184 (Op->getType() == Type::ShortTy || Op->getType() == Type::IntTy ||
3185 Op->getType() == Type::LongTy))
3186 return;
3187
3188
Chris Lattner548f61d2003-04-23 17:22:12 +00003189 unsigned DestReg = getReg(CI);
3190 MachineBasicBlock::iterator MI = BB->end();
Chris Lattnerf5854472003-06-21 16:01:24 +00003191 emitCastOperation(BB, MI, Op, CI.getType(), DestReg);
Chris Lattner548f61d2003-04-23 17:22:12 +00003192}
3193
Misha Brukman538607f2004-03-01 23:53:11 +00003194/// emitCastOperation - Common code shared between visitCastInst and constant
3195/// expression cast support.
3196///
Chris Lattner548f61d2003-04-23 17:22:12 +00003197void ISel::emitCastOperation(MachineBasicBlock *BB,
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003198 MachineBasicBlock::iterator IP,
Chris Lattner548f61d2003-04-23 17:22:12 +00003199 Value *Src, const Type *DestTy,
3200 unsigned DestReg) {
Chris Lattner3e130a22003-01-13 00:32:26 +00003201 const Type *SrcTy = Src->getType();
3202 unsigned SrcClass = getClassB(SrcTy);
Chris Lattner3e130a22003-01-13 00:32:26 +00003203 unsigned DestClass = getClassB(DestTy);
Chris Lattnerfeac3e12004-04-11 23:21:26 +00003204 unsigned SrcReg = getReg(Src, BB, IP);
3205
Chris Lattner3e130a22003-01-13 00:32:26 +00003206 // Implement casts to bool by using compare on the operand followed by set if
3207 // not zero on the result.
3208 if (DestTy == Type::BoolTy) {
Chris Lattner20772542003-06-01 03:38:24 +00003209 switch (SrcClass) {
3210 case cByte:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003211 BuildMI(*BB, IP, X86::TEST8rr, 2).addReg(SrcReg).addReg(SrcReg);
Chris Lattner20772542003-06-01 03:38:24 +00003212 break;
3213 case cShort:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003214 BuildMI(*BB, IP, X86::TEST16rr, 2).addReg(SrcReg).addReg(SrcReg);
Chris Lattner20772542003-06-01 03:38:24 +00003215 break;
3216 case cInt:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003217 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg).addReg(SrcReg);
Chris Lattner20772542003-06-01 03:38:24 +00003218 break;
3219 case cLong: {
3220 unsigned TmpReg = makeAnotherReg(Type::IntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003221 BuildMI(*BB, IP, X86::OR32rr, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
Chris Lattner20772542003-06-01 03:38:24 +00003222 break;
3223 }
3224 case cFP:
Chris Lattneree352852004-02-29 07:22:16 +00003225 BuildMI(*BB, IP, X86::FTST, 1).addReg(SrcReg);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003226 BuildMI(*BB, IP, X86::FNSTSW8r, 0);
Chris Lattneree352852004-02-29 07:22:16 +00003227 BuildMI(*BB, IP, X86::SAHF, 1);
Chris Lattner311ca2e2004-02-23 03:21:41 +00003228 break;
Chris Lattner20772542003-06-01 03:38:24 +00003229 }
3230
3231 // If the zero flag is not set, then the value is true, set the byte to
3232 // true.
Chris Lattneree352852004-02-29 07:22:16 +00003233 BuildMI(*BB, IP, X86::SETNEr, 1, DestReg);
Chris Lattner94af4142002-12-25 05:13:53 +00003234 return;
3235 }
Chris Lattner3e130a22003-01-13 00:32:26 +00003236
3237 static const unsigned RegRegMove[] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003238 X86::MOV8rr, X86::MOV16rr, X86::MOV32rr, X86::FpMOV, X86::MOV32rr
Chris Lattner3e130a22003-01-13 00:32:26 +00003239 };
3240
3241 // Implement casts between values of the same type class (as determined by
3242 // getClass) by using a register-to-register move.
3243 if (SrcClass == DestClass) {
3244 if (SrcClass <= cInt || (SrcClass == cFP && SrcTy == DestTy)) {
Chris Lattneree352852004-02-29 07:22:16 +00003245 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, DestReg).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003246 } else if (SrcClass == cFP) {
3247 if (SrcTy == Type::FloatTy) { // double -> float
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003248 assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
Chris Lattneree352852004-02-29 07:22:16 +00003249 BuildMI(*BB, IP, X86::FpMOV, 1, DestReg).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003250 } else { // float -> double
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003251 assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
3252 "Unknown cFP member!");
3253 // Truncate from double to float by storing to memory as short, then
3254 // reading it back.
3255 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
Chris Lattner3e130a22003-01-13 00:32:26 +00003256 int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003257 addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5), FrameIdx).addReg(SrcReg);
3258 addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
Chris Lattner3e130a22003-01-13 00:32:26 +00003259 }
3260 } else if (SrcClass == cLong) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003261 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
3262 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg+1).addReg(SrcReg+1);
Chris Lattner3e130a22003-01-13 00:32:26 +00003263 } else {
Chris Lattnerc53544a2003-05-12 20:16:58 +00003264 assert(0 && "Cannot handle this type of cast instruction!");
Chris Lattner548f61d2003-04-23 17:22:12 +00003265 abort();
Brian Gaeked474e9c2002-12-06 10:49:33 +00003266 }
Chris Lattner3e130a22003-01-13 00:32:26 +00003267 return;
3268 }
3269
3270 // Handle cast of SMALLER int to LARGER int using a move with sign extension
3271 // or zero extension, depending on whether the source type was signed.
3272 if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
3273 SrcClass < DestClass) {
3274 bool isLong = DestClass == cLong;
3275 if (isLong) DestClass = cInt;
3276
3277 static const unsigned Opc[][4] = {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003278 { X86::MOVSX16rr8, X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOV32rr }, // s
3279 { X86::MOVZX16rr8, X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOV32rr } // u
Chris Lattner3e130a22003-01-13 00:32:26 +00003280 };
3281
Chris Lattner96e3b422004-05-09 22:28:45 +00003282 bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
Chris Lattneree352852004-02-29 07:22:16 +00003283 BuildMI(*BB, IP, Opc[isUnsigned][SrcClass + DestClass - 1], 1,
Chris Lattner548f61d2003-04-23 17:22:12 +00003284 DestReg).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003285
3286 if (isLong) { // Handle upper 32 bits as appropriate...
3287 if (isUnsigned) // Zero out top bits...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003288 BuildMI(*BB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
Chris Lattner3e130a22003-01-13 00:32:26 +00003289 else // Sign extend bottom half...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003290 BuildMI(*BB, IP, X86::SAR32ri, 2, DestReg+1).addReg(DestReg).addImm(31);
Brian Gaeked474e9c2002-12-06 10:49:33 +00003291 }
Chris Lattner3e130a22003-01-13 00:32:26 +00003292 return;
3293 }
3294
3295 // Special case long -> int ...
3296 if (SrcClass == cLong && DestClass == cInt) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003297 BuildMI(*BB, IP, X86::MOV32rr, 1, DestReg).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003298 return;
3299 }
3300
3301 // Handle cast of LARGER int to SMALLER int using a move to EAX followed by a
3302 // move out of AX or AL.
3303 if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
3304 && SrcClass > DestClass) {
3305 static const unsigned AReg[] = { X86::AL, X86::AX, X86::EAX, 0, X86::EAX };
Chris Lattneree352852004-02-29 07:22:16 +00003306 BuildMI(*BB, IP, RegRegMove[SrcClass], 1, AReg[SrcClass]).addReg(SrcReg);
3307 BuildMI(*BB, IP, RegRegMove[DestClass], 1, DestReg).addReg(AReg[DestClass]);
Chris Lattner3e130a22003-01-13 00:32:26 +00003308 return;
3309 }
3310
3311 // Handle casts from integer to floating point now...
3312 if (DestClass == cFP) {
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003313 // Promote the integer to a type supported by FLD. We do this because there
3314 // are no unsigned FLD instructions, so we must promote an unsigned value to
3315 // a larger signed value, then use FLD on the larger value.
3316 //
3317 const Type *PromoteType = 0;
Chris Lattner85aa7092004-04-10 18:32:01 +00003318 unsigned PromoteOpcode = 0;
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003319 unsigned RealDestReg = DestReg;
Chris Lattnerf70c22b2004-06-17 18:19:28 +00003320 switch (SrcTy->getTypeID()) {
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003321 case Type::BoolTyID:
3322 case Type::SByteTyID:
3323 // We don't have the facilities for directly loading byte sized data from
3324 // memory (even signed). Promote it to 16 bits.
3325 PromoteType = Type::ShortTy;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003326 PromoteOpcode = X86::MOVSX16rr8;
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003327 break;
3328 case Type::UByteTyID:
3329 PromoteType = Type::ShortTy;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003330 PromoteOpcode = X86::MOVZX16rr8;
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003331 break;
3332 case Type::UShortTyID:
3333 PromoteType = Type::IntTy;
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003334 PromoteOpcode = X86::MOVZX32rr16;
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003335 break;
3336 case Type::UIntTyID: {
3337 // Make a 64 bit temporary... and zero out the top of it...
3338 unsigned TmpReg = makeAnotherReg(Type::LongTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003339 BuildMI(*BB, IP, X86::MOV32rr, 1, TmpReg).addReg(SrcReg);
3340 BuildMI(*BB, IP, X86::MOV32ri, 1, TmpReg+1).addImm(0);
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003341 SrcTy = Type::LongTy;
3342 SrcClass = cLong;
3343 SrcReg = TmpReg;
3344 break;
3345 }
3346 case Type::ULongTyID:
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003347 // Don't fild into the read destination.
3348 DestReg = makeAnotherReg(Type::DoubleTy);
3349 break;
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003350 default: // No promotion needed...
3351 break;
3352 }
3353
3354 if (PromoteType) {
3355 unsigned TmpReg = makeAnotherReg(PromoteType);
Chris Lattner7b92de1e2004-04-06 19:29:36 +00003356 BuildMI(*BB, IP, PromoteOpcode, 1, TmpReg).addReg(SrcReg);
Chris Lattner4d5a50a2003-05-12 20:36:13 +00003357 SrcTy = PromoteType;
3358 SrcClass = getClass(PromoteType);
Chris Lattner3e130a22003-01-13 00:32:26 +00003359 SrcReg = TmpReg;
3360 }
3361
3362 // Spill the integer to memory and reload it from there...
Chris Lattnerb6bac512004-02-25 06:13:04 +00003363 int FrameIdx =
3364 F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
Chris Lattner3e130a22003-01-13 00:32:26 +00003365
3366 if (SrcClass == cLong) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003367 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
Chris Lattneree352852004-02-29 07:22:16 +00003368 FrameIdx).addReg(SrcReg);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003369 addFrameReference(BuildMI(*BB, IP, X86::MOV32mr, 5),
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003370 FrameIdx, 4).addReg(SrcReg+1);
Chris Lattner3e130a22003-01-13 00:32:26 +00003371 } else {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003372 static const unsigned Op1[] = { X86::MOV8mr, X86::MOV16mr, X86::MOV32mr };
Chris Lattneree352852004-02-29 07:22:16 +00003373 addFrameReference(BuildMI(*BB, IP, Op1[SrcClass], 5),
3374 FrameIdx).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003375 }
3376
3377 static const unsigned Op2[] =
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003378 { 0/*byte*/, X86::FILD16m, X86::FILD32m, 0/*FP*/, X86::FILD64m };
Chris Lattneree352852004-02-29 07:22:16 +00003379 addFrameReference(BuildMI(*BB, IP, Op2[SrcClass], 5, DestReg), FrameIdx);
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003380
3381 // We need special handling for unsigned 64-bit integer sources. If the
3382 // input number has the "sign bit" set, then we loaded it incorrectly as a
3383 // negative 64-bit number. In this case, add an offset value.
3384 if (SrcTy == Type::ULongTy) {
3385 // Emit a test instruction to see if the dynamic input value was signed.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003386 BuildMI(*BB, IP, X86::TEST32rr, 2).addReg(SrcReg+1).addReg(SrcReg+1);
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003387
Chris Lattnerb6bac512004-02-25 06:13:04 +00003388 // If the sign bit is set, get a pointer to an offset, otherwise get a
3389 // pointer to a zero.
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003390 MachineConstantPool *CP = F->getConstantPool();
3391 unsigned Zero = makeAnotherReg(Type::IntTy);
Chris Lattnerb6bac512004-02-25 06:13:04 +00003392 Constant *Null = Constant::getNullValue(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003393 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Zero),
Chris Lattnerb6bac512004-02-25 06:13:04 +00003394 CP->getConstantPoolIndex(Null));
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003395 unsigned Offset = makeAnotherReg(Type::IntTy);
Chris Lattnerb6bac512004-02-25 06:13:04 +00003396 Constant *OffsetCst = ConstantUInt::get(Type::UIntTy, 0x5f800000);
3397
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003398 addConstantPoolReference(BuildMI(*BB, IP, X86::LEA32r, 5, Offset),
Chris Lattnerb6bac512004-02-25 06:13:04 +00003399 CP->getConstantPoolIndex(OffsetCst));
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003400 unsigned Addr = makeAnotherReg(Type::IntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003401 BuildMI(*BB, IP, X86::CMOVS32rr, 2, Addr).addReg(Zero).addReg(Offset);
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003402
3403 // Load the constant for an add. FIXME: this could make an 'fadd' that
3404 // reads directly from memory, but we don't support these yet.
3405 unsigned ConstReg = makeAnotherReg(Type::DoubleTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003406 addDirectMem(BuildMI(*BB, IP, X86::FLD32m, 4, ConstReg), Addr);
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003407
Chris Lattneree352852004-02-29 07:22:16 +00003408 BuildMI(*BB, IP, X86::FpADD, 2, RealDestReg)
3409 .addReg(ConstReg).addReg(DestReg);
Chris Lattnerbaa58a52004-02-23 03:10:10 +00003410 }
3411
Chris Lattner3e130a22003-01-13 00:32:26 +00003412 return;
3413 }
3414
3415 // Handle casts from floating point to integer now...
3416 if (SrcClass == cFP) {
3417 // Change the floating point control register to use "round towards zero"
3418 // mode when truncating to an integer value.
3419 //
3420 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003421 addFrameReference(BuildMI(*BB, IP, X86::FNSTCW16m, 4), CWFrameIdx);
Chris Lattner3e130a22003-01-13 00:32:26 +00003422
3423 // Load the old value of the high byte of the control word...
3424 unsigned HighPartOfCW = makeAnotherReg(Type::UByteTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003425 addFrameReference(BuildMI(*BB, IP, X86::MOV8rm, 4, HighPartOfCW),
Chris Lattneree352852004-02-29 07:22:16 +00003426 CWFrameIdx, 1);
Chris Lattner3e130a22003-01-13 00:32:26 +00003427
3428 // Set the high part to be round to zero...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003429 addFrameReference(BuildMI(*BB, IP, X86::MOV8mi, 5),
Chris Lattneree352852004-02-29 07:22:16 +00003430 CWFrameIdx, 1).addImm(12);
Chris Lattner3e130a22003-01-13 00:32:26 +00003431
3432 // Reload the modified control word now...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003433 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
Chris Lattner3e130a22003-01-13 00:32:26 +00003434
3435 // Restore the memory image of control word to original value
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003436 addFrameReference(BuildMI(*BB, IP, X86::MOV8mr, 5),
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003437 CWFrameIdx, 1).addReg(HighPartOfCW);
Chris Lattner3e130a22003-01-13 00:32:26 +00003438
3439 // We don't have the facilities for directly storing byte sized data to
3440 // memory. Promote it to 16 bits. We also must promote unsigned values to
3441 // larger classes because we only have signed FP stores.
3442 unsigned StoreClass = DestClass;
3443 const Type *StoreTy = DestTy;
3444 if (StoreClass == cByte || DestTy->isUnsigned())
3445 switch (StoreClass) {
3446 case cByte: StoreTy = Type::ShortTy; StoreClass = cShort; break;
3447 case cShort: StoreTy = Type::IntTy; StoreClass = cInt; break;
3448 case cInt: StoreTy = Type::LongTy; StoreClass = cLong; break;
Brian Gaeked4615052003-07-18 20:23:43 +00003449 // The following treatment of cLong may not be perfectly right,
3450 // but it survives chains of casts of the form
3451 // double->ulong->double.
3452 case cLong: StoreTy = Type::LongTy; StoreClass = cLong; break;
Chris Lattner3e130a22003-01-13 00:32:26 +00003453 default: assert(0 && "Unknown store class!");
3454 }
3455
3456 // Spill the integer to memory and reload it from there...
3457 int FrameIdx =
3458 F->getFrameInfo()->CreateStackObject(StoreTy, TM.getTargetData());
3459
3460 static const unsigned Op1[] =
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003461 { 0, X86::FIST16m, X86::FIST32m, 0, X86::FISTP64m };
Chris Lattneree352852004-02-29 07:22:16 +00003462 addFrameReference(BuildMI(*BB, IP, Op1[StoreClass], 5),
3463 FrameIdx).addReg(SrcReg);
Chris Lattner3e130a22003-01-13 00:32:26 +00003464
3465 if (DestClass == cLong) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003466 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg), FrameIdx);
3467 addFrameReference(BuildMI(*BB, IP, X86::MOV32rm, 4, DestReg+1),
Chris Lattneree352852004-02-29 07:22:16 +00003468 FrameIdx, 4);
Chris Lattner3e130a22003-01-13 00:32:26 +00003469 } else {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003470 static const unsigned Op2[] = { X86::MOV8rm, X86::MOV16rm, X86::MOV32rm };
Chris Lattneree352852004-02-29 07:22:16 +00003471 addFrameReference(BuildMI(*BB, IP, Op2[DestClass], 4, DestReg), FrameIdx);
Chris Lattner3e130a22003-01-13 00:32:26 +00003472 }
3473
3474 // Reload the original control word now...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003475 addFrameReference(BuildMI(*BB, IP, X86::FLDCW16m, 4), CWFrameIdx);
Chris Lattner3e130a22003-01-13 00:32:26 +00003476 return;
3477 }
3478
Brian Gaeked474e9c2002-12-06 10:49:33 +00003479 // Anything we haven't handled already, we can't (yet) handle at all.
Chris Lattnerc53544a2003-05-12 20:16:58 +00003480 assert(0 && "Unhandled cast instruction!");
Chris Lattner548f61d2003-04-23 17:22:12 +00003481 abort();
Brian Gaekefa8d5712002-11-22 11:07:01 +00003482}
Brian Gaekea1719c92002-10-31 23:03:59 +00003483
Chris Lattner73815062003-10-18 05:56:40 +00003484/// visitVANextInst - Implement the va_next instruction...
Chris Lattnereca195e2003-05-08 19:44:13 +00003485///
Chris Lattner73815062003-10-18 05:56:40 +00003486void ISel::visitVANextInst(VANextInst &I) {
3487 unsigned VAList = getReg(I.getOperand(0));
Chris Lattnereca195e2003-05-08 19:44:13 +00003488 unsigned DestReg = getReg(I);
3489
Chris Lattnereca195e2003-05-08 19:44:13 +00003490 unsigned Size;
Chris Lattnerf70c22b2004-06-17 18:19:28 +00003491 switch (I.getArgType()->getTypeID()) {
Chris Lattnereca195e2003-05-08 19:44:13 +00003492 default:
3493 std::cerr << I;
Chris Lattner73815062003-10-18 05:56:40 +00003494 assert(0 && "Error: bad type for va_next instruction!");
Chris Lattnereca195e2003-05-08 19:44:13 +00003495 return;
3496 case Type::PointerTyID:
3497 case Type::UIntTyID:
3498 case Type::IntTyID:
3499 Size = 4;
Chris Lattnereca195e2003-05-08 19:44:13 +00003500 break;
3501 case Type::ULongTyID:
3502 case Type::LongTyID:
Chris Lattnereca195e2003-05-08 19:44:13 +00003503 case Type::DoubleTyID:
3504 Size = 8;
Chris Lattnereca195e2003-05-08 19:44:13 +00003505 break;
3506 }
3507
3508 // Increment the VAList pointer...
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003509 BuildMI(BB, X86::ADD32ri, 2, DestReg).addReg(VAList).addImm(Size);
Chris Lattner73815062003-10-18 05:56:40 +00003510}
Chris Lattnereca195e2003-05-08 19:44:13 +00003511
Chris Lattner73815062003-10-18 05:56:40 +00003512void ISel::visitVAArgInst(VAArgInst &I) {
3513 unsigned VAList = getReg(I.getOperand(0));
3514 unsigned DestReg = getReg(I);
3515
Chris Lattnerf70c22b2004-06-17 18:19:28 +00003516 switch (I.getType()->getTypeID()) {
Chris Lattner73815062003-10-18 05:56:40 +00003517 default:
3518 std::cerr << I;
3519 assert(0 && "Error: bad type for va_next instruction!");
3520 return;
3521 case Type::PointerTyID:
3522 case Type::UIntTyID:
3523 case Type::IntTyID:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003524 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
Chris Lattner73815062003-10-18 05:56:40 +00003525 break;
3526 case Type::ULongTyID:
3527 case Type::LongTyID:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003528 addDirectMem(BuildMI(BB, X86::MOV32rm, 4, DestReg), VAList);
3529 addRegOffset(BuildMI(BB, X86::MOV32rm, 4, DestReg+1), VAList, 4);
Chris Lattner73815062003-10-18 05:56:40 +00003530 break;
3531 case Type::DoubleTyID:
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003532 addDirectMem(BuildMI(BB, X86::FLD64m, 4, DestReg), VAList);
Chris Lattner73815062003-10-18 05:56:40 +00003533 break;
3534 }
Chris Lattnereca195e2003-05-08 19:44:13 +00003535}
3536
Misha Brukman538607f2004-03-01 23:53:11 +00003537/// visitGetElementPtrInst - instruction-select GEP instructions
3538///
Chris Lattner3e130a22003-01-13 00:32:26 +00003539void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
Chris Lattnerb6bac512004-02-25 06:13:04 +00003540 // If this GEP instruction will be folded into all of its users, we don't need
3541 // to explicitly calculate it!
3542 unsigned A, B, C, D;
3543 if (isGEPFoldable(0, I.getOperand(0), I.op_begin()+1, I.op_end(), A,B,C,D)) {
3544 // Check all of the users of the instruction to see if they are loads and
3545 // stores.
3546 bool AllWillFold = true;
3547 for (Value::use_iterator UI = I.use_begin(), E = I.use_end(); UI != E; ++UI)
3548 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Load)
3549 if (cast<Instruction>(*UI)->getOpcode() != Instruction::Store ||
3550 cast<Instruction>(*UI)->getOperand(0) == &I) {
3551 AllWillFold = false;
3552 break;
3553 }
3554
3555 // If the instruction is foldable, and will be folded into all users, don't
3556 // emit it!
3557 if (AllWillFold) return;
3558 }
3559
Chris Lattner3e130a22003-01-13 00:32:26 +00003560 unsigned outputReg = getReg(I);
Chris Lattner827832c2004-02-22 17:05:38 +00003561 emitGEPOperation(BB, BB->end(), I.getOperand(0),
Brian Gaeke68b1edc2002-12-16 04:23:29 +00003562 I.op_begin()+1, I.op_end(), outputReg);
Chris Lattnerc0812d82002-12-13 06:56:29 +00003563}
3564
Chris Lattner985fe3d2004-02-25 03:45:50 +00003565/// getGEPIndex - Inspect the getelementptr operands specified with GEPOps and
3566/// GEPTypes (the derived types being stepped through at each level). On return
3567/// from this function, if some indexes of the instruction are representable as
3568/// an X86 lea instruction, the machine operands are put into the Ops
3569/// instruction and the consumed indexes are poped from the GEPOps/GEPTypes
3570/// lists. Otherwise, GEPOps.size() is returned. If this returns a an
3571/// addressing mode that only partially consumes the input, the BaseReg input of
3572/// the addressing mode must be left free.
3573///
3574/// Note that there is one fewer entry in GEPTypes than there is in GEPOps.
3575///
Chris Lattnerb6bac512004-02-25 06:13:04 +00003576void ISel::getGEPIndex(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
3577 std::vector<Value*> &GEPOps,
3578 std::vector<const Type*> &GEPTypes, unsigned &BaseReg,
3579 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
3580 const TargetData &TD = TM.getTargetData();
3581
Chris Lattner985fe3d2004-02-25 03:45:50 +00003582 // Clear out the state we are working with...
Chris Lattnerb6bac512004-02-25 06:13:04 +00003583 BaseReg = 0; // No base register
3584 Scale = 1; // Unit scale
3585 IndexReg = 0; // No index register
3586 Disp = 0; // No displacement
3587
Chris Lattner985fe3d2004-02-25 03:45:50 +00003588 // While there are GEP indexes that can be folded into the current address,
3589 // keep processing them.
3590 while (!GEPTypes.empty()) {
3591 if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
3592 // It's a struct access. CUI is the index into the structure,
3593 // which names the field. This index must have unsigned type.
3594 const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
3595
3596 // Use the TargetData structure to pick out what the layout of the
3597 // structure is in memory. Since the structure index must be constant, we
3598 // can get its value and use it to find the right byte offset from the
3599 // StructLayout class's list of structure member offsets.
Chris Lattnerb6bac512004-02-25 06:13:04 +00003600 Disp += TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
Chris Lattner985fe3d2004-02-25 03:45:50 +00003601 GEPOps.pop_back(); // Consume a GEP operand
3602 GEPTypes.pop_back();
3603 } else {
3604 // It's an array or pointer access: [ArraySize x ElementType].
3605 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3606 Value *idx = GEPOps.back();
3607
3608 // idx is the index into the array. Unlike with structure
3609 // indices, we may not know its actual value at code-generation
3610 // time.
Chris Lattner985fe3d2004-02-25 03:45:50 +00003611
3612 // If idx is a constant, fold it into the offset.
Chris Lattner5f2c7b12004-02-25 07:00:55 +00003613 unsigned TypeSize = TD.getTypeSize(SqTy->getElementType());
Chris Lattner985fe3d2004-02-25 03:45:50 +00003614 if (ConstantSInt *CSI = dyn_cast<ConstantSInt>(idx)) {
Chris Lattner5f2c7b12004-02-25 07:00:55 +00003615 Disp += TypeSize*CSI->getValue();
Chris Lattner28977af2004-04-05 01:30:19 +00003616 } else if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(idx)) {
3617 Disp += TypeSize*CUI->getValue();
Chris Lattner985fe3d2004-02-25 03:45:50 +00003618 } else {
Chris Lattner5f2c7b12004-02-25 07:00:55 +00003619 // If the index reg is already taken, we can't handle this index.
3620 if (IndexReg) return;
3621
3622 // If this is a size that we can handle, then add the index as
3623 switch (TypeSize) {
3624 case 1: case 2: case 4: case 8:
3625 // These are all acceptable scales on X86.
3626 Scale = TypeSize;
3627 break;
3628 default:
3629 // Otherwise, we can't handle this scale
3630 return;
3631 }
3632
3633 if (CastInst *CI = dyn_cast<CastInst>(idx))
3634 if (CI->getOperand(0)->getType() == Type::IntTy ||
3635 CI->getOperand(0)->getType() == Type::UIntTy)
3636 idx = CI->getOperand(0);
3637
3638 IndexReg = MBB ? getReg(idx, MBB, IP) : 1;
Chris Lattner985fe3d2004-02-25 03:45:50 +00003639 }
3640
3641 GEPOps.pop_back(); // Consume a GEP operand
3642 GEPTypes.pop_back();
3643 }
3644 }
Chris Lattnerb6bac512004-02-25 06:13:04 +00003645
Chris Lattnerdf040972004-05-23 21:23:12 +00003646 // GEPTypes is empty, which means we have a single operand left. Set it as
3647 // the base register.
Chris Lattnerb6bac512004-02-25 06:13:04 +00003648 //
Chris Lattnerb6bac512004-02-25 06:13:04 +00003649 assert(BaseReg == 0);
Chris Lattnerdf040972004-05-23 21:23:12 +00003650
3651#if 0 // FIXME: TODO!
3652 if (AllocaInst *AI = dyn_castFixedAlloca(V)) {
3653 // FIXME: When we can add FrameIndex values as the first operand, we can
3654 // make GEP's of allocas MUCH more efficient!
3655 unsigned FI = getFixedSizedAllocaFI(AI);
3656 GEPOps.pop_back();
3657 return;
3658 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
3659 // FIXME: When addressing modes are more powerful/correct, we could load
3660 // global addresses directly as 32-bit immediates.
3661 }
3662#endif
3663
Chris Lattner5f2c7b12004-02-25 07:00:55 +00003664 BaseReg = MBB ? getReg(GEPOps[0], MBB, IP) : 1;
Chris Lattnerb6bac512004-02-25 06:13:04 +00003665 GEPOps.pop_back(); // Consume the last GEP operand
Chris Lattner985fe3d2004-02-25 03:45:50 +00003666}
3667
3668
Chris Lattnerb6bac512004-02-25 06:13:04 +00003669/// isGEPFoldable - Return true if the specified GEP can be completely
3670/// folded into the addressing mode of a load/store or lea instruction.
3671bool ISel::isGEPFoldable(MachineBasicBlock *MBB,
3672 Value *Src, User::op_iterator IdxBegin,
3673 User::op_iterator IdxEnd, unsigned &BaseReg,
3674 unsigned &Scale, unsigned &IndexReg, unsigned &Disp) {
Chris Lattner7ca04092004-02-22 17:35:42 +00003675
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003676 std::vector<Value*> GEPOps;
3677 GEPOps.resize(IdxEnd-IdxBegin+1);
3678 GEPOps[0] = Src;
3679 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3680
Chris Lattnerdf040972004-05-23 21:23:12 +00003681 std::vector<const Type*>
3682 GEPTypes(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3683 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003684
Chris Lattnerb6bac512004-02-25 06:13:04 +00003685 MachineBasicBlock::iterator IP;
3686 if (MBB) IP = MBB->end();
3687 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
3688
3689 // We can fold it away iff the getGEPIndex call eliminated all operands.
3690 return GEPOps.empty();
3691}
3692
3693void ISel::emitGEPOperation(MachineBasicBlock *MBB,
3694 MachineBasicBlock::iterator IP,
3695 Value *Src, User::op_iterator IdxBegin,
3696 User::op_iterator IdxEnd, unsigned TargetReg) {
3697 const TargetData &TD = TM.getTargetData();
Chris Lattnerb6bac512004-02-25 06:13:04 +00003698
Chris Lattnerd2995df2004-07-15 00:58:53 +00003699 // If this is a getelementptr null, with all constant integer indices, just
3700 // replace it with TargetReg = 42.
3701 if (isa<ConstantPointerNull>(Src)) {
3702 User::op_iterator I = IdxBegin;
3703 for (; I != IdxEnd; ++I)
3704 if (!isa<ConstantInt>(*I))
3705 break;
3706 if (I == IdxEnd) { // All constant indices
3707 unsigned Offset = TD.getIndexedOffset(Src->getType(),
3708 std::vector<Value*>(IdxBegin, IdxEnd));
3709 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addImm(Offset);
3710 return;
3711 }
3712 }
3713
Chris Lattnerb6bac512004-02-25 06:13:04 +00003714 std::vector<Value*> GEPOps;
3715 GEPOps.resize(IdxEnd-IdxBegin+1);
3716 GEPOps[0] = Src;
3717 std::copy(IdxBegin, IdxEnd, GEPOps.begin()+1);
3718
3719 std::vector<const Type*> GEPTypes;
3720 GEPTypes.assign(gep_type_begin(Src->getType(), IdxBegin, IdxEnd),
3721 gep_type_end(Src->getType(), IdxBegin, IdxEnd));
Chris Lattner985fe3d2004-02-25 03:45:50 +00003722
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003723 // Keep emitting instructions until we consume the entire GEP instruction.
3724 while (!GEPOps.empty()) {
3725 unsigned OldSize = GEPOps.size();
Chris Lattnerb6bac512004-02-25 06:13:04 +00003726 unsigned BaseReg, Scale, IndexReg, Disp;
3727 getGEPIndex(MBB, IP, GEPOps, GEPTypes, BaseReg, Scale, IndexReg, Disp);
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003728
Chris Lattner985fe3d2004-02-25 03:45:50 +00003729 if (GEPOps.size() != OldSize) {
3730 // getGEPIndex consumed some of the input. Build an LEA instruction here.
Chris Lattnerb6bac512004-02-25 06:13:04 +00003731 unsigned NextTarget = 0;
3732 if (!GEPOps.empty()) {
3733 assert(BaseReg == 0 &&
3734 "getGEPIndex should have left the base register open for chaining!");
3735 NextTarget = BaseReg = makeAnotherReg(Type::UIntTy);
Chris Lattner985fe3d2004-02-25 03:45:50 +00003736 }
Chris Lattnerb6bac512004-02-25 06:13:04 +00003737
3738 if (IndexReg == 0 && Disp == 0)
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003739 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
Chris Lattnerb6bac512004-02-25 06:13:04 +00003740 else
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003741 addFullAddress(BuildMI(*MBB, IP, X86::LEA32r, 5, TargetReg),
Chris Lattnerb6bac512004-02-25 06:13:04 +00003742 BaseReg, Scale, IndexReg, Disp);
3743 --IP;
3744 TargetReg = NextTarget;
Chris Lattner985fe3d2004-02-25 03:45:50 +00003745 } else if (GEPTypes.empty()) {
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003746 // The getGEPIndex operation didn't want to build an LEA. Check to see if
3747 // all operands are consumed but the base pointer. If so, just load it
3748 // into the register.
Chris Lattner7ca04092004-02-22 17:35:42 +00003749 if (GlobalValue *GV = dyn_cast<GlobalValue>(GEPOps[0])) {
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003750 BuildMI(*MBB, IP, X86::MOV32ri, 1, TargetReg).addGlobalAddress(GV);
Chris Lattner7ca04092004-02-22 17:35:42 +00003751 } else {
3752 unsigned BaseReg = getReg(GEPOps[0], MBB, IP);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003753 BuildMI(*MBB, IP, X86::MOV32rr, 1, TargetReg).addReg(BaseReg);
Chris Lattner7ca04092004-02-22 17:35:42 +00003754 }
3755 break; // we are now done
Chris Lattnerb6bac512004-02-25 06:13:04 +00003756
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003757 } else {
Brian Gaeke20244b72002-12-12 15:33:40 +00003758 // It's an array or pointer access: [ArraySize x ElementType].
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003759 const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
3760 Value *idx = GEPOps.back();
3761 GEPOps.pop_back(); // Consume a GEP operand
3762 GEPTypes.pop_back();
Chris Lattner8a307e82002-12-16 19:32:50 +00003763
Chris Lattner28977af2004-04-05 01:30:19 +00003764 // Many GEP instructions use a [cast (int/uint) to LongTy] as their
Chris Lattnerf5854472003-06-21 16:01:24 +00003765 // operand on X86. Handle this case directly now...
3766 if (CastInst *CI = dyn_cast<CastInst>(idx))
3767 if (CI->getOperand(0)->getType() == Type::IntTy ||
3768 CI->getOperand(0)->getType() == Type::UIntTy)
3769 idx = CI->getOperand(0);
3770
Chris Lattner3e130a22003-01-13 00:32:26 +00003771 // We want to add BaseReg to(idxReg * sizeof ElementType). First, we
Chris Lattner8a307e82002-12-16 19:32:50 +00003772 // must find the size of the pointed-to type (Not coincidentally, the next
3773 // type is the type of the elements in the array).
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003774 const Type *ElTy = SqTy->getElementType();
3775 unsigned elementSize = TD.getTypeSize(ElTy);
Chris Lattner8a307e82002-12-16 19:32:50 +00003776
3777 // If idxReg is a constant, we don't need to perform the multiply!
Chris Lattner28977af2004-04-05 01:30:19 +00003778 if (ConstantInt *CSI = dyn_cast<ConstantInt>(idx)) {
Chris Lattner3e130a22003-01-13 00:32:26 +00003779 if (!CSI->isNullValue()) {
Chris Lattner28977af2004-04-05 01:30:19 +00003780 unsigned Offset = elementSize*CSI->getRawValue();
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003781 unsigned Reg = makeAnotherReg(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003782 BuildMI(*MBB, IP, X86::ADD32ri, 2, TargetReg)
Chris Lattneree352852004-02-29 07:22:16 +00003783 .addReg(Reg).addImm(Offset);
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003784 --IP; // Insert the next instruction before this one.
3785 TargetReg = Reg; // Codegen the rest of the GEP into this
Chris Lattner8a307e82002-12-16 19:32:50 +00003786 }
3787 } else if (elementSize == 1) {
3788 // If the element size is 1, we don't have to multiply, just add
3789 unsigned idxReg = getReg(idx, MBB, IP);
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003790 unsigned Reg = makeAnotherReg(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003791 BuildMI(*MBB, IP, X86::ADD32rr, 2,TargetReg).addReg(Reg).addReg(idxReg);
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003792 --IP; // Insert the next instruction before this one.
3793 TargetReg = Reg; // Codegen the rest of the GEP into this
Chris Lattner8a307e82002-12-16 19:32:50 +00003794 } else {
3795 unsigned idxReg = getReg(idx, MBB, IP);
3796 unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
Chris Lattnerb2acc512003-10-19 21:09:10 +00003797
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003798 // Make sure we can back the iterator up to point to the first
3799 // instruction emitted.
3800 MachineBasicBlock::iterator BeforeIt = IP;
3801 if (IP == MBB->begin())
3802 BeforeIt = MBB->end();
3803 else
3804 --BeforeIt;
Chris Lattnerb2acc512003-10-19 21:09:10 +00003805 doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
3806
Chris Lattner8a307e82002-12-16 19:32:50 +00003807 // Emit an ADD to add OffsetReg to the basePtr.
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003808 unsigned Reg = makeAnotherReg(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003809 BuildMI(*MBB, IP, X86::ADD32rr, 2, TargetReg)
Chris Lattneree352852004-02-29 07:22:16 +00003810 .addReg(Reg).addReg(OffsetReg);
Chris Lattner3f1e8e72004-02-22 07:04:00 +00003811
3812 // Step to the first instruction of the multiply.
3813 if (BeforeIt == MBB->end())
3814 IP = MBB->begin();
3815 else
3816 IP = ++BeforeIt;
3817
3818 TargetReg = Reg; // Codegen the rest of the GEP into this
Chris Lattner8a307e82002-12-16 19:32:50 +00003819 }
Brian Gaeke20244b72002-12-12 15:33:40 +00003820 }
Brian Gaeke20244b72002-12-12 15:33:40 +00003821 }
Brian Gaeke20244b72002-12-12 15:33:40 +00003822}
3823
Chris Lattner065faeb2002-12-28 20:24:02 +00003824/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
3825/// frame manager, otherwise do it the hard way.
3826///
3827void ISel::visitAllocaInst(AllocaInst &I) {
Chris Lattner9f1b5312004-05-13 15:12:43 +00003828 // If this is a fixed size alloca in the entry block for the function, we
3829 // statically stack allocate the space, so we don't need to do anything here.
3830 //
Chris Lattnercb2fd552004-05-13 07:40:27 +00003831 if (dyn_castFixedAlloca(&I)) return;
Chris Lattner9f1b5312004-05-13 15:12:43 +00003832
Brian Gaekee48ec012002-12-13 06:46:31 +00003833 // Find the data size of the alloca inst's getAllocatedType.
Chris Lattner065faeb2002-12-28 20:24:02 +00003834 const Type *Ty = I.getAllocatedType();
3835 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
3836
Chris Lattner065faeb2002-12-28 20:24:02 +00003837 // Create a register to hold the temporary result of multiplying the type size
3838 // constant by the variable amount.
3839 unsigned TotalSizeReg = makeAnotherReg(Type::UIntTy);
3840 unsigned SrcReg1 = getReg(I.getArraySize());
Chris Lattner065faeb2002-12-28 20:24:02 +00003841
3842 // TotalSizeReg = mul <numelements>, <TypeSize>
3843 MachineBasicBlock::iterator MBBI = BB->end();
Chris Lattnerb2acc512003-10-19 21:09:10 +00003844 doMultiplyConst(BB, MBBI, TotalSizeReg, Type::UIntTy, SrcReg1, TySize);
Chris Lattner065faeb2002-12-28 20:24:02 +00003845
3846 // AddedSize = add <TotalSizeReg>, 15
3847 unsigned AddedSizeReg = makeAnotherReg(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003848 BuildMI(BB, X86::ADD32ri, 2, AddedSizeReg).addReg(TotalSizeReg).addImm(15);
Chris Lattner065faeb2002-12-28 20:24:02 +00003849
3850 // AlignedSize = and <AddedSize>, ~15
3851 unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003852 BuildMI(BB, X86::AND32ri, 2, AlignedSize).addReg(AddedSizeReg).addImm(~15);
Chris Lattner065faeb2002-12-28 20:24:02 +00003853
Brian Gaekee48ec012002-12-13 06:46:31 +00003854 // Subtract size from stack pointer, thereby allocating some space.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003855 BuildMI(BB, X86::SUB32rr, 2, X86::ESP).addReg(X86::ESP).addReg(AlignedSize);
Chris Lattner065faeb2002-12-28 20:24:02 +00003856
Brian Gaekee48ec012002-12-13 06:46:31 +00003857 // Put a pointer to the space into the result register, by copying
3858 // the stack pointer.
Alkis Evlogimenos8295f202004-02-29 08:50:03 +00003859 BuildMI(BB, X86::MOV32rr, 1, getReg(I)).addReg(X86::ESP);
Chris Lattner065faeb2002-12-28 20:24:02 +00003860
Misha Brukman48196b32003-05-03 02:18:17 +00003861 // Inform the Frame Information that we have just allocated a variable-sized
Chris Lattner065faeb2002-12-28 20:24:02 +00003862 // object.
3863 F->getFrameInfo()->CreateVariableSizedObject();
Brian Gaeke20244b72002-12-12 15:33:40 +00003864}
Chris Lattner3e130a22003-01-13 00:32:26 +00003865
3866/// visitMallocInst - Malloc instructions are code generated into direct calls
3867/// to the library malloc.
3868///
3869void ISel::visitMallocInst(MallocInst &I) {
3870 unsigned AllocSize = TM.getTargetData().getTypeSize(I.getAllocatedType());
3871 unsigned Arg;
3872
3873 if (ConstantUInt *C = dyn_cast<ConstantUInt>(I.getOperand(0))) {
3874 Arg = getReg(ConstantUInt::get(Type::UIntTy, C->getValue() * AllocSize));
3875 } else {
3876 Arg = makeAnotherReg(Type::UIntTy);
Chris Lattnerb2acc512003-10-19 21:09:10 +00003877 unsigned Op0Reg = getReg(I.getOperand(0));
Chris Lattner3e130a22003-01-13 00:32:26 +00003878 MachineBasicBlock::iterator MBBI = BB->end();
Chris Lattnerb2acc512003-10-19 21:09:10 +00003879 doMultiplyConst(BB, MBBI, Arg, Type::UIntTy, Op0Reg, AllocSize);
Chris Lattner3e130a22003-01-13 00:32:26 +00003880 }
3881
3882 std::vector<ValueRecord> Args;
3883 Args.push_back(ValueRecord(Arg, Type::UIntTy));
3884 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003885 1).addExternalSymbol("malloc", true);
Chris Lattner3e130a22003-01-13 00:32:26 +00003886 doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
3887}
3888
3889
3890/// visitFreeInst - Free instructions are code gen'd to call the free libc
3891/// function.
3892///
3893void ISel::visitFreeInst(FreeInst &I) {
3894 std::vector<ValueRecord> Args;
Chris Lattner5e2cb8b2003-08-04 02:12:48 +00003895 Args.push_back(ValueRecord(I.getOperand(0)));
Chris Lattner3e130a22003-01-13 00:32:26 +00003896 MachineInstr *TheCall = BuildMI(X86::CALLpcrel32,
Misha Brukmanc8893fc2003-10-23 16:22:08 +00003897 1).addExternalSymbol("free", true);
Chris Lattner3e130a22003-01-13 00:32:26 +00003898 doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
3899}
3900
Chris Lattnerd281de22003-07-26 23:49:58 +00003901/// createX86SimpleInstructionSelector - This pass converts an LLVM function
Chris Lattnerb4f68ed2002-10-29 22:37:54 +00003902/// into a machine code representation is a very simple peep-hole fashion. The
Chris Lattner72614082002-10-25 22:55:53 +00003903/// generated code sucks but the implementation is nice and simple.
3904///
Chris Lattnerf70e0c22003-12-28 21:23:38 +00003905FunctionPass *llvm::createX86SimpleInstructionSelector(TargetMachine &TM) {
3906 return new ISel(TM);
Chris Lattner72614082002-10-25 22:55:53 +00003907}