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Jia Liubb481f82012-02-28 07:46:26 +00001//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00007//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00009//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
Akira Hatanaka4552c9a2011-04-15 21:51:11 +000013//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000014
15#define DEBUG_TYPE "mips-lower"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000016#include "MipsISelLowering.h"
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +000017#include "MipsMachineFunction.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000018#include "MipsTargetMachine.h"
Chris Lattnerb71b9092009-08-13 06:28:06 +000019#include "MipsTargetObjectFile.h"
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000020#include "MipsSubtarget.h"
Craig Topper79aa3412012-03-17 18:46:09 +000021#include "InstPrinter/MipsInstPrinter.h"
22#include "MCTargetDesc/MipsBaseInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000023#include "llvm/DerivedTypes.h"
24#include "llvm/Function.h"
Bruno Cardoso Lopes91fd5322008-07-21 18:52:34 +000025#include "llvm/GlobalVariable.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000026#include "llvm/Intrinsics.h"
27#include "llvm/CallingConv.h"
28#include "llvm/CodeGen/CallingConvLower.h"
29#include "llvm/CodeGen/MachineFrameInfo.h"
30#include "llvm/CodeGen/MachineFunction.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattner84bc5422007-12-31 04:13:23 +000032#include "llvm/CodeGen/MachineRegisterInfo.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000033#include "llvm/CodeGen/SelectionDAGISel.h"
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000034#include "llvm/CodeGen/ValueTypes.h"
35#include "llvm/Support/Debug.h"
Torok Edwinc25e7582009-07-11 20:10:48 +000036#include "llvm/Support/ErrorHandling.h"
NAKAMURA Takumi89593932012-04-21 15:31:45 +000037#include "llvm/Support/raw_ostream.h"
38
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000039using namespace llvm;
40
Jia Liubb481f82012-02-28 07:46:26 +000041// If I is a shifted mask, set the size (Size) and the first bit of the
Akira Hatanakadbe9a312011-08-18 20:07:42 +000042// mask (Pos), and return true.
Jia Liubb481f82012-02-28 07:46:26 +000043// For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
Akira Hatanaka854a7db2011-08-19 22:59:00 +000044static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
Akira Hatanakad6bc5232011-12-05 21:26:34 +000045 if (!isShiftedMask_64(I))
Akira Hatanaka854a7db2011-08-19 22:59:00 +000046 return false;
Akira Hatanakabb15e112011-08-17 02:05:42 +000047
Akira Hatanakad6bc5232011-12-05 21:26:34 +000048 Size = CountPopulation_64(I);
49 Pos = CountTrailingZeros_64(I);
Akira Hatanakadbe9a312011-08-18 20:07:42 +000050 return true;
Akira Hatanakabb15e112011-08-17 02:05:42 +000051}
52
Akira Hatanaka648f00c2012-02-24 22:34:47 +000053static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) {
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
56}
57
Chris Lattnerf0144122009-07-28 03:13:23 +000058const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
59 switch (Opcode) {
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000060 case MipsISD::JmpLink: return "MipsISD::JmpLink";
61 case MipsISD::Hi: return "MipsISD::Hi";
62 case MipsISD::Lo: return "MipsISD::Lo";
63 case MipsISD::GPRel: return "MipsISD::GPRel";
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +000064 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
Akira Hatanakabdd2ce92011-05-23 21:13:59 +000065 case MipsISD::Ret: return "MipsISD::Ret";
66 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
67 case MipsISD::FPCmp: return "MipsISD::FPCmp";
68 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
69 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
70 case MipsISD::FPRound: return "MipsISD::FPRound";
71 case MipsISD::MAdd: return "MipsISD::MAdd";
72 case MipsISD::MAddu: return "MipsISD::MAddu";
73 case MipsISD::MSub: return "MipsISD::MSub";
74 case MipsISD::MSubu: return "MipsISD::MSubu";
75 case MipsISD::DivRem: return "MipsISD::DivRem";
76 case MipsISD::DivRemU: return "MipsISD::DivRemU";
77 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
78 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
Akira Hatanakabfcb83f2011-12-12 22:38:19 +000079 case MipsISD::Wrapper: return "MipsISD::Wrapper";
Akira Hatanaka21afc632011-06-21 00:40:49 +000080 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
Akira Hatanakadb548262011-07-19 23:30:50 +000081 case MipsISD::Sync: return "MipsISD::Sync";
Akira Hatanakabb15e112011-08-17 02:05:42 +000082 case MipsISD::Ext: return "MipsISD::Ext";
83 case MipsISD::Ins: return "MipsISD::Ins";
Akira Hatanaka0f843822011-06-07 18:58:42 +000084 default: return NULL;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000085 }
86}
87
88MipsTargetLowering::
Chris Lattnerf0144122009-07-28 03:13:23 +000089MipsTargetLowering(MipsTargetMachine &TM)
Akira Hatanaka8b4198d2011-09-26 21:47:02 +000090 : TargetLowering(TM, new MipsTargetObjectFile()),
91 Subtarget(&TM.getSubtarget<MipsSubtarget>()),
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +000092 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()),
93 IsO32(Subtarget->isABI_O32()) {
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +000094
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000095 // Mips does not have i1 type, so use i32 for
Wesley Peckbf17cfa2010-11-23 03:31:01 +000096 // setcc operations results (slt, sgt, ...).
Duncan Sands03228082008-11-23 15:47:28 +000097 setBooleanContents(ZeroOrOneBooleanContent);
Duncan Sands28b77e92011-09-06 19:07:46 +000098 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +000099
100 // Set up the register classes
Craig Topper420761a2012-04-20 07:30:17 +0000101 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000102
Akira Hatanaka95934842011-09-24 01:34:44 +0000103 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000104 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass);
Akira Hatanaka95934842011-09-24 01:34:44 +0000105
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000106 if (!TM.Options.UseSoftFloat) {
Craig Topper420761a2012-04-20 07:30:17 +0000107 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000108
109 // When dealing with single precision only, use libcalls
110 if (!Subtarget->isSingleFloat()) {
111 if (HasMips64)
Craig Topper420761a2012-04-20 07:30:17 +0000112 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000113 else
Craig Topper420761a2012-04-20 07:30:17 +0000114 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
Akira Hatanakab0e7af72012-01-04 19:29:11 +0000115 }
Akira Hatanaka792016b2011-09-23 18:28:39 +0000116 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000117
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000118 // Load extented operations for i1 types must be promoted
Owen Anderson825b72b2009-08-11 20:47:22 +0000119 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
120 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
121 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000122
Eli Friedman6055a6a2009-07-17 04:07:24 +0000123 // MIPS doesn't have extending float->double load/store
Owen Anderson825b72b2009-08-11 20:47:22 +0000124 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
125 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
Eli Friedman10a36592009-07-17 02:28:12 +0000126
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000127 // Used by legalize types to correctly generate the setcc result.
128 // Without this, every float setcc comes with a AND/OR with the result,
129 // we don't want this, since the fpcmp result goes to a flag register,
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000130 // which is used implicitly by brcond and select operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000131 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +0000132
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000133 // Mips Custom Operations
Owen Anderson825b72b2009-08-11 20:47:22 +0000134 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000135 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000136 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
137 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
138 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
139 setOperationAction(ISD::SELECT, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT, MVT::f64, Custom);
141 setOperationAction(ISD::SELECT, MVT::i32, Custom);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000142 setOperationAction(ISD::SETCC, MVT::f32, Custom);
143 setOperationAction(ISD::SETCC, MVT::f64, Custom);
Owen Anderson825b72b2009-08-11 20:47:22 +0000144 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
145 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000146 setOperationAction(ISD::VASTART, MVT::Other, Custom);
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000147 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
148 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
149 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
150 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
151
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000152 if (!TM.Options.NoNaNsFPMath) {
153 setOperationAction(ISD::FABS, MVT::f32, Custom);
154 setOperationAction(ISD::FABS, MVT::f64, Custom);
155 }
156
Akira Hatanakad229b7b2012-03-10 00:03:50 +0000157 if (HasMips64) {
158 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
159 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
160 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
161 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
162 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
163 setOperationAction(ISD::SELECT, MVT::i64, Custom);
164 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
165 }
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000166
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000167 if (!HasMips64) {
168 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
169 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
170 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
171 }
172
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000173 setOperationAction(ISD::SDIV, MVT::i32, Expand);
174 setOperationAction(ISD::SREM, MVT::i32, Expand);
175 setOperationAction(ISD::UDIV, MVT::i32, Expand);
176 setOperationAction(ISD::UREM, MVT::i32, Expand);
Akira Hatanakadda4a072011-10-03 21:06:13 +0000177 setOperationAction(ISD::SDIV, MVT::i64, Expand);
178 setOperationAction(ISD::SREM, MVT::i64, Expand);
179 setOperationAction(ISD::UDIV, MVT::i64, Expand);
180 setOperationAction(ISD::UREM, MVT::i64, Expand);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000181
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000182 // Operations not directly supported by Mips.
Owen Anderson825b72b2009-08-11 20:47:22 +0000183 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
184 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
185 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
186 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000187 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000188 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
Akira Hatanakae1bcd6b2011-12-20 23:40:56 +0000189 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000190 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
191 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000192 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000193 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
Akira Hatanaka7f162742011-12-21 00:14:05 +0000194 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
Chandler Carruth63974b22011-12-13 01:56:10 +0000195 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
198 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000199 setOperationAction(ISD::ROTL, MVT::i32, Expand);
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000200 setOperationAction(ISD::ROTL, MVT::i64, Expand);
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000201
Akira Hatanaka56633442011-09-20 23:53:09 +0000202 if (!Subtarget->hasMips32r2())
Bruno Cardoso Lopes908b6dd2010-12-09 17:32:30 +0000203 setOperationAction(ISD::ROTR, MVT::i32, Expand);
204
Akira Hatanakac7bafe92011-09-30 18:51:46 +0000205 if (!Subtarget->hasMips64r2())
206 setOperationAction(ISD::ROTR, MVT::i64, Expand);
207
Owen Anderson825b72b2009-08-11 20:47:22 +0000208 setOperationAction(ISD::FSIN, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000209 setOperationAction(ISD::FSIN, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000210 setOperationAction(ISD::FCOS, MVT::f32, Expand);
Bruno Cardoso Lopes5d6fb5d2011-03-04 18:54:14 +0000211 setOperationAction(ISD::FCOS, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000212 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
213 setOperationAction(ISD::FPOW, MVT::f32, Expand);
Akira Hatanaka46da1362011-05-23 22:23:58 +0000214 setOperationAction(ISD::FPOW, MVT::f64, Expand);
Owen Anderson825b72b2009-08-11 20:47:22 +0000215 setOperationAction(ISD::FLOG, MVT::f32, Expand);
216 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
217 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
218 setOperationAction(ISD::FEXP, MVT::f32, Expand);
Cameron Zwarich33390842011-07-08 21:39:21 +0000219 setOperationAction(ISD::FMA, MVT::f32, Expand);
220 setOperationAction(ISD::FMA, MVT::f64, Expand);
Akira Hatanaka21ecc2f2012-03-29 18:43:11 +0000221 setOperationAction(ISD::FREM, MVT::f32, Expand);
222 setOperationAction(ISD::FREM, MVT::f64, Expand);
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000223
Akira Hatanaka1cc63332012-04-11 22:59:08 +0000224 if (!TM.Options.NoNaNsFPMath) {
225 setOperationAction(ISD::FNEG, MVT::f32, Expand);
226 setOperationAction(ISD::FNEG, MVT::f64, Expand);
227 }
228
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000229 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000230 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000231 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
Akira Hatanaka590baca2012-02-02 03:13:40 +0000232 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
Eric Christopher471e4222011-06-08 23:55:35 +0000233
Bruno Cardoso Lopes954dac02011-03-09 19:22:22 +0000234 setOperationAction(ISD::VAARG, MVT::Other, Expand);
235 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
236 setOperationAction(ISD::VAEND, MVT::Other, Expand);
237
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +0000238 // Use the default for now
Owen Anderson825b72b2009-08-11 20:47:22 +0000239 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
240 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
Eli Friedman14648462011-07-27 22:21:52 +0000241
Jia Liubb481f82012-02-28 07:46:26 +0000242 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
243 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
244 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
245 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
Eli Friedman4db5aca2011-08-29 18:23:02 +0000246
Eli Friedman26689ac2011-08-03 21:06:02 +0000247 setInsertFencesForAtomic(true);
248
Bruno Cardoso Lopesea9d4d62008-08-04 06:44:31 +0000249 if (Subtarget->isSingleFloat())
Owen Anderson825b72b2009-08-11 20:47:22 +0000250 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000251
Bruno Cardoso Lopes7728f7e2008-07-09 05:32:22 +0000252 if (!Subtarget->hasSEInReg()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
254 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +0000255 }
256
Akira Hatanakac79507a2011-12-21 00:20:27 +0000257 if (!Subtarget->hasBitCount()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000258 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
Akira Hatanakac79507a2011-12-21 00:20:27 +0000259 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
260 }
Bruno Cardoso Lopes65ad4522008-08-08 06:16:31 +0000261
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000262 if (!Subtarget->hasSwap()) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000263 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
Akira Hatanakac0ea0432011-12-20 23:56:43 +0000264 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
265 }
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +0000266
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000267 setTargetDAGCombine(ISD::ADDE);
268 setTargetDAGCombine(ISD::SUBE);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000269 setTargetDAGCombine(ISD::SDIVREM);
270 setTargetDAGCombine(ISD::UDIVREM);
Akira Hatanakaee8c3b02012-03-08 03:26:37 +0000271 setTargetDAGCombine(ISD::SELECT);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000272 setTargetDAGCombine(ISD::AND);
273 setTargetDAGCombine(ISD::OR);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000274
Akira Hatanaka5fdf5002012-03-08 01:59:33 +0000275 setMinFunctionAlignment(HasMips64 ? 3 : 2);
Eli Friedmanfc5d3052011-05-06 20:34:06 +0000276
Akira Hatanaka3f5b1072012-02-02 03:17:04 +0000277 setStackPointerRegisterToSaveRestore(IsN64 ? Mips::SP_64 : Mips::SP);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000278 computeRegisterProperties();
Akira Hatanakacf0cd802011-05-26 18:59:03 +0000279
Akira Hatanaka590baca2012-02-02 03:13:40 +0000280 setExceptionPointerRegister(IsN64 ? Mips::A0_64 : Mips::A0);
281 setExceptionSelectorRegister(IsN64 ? Mips::A1_64 : Mips::A1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000282}
283
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000284bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
Akira Hatanaka511961a2011-08-17 18:49:18 +0000285 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
Jia Liubb481f82012-02-28 07:46:26 +0000286
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000287 switch (SVT) {
288 case MVT::i64:
289 case MVT::i32:
290 case MVT::i16:
291 return true;
292 case MVT::f32:
Akira Hatanaka44b6c712012-02-28 02:55:02 +0000293 return Subtarget->hasMips32r2Or64();
294 default:
295 return false;
296 }
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +0000297}
298
Duncan Sands28b77e92011-09-06 19:07:46 +0000299EVT MipsTargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson825b72b2009-08-11 20:47:22 +0000300 return MVT::i32;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000301}
302
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000303// SelectMadd -
304// Transforms a subgraph in CurDAG if the following pattern is found:
305// (addc multLo, Lo0), (adde multHi, Hi0),
306// where,
307// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000308// Lo0: initial value of Lo register
309// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000310// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000311static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000312 // ADDENode's second operand must be a flag output of an ADDC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000313 // for the matching to be successful.
314 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
315
316 if (ADDCNode->getOpcode() != ISD::ADDC)
317 return false;
318
319 SDValue MultHi = ADDENode->getOperand(0);
320 SDValue MultLo = ADDCNode->getOperand(0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000321 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000322 unsigned MultOpc = MultHi.getOpcode();
323
324 // MultHi and MultLo must be generated by the same node,
325 if (MultLo.getNode() != MultNode)
326 return false;
327
328 // and it must be a multiplication.
329 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
330 return false;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000331
332 // MultLo amd MultHi must be the first and second output of MultNode
333 // respectively.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000334 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
335 return false;
336
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000337 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000338 // of the values of MultNode, in which case MultNode will be removed in later
339 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000340 // If there exist users other than ADDENode or ADDCNode, this function returns
341 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000342 // instruction node rather than a pair of MULT and MADD instructions being
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000343 // produced.
344 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
345 return false;
346
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000347 SDValue Chain = CurDAG->getEntryNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000348 DebugLoc dl = ADDENode->getDebugLoc();
349
350 // create MipsMAdd(u) node
351 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000352
Akira Hatanaka82099682011-12-19 19:52:25 +0000353 SDValue MAdd = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000354 MultNode->getOperand(0),// Factor 0
355 MultNode->getOperand(1),// Factor 1
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000356 ADDCNode->getOperand(1),// Lo0
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000357 ADDENode->getOperand(1));// Hi0
358
359 // create CopyFromReg nodes
360 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
361 MAdd);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000362 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000363 Mips::HI, MVT::i32,
364 CopyFromLo.getValue(2));
365
366 // replace uses of adde and addc here
367 if (!SDValue(ADDCNode, 0).use_empty())
368 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
369
370 if (!SDValue(ADDENode, 0).use_empty())
371 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
372
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000373 return true;
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000374}
375
376// SelectMsub -
377// Transforms a subgraph in CurDAG if the following pattern is found:
378// (addc Lo0, multLo), (sube Hi0, multHi),
379// where,
380// multHi/Lo: product of multiplication
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000381// Lo0: initial value of Lo register
382// Hi0: initial value of Hi register
Akira Hatanaka81bd78b2011-03-30 21:15:35 +0000383// Return true if pattern matching was successful.
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000384static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000385 // SUBENode's second operand must be a flag output of an SUBC node in order
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000386 // for the matching to be successful.
387 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
388
389 if (SUBCNode->getOpcode() != ISD::SUBC)
390 return false;
391
392 SDValue MultHi = SUBENode->getOperand(1);
393 SDValue MultLo = SUBCNode->getOperand(1);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000394 SDNode* MultNode = MultHi.getNode();
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000395 unsigned MultOpc = MultHi.getOpcode();
396
397 // MultHi and MultLo must be generated by the same node,
398 if (MultLo.getNode() != MultNode)
399 return false;
400
401 // and it must be a multiplication.
402 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
403 return false;
404
405 // MultLo amd MultHi must be the first and second output of MultNode
406 // respectively.
407 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
408 return false;
409
410 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
411 // of the values of MultNode, in which case MultNode will be removed in later
412 // phases.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000413 // If there exist users other than SUBENode or SUBCNode, this function returns
414 // here, which will result in MultNode being mapped to a single MULT
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000415 // instruction node rather than a pair of MULT and MSUB instructions being
416 // produced.
417 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
418 return false;
419
420 SDValue Chain = CurDAG->getEntryNode();
421 DebugLoc dl = SUBENode->getDebugLoc();
422
423 // create MipsSub(u) node
424 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
425
Akira Hatanaka82099682011-12-19 19:52:25 +0000426 SDValue MSub = CurDAG->getNode(MultOpc, dl, MVT::Glue,
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000427 MultNode->getOperand(0),// Factor 0
428 MultNode->getOperand(1),// Factor 1
429 SUBCNode->getOperand(0),// Lo0
430 SUBENode->getOperand(0));// Hi0
431
432 // create CopyFromReg nodes
433 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
434 MSub);
435 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
436 Mips::HI, MVT::i32,
437 CopyFromLo.getValue(2));
438
439 // replace uses of sube and subc here
440 if (!SDValue(SUBCNode, 0).use_empty())
441 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
442
443 if (!SDValue(SUBENode, 0).use_empty())
444 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
445
446 return true;
447}
448
449static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
450 TargetLowering::DAGCombinerInfo &DCI,
451 const MipsSubtarget* Subtarget) {
452 if (DCI.isBeforeLegalize())
453 return SDValue();
454
Akira Hatanakae184fec2011-11-11 04:18:21 +0000455 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
456 SelectMadd(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000457 return SDValue(N, 0);
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000458
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000459 return SDValue();
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000460}
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000461
462static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
463 TargetLowering::DAGCombinerInfo &DCI,
464 const MipsSubtarget* Subtarget) {
465 if (DCI.isBeforeLegalize())
466 return SDValue();
467
Akira Hatanakae184fec2011-11-11 04:18:21 +0000468 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 &&
469 SelectMsub(N, &DAG))
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000470 return SDValue(N, 0);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000471
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000472 return SDValue();
473}
474
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000475static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
476 TargetLowering::DAGCombinerInfo &DCI,
477 const MipsSubtarget* Subtarget) {
478 if (DCI.isBeforeLegalizeOps())
479 return SDValue();
480
Akira Hatanakadda4a072011-10-03 21:06:13 +0000481 EVT Ty = N->getValueType(0);
Jia Liubb481f82012-02-28 07:46:26 +0000482 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64;
483 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64;
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000484 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem :
485 MipsISD::DivRemU;
486 DebugLoc dl = N->getDebugLoc();
487
488 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue,
489 N->getOperand(0), N->getOperand(1));
490 SDValue InChain = DAG.getEntryNode();
491 SDValue InGlue = DivRem;
492
493 // insert MFLO
494 if (N->hasAnyUseOfValue(0)) {
Akira Hatanakadda4a072011-10-03 21:06:13 +0000495 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty,
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000496 InGlue);
497 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
498 InChain = CopyFromLo.getValue(1);
499 InGlue = CopyFromLo.getValue(2);
500 }
501
502 // insert MFHI
503 if (N->hasAnyUseOfValue(1)) {
504 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl,
Akira Hatanakadda4a072011-10-03 21:06:13 +0000505 HI, Ty, InGlue);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000506 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
507 }
508
509 return SDValue();
510}
511
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000512static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
513 switch (CC) {
514 default: llvm_unreachable("Unknown fp condition code!");
515 case ISD::SETEQ:
516 case ISD::SETOEQ: return Mips::FCOND_OEQ;
517 case ISD::SETUNE: return Mips::FCOND_UNE;
518 case ISD::SETLT:
519 case ISD::SETOLT: return Mips::FCOND_OLT;
520 case ISD::SETGT:
521 case ISD::SETOGT: return Mips::FCOND_OGT;
522 case ISD::SETLE:
523 case ISD::SETOLE: return Mips::FCOND_OLE;
524 case ISD::SETGE:
525 case ISD::SETOGE: return Mips::FCOND_OGE;
526 case ISD::SETULT: return Mips::FCOND_ULT;
527 case ISD::SETULE: return Mips::FCOND_ULE;
528 case ISD::SETUGT: return Mips::FCOND_UGT;
529 case ISD::SETUGE: return Mips::FCOND_UGE;
530 case ISD::SETUO: return Mips::FCOND_UN;
531 case ISD::SETO: return Mips::FCOND_OR;
532 case ISD::SETNE:
533 case ISD::SETONE: return Mips::FCOND_ONE;
534 case ISD::SETUEQ: return Mips::FCOND_UEQ;
535 }
536}
537
538
539// Returns true if condition code has to be inverted.
540static bool InvertFPCondCode(Mips::CondCode CC) {
541 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
542 return false;
543
Akira Hatanaka82099682011-12-19 19:52:25 +0000544 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
545 "Illegal Condition Code");
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000546
Akira Hatanaka82099682011-12-19 19:52:25 +0000547 return true;
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000548}
549
550// Creates and returns an FPCmp node from a setcc node.
551// Returns Op if setcc is not a floating point comparison.
552static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) {
553 // must be a SETCC node
554 if (Op.getOpcode() != ISD::SETCC)
555 return Op;
556
557 SDValue LHS = Op.getOperand(0);
558
559 if (!LHS.getValueType().isFloatingPoint())
560 return Op;
561
562 SDValue RHS = Op.getOperand(1);
563 DebugLoc dl = Op.getDebugLoc();
564
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +0000565 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
566 // node if necessary.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000567 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
568
569 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS,
570 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
571}
572
573// Creates and returns a CMovFPT/F node.
574static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True,
575 SDValue False, DebugLoc DL) {
576 bool invert = InvertFPCondCode((Mips::CondCode)
577 cast<ConstantSDNode>(Cond.getOperand(2))
578 ->getSExtValue());
579
580 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
581 True.getValueType(), True, False, Cond);
582}
583
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000584static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG& DAG,
585 TargetLowering::DAGCombinerInfo &DCI,
586 const MipsSubtarget* Subtarget) {
587 if (DCI.isBeforeLegalizeOps())
588 return SDValue();
589
590 SDValue SetCC = N->getOperand(0);
591
592 if ((SetCC.getOpcode() != ISD::SETCC) ||
593 !SetCC.getOperand(0).getValueType().isInteger())
594 return SDValue();
595
596 SDValue False = N->getOperand(2);
597 EVT FalseTy = False.getValueType();
598
599 if (!FalseTy.isInteger())
600 return SDValue();
601
602 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False);
603
604 if (!CN || CN->getZExtValue())
605 return SDValue();
606
607 const DebugLoc DL = N->getDebugLoc();
608 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
609 SDValue True = N->getOperand(1);
610
611 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
612 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
613
614 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
615}
616
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000617static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
618 TargetLowering::DAGCombinerInfo &DCI,
619 const MipsSubtarget* Subtarget) {
620 // Pattern match EXT.
621 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
622 // => ext $dst, $src, size, pos
Akira Hatanaka56633442011-09-20 23:53:09 +0000623 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000624 return SDValue();
625
626 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000627 unsigned ShiftRightOpc = ShiftRight.getOpcode();
628
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000629 // Op's first operand must be a shift right.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000630 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000631 return SDValue();
632
633 // The second operand of the shift must be an immediate.
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000634 ConstantSDNode *CN;
635 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
636 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000637
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000638 uint64_t Pos = CN->getZExtValue();
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000639 uint64_t SMPos, SMSize;
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000640
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000641 // Op's second operand must be a shifted mask.
642 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000643 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000644 return SDValue();
645
646 // Return if the shifted mask does not start at bit 0 or the sum of its size
647 // and Pos exceeds the word's size.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000648 EVT ValTy = N->getValueType(0);
649 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000650 return SDValue();
651
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000652 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), ValTy,
Akira Hatanaka82099682011-12-19 19:52:25 +0000653 ShiftRight.getOperand(0), DAG.getConstant(Pos, MVT::i32),
Akira Hatanaka667645f2011-08-17 22:59:46 +0000654 DAG.getConstant(SMSize, MVT::i32));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000655}
Jia Liubb481f82012-02-28 07:46:26 +0000656
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000657static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
658 TargetLowering::DAGCombinerInfo &DCI,
659 const MipsSubtarget* Subtarget) {
660 // Pattern match INS.
661 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
Jia Liubb481f82012-02-28 07:46:26 +0000662 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000663 // => ins $dst, $src, size, pos, $src1
Akira Hatanaka56633442011-09-20 23:53:09 +0000664 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2())
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000665 return SDValue();
666
667 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
668 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
669 ConstantSDNode *CN;
670
671 // See if Op's first operand matches (and $src1 , mask0).
672 if (And0.getOpcode() != ISD::AND)
673 return SDValue();
674
675 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000676 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000677 return SDValue();
678
679 // See if Op's second operand matches (and (shl $src, pos), mask1).
680 if (And1.getOpcode() != ISD::AND)
681 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000682
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000683 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
Akira Hatanaka854a7db2011-08-19 22:59:00 +0000684 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000685 return SDValue();
686
687 // The shift masks must have the same position and size.
688 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
689 return SDValue();
690
691 SDValue Shl = And1.getOperand(0);
692 if (Shl.getOpcode() != ISD::SHL)
693 return SDValue();
694
695 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
696 return SDValue();
697
698 unsigned Shamt = CN->getZExtValue();
699
700 // Return if the shift amount and the first bit position of mask are not the
Jia Liubb481f82012-02-28 07:46:26 +0000701 // same.
Akira Hatanakad6bc5232011-12-05 21:26:34 +0000702 EVT ValTy = N->getValueType(0);
703 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000704 return SDValue();
Jia Liubb481f82012-02-28 07:46:26 +0000705
Akira Hatanaka82099682011-12-19 19:52:25 +0000706 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), ValTy, Shl.getOperand(0),
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000707 DAG.getConstant(SMPos0, MVT::i32),
Akira Hatanaka82099682011-12-19 19:52:25 +0000708 DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000709}
Jia Liubb481f82012-02-28 07:46:26 +0000710
Bruno Cardoso Lopes8e826e62011-02-10 18:05:10 +0000711SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000712 const {
713 SelectionDAG &DAG = DCI.DAG;
714 unsigned opc = N->getOpcode();
715
716 switch (opc) {
717 default: break;
718 case ISD::ADDE:
719 return PerformADDECombine(N, DAG, DCI, Subtarget);
720 case ISD::SUBE:
721 return PerformSUBECombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes38b5e862011-03-04 21:03:24 +0000722 case ISD::SDIVREM:
723 case ISD::UDIVREM:
724 return PerformDivRemCombine(N, DAG, DCI, Subtarget);
Akira Hatanakae2bdf7f2012-03-08 02:14:24 +0000725 case ISD::SELECT:
726 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka77b85b62011-08-17 17:45:08 +0000727 case ISD::AND:
728 return PerformANDCombine(N, DAG, DCI, Subtarget);
729 case ISD::OR:
730 return PerformORCombine(N, DAG, DCI, Subtarget);
Bruno Cardoso Lopes8be76112011-01-18 19:29:17 +0000731 }
732
733 return SDValue();
734}
735
Dan Gohman475871a2008-07-27 21:46:04 +0000736SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +0000737LowerOperation(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000738{
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000739 switch (Op.getOpcode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000740 {
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000741 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000742 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
743 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000744 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +0000745 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000746 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
747 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +0000748 case ISD::SELECT: return LowerSELECT(Op, DAG);
Akira Hatanaka0a40c232012-03-09 23:46:03 +0000749 case ISD::SETCC: return LowerSETCC(Op, DAG);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +0000750 case ISD::VASTART: return LowerVASTART(Op, DAG);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +0000751 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
Akira Hatanakac12a6e62012-04-11 22:49:04 +0000752 case ISD::FABS: return LowerFABS(Op, DAG);
Akira Hatanaka2e591472011-06-02 00:24:44 +0000753 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
Akira Hatanakadb548262011-07-19 23:30:50 +0000754 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG);
Eli Friedman14648462011-07-27 22:21:52 +0000755 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
Akira Hatanakaa284acb2012-05-09 00:55:21 +0000756 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
757 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, true);
758 case ISD::SRL_PARTS: return LowerShiftRightParts(Op, DAG, false);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000759 }
Dan Gohman475871a2008-07-27 21:46:04 +0000760 return SDValue();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000761}
762
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000763//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000764// Lower helper functions
Akira Hatanaka4552c9a2011-04-15 21:51:11 +0000765//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000766
767// AddLiveIn - This helper function adds the specified physical register to the
768// MachineFunction as a live in value. It also creates a corresponding
769// virtual register for it.
770static unsigned
Craig Topper44d23822012-02-22 05:59:10 +0000771AddLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000772{
773 assert(RC->contains(PReg) && "Not the correct regclass!");
Chris Lattner84bc5422007-12-31 04:13:23 +0000774 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
775 MF.getRegInfo().addLiveIn(PReg, VReg);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +0000776 return VReg;
777}
778
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000779// Get fp branch code (not opcode) from condition code.
780static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
781 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
782 return Mips::BRANCH_T;
783
Akira Hatanaka82099682011-12-19 19:52:25 +0000784 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
785 "Invalid CondCode.");
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000786
Akira Hatanaka82099682011-12-19 19:52:25 +0000787 return Mips::BRANCH_F;
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +0000788}
Wesley Peckbf17cfa2010-11-23 03:31:01 +0000789
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000790/*
Akira Hatanaka14487d42011-06-07 19:28:39 +0000791static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB,
792 DebugLoc dl,
793 const MipsSubtarget* Subtarget,
794 const TargetInstrInfo *TII,
795 bool isFPCmp, unsigned Opc) {
796 // There is no need to expand CMov instructions if target has
797 // conditional moves.
798 if (Subtarget->hasCondMov())
799 return BB;
800
801 // To "insert" a SELECT_CC instruction, we actually have to insert the
802 // diamond control-flow pattern. The incoming instruction knows the
803 // destination vreg to set, the condition code register to branch on, the
804 // true/false values to select between, and a branch opcode to use.
805 const BasicBlock *LLVM_BB = BB->getBasicBlock();
806 MachineFunction::iterator It = BB;
807 ++It;
808
809 // thisMBB:
810 // ...
811 // TrueVal = ...
812 // setcc r1, r2, r3
813 // bNE r1, r0, copy1MBB
814 // fallthrough --> copy0MBB
815 MachineBasicBlock *thisMBB = BB;
816 MachineFunction *F = BB->getParent();
817 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
818 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
819 F->insert(It, copy0MBB);
820 F->insert(It, sinkMBB);
821
822 // Transfer the remainder of BB and its successor edges to sinkMBB.
823 sinkMBB->splice(sinkMBB->begin(), BB,
824 llvm::next(MachineBasicBlock::iterator(MI)),
825 BB->end());
826 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
827
828 // Next, add the true and fallthrough blocks as its successors.
829 BB->addSuccessor(copy0MBB);
830 BB->addSuccessor(sinkMBB);
831
832 // Emit the right instruction according to the type of the operands compared
833 if (isFPCmp)
834 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
835 else
836 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg())
837 .addReg(Mips::ZERO).addMBB(sinkMBB);
838
839 // copy0MBB:
840 // %FalseValue = ...
841 // # fallthrough to sinkMBB
842 BB = copy0MBB;
843
844 // Update machine-CFG edges
845 BB->addSuccessor(sinkMBB);
846
847 // sinkMBB:
848 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
849 // ...
850 BB = sinkMBB;
851
852 if (isFPCmp)
853 BuildMI(*BB, BB->begin(), dl,
854 TII->get(Mips::PHI), MI->getOperand(0).getReg())
855 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
856 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
857 else
858 BuildMI(*BB, BB->begin(), dl,
859 TII->get(Mips::PHI), MI->getOperand(0).getReg())
860 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB)
861 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB);
862
863 MI->eraseFromParent(); // The pseudo instruction is gone now.
864 return BB;
865}
Akira Hatanaka8ae330a2011-10-17 18:53:29 +0000866*/
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000867MachineBasicBlock *
868MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000869 MachineBasicBlock *BB) const {
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000870 switch (MI->getOpcode()) {
Craig Topperbc219812012-02-07 02:50:20 +0000871 default: llvm_unreachable("Unexpected instr type to insert");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000872 case Mips::ATOMIC_LOAD_ADD_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000873 case Mips::ATOMIC_LOAD_ADD_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000874 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
875 case Mips::ATOMIC_LOAD_ADD_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000876 case Mips::ATOMIC_LOAD_ADD_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000877 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
878 case Mips::ATOMIC_LOAD_ADD_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000879 case Mips::ATOMIC_LOAD_ADD_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000880 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000881 case Mips::ATOMIC_LOAD_ADD_I64:
882 case Mips::ATOMIC_LOAD_ADD_I64_P8:
883 return EmitAtomicBinary(MI, BB, 8, Mips::DADDu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000884
885 case Mips::ATOMIC_LOAD_AND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000886 case Mips::ATOMIC_LOAD_AND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000887 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
888 case Mips::ATOMIC_LOAD_AND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000889 case Mips::ATOMIC_LOAD_AND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000890 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
891 case Mips::ATOMIC_LOAD_AND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000892 case Mips::ATOMIC_LOAD_AND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000893 return EmitAtomicBinary(MI, BB, 4, Mips::AND);
Akira Hatanaka59068062011-11-11 04:14:30 +0000894 case Mips::ATOMIC_LOAD_AND_I64:
895 case Mips::ATOMIC_LOAD_AND_I64_P8:
Akira Hatanaka73866122011-11-12 02:38:12 +0000896 return EmitAtomicBinary(MI, BB, 8, Mips::AND64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000897
898 case Mips::ATOMIC_LOAD_OR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000899 case Mips::ATOMIC_LOAD_OR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000900 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
901 case Mips::ATOMIC_LOAD_OR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000902 case Mips::ATOMIC_LOAD_OR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000903 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
904 case Mips::ATOMIC_LOAD_OR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000905 case Mips::ATOMIC_LOAD_OR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000906 return EmitAtomicBinary(MI, BB, 4, Mips::OR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000907 case Mips::ATOMIC_LOAD_OR_I64:
908 case Mips::ATOMIC_LOAD_OR_I64_P8:
909 return EmitAtomicBinary(MI, BB, 8, Mips::OR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000910
911 case Mips::ATOMIC_LOAD_XOR_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000912 case Mips::ATOMIC_LOAD_XOR_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000913 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
914 case Mips::ATOMIC_LOAD_XOR_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000915 case Mips::ATOMIC_LOAD_XOR_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000916 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
917 case Mips::ATOMIC_LOAD_XOR_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000918 case Mips::ATOMIC_LOAD_XOR_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000919 return EmitAtomicBinary(MI, BB, 4, Mips::XOR);
Akira Hatanaka59068062011-11-11 04:14:30 +0000920 case Mips::ATOMIC_LOAD_XOR_I64:
921 case Mips::ATOMIC_LOAD_XOR_I64_P8:
922 return EmitAtomicBinary(MI, BB, 8, Mips::XOR64);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000923
924 case Mips::ATOMIC_LOAD_NAND_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000925 case Mips::ATOMIC_LOAD_NAND_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000926 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true);
927 case Mips::ATOMIC_LOAD_NAND_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000928 case Mips::ATOMIC_LOAD_NAND_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000929 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true);
930 case Mips::ATOMIC_LOAD_NAND_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000931 case Mips::ATOMIC_LOAD_NAND_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000932 return EmitAtomicBinary(MI, BB, 4, 0, true);
Akira Hatanaka59068062011-11-11 04:14:30 +0000933 case Mips::ATOMIC_LOAD_NAND_I64:
934 case Mips::ATOMIC_LOAD_NAND_I64_P8:
935 return EmitAtomicBinary(MI, BB, 8, 0, true);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000936
937 case Mips::ATOMIC_LOAD_SUB_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000938 case Mips::ATOMIC_LOAD_SUB_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000939 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
940 case Mips::ATOMIC_LOAD_SUB_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000941 case Mips::ATOMIC_LOAD_SUB_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000942 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
943 case Mips::ATOMIC_LOAD_SUB_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000944 case Mips::ATOMIC_LOAD_SUB_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000945 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu);
Akira Hatanaka59068062011-11-11 04:14:30 +0000946 case Mips::ATOMIC_LOAD_SUB_I64:
947 case Mips::ATOMIC_LOAD_SUB_I64_P8:
948 return EmitAtomicBinary(MI, BB, 8, Mips::DSUBu);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000949
950 case Mips::ATOMIC_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000951 case Mips::ATOMIC_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000952 return EmitAtomicBinaryPartword(MI, BB, 1, 0);
953 case Mips::ATOMIC_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000954 case Mips::ATOMIC_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000955 return EmitAtomicBinaryPartword(MI, BB, 2, 0);
956 case Mips::ATOMIC_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000957 case Mips::ATOMIC_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000958 return EmitAtomicBinary(MI, BB, 4, 0);
Akira Hatanaka59068062011-11-11 04:14:30 +0000959 case Mips::ATOMIC_SWAP_I64:
960 case Mips::ATOMIC_SWAP_I64_P8:
961 return EmitAtomicBinary(MI, BB, 8, 0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000962
963 case Mips::ATOMIC_CMP_SWAP_I8:
Akira Hatanaka59068062011-11-11 04:14:30 +0000964 case Mips::ATOMIC_CMP_SWAP_I8_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000965 return EmitAtomicCmpSwapPartword(MI, BB, 1);
966 case Mips::ATOMIC_CMP_SWAP_I16:
Akira Hatanaka59068062011-11-11 04:14:30 +0000967 case Mips::ATOMIC_CMP_SWAP_I16_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000968 return EmitAtomicCmpSwapPartword(MI, BB, 2);
969 case Mips::ATOMIC_CMP_SWAP_I32:
Akira Hatanaka59068062011-11-11 04:14:30 +0000970 case Mips::ATOMIC_CMP_SWAP_I32_P8:
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000971 return EmitAtomicCmpSwap(MI, BB, 4);
Akira Hatanaka59068062011-11-11 04:14:30 +0000972 case Mips::ATOMIC_CMP_SWAP_I64:
973 case Mips::ATOMIC_CMP_SWAP_I64_P8:
974 return EmitAtomicCmpSwap(MI, BB, 8);
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +0000975 }
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +0000976}
977
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000978// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
979// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
980MachineBasicBlock *
981MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
Eric Christopher471e4222011-06-08 23:55:35 +0000982 unsigned Size, unsigned BinOpcode,
Akira Hatanaka0f843822011-06-07 18:58:42 +0000983 bool Nand) const {
Akira Hatanaka59068062011-11-11 04:14:30 +0000984 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000985
986 MachineFunction *MF = BB->getParent();
987 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +0000988 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +0000989 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
990 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +0000991 unsigned LL, SC, AND, NOR, ZERO, BEQ;
992
993 if (Size == 4) {
994 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
995 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
996 AND = Mips::AND;
997 NOR = Mips::NOR;
998 ZERO = Mips::ZERO;
999 BEQ = Mips::BEQ;
1000 }
1001 else {
1002 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1003 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1004 AND = Mips::AND64;
1005 NOR = Mips::NOR64;
1006 ZERO = Mips::ZERO_64;
1007 BEQ = Mips::BEQ64;
1008 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001009
Akira Hatanaka4061da12011-07-19 20:11:17 +00001010 unsigned OldVal = MI->getOperand(0).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001011 unsigned Ptr = MI->getOperand(1).getReg();
1012 unsigned Incr = MI->getOperand(2).getReg();
1013
Akira Hatanaka4061da12011-07-19 20:11:17 +00001014 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1015 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1016 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001017
1018 // insert new blocks after the current block
1019 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1020 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1021 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1022 MachineFunction::iterator It = BB;
1023 ++It;
1024 MF->insert(It, loopMBB);
1025 MF->insert(It, exitMBB);
1026
1027 // Transfer the remainder of BB and its successor edges to exitMBB.
1028 exitMBB->splice(exitMBB->begin(), BB,
1029 llvm::next(MachineBasicBlock::iterator(MI)),
1030 BB->end());
1031 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1032
1033 // thisMBB:
1034 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001035 // fallthrough --> loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001036 BB->addSuccessor(loopMBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001037 loopMBB->addSuccessor(loopMBB);
1038 loopMBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001039
1040 // loopMBB:
1041 // ll oldval, 0(ptr)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001042 // <binop> storeval, oldval, incr
1043 // sc success, storeval, 0(ptr)
1044 // beq success, $0, loopMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001045 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001046 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001047 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001048 // and andres, oldval, incr
1049 // nor storeval, $0, andres
Akira Hatanaka59068062011-11-11 04:14:30 +00001050 BuildMI(BB, dl, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1051 BuildMI(BB, dl, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001052 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001053 // <binop> storeval, oldval, incr
1054 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001055 } else {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001056 StoreVal = Incr;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001057 }
Akira Hatanaka59068062011-11-11 04:14:30 +00001058 BuildMI(BB, dl, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1059 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001060
1061 MI->eraseFromParent(); // The instruction is gone now.
1062
Akira Hatanaka939ece12011-07-19 03:42:13 +00001063 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001064}
1065
1066MachineBasicBlock *
1067MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001068 MachineBasicBlock *BB,
1069 unsigned Size, unsigned BinOpcode,
1070 bool Nand) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001071 assert((Size == 1 || Size == 2) &&
1072 "Unsupported size for EmitAtomicBinaryPartial.");
1073
1074 MachineFunction *MF = BB->getParent();
1075 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1076 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1077 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1078 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001079 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1080 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001081
1082 unsigned Dest = MI->getOperand(0).getReg();
1083 unsigned Ptr = MI->getOperand(1).getReg();
1084 unsigned Incr = MI->getOperand(2).getReg();
1085
Akira Hatanaka4061da12011-07-19 20:11:17 +00001086 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1087 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001088 unsigned Mask = RegInfo.createVirtualRegister(RC);
1089 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001090 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1091 unsigned OldVal = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001092 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001093 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1094 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1095 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1096 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1097 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001098 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001099 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1100 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1101 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1102 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1103 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001104
1105 // insert new blocks after the current block
1106 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1107 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001108 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001109 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1110 MachineFunction::iterator It = BB;
1111 ++It;
1112 MF->insert(It, loopMBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001113 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001114 MF->insert(It, exitMBB);
1115
1116 // Transfer the remainder of BB and its successor edges to exitMBB.
1117 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001118 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001119 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1120
Akira Hatanaka81b44112011-07-19 17:09:53 +00001121 BB->addSuccessor(loopMBB);
1122 loopMBB->addSuccessor(loopMBB);
1123 loopMBB->addSuccessor(sinkMBB);
1124 sinkMBB->addSuccessor(exitMBB);
1125
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001126 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001127 // addiu masklsb2,$0,-4 # 0xfffffffc
1128 // and alignedaddr,ptr,masklsb2
1129 // andi ptrlsb2,ptr,3
1130 // sll shiftamt,ptrlsb2,3
1131 // ori maskupper,$0,255 # 0xff
1132 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001133 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001134 // sll incr2,incr,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001135
1136 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001137 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1138 .addReg(Mips::ZERO).addImm(-4);
1139 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1140 .addReg(Ptr).addReg(MaskLSB2);
1141 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1142 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1143 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1144 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001145 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1146 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001147 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001148 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr);
Bruno Cardoso Lopescada2d02011-05-31 20:25:26 +00001149
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001150 // atomic.load.binop
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001151 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001152 // ll oldval,0(alignedaddr)
1153 // binop binopres,oldval,incr2
1154 // and newval,binopres,mask
1155 // and maskedoldval0,oldval,mask2
1156 // or storeval,maskedoldval0,newval
1157 // sc success,storeval,0(alignedaddr)
1158 // beq success,$0,loopMBB
1159
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001160 // atomic.swap
1161 // loopMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001162 // ll oldval,0(alignedaddr)
Akira Hatanaka70564a92011-07-19 18:14:26 +00001163 // and newval,incr2,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001164 // and maskedoldval0,oldval,mask2
1165 // or storeval,maskedoldval0,newval
1166 // sc success,storeval,0(alignedaddr)
1167 // beq success,$0,loopMBB
Akira Hatanaka0d7d0b52011-07-18 18:52:12 +00001168
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001169 BB = loopMBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001170 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001171 if (Nand) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001172 // and andres, oldval, incr2
1173 // nor binopres, $0, andres
1174 // and newval, binopres, mask
1175 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1176 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes)
1177 .addReg(Mips::ZERO).addReg(AndRes);
1178 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001179 } else if (BinOpcode) {
Akira Hatanaka4061da12011-07-19 20:11:17 +00001180 // <binop> binopres, oldval, incr2
1181 // and newval, binopres, mask
1182 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1183 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001184 } else {// atomic.swap
Akira Hatanaka4061da12011-07-19 20:11:17 +00001185 // and newval, incr2, mask
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001186 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
Akira Hatanaka70564a92011-07-19 18:14:26 +00001187 }
Jia Liubb481f82012-02-28 07:46:26 +00001188
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001189 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001190 .addReg(OldVal).addReg(Mask2);
1191 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
Akira Hatanakabdd83fe2011-07-19 20:56:53 +00001192 .addReg(MaskedOldVal0).addReg(NewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001193 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001194 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001195 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001196 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001197
Akira Hatanaka939ece12011-07-19 03:42:13 +00001198 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001199 // and maskedoldval1,oldval,mask
1200 // srl srlres,maskedoldval1,shiftamt
1201 // sll sllres,srlres,24
1202 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001203 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001204 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001205
Akira Hatanaka4061da12011-07-19 20:11:17 +00001206 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1207 .addReg(OldVal).addReg(Mask);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001208 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1209 .addReg(ShiftAmt).addReg(MaskedOldVal1);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001210 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1211 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001212 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001213 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001214
1215 MI->eraseFromParent(); // The instruction is gone now.
1216
Akira Hatanaka939ece12011-07-19 03:42:13 +00001217 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001218}
1219
1220MachineBasicBlock *
1221MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001222 MachineBasicBlock *BB,
1223 unsigned Size) const {
Akira Hatanaka59068062011-11-11 04:14:30 +00001224 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001225
1226 MachineFunction *MF = BB->getParent();
1227 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Akira Hatanaka59068062011-11-11 04:14:30 +00001228 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001229 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1230 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001231 unsigned LL, SC, ZERO, BNE, BEQ;
1232
1233 if (Size == 4) {
1234 LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1235 SC = IsN64 ? Mips::SC_P8 : Mips::SC;
1236 ZERO = Mips::ZERO;
1237 BNE = Mips::BNE;
1238 BEQ = Mips::BEQ;
1239 }
1240 else {
1241 LL = IsN64 ? Mips::LLD_P8 : Mips::LLD;
1242 SC = IsN64 ? Mips::SCD_P8 : Mips::SCD;
1243 ZERO = Mips::ZERO_64;
1244 BNE = Mips::BNE64;
1245 BEQ = Mips::BEQ64;
1246 }
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001247
1248 unsigned Dest = MI->getOperand(0).getReg();
1249 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001250 unsigned OldVal = MI->getOperand(2).getReg();
1251 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001252
Akira Hatanaka4061da12011-07-19 20:11:17 +00001253 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001254
1255 // insert new blocks after the current block
1256 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1257 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1258 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1259 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1260 MachineFunction::iterator It = BB;
1261 ++It;
1262 MF->insert(It, loop1MBB);
1263 MF->insert(It, loop2MBB);
1264 MF->insert(It, exitMBB);
1265
1266 // Transfer the remainder of BB and its successor edges to exitMBB.
1267 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001268 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001269 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1270
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001271 // thisMBB:
1272 // ...
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001273 // fallthrough --> loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001274 BB->addSuccessor(loop1MBB);
Akira Hatanaka81b44112011-07-19 17:09:53 +00001275 loop1MBB->addSuccessor(exitMBB);
1276 loop1MBB->addSuccessor(loop2MBB);
1277 loop2MBB->addSuccessor(loop1MBB);
1278 loop2MBB->addSuccessor(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001279
1280 // loop1MBB:
1281 // ll dest, 0(ptr)
1282 // bne dest, oldval, exitMBB
1283 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001284 BuildMI(BB, dl, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1285 BuildMI(BB, dl, TII->get(BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001286 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001287
1288 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001289 // sc success, newval, 0(ptr)
1290 // beq success, $0, loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001291 BB = loop2MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001292 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001293 .addReg(NewVal).addReg(Ptr).addImm(0);
Akira Hatanaka59068062011-11-11 04:14:30 +00001294 BuildMI(BB, dl, TII->get(BEQ))
1295 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001296
1297 MI->eraseFromParent(); // The instruction is gone now.
1298
Akira Hatanaka939ece12011-07-19 03:42:13 +00001299 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001300}
1301
1302MachineBasicBlock *
1303MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
Akira Hatanaka0f843822011-06-07 18:58:42 +00001304 MachineBasicBlock *BB,
1305 unsigned Size) const {
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001306 assert((Size == 1 || Size == 2) &&
1307 "Unsupported size for EmitAtomicCmpSwapPartial.");
1308
1309 MachineFunction *MF = BB->getParent();
1310 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1311 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1313 DebugLoc dl = MI->getDebugLoc();
Akira Hatanaka59068062011-11-11 04:14:30 +00001314 unsigned LL = IsN64 ? Mips::LL_P8 : Mips::LL;
1315 unsigned SC = IsN64 ? Mips::SC_P8 : Mips::SC;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001316
1317 unsigned Dest = MI->getOperand(0).getReg();
1318 unsigned Ptr = MI->getOperand(1).getReg();
Akira Hatanaka4061da12011-07-19 20:11:17 +00001319 unsigned CmpVal = MI->getOperand(2).getReg();
1320 unsigned NewVal = MI->getOperand(3).getReg();
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001321
Akira Hatanaka4061da12011-07-19 20:11:17 +00001322 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1323 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001324 unsigned Mask = RegInfo.createVirtualRegister(RC);
1325 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001326 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1327 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1328 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1329 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1330 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1331 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1332 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1333 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1334 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1335 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1336 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1337 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1338 unsigned SllRes = RegInfo.createVirtualRegister(RC);
1339 unsigned Success = RegInfo.createVirtualRegister(RC);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001340
1341 // insert new blocks after the current block
1342 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1343 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1344 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001345 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001346 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1347 MachineFunction::iterator It = BB;
1348 ++It;
1349 MF->insert(It, loop1MBB);
1350 MF->insert(It, loop2MBB);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001351 MF->insert(It, sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001352 MF->insert(It, exitMBB);
1353
1354 // Transfer the remainder of BB and its successor edges to exitMBB.
1355 exitMBB->splice(exitMBB->begin(), BB,
Akira Hatanaka82099682011-12-19 19:52:25 +00001356 llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001357 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1358
Akira Hatanaka81b44112011-07-19 17:09:53 +00001359 BB->addSuccessor(loop1MBB);
1360 loop1MBB->addSuccessor(sinkMBB);
1361 loop1MBB->addSuccessor(loop2MBB);
1362 loop2MBB->addSuccessor(loop1MBB);
1363 loop2MBB->addSuccessor(sinkMBB);
1364 sinkMBB->addSuccessor(exitMBB);
1365
Akira Hatanaka70564a92011-07-19 18:14:26 +00001366 // FIXME: computation of newval2 can be moved to loop2MBB.
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001367 // thisMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001368 // addiu masklsb2,$0,-4 # 0xfffffffc
1369 // and alignedaddr,ptr,masklsb2
1370 // andi ptrlsb2,ptr,3
1371 // sll shiftamt,ptrlsb2,3
1372 // ori maskupper,$0,255 # 0xff
1373 // sll mask,maskupper,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001374 // nor mask2,$0,mask
Akira Hatanaka4061da12011-07-19 20:11:17 +00001375 // andi maskedcmpval,cmpval,255
1376 // sll shiftedcmpval,maskedcmpval,shiftamt
1377 // andi maskednewval,newval,255
1378 // sll shiftednewval,maskednewval,shiftamt
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001379 int64_t MaskImm = (Size == 1) ? 255 : 65535;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001380 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2)
1381 .addReg(Mips::ZERO).addImm(-4);
1382 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr)
1383 .addReg(Ptr).addReg(MaskLSB2);
1384 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1385 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1386 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper)
1387 .addReg(Mips::ZERO).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001388 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask)
1389 .addReg(ShiftAmt).addReg(MaskUpper);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001390 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001391 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal)
1392 .addReg(CmpVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001393 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal)
1394 .addReg(ShiftAmt).addReg(MaskedCmpVal);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001395 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal)
1396 .addReg(NewVal).addImm(MaskImm);
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001397 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal)
1398 .addReg(ShiftAmt).addReg(MaskedNewVal);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001399
1400 // loop1MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001401 // ll oldval,0(alginedaddr)
1402 // and maskedoldval0,oldval,mask
1403 // bne maskedoldval0,shiftedcmpval,sinkMBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001404 BB = loop1MBB;
Akira Hatanaka59068062011-11-11 04:14:30 +00001405 BuildMI(BB, dl, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001406 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0)
1407 .addReg(OldVal).addReg(Mask);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001408 BuildMI(BB, dl, TII->get(Mips::BNE))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001409 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001410
1411 // loop2MBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001412 // and maskedoldval1,oldval,mask2
1413 // or storeval,maskedoldval1,shiftednewval
1414 // sc success,storeval,0(alignedaddr)
1415 // beq success,$0,loop1MBB
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001416 BB = loop2MBB;
Akira Hatanaka4061da12011-07-19 20:11:17 +00001417 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1)
1418 .addReg(OldVal).addReg(Mask2);
1419 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal)
1420 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
Akira Hatanaka59068062011-11-11 04:14:30 +00001421 BuildMI(BB, dl, TII->get(SC), Success)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001422 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001423 BuildMI(BB, dl, TII->get(Mips::BEQ))
Akira Hatanaka4061da12011-07-19 20:11:17 +00001424 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001425
Akira Hatanaka939ece12011-07-19 03:42:13 +00001426 // sinkMBB:
Akira Hatanaka4061da12011-07-19 20:11:17 +00001427 // srl srlres,maskedoldval0,shiftamt
1428 // sll sllres,srlres,24
1429 // sra dest,sllres,24
Akira Hatanaka939ece12011-07-19 03:42:13 +00001430 BB = sinkMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001431 int64_t ShiftImm = (Size == 1) ? 24 : 16;
Akira Hatanakaa308c672011-07-19 03:14:58 +00001432
Akira Hatanakacc7ecc72011-07-19 20:34:00 +00001433 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes)
1434 .addReg(ShiftAmt).addReg(MaskedOldVal0);
Akira Hatanaka4061da12011-07-19 20:11:17 +00001435 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1436 .addReg(SrlRes).addImm(ShiftImm);
Akira Hatanaka939ece12011-07-19 03:42:13 +00001437 BuildMI(BB, dl, TII->get(Mips::SRA), Dest)
Akira Hatanaka4061da12011-07-19 20:11:17 +00001438 .addReg(SllRes).addImm(ShiftImm);
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001439
1440 MI->eraseFromParent(); // The instruction is gone now.
1441
Akira Hatanaka939ece12011-07-19 03:42:13 +00001442 return exitMBB;
Bruno Cardoso Lopes4e694c92011-05-31 02:54:07 +00001443}
1444
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001445//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00001446// Misc Lower Operation implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001447//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesd3bdf192009-05-27 17:23:44 +00001448SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001449LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001450{
Akira Hatanaka21afc632011-06-21 00:40:49 +00001451 MachineFunction &MF = DAG.getMachineFunction();
1452 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001453 unsigned SP = IsN64 ? Mips::SP_64 : Mips::SP;
Akira Hatanaka21afc632011-06-21 00:40:49 +00001454
1455 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
Akira Hatanaka053546c2011-05-25 02:20:00 +00001456 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
1457 "Cannot lower if the alignment of the allocated space is larger than \
1458 that of the stack.");
1459
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001460 SDValue Chain = Op.getOperand(0);
1461 SDValue Size = Op.getOperand(1);
Dale Johannesena05dca42009-02-04 23:02:30 +00001462 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001463
1464 // Get a reference from Mips stack pointer
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001465 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SP, getPointerTy());
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001466
1467 // Subtract the dynamic size from the actual stack size to
1468 // obtain the new stack size.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001469 SDValue Sub = DAG.getNode(ISD::SUB, dl, getPointerTy(), StackPointer, Size);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001470
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001471 // The Sub result contains the new stack start address, so it
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001472 // must be placed in the stack pointer register.
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001473 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, SP, Sub, SDValue());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001474
1475 // This node always has two return values: a new stack pointer
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001476 // value and a chain
Akira Hatanakac742e4f2011-11-11 04:06:38 +00001477 SDVTList VTLs = DAG.getVTList(getPointerTy(), MVT::Other);
Akira Hatanaka21afc632011-06-21 00:40:49 +00001478 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
1479 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
1480
1481 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
Bruno Cardoso Lopes7da151c2008-08-07 19:08:11 +00001482}
1483
1484SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001485LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001486{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001487 // The first operand is the chain, the second is the condition, the third is
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001488 // the block to branch to if the condition is true.
1489 SDValue Chain = Op.getOperand(0);
1490 SDValue Dest = Op.getOperand(2);
Dale Johannesende064702009-02-06 21:50:26 +00001491 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001492
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001493 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1));
1494
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001495 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001496 if (CondRes.getOpcode() != MipsISD::FPCmp)
Bruno Cardoso Lopes4b877ca2008-07-30 17:06:13 +00001497 return Op;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001498
Bruno Cardoso Lopes77283772008-07-31 18:31:28 +00001499 SDValue CCNode = CondRes.getOperand(2);
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +00001500 Mips::CondCode CC =
1501 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001502 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001503
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001504 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001505 Dest, CondRes);
Bruno Cardoso Lopes85e31e32008-07-28 19:11:24 +00001506}
1507
1508SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001509LowerSELECT(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001510{
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001511 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0));
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001512
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001513 // Return if flag is not set by a floating point comparison.
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001514 if (Cond.getOpcode() != MipsISD::FPCmp)
1515 return Op;
Bruno Cardoso Lopes739e4412008-08-13 07:13:40 +00001516
Akira Hatanaka1d6b38d2011-03-31 18:26:17 +00001517 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1518 Op.getDebugLoc());
Bruno Cardoso Lopes6d399bd2008-07-29 19:05:28 +00001519}
1520
Akira Hatanaka0a40c232012-03-09 23:46:03 +00001521SDValue MipsTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1522 SDValue Cond = CreateFPCmp(DAG, Op);
1523
1524 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1525 "Floating point operand expected.");
1526
1527 SDValue True = DAG.getConstant(1, MVT::i32);
1528 SDValue False = DAG.getConstant(0, MVT::i32);
1529
1530 return CreateCMovFP(DAG, Cond, True, False, Op.getDebugLoc());
1531}
1532
Dan Gohmand858e902010-04-17 15:26:15 +00001533SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
1534 SelectionDAG &DAG) const {
Dale Johannesende064702009-02-06 21:50:26 +00001535 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001536 DebugLoc dl = Op.getDebugLoc();
Jia Liubb481f82012-02-28 07:46:26 +00001537 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001538
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001539 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Chris Lattnere3736f82009-08-13 05:41:27 +00001540 SDVTList VTs = DAG.getVTList(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001541
Chris Lattnerb71b9092009-08-13 06:28:06 +00001542 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001543
Chris Lattnere3736f82009-08-13 05:41:27 +00001544 // %gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001545 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
1546 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001547 MipsII::MO_GPREL);
Chris Lattnere3736f82009-08-13 05:41:27 +00001548 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
1549 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001550 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
Chris Lattnere3736f82009-08-13 05:41:27 +00001551 }
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001552 // %hi/%lo relocation
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001553 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1554 MipsII::MO_ABS_HI);
1555 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
1556 MipsII::MO_ABS_LO);
1557 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1);
1558 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001559 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001560 }
1561
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001562 EVT ValTy = Op.getValueType();
1563 bool HasGotOfst = (GV->hasInternalLinkage() ||
1564 (GV->hasLocalLinkage() && !isa<Function>(GV)));
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001565 unsigned GotFlag = HasMips64 ?
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001566 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) :
Bruno Cardoso Lopese3d35722011-12-07 00:28:57 +00001567 (HasGotOfst ? MipsII::MO_GOT : MipsII::MO_GOT16);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001568 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001569 GA = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), GA);
Akira Hatanaka82099682011-12-19 19:52:25 +00001570 SDValue ResNode = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), GA,
1571 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka0f843822011-06-07 18:58:42 +00001572 // On functions and global targets not internal linked only
1573 // a load from got/GP is necessary for PIC to work.
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001574 if (!HasGotOfst)
Akira Hatanaka0f843822011-06-07 18:58:42 +00001575 return ResNode;
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001576 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0,
Akira Hatanaka56ce6b32012-04-04 22:16:36 +00001577 HasMips64 ? MipsII::MO_GOT_OFST :
1578 MipsII::MO_ABS_LO);
Akira Hatanakaa5903ac2011-10-11 00:55:05 +00001579 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo);
1580 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001581}
1582
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001583SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op,
1584 SelectionDAG &DAG) const {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001585 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1586 // FIXME there isn't actually debug info here
1587 DebugLoc dl = Op.getDebugLoc();
1588
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001589 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001590 // %hi/%lo relocation
Akira Hatanaka82099682011-12-19 19:52:25 +00001591 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_HI);
1592 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, MipsII::MO_ABS_LO);
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001593 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi);
1594 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo);
1595 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001596 }
Akira Hatanakaf48eb532011-04-25 17:10:45 +00001597
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001598 EVT ValTy = Op.getValueType();
Akira Hatanaka03d830e2012-04-04 18:22:53 +00001599 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1600 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001601 SDValue BAGOTOffset = DAG.getBlockAddress(BA, ValTy, true, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001602 BAGOTOffset = DAG.getNode(MipsISD::Wrapper, dl, ValTy,
1603 GetGlobalReg(DAG, ValTy), BAGOTOffset);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001604 SDValue BALOOffset = DAG.getBlockAddress(BA, ValTy, true, OFSTFlag);
Akira Hatanaka82099682011-12-19 19:52:25 +00001605 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), BAGOTOffset,
Pete Cooperd752e0f2011-11-08 18:42:53 +00001606 MachinePointerInfo(), false, false, false, 0);
Akira Hatanaka9b944a82011-11-16 22:42:10 +00001607 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, BALOOffset);
1608 return DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesca8a2aa2011-03-04 20:01:52 +00001609}
1610
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001611SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001612LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001613{
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001614 // If the relocation model is PIC, use the General Dynamic TLS Model or
1615 // Local Dynamic TLS model, otherwise use the Initial Exec or
1616 // Local Exec TLS Model.
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001617
1618 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1619 DebugLoc dl = GA->getDebugLoc();
1620 const GlobalValue *GV = GA->getGlobal();
1621 EVT PtrVT = getPointerTy();
1622
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001623 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1624
1625 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001626 // General Dynamic TLS Model
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001627 bool LocalDynamic = GV->hasInternalLinkage();
1628 unsigned Flag = LocalDynamic ? MipsII::MO_TLSLDM :MipsII::MO_TLSGD;
1629 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, Flag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001630 SDValue Argument = DAG.getNode(MipsISD::Wrapper, dl, PtrVT,
1631 GetGlobalReg(DAG, PtrVT), TGA);
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001632 unsigned PtrSize = PtrVT.getSizeInBits();
1633 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1634
Benjamin Kramer5eccf672011-12-11 12:21:34 +00001635 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001636
1637 ArgListTy Args;
1638 ArgListEntry Entry;
1639 Entry.Node = Argument;
Akira Hatanakaca074792011-12-08 20:34:32 +00001640 Entry.Ty = PtrTy;
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001641 Args.push_back(Entry);
Jia Liubb481f82012-02-28 07:46:26 +00001642
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001643 std::pair<SDValue, SDValue> CallResult =
Akira Hatanakaca074792011-12-08 20:34:32 +00001644 LowerCallTo(DAG.getEntryNode(), PtrTy,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00001645 false, false, false, false, 0, CallingConv::C,
1646 /*isTailCall=*/false, /*doesNotRet=*/false,
1647 /*isReturnValueUsed=*/true,
Akira Hatanaka7a7194b2011-12-08 21:05:38 +00001648 TlsGetAddr, Args, DAG, dl);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001649
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001650 SDValue Ret = CallResult.first;
1651
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001652 if (model != TLSModel::LocalDynamic)
Akira Hatanaka3faac0a2011-12-14 18:26:41 +00001653 return Ret;
1654
1655 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1656 MipsII::MO_DTPREL_HI);
1657 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1658 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1659 MipsII::MO_DTPREL_LO);
1660 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1661 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Ret);
1662 return DAG.getNode(ISD::ADD, dl, PtrVT, Add, Lo);
Bruno Cardoso Lopesd9796862011-05-31 02:53:58 +00001663 }
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001664
1665 SDValue Offset;
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001666 if (model == TLSModel::InitialExec) {
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001667 // Initial Exec TLS Model
Akira Hatanakaca074792011-12-08 20:34:32 +00001668 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001669 MipsII::MO_GOTTPREL);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001670 TGA = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1671 TGA);
Akira Hatanakaca074792011-12-08 20:34:32 +00001672 Offset = DAG.getLoad(PtrVT, dl,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001673 DAG.getEntryNode(), TGA, MachinePointerInfo(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00001674 false, false, false, 0);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001675 } else {
1676 // Local Exec TLS Model
Hans Wennborgfd5abd52012-05-04 09:40:39 +00001677 assert(model == TLSModel::LocalExec);
Akira Hatanakaca074792011-12-08 20:34:32 +00001678 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001679 MipsII::MO_TPREL_HI);
Akira Hatanakaca074792011-12-08 20:34:32 +00001680 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001681 MipsII::MO_TPREL_LO);
Akira Hatanakaca074792011-12-08 20:34:32 +00001682 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, PtrVT, TGAHi);
1683 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, TGALo);
1684 Offset = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00001685 }
1686
1687 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
1688 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
Bruno Cardoso Lopes97843cd2008-07-29 19:29:50 +00001689}
1690
1691SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001692LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001693{
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001694 SDValue HiPart, JTI, JTILo;
Dale Johannesende064702009-02-06 21:50:26 +00001695 // FIXME there isn't actually debug info here
Dale Johannesen33c960f2009-02-04 20:06:27 +00001696 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00001697 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Owen Andersone50ed302009-08-10 22:56:29 +00001698 EVT PtrVT = Op.getValueType();
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001699 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001700
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001701 if (!IsPIC && !IsN64) {
1702 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_HI);
1703 HiPart = DAG.getNode(MipsISD::Hi, dl, PtrVT, JTI);
1704 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001705 } else {// Emit Load from Global Pointer
Akira Hatanakac75ceb72012-04-04 18:31:32 +00001706 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1707 unsigned OfstFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001708 JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001709 JTI = DAG.getNode(MipsISD::Wrapper, dl, PtrVT, GetGlobalReg(DAG, PtrVT),
1710 JTI);
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001711 HiPart = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), JTI,
1712 MachinePointerInfo(), false, false, false, 0);
1713 JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OfstFlag);
Akira Hatanaka342837d2011-05-28 01:07:07 +00001714 }
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001715
Akira Hatanaka2bf08ec2011-12-05 21:03:03 +00001716 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, PtrVT, JTILo);
1717 return DAG.getNode(ISD::ADD, dl, PtrVT, HiPart, Lo);
Bruno Cardoso Lopes753a9872007-11-12 19:49:57 +00001718}
1719
Dan Gohman475871a2008-07-27 21:46:04 +00001720SDValue MipsTargetLowering::
Dan Gohmand858e902010-04-17 15:26:15 +00001721LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001722{
Dan Gohman475871a2008-07-27 21:46:04 +00001723 SDValue ResNode;
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001724 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
Dan Gohman46510a72010-04-15 01:51:59 +00001725 const Constant *C = N->getConstVal();
Dale Johannesende064702009-02-06 21:50:26 +00001726 // FIXME there isn't actually debug info here
1727 DebugLoc dl = Op.getDebugLoc();
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001728
1729 // gp_rel relocation
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001730 // FIXME: we should reference the constant pool using small data sections,
Chris Lattner7a2bdde2011-04-15 05:18:47 +00001731 // but the asm printer currently doesn't support this feature without
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001732 // hacking it. This feature should come soon so we can uncomment the
Bruno Cardoso Lopesf33bc432008-07-28 19:26:25 +00001733 // stuff below.
Eli Friedmane2c74082009-08-03 02:22:28 +00001734 //if (IsInSmallSection(C->getType())) {
Owen Anderson825b72b2009-08-11 20:47:22 +00001735 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
1736 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00001737 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001738
Akira Hatanaka13daee32012-03-27 02:55:31 +00001739 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001740 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001741 N->getOffset(), MipsII::MO_ABS_HI);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001742 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00001743 N->getOffset(), MipsII::MO_ABS_LO);
Akira Hatanakae2e436a2011-04-01 21:41:06 +00001744 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi);
1745 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo);
Owen Anderson825b72b2009-08-11 20:47:22 +00001746 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001747 } else {
Akira Hatanaka620db892011-11-16 22:44:38 +00001748 EVT ValTy = Op.getValueType();
Akira Hatanaka86a27332012-04-04 18:26:12 +00001749 unsigned GOTFlag = HasMips64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
1750 unsigned OFSTFlag = HasMips64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
Akira Hatanaka620db892011-11-16 22:44:38 +00001751 SDValue CP = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1752 N->getOffset(), GOTFlag);
Akira Hatanaka648f00c2012-02-24 22:34:47 +00001753 CP = DAG.getNode(MipsISD::Wrapper, dl, ValTy, GetGlobalReg(DAG, ValTy), CP);
Akira Hatanaka82099682011-12-19 19:52:25 +00001754 SDValue Load = DAG.getLoad(ValTy, dl, DAG.getEntryNode(), CP,
1755 MachinePointerInfo::getConstantPool(), false,
1756 false, false, 0);
Akira Hatanaka620db892011-11-16 22:44:38 +00001757 SDValue CPLo = DAG.getTargetConstantPool(C, ValTy, N->getAlignment(),
1758 N->getOffset(), OFSTFlag);
1759 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, CPLo);
1760 ResNode = DAG.getNode(ISD::ADD, dl, ValTy, Load, Lo);
Bruno Cardoso Lopesd71cebf2009-11-25 12:17:58 +00001761 }
Bruno Cardoso Lopes92e87f22008-07-23 16:01:50 +00001762
1763 return ResNode;
Bruno Cardoso Lopes97c25372008-07-09 04:15:08 +00001764}
1765
Dan Gohmand858e902010-04-17 15:26:15 +00001766SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
Dan Gohman1e93df62010-04-17 14:41:14 +00001767 MachineFunction &MF = DAG.getMachineFunction();
1768 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1769
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001770 DebugLoc dl = Op.getDebugLoc();
Dan Gohman1e93df62010-04-17 14:41:14 +00001771 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1772 getPointerTy());
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001773
1774 // vastart just stores the address of the VarArgsFrameIndex slot into the
1775 // memory location argument.
1776 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
Chris Lattner8026a9d2010-09-21 17:50:43 +00001777 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
Akira Hatanaka82099682011-12-19 19:52:25 +00001778 MachinePointerInfo(SV), false, false, 0);
Bruno Cardoso Lopes6059b852010-02-06 21:00:02 +00001779}
Jia Liubb481f82012-02-28 07:46:26 +00001780
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001781static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1782 EVT TyX = Op.getOperand(0).getValueType();
1783 EVT TyY = Op.getOperand(1).getValueType();
1784 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1785 SDValue Const31 = DAG.getConstant(31, MVT::i32);
1786 DebugLoc DL = Op.getDebugLoc();
1787 SDValue Res;
1788
1789 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1790 // to i32.
1791 SDValue X = (TyX == MVT::f32) ?
1792 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1793 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1794 Const1);
1795 SDValue Y = (TyY == MVT::f32) ?
1796 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1797 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1798 Const1);
1799
1800 if (HasR2) {
1801 // ext E, Y, 31, 1 ; extract bit31 of Y
1802 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1803 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1804 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1805 } else {
1806 // sll SllX, X, 1
1807 // srl SrlX, SllX, 1
1808 // srl SrlY, Y, 31
1809 // sll SllY, SrlX, 31
1810 // or Or, SrlX, SllY
1811 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1812 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1813 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1814 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1815 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1816 }
1817
1818 if (TyX == MVT::f32)
1819 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1820
1821 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1822 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1823 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001824}
1825
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001826static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1827 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1828 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1829 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1830 SDValue Const1 = DAG.getConstant(1, MVT::i32);
1831 DebugLoc DL = Op.getDebugLoc();
Eric Christopher471e4222011-06-08 23:55:35 +00001832
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001833 // Bitcast to integer nodes.
1834 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1835 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001836
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001837 if (HasR2) {
1838 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1839 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1840 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1841 DAG.getConstant(WidthY - 1, MVT::i32), Const1);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001842
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001843 if (WidthX > WidthY)
1844 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1845 else if (WidthY > WidthX)
1846 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001847
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001848 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1849 DAG.getConstant(WidthX - 1, MVT::i32), Const1, X);
1850 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1851 }
1852
1853 // (d)sll SllX, X, 1
1854 // (d)srl SrlX, SllX, 1
1855 // (d)srl SrlY, Y, width(Y)-1
1856 // (d)sll SllY, SrlX, width(Y)-1
1857 // or Or, SrlX, SllY
1858 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1859 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1860 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1861 DAG.getConstant(WidthY - 1, MVT::i32));
1862
1863 if (WidthX > WidthY)
1864 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
1865 else if (WidthY > WidthX)
1866 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
1867
1868 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
1869 DAG.getConstant(WidthX - 1, MVT::i32));
1870 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
1871 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001872}
1873
Akira Hatanaka82099682011-12-19 19:52:25 +00001874SDValue
1875MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001876 if (Subtarget->hasMips64())
1877 return LowerFCOPYSIGN64(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001878
Akira Hatanaka056c51e2012-04-11 22:13:04 +00001879 return LowerFCOPYSIGN32(Op, DAG, Subtarget->hasMips32r2());
Akira Hatanaka9c3d57c2011-05-25 19:32:07 +00001880}
1881
Akira Hatanakac12a6e62012-04-11 22:49:04 +00001882static SDValue LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1883 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1884 DebugLoc DL = Op.getDebugLoc();
1885
1886 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1887 // to i32.
1888 SDValue X = (Op.getValueType() == MVT::f32) ?
1889 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1890 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1891 Const1);
1892
1893 // Clear MSB.
1894 if (HasR2)
1895 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
1896 DAG.getRegister(Mips::ZERO, MVT::i32),
1897 DAG.getConstant(31, MVT::i32), Const1, X);
1898 else {
1899 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1900 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1901 }
1902
1903 if (Op.getValueType() == MVT::f32)
1904 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
1905
1906 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1907 Op.getOperand(0), DAG.getConstant(0, MVT::i32));
1908 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1909}
1910
1911static SDValue LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) {
1912 SDValue Res, Const1 = DAG.getConstant(1, MVT::i32);
1913 DebugLoc DL = Op.getDebugLoc();
1914
1915 // Bitcast to integer node.
1916 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
1917
1918 // Clear MSB.
1919 if (HasR2)
1920 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
1921 DAG.getRegister(Mips::ZERO_64, MVT::i64),
1922 DAG.getConstant(63, MVT::i32), Const1, X);
1923 else {
1924 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
1925 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
1926 }
1927
1928 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
1929}
1930
1931SDValue
1932MipsTargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
1933 if (Subtarget->hasMips64() && (Op.getValueType() == MVT::f64))
1934 return LowerFABS64(Op, DAG, Subtarget->hasMips32r2());
1935
1936 return LowerFABS32(Op, DAG, Subtarget->hasMips32r2());
1937}
1938
Akira Hatanaka2e591472011-06-02 00:24:44 +00001939SDValue MipsTargetLowering::
1940LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
Bruno Cardoso Lopese0b5cfc2011-06-16 00:40:02 +00001941 // check the depth
1942 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
Akira Hatanaka0f843822011-06-07 18:58:42 +00001943 "Frame address can only be determined for current frame.");
Akira Hatanaka2e591472011-06-02 00:24:44 +00001944
1945 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1946 MFI->setFrameAddressIsTaken(true);
1947 EVT VT = Op.getValueType();
1948 DebugLoc dl = Op.getDebugLoc();
Akira Hatanaka46ac4392011-11-11 04:11:56 +00001949 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1950 IsN64 ? Mips::FP_64 : Mips::FP, VT);
Akira Hatanaka2e591472011-06-02 00:24:44 +00001951 return FrameAddr;
1952}
1953
Akira Hatanakadb548262011-07-19 23:30:50 +00001954// TODO: set SType according to the desired memory barrier behavior.
Akira Hatanaka82099682011-12-19 19:52:25 +00001955SDValue
1956MipsTargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const {
Akira Hatanakadb548262011-07-19 23:30:50 +00001957 unsigned SType = 0;
1958 DebugLoc dl = Op.getDebugLoc();
1959 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1960 DAG.getConstant(SType, MVT::i32));
1961}
1962
Eli Friedman14648462011-07-27 22:21:52 +00001963SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op,
1964 SelectionDAG& DAG) const {
1965 // FIXME: Need pseudo-fence for 'singlethread' fences
1966 // FIXME: Set SType for weaker fences where supported/appropriate.
1967 unsigned SType = 0;
1968 DebugLoc dl = Op.getDebugLoc();
1969 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0),
1970 DAG.getConstant(SType, MVT::i32));
1971}
1972
Akira Hatanakaa284acb2012-05-09 00:55:21 +00001973SDValue MipsTargetLowering::LowerShiftLeftParts(SDValue Op,
1974 SelectionDAG& DAG) const {
1975 DebugLoc DL = Op.getDebugLoc();
1976 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
1977 SDValue Shamt = Op.getOperand(2);
1978
1979 // if shamt < 32:
1980 // lo = (shl lo, shamt)
1981 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
1982 // else:
1983 // lo = 0
1984 // hi = (shl lo, shamt[4:0])
1985 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
1986 DAG.getConstant(-1, MVT::i32));
1987 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
1988 DAG.getConstant(1, MVT::i32));
1989 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
1990 Not);
1991 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
1992 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
1993 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
1994 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
1995 DAG.getConstant(0x20, MVT::i32));
1996 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, DAG.getConstant(0, MVT::i32),
1997 ShiftLeftLo);
1998 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
1999
2000 SDValue Ops[2] = {Lo, Hi};
2001 return DAG.getMergeValues(Ops, 2, DL);
2002}
2003
2004SDValue MipsTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
2005 bool IsSRA) const {
2006 DebugLoc DL = Op.getDebugLoc();
2007 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2008 SDValue Shamt = Op.getOperand(2);
2009
2010 // if shamt < 32:
2011 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2012 // if isSRA:
2013 // hi = (sra hi, shamt)
2014 // else:
2015 // hi = (srl hi, shamt)
2016 // else:
2017 // if isSRA:
2018 // lo = (sra hi, shamt[4:0])
2019 // hi = (sra hi, 31)
2020 // else:
2021 // lo = (srl hi, shamt[4:0])
2022 // hi = 0
2023 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2024 DAG.getConstant(-1, MVT::i32));
2025 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
2026 DAG.getConstant(1, MVT::i32));
2027 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
2028 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
2029 SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
2030 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2031 Hi, Shamt);
2032 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2033 DAG.getConstant(0x20, MVT::i32));
2034 SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
2035 DAG.getConstant(31, MVT::i32));
2036 Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
2037 Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
2038 IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2039 ShiftRightHi);
2040
2041 SDValue Ops[2] = {Lo, Hi};
2042 return DAG.getMergeValues(Ops, 2, DL);
2043}
2044
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002045//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002046// Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002047//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002048
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002049//===----------------------------------------------------------------------===//
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002050// TODO: Implement a generic logic using tblgen that can support this.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002051// Mips O32 ABI rules:
2052// ---
2053// i32 - Passed in A0, A1, A2, A3 and stack
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002054// f32 - Only passed in f32 registers if no int reg has been used yet to hold
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002055// an argument. Otherwise, passed in A1, A2, A3 and stack.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002056// f64 - Only passed in two aliased f32 registers if no int reg has been used
2057// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002058// not used, it must be shadowed. If only A3 is avaiable, shadow it and
2059// go to stack.
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002060//
2061// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002062//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002063
Duncan Sands1e96bab2010-11-04 10:49:57 +00002064static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
Duncan Sands1440e8b2010-11-03 11:35:31 +00002065 MVT LocVT, CCValAssign::LocInfo LocInfo,
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002066 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2067
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002068 static const unsigned IntRegsSize=4, FloatRegsSize=2;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002069
Craig Topperc5eaae42012-03-11 07:57:25 +00002070 static const uint16_t IntRegs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002071 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2072 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002073 static const uint16_t F32Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002074 Mips::F12, Mips::F14
2075 };
Craig Topperc5eaae42012-03-11 07:57:25 +00002076 static const uint16_t F64Regs[] = {
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002077 Mips::D6, Mips::D7
2078 };
2079
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002080 // ByVal Args
2081 if (ArgFlags.isByVal()) {
2082 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo,
2083 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags);
2084 unsigned NextReg = (State.getNextStackOffset() + 3) / 4;
2085 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize);
2086 r < std::min(IntRegsSize, NextReg); ++r)
2087 State.AllocateReg(IntRegs[r]);
2088 return false;
2089 }
2090
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002091 // Promote i8 and i16
2092 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2093 LocVT = MVT::i32;
2094 if (ArgFlags.isSExt())
2095 LocInfo = CCValAssign::SExt;
2096 else if (ArgFlags.isZExt())
2097 LocInfo = CCValAssign::ZExt;
2098 else
2099 LocInfo = CCValAssign::AExt;
2100 }
2101
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002102 unsigned Reg;
2103
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002104 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2105 // is true: function is vararg, argument is 3rd or higher, there is previous
2106 // argument which is not f32 or f64.
2107 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1
2108 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo;
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002109 unsigned OrigAlign = ArgFlags.getOrigAlign();
2110 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002111
2112 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002113 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Akira Hatanakaa1a7ba82011-05-19 20:29:48 +00002114 // If this is the first part of an i64 arg,
2115 // the allocated register must be either A0 or A2.
2116 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2117 Reg = State.AllocateReg(IntRegs, IntRegsSize);
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002118 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002119 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2120 // Allocate int register and shadow next int register. If first
2121 // available register is Mips::A1 or Mips::A3, shadow it too.
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002122 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2123 if (Reg == Mips::A1 || Reg == Mips::A3)
2124 Reg = State.AllocateReg(IntRegs, IntRegsSize);
2125 State.AllocateReg(IntRegs, IntRegsSize);
2126 LocVT = MVT::i32;
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002127 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2128 // we are guaranteed to find an available float register
2129 if (ValVT == MVT::f32) {
2130 Reg = State.AllocateReg(F32Regs, FloatRegsSize);
2131 // Shadow int register
2132 State.AllocateReg(IntRegs, IntRegsSize);
2133 } else {
2134 Reg = State.AllocateReg(F64Regs, FloatRegsSize);
2135 // Shadow int registers
2136 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize);
2137 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2138 State.AllocateReg(IntRegs, IntRegsSize);
2139 State.AllocateReg(IntRegs, IntRegsSize);
2140 }
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002141 } else
2142 llvm_unreachable("Cannot handle this ValVT.");
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002143
Akira Hatanakad37776d2011-05-20 21:39:54 +00002144 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
2145 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign);
2146
2147 if (!Reg)
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002148 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
Akira Hatanakad37776d2011-05-20 21:39:54 +00002149 else
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002151
Bruno Cardoso Lopesc42fb5f2011-03-04 20:27:44 +00002152 return false; // CC must always match
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002153}
2154
Craig Topperc5eaae42012-03-11 07:57:25 +00002155static const uint16_t Mips64IntRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002156 {Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
2157 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64};
Craig Topperc5eaae42012-03-11 07:57:25 +00002158static const uint16_t Mips64DPRegs[8] =
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002159 {Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
2160 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64};
2161
2162static bool CC_Mips64Byval(unsigned ValNo, MVT ValVT, MVT LocVT,
2163 CCValAssign::LocInfo LocInfo,
2164 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2165 unsigned Align = std::max(ArgFlags.getByValAlign(), (unsigned)8);
2166 unsigned Size = (ArgFlags.getByValSize() + 7) / 8 * 8;
2167 unsigned FirstIdx = State.getFirstUnallocated(Mips64IntRegs, 8);
2168
2169 assert(Align <= 16 && "Cannot handle alignments larger than 16.");
2170
Jia Liubb481f82012-02-28 07:46:26 +00002171 // If byval is 16-byte aligned, the first arg register must be even.
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002172 if ((Align == 16) && (FirstIdx % 2)) {
2173 State.AllocateReg(Mips64IntRegs[FirstIdx], Mips64DPRegs[FirstIdx]);
2174 ++FirstIdx;
2175 }
2176
2177 // Mark the registers allocated.
2178 for (unsigned I = FirstIdx; Size && (I < 8); Size -= 8, ++I)
2179 State.AllocateReg(Mips64IntRegs[I], Mips64DPRegs[I]);
2180
2181 // Allocate space on caller's stack.
2182 unsigned Offset = State.AllocateStack(Size, Align);
Jia Liubb481f82012-02-28 07:46:26 +00002183
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002184 if (FirstIdx < 8)
2185 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Mips64IntRegs[FirstIdx],
Jia Liubb481f82012-02-28 07:46:26 +00002186 LocVT, LocInfo));
Akira Hatanaka2c5d6522011-11-12 02:20:46 +00002187 else
2188 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2189
2190 return true;
2191}
2192
2193#include "MipsGenCallingConv.inc"
2194
Akira Hatanaka49617092011-11-14 19:02:54 +00002195static void
Akira Hatanaka08067b22012-01-24 22:07:36 +00002196AnalyzeMips64CallOperands(CCState &CCInfo,
Akira Hatanaka49617092011-11-14 19:02:54 +00002197 const SmallVectorImpl<ISD::OutputArg> &Outs) {
2198 unsigned NumOps = Outs.size();
2199 for (unsigned i = 0; i != NumOps; ++i) {
2200 MVT ArgVT = Outs[i].VT;
2201 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2202 bool R;
2203
2204 if (Outs[i].IsFixed)
2205 R = CC_MipsN(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2206 else
2207 R = CC_MipsN_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
Jia Liubb481f82012-02-28 07:46:26 +00002208
Akira Hatanaka49617092011-11-14 19:02:54 +00002209 if (R) {
Benjamin Kramer6296ee32011-11-14 19:51:48 +00002210#ifndef NDEBUG
Akira Hatanaka49617092011-11-14 19:02:54 +00002211 dbgs() << "Call operand #" << i << " has unhandled type "
2212 << EVT(ArgVT).getEVTString();
2213#endif
2214 llvm_unreachable(0);
2215 }
2216 }
2217}
2218
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002219//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002220// Call Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002221//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002222
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002223static const unsigned O32IntRegsSize = 4;
2224
Craig Topperc5eaae42012-03-11 07:57:25 +00002225static const uint16_t O32IntRegs[] = {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002226 Mips::A0, Mips::A1, Mips::A2, Mips::A3
2227};
2228
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002229// Return next O32 integer argument register.
2230static unsigned getNextIntArgReg(unsigned Reg) {
2231 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2232 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2233}
2234
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002235// Write ByVal Arg to arg registers and stack.
2236static void
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002237WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002238 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2239 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2240 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
Akira Hatanakaedacba82011-05-25 17:32:06 +00002241 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002242 MVT PtrType, bool isLittle) {
2243 unsigned LocMemOffset = VA.getLocMemOffset();
2244 unsigned Offset = 0;
2245 uint32_t RemainingSize = Flags.getByValSize();
Akira Hatanaka5c21c9e2011-08-12 21:30:06 +00002246 unsigned ByValAlign = Flags.getByValAlign();
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002247
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002248 // Copy the first 4 words of byval arg to registers A0 - A3.
2249 // FIXME: Use a stricter alignment if it enables better optimization in passes
2250 // run later.
2251 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4;
2252 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002253 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002254 DAG.getConstant(Offset, MVT::i32));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002255 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr,
Akira Hatanaka82099682011-12-19 19:52:25 +00002256 MachinePointerInfo(), false, false, false,
2257 std::min(ByValAlign, (unsigned )4));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002258 MemOpChains.push_back(LoadVal.getValue(1));
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002259 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002260 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2261 }
2262
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002263 if (RemainingSize == 0)
2264 return;
2265
2266 // If there still is a register available for argument passing, write the
2267 // remaining part of the structure to it using subword loads and shifts.
2268 if (LocMemOffset < 4 * 4) {
2269 assert(RemainingSize <= 3 && RemainingSize >= 1 &&
2270 "There must be one to three bytes remaining.");
2271 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize);
2272 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2273 DAG.getConstant(Offset, MVT::i32));
2274 unsigned Alignment = std::min(ByValAlign, (unsigned )4);
2275 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2276 LoadPtr, MachinePointerInfo(),
2277 MVT::getIntegerVT(LoadSize * 8), false,
2278 false, Alignment);
2279 MemOpChains.push_back(LoadVal.getValue(1));
2280
2281 // If target is big endian, shift it to the most significant half-word or
2282 // byte.
2283 if (!isLittle)
2284 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal,
2285 DAG.getConstant(32 - LoadSize * 8, MVT::i32));
2286
2287 Offset += LoadSize;
2288 RemainingSize -= LoadSize;
2289
2290 // Read second subword if necessary.
2291 if (RemainingSize != 0) {
2292 assert(RemainingSize == 1 && "There must be one byte remaining.");
Jia Liubb481f82012-02-28 07:46:26 +00002293 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002294 DAG.getConstant(Offset, MVT::i32));
2295 unsigned Alignment = std::min(ByValAlign, (unsigned )2);
2296 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
2297 LoadPtr, MachinePointerInfo(),
2298 MVT::i8, false, false, Alignment);
2299 MemOpChains.push_back(Subword.getValue(1));
2300 // Insert the loaded byte to LoadVal.
2301 // FIXME: Use INS if supported by target.
2302 unsigned ShiftAmt = isLittle ? 16 : 8;
2303 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword,
2304 DAG.getConstant(ShiftAmt, MVT::i32));
2305 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift);
2306 }
2307
2308 unsigned DstReg = O32IntRegs[LocMemOffset / 4];
2309 RegsToPass.push_back(std::make_pair(DstReg, LoadVal));
2310 return;
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002311 }
Akira Hatanaka5ac85472011-08-18 23:39:37 +00002312
2313 // Create a fixed object on stack at offset LocMemOffset and copy
2314 // remaining part of byval arg to it using memcpy.
2315 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg,
2316 DAG.getConstant(Offset, MVT::i32));
2317 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true);
2318 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType);
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002319 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2320 DAG.getConstant(RemainingSize, MVT::i32),
2321 std::min(ByValAlign, (unsigned)4),
2322 /*isVolatile=*/false, /*AlwaysInline=*/false,
2323 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002324}
2325
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002326// Copy Mips64 byVal arg to registers and stack.
2327void static
2328PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
2329 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass,
2330 SmallVector<SDValue, 8>& MemOpChains, int& LastFI,
2331 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
2332 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2333 EVT PtrTy, bool isLittle) {
2334 unsigned ByValSize = Flags.getByValSize();
2335 unsigned Alignment = std::min(Flags.getByValAlign(), (unsigned)8);
2336 bool IsRegLoc = VA.isRegLoc();
2337 unsigned Offset = 0; // Offset in # of bytes from the beginning of struct.
2338 unsigned LocMemOffset = 0;
Akira Hatanaka16040852011-11-15 18:42:25 +00002339 unsigned MemCpySize = ByValSize;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002340
2341 if (!IsRegLoc)
2342 LocMemOffset = VA.getLocMemOffset();
2343 else {
Craig Topperc5eaae42012-03-11 07:57:25 +00002344 const uint16_t *Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8,
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002345 VA.getLocReg());
Craig Topperc5eaae42012-03-11 07:57:25 +00002346 const uint16_t *RegEnd = Mips64IntRegs + 8;
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002347
2348 // Copy double words to registers.
2349 for (; (Reg != RegEnd) && (ByValSize >= Offset + 8); ++Reg, Offset += 8) {
2350 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2351 DAG.getConstant(Offset, PtrTy));
2352 SDValue LoadVal = DAG.getLoad(MVT::i64, dl, Chain, LoadPtr,
2353 MachinePointerInfo(), false, false, false,
2354 Alignment);
2355 MemOpChains.push_back(LoadVal.getValue(1));
2356 RegsToPass.push_back(std::make_pair(*Reg, LoadVal));
2357 }
2358
Jia Liubb481f82012-02-28 07:46:26 +00002359 // Return if the struct has been fully copied.
Akira Hatanaka16040852011-11-15 18:42:25 +00002360 if (!(MemCpySize = ByValSize - Offset))
2361 return;
2362
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002363 // If there is an argument register available, copy the remainder of the
2364 // byval argument with sub-doubleword loads and shifts.
Akira Hatanaka16040852011-11-15 18:42:25 +00002365 if (Reg != RegEnd) {
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002366 assert((ByValSize < Offset + 8) &&
2367 "Size of the remainder should be smaller than 8-byte.");
2368 SDValue Val;
2369 for (unsigned LoadSize = 4; Offset < ByValSize; LoadSize /= 2) {
2370 unsigned RemSize = ByValSize - Offset;
2371
2372 if (RemSize < LoadSize)
2373 continue;
Jia Liubb481f82012-02-28 07:46:26 +00002374
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002375 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2376 DAG.getConstant(Offset, PtrTy));
Jia Liubb481f82012-02-28 07:46:26 +00002377 SDValue LoadVal =
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002378 DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i64, Chain, LoadPtr,
2379 MachinePointerInfo(), MVT::getIntegerVT(LoadSize * 8),
2380 false, false, Alignment);
2381 MemOpChains.push_back(LoadVal.getValue(1));
2382
2383 // Offset in number of bits from double word boundary.
2384 unsigned OffsetDW = (Offset % 8) * 8;
2385 unsigned Shamt = isLittle ? OffsetDW : 64 - (OffsetDW + LoadSize * 8);
2386 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i64, LoadVal,
2387 DAG.getConstant(Shamt, MVT::i32));
Jia Liubb481f82012-02-28 07:46:26 +00002388
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002389 Val = Val.getNode() ? DAG.getNode(ISD::OR, dl, MVT::i64, Val, Shift) :
2390 Shift;
2391 Offset += LoadSize;
2392 Alignment = std::min(Alignment, LoadSize);
2393 }
Jia Liubb481f82012-02-28 07:46:26 +00002394
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002395 RegsToPass.push_back(std::make_pair(*Reg, Val));
2396 return;
2397 }
2398 }
2399
Akira Hatanaka16040852011-11-15 18:42:25 +00002400 assert(MemCpySize && "MemCpySize must not be zero.");
2401
2402 // Create a fixed object on stack at offset LocMemOffset and copy
2403 // remainder of byval arg to it with memcpy.
2404 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrTy, Arg,
2405 DAG.getConstant(Offset, PtrTy));
2406 LastFI = MFI->CreateFixedObject(MemCpySize, LocMemOffset, true);
2407 SDValue Dst = DAG.getFrameIndex(LastFI, PtrTy);
2408 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src,
2409 DAG.getConstant(MemCpySize, PtrTy), Alignment,
2410 /*isVolatile=*/false, /*AlwaysInline=*/false,
2411 MachinePointerInfo(0), MachinePointerInfo(0));
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002412}
2413
Dan Gohman98ca4f22009-08-05 01:29:28 +00002414/// LowerCall - functions arguments are copied from virtual regs to
Nate Begeman5bf4b752009-01-26 03:15:54 +00002415/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002416/// TODO: isTailCall.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002417SDValue
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002418MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002419 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +00002420 bool doesNotRet, bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002421 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00002422 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002423 const SmallVectorImpl<ISD::InputArg> &Ins,
2424 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002425 SmallVectorImpl<SDValue> &InVals) const {
Evan Cheng0c439eb2010-01-27 00:07:07 +00002426 // MIPs target does not yet support tail call optimization.
2427 isTailCall = false;
Dan Gohman98ca4f22009-08-05 01:29:28 +00002428
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002429 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002430 MachineFrameInfo *MFI = MF.getFrameInfo();
Akira Hatanakad37776d2011-05-20 21:39:54 +00002431 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering();
Bruno Cardoso Lopesc517cb02009-09-01 17:27:58 +00002432 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
Akira Hatanaka17a1e872011-05-20 18:39:33 +00002433 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002434
2435 // Analyze operands of the call, assigning locations to each operand.
2436 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002437 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002438 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002439
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002440 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002441 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32);
Akira Hatanaka49617092011-11-14 19:02:54 +00002442 else if (HasMips64)
2443 AnalyzeMips64CallOperands(CCInfo, Outs);
Akira Hatanakabdd2ce92011-05-23 21:13:59 +00002444 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002445 CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002446
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002447 // Get a count of how many bytes are to be pushed on the stack.
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002448 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2449
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002450 // Chain is the output chain of the last Load/Store or CopyToReg node.
2451 // ByValChain is the output chain of the last Memcpy node created for copying
2452 // byval arguments to the stack.
2453 SDValue Chain, CallSeqStart, ByValChain;
2454 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true);
2455 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal);
2456 ByValChain = InChain;
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002457
Akira Hatanaka21afc632011-06-21 00:40:49 +00002458 // Get the frame index of the stack frame object that points to the location
2459 // of dynamically allocated area on the stack.
2460 int DynAllocFI = MipsFI->getDynAllocFI();
2461
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002462 // Update size of the maximum argument space.
2463 // For O32, a minimum of four words (16 bytes) of argument space is
2464 // allocated.
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002465 if (IsO32)
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002466 NextStackOffset = std::max(NextStackOffset, (unsigned)16);
2467
2468 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize();
2469
2470 if (MaxCallFrameSize < NextStackOffset) {
2471 MipsFI->setMaxCallFrameSize(NextStackOffset);
2472
Akira Hatanaka21afc632011-06-21 00:40:49 +00002473 // Set the offsets relative to $sp of the $gp restore slot and dynamically
2474 // allocated stack space. These offsets must be aligned to a boundary
2475 // determined by the stack alignment of the ABI.
2476 unsigned StackAlignment = TFL->getStackAlignment();
2477 NextStackOffset = (NextStackOffset + StackAlignment - 1) /
2478 StackAlignment * StackAlignment;
2479
Akira Hatanaka21afc632011-06-21 00:40:49 +00002480 MFI->setObjectOffset(DynAllocFI, NextStackOffset);
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002481 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002482
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002483 // With EABI is it possible to have 16 args on registers.
Dan Gohman475871a2008-07-27 21:46:04 +00002484 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
2485 SmallVector<SDValue, 8> MemOpChains;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002486
Eric Christopher471e4222011-06-08 23:55:35 +00002487 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0;
Akira Hatanaka43299772011-05-20 23:22:14 +00002488
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002489 // Walk the register/memloc assignments, inserting copies/loads.
2490 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
Dan Gohmanc9403652010-07-07 15:54:55 +00002491 SDValue Arg = OutVals[i];
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002492 CCValAssign &VA = ArgLocs[i];
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002493 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002494 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2495
2496 // ByVal Arg.
2497 if (Flags.isByVal()) {
2498 assert(Flags.getByValSize() &&
2499 "ByVal args of size 0 should have been ignored by front-end.");
2500 if (IsO32)
2501 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
2502 MFI, DAG, Arg, VA, Flags, getPointerTy(),
2503 Subtarget->isLittle());
2504 else
2505 PassByValArg64(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI,
Jia Liubb481f82012-02-28 07:46:26 +00002506 MFI, DAG, Arg, VA, Flags, getPointerTy(),
Akira Hatanaka6df3e7b2011-11-12 02:34:50 +00002507 Subtarget->isLittle());
2508 continue;
2509 }
Jia Liubb481f82012-02-28 07:46:26 +00002510
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002511 // Promote the value if needed.
2512 switch (VA.getLocInfo()) {
Torok Edwinc23197a2009-07-14 16:55:14 +00002513 default: llvm_unreachable("Unknown loc info!");
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002514 case CCValAssign::Full:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002515 if (VA.isRegLoc()) {
2516 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2517 (ValVT == MVT::f64 && LocVT == MVT::i64))
2518 Arg = DAG.getNode(ISD::BITCAST, dl, LocVT, Arg);
2519 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002520 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2521 Arg, DAG.getConstant(0, MVT::i32));
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002522 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32,
2523 Arg, DAG.getConstant(1, MVT::i32));
Akira Hatanaka99a2e982011-04-15 19:52:08 +00002524 if (!Subtarget->isLittle())
2525 std::swap(Lo, Hi);
Jia Liubb481f82012-02-28 07:46:26 +00002526 unsigned LocRegLo = VA.getLocReg();
Akira Hatanaka373e3a42011-09-23 00:58:33 +00002527 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2528 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2529 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002530 continue;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002531 }
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002532 }
2533 break;
Chris Lattnere0b12152008-03-17 06:57:02 +00002534 case CCValAssign::SExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002535 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002536 break;
2537 case CCValAssign::ZExt:
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002538 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002539 break;
2540 case CCValAssign::AExt:
Akira Hatanaka38bdc572012-02-17 02:20:26 +00002541 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, LocVT, Arg);
Chris Lattnere0b12152008-03-17 06:57:02 +00002542 break;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002543 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002544
2545 // Arguments that can be passed on register must be kept at
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002546 // RegsToPass vector
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002547 if (VA.isRegLoc()) {
2548 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
Chris Lattnere0b12152008-03-17 06:57:02 +00002549 continue;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002550 }
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002551
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002552 // Register can't get to this point...
Chris Lattnere0b12152008-03-17 06:57:02 +00002553 assert(VA.isMemLoc());
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002554
Chris Lattnere0b12152008-03-17 06:57:02 +00002555 // Create the frame index object for this incoming parameter
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002556 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002557 VA.getLocMemOffset(), true);
Akira Hatanaka43299772011-05-20 23:22:14 +00002558 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
Chris Lattnere0b12152008-03-17 06:57:02 +00002559
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002560 // emit ISD::STORE whichs stores the
Chris Lattnere0b12152008-03-17 06:57:02 +00002561 // parameter value to a stack Location
Chris Lattner8026a9d2010-09-21 17:50:43 +00002562 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002563 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002564 }
2565
Akira Hatanaka3d21c242011-06-08 17:39:33 +00002566 // Extend range of indices of frame objects for outgoing arguments that were
2567 // created during this function call. Skip this step if no such objects were
2568 // created.
2569 if (LastFI)
2570 MipsFI->extendOutArgFIRange(FirstFI, LastFI);
2571
Akira Hatanakada7f5f12011-09-19 20:26:02 +00002572 // If a memcpy has been created to copy a byval arg to a stack, replace the
2573 // chain input of CallSeqStart with ByValChain.
2574 if (InChain != ByValChain)
2575 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain,
2576 NextStackOffsetVal);
2577
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002578 // Transform all store nodes into one single node because all store
2579 // nodes are independent of each other.
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002580 if (!MemOpChains.empty())
2581 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002582 &MemOpChains[0], MemOpChains.size());
2583
Bill Wendling056292f2008-09-16 21:48:12 +00002584 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002585 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2586 // node so that legalize doesn't hack it.
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002587 unsigned char OpFlag;
2588 bool IsPICCall = (IsN64 || IsPIC); // true if calls are translated to jalr $25
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002589 bool GlobalOrExternal = false;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002590 SDValue CalleeLo;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002591
2592 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002593 if (IsPICCall && G->getGlobal()->hasInternalLinkage()) {
2594 OpFlag = IsO32 ? MipsII::MO_GOT : MipsII::MO_GOT_PAGE;
2595 unsigned char LoFlag = IsO32 ? MipsII::MO_ABS_LO : MipsII::MO_GOT_OFST;
2596 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 0,
2597 OpFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002598 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(),
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002599 0, LoFlag);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002600 } else {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002601 OpFlag = IsPICCall ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002602 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2603 getPointerTy(), 0, OpFlag);
2604 }
2605
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002606 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002607 }
2608 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002609 if (IsN64 || (!IsO32 && IsPIC))
2610 OpFlag = MipsII::MO_GOT_DISP;
2611 else if (!IsPIC) // !N64 && static
2612 OpFlag = MipsII::MO_NO_FLAG;
2613 else // O32 & PIC
2614 OpFlag = MipsII::MO_GOT_CALL;
Akira Hatanaka82099682011-12-19 19:52:25 +00002615 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2616 OpFlag);
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002617 GlobalOrExternal = true;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002618 }
2619
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002620 SDValue InFlag;
2621
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002622 // Create nodes that load address of callee and copy it to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002623 if (IsPICCall) {
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002624 if (GlobalOrExternal) {
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002625 // Load callee address
Akira Hatanaka648f00c2012-02-24 22:34:47 +00002626 Callee = DAG.getNode(MipsISD::Wrapper, dl, getPointerTy(),
2627 GetGlobalReg(DAG, getPointerTy()), Callee);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002628 SDValue LoadValue = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
2629 Callee, MachinePointerInfo::getGOT(),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002630 false, false, false, 0);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002631
2632 // Use GOT+LO if callee has internal linkage.
2633 if (CalleeLo.getNode()) {
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002634 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, getPointerTy(), CalleeLo);
2635 Callee = DAG.getNode(ISD::ADD, dl, getPointerTy(), LoadValue, Lo);
Akira Hatanaka9777e7a2011-04-07 19:51:44 +00002636 } else
2637 Callee = LoadValue;
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002638 }
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002639 }
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002640
Jia Liubb481f82012-02-28 07:46:26 +00002641 // T9 should contain the address of the callee function if
Akira Hatanaka0dca9452011-12-09 01:45:12 +00002642 // -reloction-model=pic or it is an indirect call.
2643 if (IsPICCall || !GlobalOrExternal) {
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002644 // copy to T9
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002645 unsigned T9Reg = IsN64 ? Mips::T9_64 : Mips::T9;
2646 Chain = DAG.getCopyToReg(Chain, dl, T9Reg, Callee, SDValue(0, 0));
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002647 InFlag = Chain.getValue(1);
Akira Hatanakae42f33b2011-10-28 19:49:00 +00002648 Callee = DAG.getRegister(T9Reg, getPointerTy());
Akira Hatanakaf49fde22011-04-04 17:11:07 +00002649 }
Bill Wendling056292f2008-09-16 21:48:12 +00002650
Akira Hatanaka92d4aec2012-05-12 03:19:04 +00002651 // Insert node "GP copy globalreg" before call to function.
2652 // Lazy-binding stubs require GP to point to the GOT.
2653 if (IsPICCall) {
2654 unsigned GPReg = IsN64 ? Mips::GP_64 : Mips::GP;
2655 EVT Ty = IsN64 ? MVT::i64 : MVT::i32;
2656 RegsToPass.push_back(std::make_pair(GPReg, GetGlobalReg(DAG, Ty)));
2657 }
2658
Akira Hatanakacd0f90f2011-05-20 02:30:51 +00002659 // Build a sequence of copy-to-reg nodes chained together with token
2660 // chain and flag operands which copy the outgoing args into registers.
2661 // The InFlag in necessary since all emitted instructions must be
2662 // stuck together.
2663 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2664 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2665 RegsToPass[i].second, InFlag);
2666 InFlag = Chain.getValue(1);
2667 }
2668
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002669 // MipsJmpLink = #chain, #target_address, #opt_in_flags...
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002670 // = Chain, Callee, Reg#1, Reg#2, ...
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002671 //
2672 // Returns a chain & a flag for retval copy to use.
Chris Lattnerf1b4eaf2010-12-21 02:38:05 +00002673 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
Dan Gohman475871a2008-07-27 21:46:04 +00002674 SmallVector<SDValue, 8> Ops;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002675 Ops.push_back(Chain);
2676 Ops.push_back(Callee);
2677
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002678 // Add argument registers to the end of the list so that they are
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002679 // known live into the call.
2680 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2681 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2682 RegsToPass[i].second.getValueType()));
2683
Akira Hatanakab2930b92012-03-01 22:27:29 +00002684 // Add a register mask operand representing the call-preserved registers.
2685 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2686 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2687 assert(Mask && "Missing call preserved mask for calling convention");
2688 Ops.push_back(DAG.getRegisterMask(Mask));
2689
Gabor Greifba36cb52008-08-28 21:40:38 +00002690 if (InFlag.getNode())
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002691 Ops.push_back(InFlag);
2692
Dale Johannesen33c960f2009-02-04 20:06:27 +00002693 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002694 InFlag = Chain.getValue(1);
2695
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002696 // Create the CALLSEQ_END node.
Akira Hatanaka5f7451f2011-06-21 01:02:03 +00002697 Chain = DAG.getCALLSEQ_END(Chain,
2698 DAG.getIntPtrConstant(NextStackOffset, true),
Bruno Cardoso Lopes3ed6f872010-01-30 18:32:07 +00002699 DAG.getIntPtrConstant(0, true), InFlag);
2700 InFlag = Chain.getValue(1);
2701
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002702 // Handle result values, copying them out of physregs into vregs that we
2703 // return.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002704 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2705 Ins, dl, DAG, InVals);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002706}
2707
Dan Gohman98ca4f22009-08-05 01:29:28 +00002708/// LowerCallResult - Lower the result values of a call into the
2709/// appropriate copies out of appropriate physical registers.
2710SDValue
2711MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00002712 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00002713 const SmallVectorImpl<ISD::InputArg> &Ins,
2714 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +00002715 SmallVectorImpl<SDValue> &InVals) const {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002716 // Assign locations to each value returned by this call.
2717 SmallVector<CCValAssign, 16> RVLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002718 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2719 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002720
Dan Gohman98ca4f22009-08-05 01:29:28 +00002721 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002722
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002723 // Copy all of the result registers out of their specified physreg.
2724 for (unsigned i = 0; i != RVLocs.size(); ++i) {
Dale Johannesen33c960f2009-02-04 20:06:27 +00002725 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
Dan Gohman98ca4f22009-08-05 01:29:28 +00002726 RVLocs[i].getValVT(), InFlag).getValue(1);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002727 InFlag = Chain.getValue(2);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002728 InVals.push_back(Chain.getValue(0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002729 }
Bruno Cardoso Lopesc7db5612007-11-05 03:02:32 +00002730
Dan Gohman98ca4f22009-08-05 01:29:28 +00002731 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002732}
2733
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002734//===----------------------------------------------------------------------===//
Dan Gohman98ca4f22009-08-05 01:29:28 +00002735// Formal Arguments Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002736//===----------------------------------------------------------------------===//
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002737static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2738 std::vector<SDValue>& OutChains,
2739 SelectionDAG &DAG, unsigned NumWords, SDValue FIN,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002740 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2741 const Argument *FuncArg) {
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002742 unsigned LocMem = VA.getLocMemOffset();
2743 unsigned FirstWord = LocMem / 4;
2744
2745 // copy register A0 - A3 to frame object
2746 for (unsigned i = 0; i < NumWords; ++i) {
2747 unsigned CurWord = FirstWord + i;
2748 if (CurWord >= O32IntRegsSize)
2749 break;
2750
2751 unsigned SrcReg = O32IntRegs[CurWord];
Craig Topper420761a2012-04-20 07:30:17 +00002752 unsigned Reg = AddLiveIn(MF, SrcReg, &Mips::CPURegsRegClass);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002753 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN,
2754 DAG.getConstant(i * 4, MVT::i32));
2755 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002756 StorePtr, MachinePointerInfo(FuncArg, i * 4),
2757 false, false, 0);
Akira Hatanaka4231c7e2011-05-24 19:18:33 +00002758 OutChains.push_back(Store);
2759 }
2760}
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002761
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002762// Create frame object on stack and copy registers used for byval passing to it.
2763static unsigned
2764CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl,
2765 std::vector<SDValue>& OutChains, SelectionDAG &DAG,
2766 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags,
2767 MachineFrameInfo *MFI, bool IsRegLoc,
2768 SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002769 EVT PtrTy, const Argument *FuncArg) {
Craig Topperc5eaae42012-03-11 07:57:25 +00002770 const uint16_t *Reg = Mips64IntRegs + 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002771 int FOOffset; // Frame object offset from virtual frame pointer.
2772
2773 if (IsRegLoc) {
2774 Reg = std::find(Mips64IntRegs, Mips64IntRegs + 8, VA.getLocReg());
2775 FOOffset = (Reg - Mips64IntRegs) * 8 - 8 * 8;
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002776 }
2777 else
2778 FOOffset = VA.getLocMemOffset();
2779
2780 // Create frame object.
2781 unsigned NumRegs = (Flags.getByValSize() + 7) / 8;
2782 unsigned LastFI = MFI->CreateFixedObject(NumRegs * 8, FOOffset, true);
2783 SDValue FIN = DAG.getFrameIndex(LastFI, PtrTy);
2784 InVals.push_back(FIN);
2785
2786 // Copy arg registers.
2787 for (unsigned I = 0; (Reg != Mips64IntRegs + 8) && (I < NumRegs);
2788 ++Reg, ++I) {
Craig Topper420761a2012-04-20 07:30:17 +00002789 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002790 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, PtrTy, FIN,
2791 DAG.getConstant(I * 8, PtrTy));
2792 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
Akira Hatanakab4549e12012-03-27 03:13:56 +00002793 StorePtr, MachinePointerInfo(FuncArg, I * 8),
2794 false, false, 0);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002795 OutChains.push_back(Store);
2796 }
Jia Liubb481f82012-02-28 07:46:26 +00002797
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002798 return LastFI;
2799}
2800
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002801/// LowerFormalArguments - transform physical registers into virtual registers
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002802/// and generate load operations for arguments places on the stack.
Dan Gohman98ca4f22009-08-05 01:29:28 +00002803SDValue
2804MipsTargetLowering::LowerFormalArguments(SDValue Chain,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002805 CallingConv::ID CallConv,
2806 bool isVarArg,
Akira Hatanaka82099682011-12-19 19:52:25 +00002807 const SmallVectorImpl<ISD::InputArg> &Ins,
Akira Hatanaka0bf3dfb2011-04-15 21:00:26 +00002808 DebugLoc dl, SelectionDAG &DAG,
2809 SmallVectorImpl<SDValue> &InVals)
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002810 const {
Bruno Cardoso Lopesf7f3b502008-08-04 07:12:52 +00002811 MachineFunction &MF = DAG.getMachineFunction();
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002812 MachineFrameInfo *MFI = MF.getFrameInfo();
Bruno Cardoso Lopesa2b1bb52007-08-28 05:08:16 +00002813 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002814
Dan Gohman1e93df62010-04-17 14:41:14 +00002815 MipsFI->setVarArgsFrameIndex(0);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002816
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002817 // Used with vargs to acumulate store chains.
2818 std::vector<SDValue> OutChains;
2819
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002820 // Assign locations to all of the incoming arguments.
2821 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopher471e4222011-06-08 23:55:35 +00002822 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
Akira Hatanaka82099682011-12-19 19:52:25 +00002823 getTargetMachine(), ArgLocs, *DAG.getContext());
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00002824
Akira Hatanaka2ec69fa2011-10-28 18:47:24 +00002825 if (IsO32)
Akira Hatanaka95b8ae12011-05-19 18:06:05 +00002826 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002827 else
Dan Gohman98ca4f22009-08-05 01:29:28 +00002828 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002829
Akira Hatanakab4549e12012-03-27 03:13:56 +00002830 Function::const_arg_iterator FuncArg =
2831 DAG.getMachineFunction().getFunction()->arg_begin();
Akira Hatanaka43299772011-05-20 23:22:14 +00002832 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function.
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002833
Akira Hatanakab4549e12012-03-27 03:13:56 +00002834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++FuncArg) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002835 CCValAssign &VA = ArgLocs[i];
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002836 EVT ValVT = VA.getValVT();
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002837 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2838 bool IsRegLoc = VA.isRegLoc();
2839
2840 if (Flags.isByVal()) {
2841 assert(Flags.getByValSize() &&
2842 "ByVal args of size 0 should have been ignored by front-end.");
2843 if (IsO32) {
2844 unsigned NumWords = (Flags.getByValSize() + 3) / 4;
2845 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(),
2846 true);
2847 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
2848 InVals.push_back(FIN);
Akira Hatanakab4549e12012-03-27 03:13:56 +00002849 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags,
2850 &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002851 } else // N32/64
2852 LastFI = CopyMips64ByValRegs(MF, Chain, dl, OutChains, DAG, VA, Flags,
2853 MFI, IsRegLoc, InVals, MipsFI,
Akira Hatanakab4549e12012-03-27 03:13:56 +00002854 getPointerTy(), &*FuncArg);
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002855 continue;
2856 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002857
2858 // Arguments stored on registers
Akira Hatanaka3a5257d2011-11-12 02:29:58 +00002859 if (IsRegLoc) {
Owen Andersone50ed302009-08-10 22:56:29 +00002860 EVT RegVT = VA.getLocVT();
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002861 unsigned ArgReg = VA.getLocReg();
Craig Topper44d23822012-02-22 05:59:10 +00002862 const TargetRegisterClass *RC;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002863
Owen Anderson825b72b2009-08-11 20:47:22 +00002864 if (RegVT == MVT::i32)
Craig Topper420761a2012-04-20 07:30:17 +00002865 RC = &Mips::CPURegsRegClass;
Akira Hatanaka95934842011-09-24 01:34:44 +00002866 else if (RegVT == MVT::i64)
Craig Topper420761a2012-04-20 07:30:17 +00002867 RC = &Mips::CPU64RegsRegClass;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002868 else if (RegVT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00002869 RC = &Mips::FGR32RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002870 else if (RegVT == MVT::f64)
Craig Topper420761a2012-04-20 07:30:17 +00002871 RC = HasMips64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
Akira Hatanaka09dd60f2011-09-26 21:37:50 +00002872 else
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002873 llvm_unreachable("RegVT not supported by FormalArguments Lowering");
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002874
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002875 // Transform the arguments stored on
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002876 // physical registers into virtual ones
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002877 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC);
Dan Gohman98ca4f22009-08-05 01:29:28 +00002878 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002879
2880 // If this is an 8 or 16-bit value, it has been passed promoted
2881 // to 32 bits. Insert an assert[sz]ext to capture this, then
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002882 // truncate to the right size.
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002883 if (VA.getLocInfo() != CCValAssign::Full) {
Chris Lattnerd4015072009-03-26 05:28:14 +00002884 unsigned Opcode = 0;
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002885 if (VA.getLocInfo() == CCValAssign::SExt)
2886 Opcode = ISD::AssertSext;
2887 else if (VA.getLocInfo() == CCValAssign::ZExt)
2888 Opcode = ISD::AssertZext;
Chris Lattnerd4015072009-03-26 05:28:14 +00002889 if (Opcode)
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002890 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002891 DAG.getValueType(ValVT));
2892 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002893 }
2894
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002895 // Handle floating point arguments passed in integer registers.
2896 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
2897 (RegVT == MVT::i64 && ValVT == MVT::f64))
2898 ArgValue = DAG.getNode(ISD::BITCAST, dl, ValVT, ArgValue);
2899 else if (IsO32 && RegVT == MVT::i32 && ValVT == MVT::f64) {
2900 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
2901 getNextIntArgReg(ArgReg), RC);
2902 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
2903 if (!Subtarget->isLittle())
2904 std::swap(ArgValue, ArgValue2);
2905 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64,
2906 ArgValue, ArgValue2);
Bruno Cardoso Lopesb53db4f2009-03-19 02:12:28 +00002907 }
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002908
Dan Gohman98ca4f22009-08-05 01:29:28 +00002909 InVals.push_back(ArgValue);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002910 } else { // VA.isRegLoc()
2911
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002912 // sanity check
2913 assert(VA.isMemLoc());
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002914
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002915 // The stack pointer offset is relative to the caller stack frame.
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002916 LastFI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002917 VA.getLocMemOffset(), true);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002918
2919 // Create load nodes to retrieve arguments from the stack
Akira Hatanaka43299772011-05-20 23:22:14 +00002920 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy());
Akira Hatanakafeaa4c32011-10-28 19:55:48 +00002921 InVals.push_back(DAG.getLoad(ValVT, dl, Chain, FIN,
Akira Hatanaka43299772011-05-20 23:22:14 +00002922 MachinePointerInfo::getFixedStack(LastFI),
Pete Cooperd752e0f2011-11-08 18:42:53 +00002923 false, false, false, 0));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002924 }
2925 }
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002926
2927 // The mips ABIs for returning structs by value requires that we copy
2928 // the sret argument into $v0 for the return. Save the argument into
2929 // a virtual register so that we can access it from the return points.
2930 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
2931 unsigned Reg = MipsFI->getSRetReturnReg();
2932 if (!Reg) {
Owen Anderson825b72b2009-08-11 20:47:22 +00002933 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002934 MipsFI->setSRetReturnReg(Reg);
2935 }
Dan Gohman98ca4f22009-08-05 01:29:28 +00002936 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
Owen Anderson825b72b2009-08-11 20:47:22 +00002937 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00002938 }
2939
Akira Hatanakabad53f42011-11-14 19:01:09 +00002940 if (isVarArg) {
2941 unsigned NumOfRegs = IsO32 ? 4 : 8;
Craig Topperc5eaae42012-03-11 07:57:25 +00002942 const uint16_t *ArgRegs = IsO32 ? O32IntRegs : Mips64IntRegs;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002943 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumOfRegs);
2944 int FirstRegSlotOffset = IsO32 ? 0 : -64 ; // offset of $a0's slot.
Craig Topper420761a2012-04-20 07:30:17 +00002945 const TargetRegisterClass *RC = IsO32 ?
2946 (const TargetRegisterClass*)&Mips::CPURegsRegClass :
2947 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
Akira Hatanakabad53f42011-11-14 19:01:09 +00002948 unsigned RegSize = RC->getSize();
2949 int RegSlotOffset = FirstRegSlotOffset + Idx * RegSize;
2950
2951 // Offset of the first variable argument from stack pointer.
2952 int FirstVaArgOffset;
2953
2954 if (IsO32 || (Idx == NumOfRegs)) {
2955 FirstVaArgOffset =
2956 (CCInfo.getNextStackOffset() + RegSize - 1) / RegSize * RegSize;
2957 } else
2958 FirstVaArgOffset = RegSlotOffset;
2959
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002960 // Record the frame index of the first variable argument
Eric Christopher471e4222011-06-08 23:55:35 +00002961 // which is a value necessary to VASTART.
Akira Hatanakabad53f42011-11-14 19:01:09 +00002962 LastFI = MFI->CreateFixedObject(RegSize, FirstVaArgOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002963 MipsFI->setVarArgsFrameIndex(LastFI);
Akira Hatanakaedacba82011-05-25 17:32:06 +00002964
Akira Hatanakabad53f42011-11-14 19:01:09 +00002965 // Copy the integer registers that have not been used for argument passing
2966 // to the argument register save area. For O32, the save area is allocated
2967 // in the caller's stack frame, while for N32/64, it is allocated in the
2968 // callee's stack frame.
2969 for (int StackOffset = RegSlotOffset;
2970 Idx < NumOfRegs; ++Idx, StackOffset += RegSize) {
2971 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegs[Idx], RC);
2972 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2973 MVT::getIntegerVT(RegSize * 8));
2974 LastFI = MFI->CreateFixedObject(RegSize, StackOffset, true);
Akira Hatanakab4d8d312011-05-24 00:23:52 +00002975 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy());
2976 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
Akira Hatanaka82099682011-12-19 19:52:25 +00002977 MachinePointerInfo(), false, false, 0));
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002978 }
2979 }
2980
Akira Hatanaka43299772011-05-20 23:22:14 +00002981 MipsFI->setLastInArgFI(LastFI);
2982
Wesley Peckbf17cfa2010-11-23 03:31:01 +00002983 // All stores are grouped in one node to allow the matching between
Bruno Cardoso Lopesb37a7422010-02-06 19:20:49 +00002984 // the size of Ins and InVals. This only happens when on varg functions
2985 if (!OutChains.empty()) {
2986 OutChains.push_back(Chain);
2987 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2988 &OutChains[0], OutChains.size());
2989 }
2990
Dan Gohman98ca4f22009-08-05 01:29:28 +00002991 return Chain;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002992}
2993
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002994//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002995// Return Value Calling Convention Implementation
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00002996//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00002997
Dan Gohman98ca4f22009-08-05 01:29:28 +00002998SDValue
2999MipsTargetLowering::LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +00003000 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +00003001 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +00003002 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +00003003 DebugLoc dl, SelectionDAG &DAG) const {
Dan Gohman98ca4f22009-08-05 01:29:28 +00003004
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003005 // CCValAssign - represent the assignment of
3006 // the return value to a location
3007 SmallVector<CCValAssign, 16> RVLocs;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003008
3009 // CCState - Info about the registers and stack slot.
Eric Christopher471e4222011-06-08 23:55:35 +00003010 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3011 getTargetMachine(), RVLocs, *DAG.getContext());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003012
Dan Gohman98ca4f22009-08-05 01:29:28 +00003013 // Analize return values.
3014 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003015
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003016 // If this is the first return lowered for this function, add
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003017 // the regs to the liveout set for the function.
Chris Lattner84bc5422007-12-31 04:13:23 +00003018 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003019 for (unsigned i = 0; i != RVLocs.size(); ++i)
Bruno Cardoso Lopes2ab22d12007-07-11 23:16:16 +00003020 if (RVLocs[i].isRegLoc())
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003021 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003022 }
3023
Dan Gohman475871a2008-07-27 21:46:04 +00003024 SDValue Flag;
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003025
3026 // Copy the result values into the output registers.
3027 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3028 CCValAssign &VA = RVLocs[i];
3029 assert(VA.isRegLoc() && "Can only return in registers!");
3030
Akira Hatanaka82099682011-12-19 19:52:25 +00003031 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003032
3033 // guarantee that all emitted copies are
3034 // stuck together, avoiding something bad
3035 Flag = Chain.getValue(1);
3036 }
3037
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003038 // The mips ABIs for returning structs by value requires that we copy
3039 // the sret argument into $v0 for the return. We saved the argument into
3040 // a virtual register in the entry block, so now we copy the value out
3041 // and into $v0.
3042 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
3043 MachineFunction &MF = DAG.getMachineFunction();
3044 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3045 unsigned Reg = MipsFI->getSRetReturnReg();
3046
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003047 if (!Reg)
Torok Edwinc23197a2009-07-14 16:55:14 +00003048 llvm_unreachable("sret virtual register not created in the entry block");
Dale Johannesena05dca42009-02-04 23:02:30 +00003049 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003050
Dale Johannesena05dca42009-02-04 23:02:30 +00003051 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003052 Flag = Chain.getValue(1);
3053 }
3054
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003055 // Return on Mips is always a "jr $ra"
Gabor Greifba36cb52008-08-28 21:40:38 +00003056 if (Flag.getNode())
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003057 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00003058 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003059 else // Return Void
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003060 return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
Owen Anderson825b72b2009-08-11 20:47:22 +00003061 Chain, DAG.getRegister(Mips::RA, MVT::i32));
Bruno Cardoso Lopes972f5892007-06-06 07:42:06 +00003062}
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003063
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003064//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003065// Mips Inline Assembly Support
Akira Hatanaka4552c9a2011-04-15 21:51:11 +00003066//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003067
3068/// getConstraintType - Given a constraint letter, return the type of
3069/// constraint it is for this target.
3070MipsTargetLowering::ConstraintType MipsTargetLowering::
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003071getConstraintType(const std::string &Constraint) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003072{
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003073 // Mips specific constrainy
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003074 // GCC config/mips/constraints.md
3075 //
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003076 // 'd' : An address register. Equivalent to r
3077 // unless generating MIPS16 code.
3078 // 'y' : Equivalent to r; retained for
3079 // backwards compatibility.
Eric Christopher1d5a3922012-05-07 06:25:10 +00003080 // 'c' : A register suitable for use in an indirect
3081 // jump. This will always be $25 for -mabicalls.
Eric Christopheraf97f732012-05-07 06:25:19 +00003082 // 'l' : The lo register. 1 word storage.
3083 // 'x' : The hilo register pair. Double word storage.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003084 if (Constraint.size() == 1) {
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003085 switch (Constraint[0]) {
3086 default : break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003087 case 'd':
3088 case 'y':
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003089 case 'f':
Eric Christopher1d5a3922012-05-07 06:25:10 +00003090 case 'c':
Eric Christopher4adbefe2012-05-07 06:25:15 +00003091 case 'l':
Eric Christopheraf97f732012-05-07 06:25:19 +00003092 case 'x':
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003093 return C_RegisterClass;
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003094 }
3095 }
3096 return TargetLowering::getConstraintType(Constraint);
3097}
3098
John Thompson44ab89e2010-10-29 17:29:13 +00003099/// Examine constraint type and operand type and determine a weight value.
3100/// This object must already have been set up with the operand type
3101/// and the current alternative constraint selected.
3102TargetLowering::ConstraintWeight
3103MipsTargetLowering::getSingleConstraintMatchWeight(
3104 AsmOperandInfo &info, const char *constraint) const {
3105 ConstraintWeight weight = CW_Invalid;
3106 Value *CallOperandVal = info.CallOperandVal;
3107 // If we don't have a value, we can't do a match,
3108 // but allow it at the lowest weight.
3109 if (CallOperandVal == NULL)
3110 return CW_Default;
Chris Lattnerdb125cf2011-07-18 04:54:35 +00003111 Type *type = CallOperandVal->getType();
John Thompson44ab89e2010-10-29 17:29:13 +00003112 // Look at the constraint type.
3113 switch (*constraint) {
3114 default:
3115 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3116 break;
Wesley Peckbf17cfa2010-11-23 03:31:01 +00003117 case 'd':
3118 case 'y':
John Thompson44ab89e2010-10-29 17:29:13 +00003119 if (type->isIntegerTy())
3120 weight = CW_Register;
3121 break;
3122 case 'f':
3123 if (type->isFloatTy())
3124 weight = CW_Register;
3125 break;
Eric Christopher1d5a3922012-05-07 06:25:10 +00003126 case 'c': // $25 for indirect jumps
Eric Christopher4adbefe2012-05-07 06:25:15 +00003127 case 'l': // lo register
Eric Christopheraf97f732012-05-07 06:25:19 +00003128 case 'x': // hilo register pair
Eric Christopher1d5a3922012-05-07 06:25:10 +00003129 if (type->isIntegerTy())
3130 weight = CW_SpecificReg;
3131 break;
Eric Christopher50ab0392012-05-07 03:13:32 +00003132 case 'I': // signed 16 bit immediate
Eric Christophere5076d42012-05-07 03:13:42 +00003133 case 'J': // integer zero
Eric Christopherf49f8462012-05-07 05:46:29 +00003134 case 'K': // unsigned 16 bit immediate
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003135 case 'L': // signed 32 bit immediate where lower 16 bits are 0
Eric Christopher60cfc792012-05-07 05:46:43 +00003136 case 'N': // immediate in the range of -65535 to -1 (inclusive)
Eric Christopher1ce20342012-05-07 05:46:48 +00003137 case 'O': // signed 15 bit immediate (+- 16383)
Eric Christopher54412a72012-05-07 06:25:02 +00003138 case 'P': // immediate in the range of 65535 to 1 (inclusive)
Eric Christopher50ab0392012-05-07 03:13:32 +00003139 if (isa<ConstantInt>(CallOperandVal))
3140 weight = CW_Constant;
3141 break;
John Thompson44ab89e2010-10-29 17:29:13 +00003142 }
3143 return weight;
3144}
3145
Eric Christopher38d64262011-06-29 19:33:04 +00003146/// Given a register class constraint, like 'r', if this corresponds directly
3147/// to an LLVM register class, return a register of 0 and the register class
3148/// pointer.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003149std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
Owen Andersone50ed302009-08-10 22:56:29 +00003150getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003151{
3152 if (Constraint.size() == 1) {
3153 switch (Constraint[0]) {
Eric Christopher314aff12011-06-29 19:04:31 +00003154 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3155 case 'y': // Same as 'r'. Exists for compatibility.
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003156 case 'r':
Eric Christopher3ccbd472012-05-07 03:13:16 +00003157 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
Craig Topper420761a2012-04-20 07:30:17 +00003158 return std::make_pair(0U, &Mips::CPURegsRegClass);
Eric Christopher0ed1f762012-05-07 03:13:22 +00003159 if (VT == MVT::i64 && HasMips64)
3160 return std::make_pair(0U, &Mips::CPU64RegsRegClass);
3161 // This will generate an error message
3162 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes225ca9c2008-07-05 19:05:21 +00003163 case 'f':
Owen Anderson825b72b2009-08-11 20:47:22 +00003164 if (VT == MVT::f32)
Craig Topper420761a2012-04-20 07:30:17 +00003165 return std::make_pair(0U, &Mips::FGR32RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003166 if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) {
3167 if (Subtarget->isFP64bit())
Craig Topper420761a2012-04-20 07:30:17 +00003168 return std::make_pair(0U, &Mips::FGR64RegClass);
3169 return std::make_pair(0U, &Mips::AFGR64RegClass);
Akira Hatanakacb9dd722012-01-04 02:45:01 +00003170 }
Eric Christopher1d5a3922012-05-07 06:25:10 +00003171 break;
3172 case 'c': // register suitable for indirect jump
3173 if (VT == MVT::i32)
3174 return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
3175 assert(VT == MVT::i64 && "Unexpected type.");
3176 return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
Eric Christopher4adbefe2012-05-07 06:25:15 +00003177 case 'l': // register suitable for indirect jump
3178 if (VT == MVT::i32)
3179 return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
3180 return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
Eric Christopheraf97f732012-05-07 06:25:19 +00003181 case 'x': // register suitable for indirect jump
3182 // Fixme: Not triggering the use of both hi and low
3183 // This will generate an error message
3184 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Bruno Cardoso Lopes84f47c52007-08-21 16:09:25 +00003185 }
3186 }
3187 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3188}
3189
Eric Christopher50ab0392012-05-07 03:13:32 +00003190/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3191/// vector. If it is invalid, don't add anything to Ops.
3192void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3193 std::string &Constraint,
3194 std::vector<SDValue>&Ops,
3195 SelectionDAG &DAG) const {
3196 SDValue Result(0, 0);
3197
3198 // Only support length 1 constraints for now.
3199 if (Constraint.length() > 1) return;
3200
3201 char ConstraintLetter = Constraint[0];
3202 switch (ConstraintLetter) {
3203 default: break; // This will fall through to the generic implementation
3204 case 'I': // Signed 16 bit constant
3205 // If this fails, the parent routine will give an error
3206 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3207 EVT Type = Op.getValueType();
3208 int64_t Val = C->getSExtValue();
3209 if (isInt<16>(Val)) {
3210 Result = DAG.getTargetConstant(Val, Type);
3211 break;
3212 }
3213 }
3214 return;
Eric Christophere5076d42012-05-07 03:13:42 +00003215 case 'J': // integer zero
3216 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3217 EVT Type = Op.getValueType();
3218 int64_t Val = C->getZExtValue();
3219 if (Val == 0) {
3220 Result = DAG.getTargetConstant(0, Type);
3221 break;
3222 }
3223 }
3224 return;
Eric Christopherf49f8462012-05-07 05:46:29 +00003225 case 'K': // unsigned 16 bit immediate
3226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3227 EVT Type = Op.getValueType();
3228 uint64_t Val = (uint64_t)C->getZExtValue();
3229 if (isUInt<16>(Val)) {
3230 Result = DAG.getTargetConstant(Val, Type);
3231 break;
3232 }
3233 }
3234 return;
Eric Christopher5ac47bb2012-05-07 05:46:37 +00003235 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3237 EVT Type = Op.getValueType();
3238 int64_t Val = C->getSExtValue();
3239 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3240 Result = DAG.getTargetConstant(Val, Type);
3241 break;
3242 }
3243 }
3244 return;
Eric Christopher60cfc792012-05-07 05:46:43 +00003245 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3246 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3247 EVT Type = Op.getValueType();
3248 int64_t Val = C->getSExtValue();
3249 if ((Val >= -65535) && (Val <= -1)) {
3250 Result = DAG.getTargetConstant(Val, Type);
3251 break;
3252 }
3253 }
3254 return;
Eric Christopher1ce20342012-05-07 05:46:48 +00003255 case 'O': // signed 15 bit immediate
3256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3257 EVT Type = Op.getValueType();
3258 int64_t Val = C->getSExtValue();
3259 if ((isInt<15>(Val))) {
3260 Result = DAG.getTargetConstant(Val, Type);
3261 break;
3262 }
3263 }
3264 return;
Eric Christopher54412a72012-05-07 06:25:02 +00003265 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3267 EVT Type = Op.getValueType();
3268 int64_t Val = C->getSExtValue();
3269 if ((Val <= 65535) && (Val >= 1)) {
3270 Result = DAG.getTargetConstant(Val, Type);
3271 break;
3272 }
3273 }
3274 return;
Eric Christopher50ab0392012-05-07 03:13:32 +00003275 }
3276
3277 if (Result.getNode()) {
3278 Ops.push_back(Result);
3279 return;
3280 }
3281
3282 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3283}
3284
Dan Gohman6520e202008-10-18 02:06:02 +00003285bool
3286MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3287 // The Mips target isn't yet aware of offsets.
3288 return false;
3289}
Evan Chengeb2f9692009-10-27 19:56:55 +00003290
Evan Chenga1eaa3c2009-10-28 01:43:28 +00003291bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3292 if (VT != MVT::f32 && VT != MVT::f64)
3293 return false;
Bruno Cardoso Lopes6b902822011-01-18 19:41:41 +00003294 if (Imm.isNegZero())
3295 return false;
Evan Chengeb2f9692009-10-27 19:56:55 +00003296 return Imm.isZero();
3297}
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003298
3299unsigned MipsTargetLowering::getJumpTableEncoding() const {
3300 if (IsN64)
3301 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
Jia Liubb481f82012-02-28 07:46:26 +00003302
Akira Hatanaka6c2cf8b2012-02-03 04:33:00 +00003303 return TargetLowering::getJumpTableEncoding();
3304}