Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 1 | //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===// |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 2 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | b5f662f | 2005-04-21 23:30:14 +0000 | [diff] [blame] | 7 | // |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 10 | // This file contains the SPARC implementation of the MRegisterInfo class. |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 14 | #include "Sparc.h" |
| 15 | #include "SparcRegisterInfo.h" |
| 16 | #include "SparcSubtarget.h" |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 18 | #include "llvm/CodeGen/MachineFunction.h" |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/MachineFrameInfo.h" |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 20 | #include "llvm/CodeGen/MachineLocation.h" |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetInstrInfo.h" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 22 | #include "llvm/Type.h" |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 23 | #include "llvm/ADT/BitVector.h" |
Brian Gaeke | 74dfcf1 | 2004-09-02 02:37:43 +0000 | [diff] [blame] | 24 | #include "llvm/ADT/STLExtras.h" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 25 | using namespace llvm; |
| 26 | |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 27 | SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, |
| 28 | const TargetInstrInfo &tii) |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 29 | : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), |
Evan Cheng | 7ce4578 | 2006-11-13 23:36:35 +0000 | [diff] [blame] | 30 | Subtarget(st), TII(tii) { |
Chris Lattner | 69d3909 | 2006-02-04 06:58:46 +0000 | [diff] [blame] | 31 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 32 | |
Evan Cheng | bf2c8b3 | 2007-03-20 08:09:38 +0000 | [diff] [blame] | 33 | void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB, |
| 34 | MachineBasicBlock::iterator I, |
| 35 | unsigned DestReg, |
| 36 | const MachineInstr *Orig) const { |
| 37 | MachineInstr *MI = Orig->clone(); |
| 38 | MI->getOperand(0).setReg(DestReg); |
| 39 | MBB.insert(I, MI); |
| 40 | } |
| 41 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 42 | MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI, |
Evan Cheng | aee4af6 | 2007-12-02 08:30:39 +0000 | [diff] [blame] | 43 | SmallVectorImpl<unsigned> &Ops, |
| 44 | int FI) const { |
| 45 | if (Ops.size() != 1) return NULL; |
| 46 | |
| 47 | unsigned OpNum = Ops[0]; |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 48 | bool isFloat = false; |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 49 | MachineInstr *NewMI = NULL; |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 50 | switch (MI->getOpcode()) { |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 51 | case SP::ORrr: |
| 52 | if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 53 | MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { |
| 54 | if (OpNum == 0) // COPY -> STORE |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 55 | NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 56 | .addReg(MI->getOperand(2).getReg()); |
| 57 | else // COPY -> LOAD |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 58 | NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg()) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 59 | .addFrameIndex(FI).addImm(0); |
| 60 | } |
| 61 | break; |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 62 | case SP::FMOVS: |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 63 | isFloat = true; |
| 64 | // FALLTHROUGH |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 65 | case SP::FMOVD: |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 66 | if (OpNum == 0) // COPY -> STORE |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 67 | NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri)) |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 68 | .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg()); |
| 69 | else // COPY -> LOAD |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 70 | NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri), |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 71 | MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0); |
| 72 | break; |
| 73 | } |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 74 | |
| 75 | if (NewMI) |
| 76 | NewMI->copyKillDeadInfo(MI); |
| 77 | return NewMI; |
Chris Lattner | 6184f9c | 2006-02-03 07:06:25 +0000 | [diff] [blame] | 78 | } |
| 79 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 80 | const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) |
| 81 | const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 82 | static const unsigned CalleeSavedRegs[] = { 0 }; |
| 83 | return CalleeSavedRegs; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 84 | } |
| 85 | |
Evan Cheng | b371f45 | 2007-02-19 21:49:54 +0000 | [diff] [blame] | 86 | BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { |
| 87 | BitVector Reserved(getNumRegs()); |
| 88 | Reserved.set(SP::G2); |
| 89 | Reserved.set(SP::G3); |
| 90 | Reserved.set(SP::G4); |
| 91 | Reserved.set(SP::O6); |
| 92 | Reserved.set(SP::I6); |
| 93 | Reserved.set(SP::I7); |
| 94 | Reserved.set(SP::G0); |
| 95 | Reserved.set(SP::G5); |
| 96 | Reserved.set(SP::G6); |
| 97 | Reserved.set(SP::G7); |
| 98 | return Reserved; |
| 99 | } |
| 100 | |
| 101 | |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 102 | const TargetRegisterClass* const* |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 103 | SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { |
Evan Cheng | c2b861d | 2007-01-02 21:33:40 +0000 | [diff] [blame] | 104 | static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 }; |
| 105 | return CalleeSavedRegClasses; |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 106 | } |
| 107 | |
Evan Cheng | dc77540 | 2007-01-23 00:57:47 +0000 | [diff] [blame] | 108 | bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const { |
| 109 | return false; |
| 110 | } |
Evan Cheng | 0f3ac8d | 2006-05-18 00:12:58 +0000 | [diff] [blame] | 111 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 112 | void SparcRegisterInfo:: |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 113 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 114 | MachineBasicBlock::iterator I) const { |
Brian Gaeke | 85c0835 | 2004-10-10 19:57:21 +0000 | [diff] [blame] | 115 | MachineInstr &MI = *I; |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 116 | int Size = MI.getOperand(0).getImm(); |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 117 | if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) |
Chris Lattner | 43875e6 | 2005-12-19 02:51:12 +0000 | [diff] [blame] | 118 | Size = -Size; |
| 119 | if (Size) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 120 | BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); |
Chris Lattner | 43875e6 | 2005-12-19 02:51:12 +0000 | [diff] [blame] | 121 | MBB.erase(I); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 122 | } |
| 123 | |
Evan Cheng | 5e6df46 | 2007-02-28 00:21:17 +0000 | [diff] [blame] | 124 | void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Evan Cheng | 97de913 | 2007-05-01 09:13:03 +0000 | [diff] [blame] | 125 | int SPAdj, RegScavenger *RS) const { |
| 126 | assert(SPAdj == 0 && "Unexpected"); |
| 127 | |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 128 | unsigned i = 0; |
| 129 | MachineInstr &MI = *II; |
| 130 | while (!MI.getOperand(i).isFrameIndex()) { |
| 131 | ++i; |
| 132 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 133 | } |
| 134 | |
Chris Lattner | 8aa797a | 2007-12-30 23:10:15 +0000 | [diff] [blame] | 135 | int FrameIndex = MI.getOperand(i).getIndex(); |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 136 | |
Brian Gaeke | 3a8ad62 | 2004-04-06 22:10:22 +0000 | [diff] [blame] | 137 | // Addressable stack objects are accessed using neg. offsets from %fp |
Chris Lattner | b8ce4c4 | 2004-08-14 22:57:22 +0000 | [diff] [blame] | 138 | MachineFunction &MF = *MI.getParent()->getParent(); |
Brian Gaeke | 3a8ad62 | 2004-04-06 22:10:22 +0000 | [diff] [blame] | 139 | int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + |
Chris Lattner | 9a1ceae | 2007-12-30 20:49:49 +0000 | [diff] [blame] | 140 | MI.getOperand(i+1).getImm(); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 141 | |
| 142 | // Replace frame index with a frame pointer reference. |
| 143 | if (Offset >= -4096 && Offset <= 4095) { |
| 144 | // If the offset is small enough to fit in the immediate field, directly |
| 145 | // encode it. |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 146 | MI.getOperand(i).ChangeToRegister(SP::I6, false); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 147 | MI.getOperand(i+1).ChangeToImmediate(Offset); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 148 | } else { |
| 149 | // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to |
| 150 | // scavenge a register here instead of reserving G1 all of the time. |
| 151 | unsigned OffHi = (unsigned)Offset >> 10U; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 152 | BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 153 | // Emit G1 = G1 + I6 |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 154 | BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) |
| 155 | .addReg(SP::I6); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 156 | // Insert: G1+%lo(offset) into the user. |
Chris Lattner | 09e4606 | 2006-09-05 02:31:13 +0000 | [diff] [blame] | 157 | MI.getOperand(i).ChangeToRegister(SP::G1, false); |
Chris Lattner | e53f4a0 | 2006-05-04 17:52:23 +0000 | [diff] [blame] | 158 | MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 159 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 160 | } |
| 161 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 162 | void SparcRegisterInfo:: |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 163 | processFunctionBeforeFrameFinalized(MachineFunction &MF) const {} |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 164 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 165 | void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const { |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 166 | MachineBasicBlock &MBB = MF.front(); |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 167 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 168 | |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 169 | // Get the number of bytes to allocate from the FrameInfo |
Brian Gaeke | ef8e48a | 2004-04-13 18:28:37 +0000 | [diff] [blame] | 170 | int NumBytes = (int) MFI->getStackSize(); |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 171 | |
Brian Gaeke | 85c0835 | 2004-10-10 19:57:21 +0000 | [diff] [blame] | 172 | // Emit the correct save instruction based on the number of bytes in |
| 173 | // the frame. Minimum stack frame size according to V8 ABI is: |
Brian Gaeke | 6c5526e | 2004-04-02 20:53:37 +0000 | [diff] [blame] | 174 | // 16 words for register window spill |
| 175 | // 1 word for address of returned aggregate-value |
| 176 | // + 6 words for passing parameters on the stack |
| 177 | // ---------- |
| 178 | // 23 words * 4 bytes per word = 92 bytes |
| 179 | NumBytes += 92; |
Brian Gaeke | 6713d98 | 2004-06-17 22:34:48 +0000 | [diff] [blame] | 180 | // Round up to next doubleword boundary -- a double-word boundary |
| 181 | // is required by the ABI. |
| 182 | NumBytes = (NumBytes + 7) & ~7; |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 183 | NumBytes = -NumBytes; |
| 184 | |
| 185 | if (NumBytes >= -4096) { |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 186 | BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri), |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 187 | SP::O6).addImm(NumBytes).addReg(SP::O6); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 188 | } else { |
| 189 | MachineBasicBlock::iterator InsertPt = MBB.begin(); |
| 190 | // Emit this the hard way. This clobbers G1 which we always know is |
| 191 | // available here. |
| 192 | unsigned OffHi = (unsigned)NumBytes >> 10U; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 193 | BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 194 | // Emit G1 = G1 + I6 |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 195 | BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1) |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 196 | .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 197 | BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6) |
| 198 | .addReg(SP::O6).addReg(SP::G1); |
Chris Lattner | 85e42b4 | 2005-12-20 07:56:31 +0000 | [diff] [blame] | 199 | } |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 200 | } |
| 201 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 202 | void SparcRegisterInfo::emitEpilogue(MachineFunction &MF, |
| 203 | MachineBasicBlock &MBB) const { |
Chris Lattner | e1274de | 2004-02-29 05:18:30 +0000 | [diff] [blame] | 204 | MachineBasicBlock::iterator MBBI = prior(MBB.end()); |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 205 | assert(MBBI->getOpcode() == SP::RETL && |
Brian Gaeke | d69b3c5 | 2004-03-06 05:31:21 +0000 | [diff] [blame] | 206 | "Can only put epilog before 'retl' instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 207 | BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) |
| 208 | .addReg(SP::G0); |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 209 | } |
| 210 | |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 211 | unsigned SparcRegisterInfo::getRARegister() const { |
| 212 | assert(0 && "What is the return address register"); |
| 213 | return 0; |
| 214 | } |
| 215 | |
Jim Laskey | a997918 | 2006-03-28 13:48:33 +0000 | [diff] [blame] | 216 | unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const { |
Jim Laskey | 4188699 | 2006-04-07 16:34:46 +0000 | [diff] [blame] | 217 | assert(0 && "What is the frame register"); |
| 218 | return SP::G1; |
Jim Laskey | f1d78e8 | 2006-03-23 18:12:57 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Jim Laskey | 62819f3 | 2007-02-21 22:54:50 +0000 | [diff] [blame] | 221 | unsigned SparcRegisterInfo::getEHExceptionRegister() const { |
| 222 | assert(0 && "What is the exception register"); |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | unsigned SparcRegisterInfo::getEHHandlerRegister() const { |
| 227 | assert(0 && "What is the exception handler register"); |
| 228 | return 0; |
| 229 | } |
| 230 | |
Dale Johannesen | b97aec6 | 2007-11-13 19:13:01 +0000 | [diff] [blame] | 231 | int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { |
Anton Korobeynikov | f191c80 | 2007-11-11 19:50:10 +0000 | [diff] [blame] | 232 | assert(0 && "What is the dwarf register number"); |
| 233 | return -1; |
| 234 | } |
| 235 | |
Chris Lattner | 7c90f73 | 2006-02-05 05:50:24 +0000 | [diff] [blame] | 236 | #include "SparcGenRegisterInfo.inc" |
Brian Gaeke | e785e53 | 2004-02-25 19:28:19 +0000 | [diff] [blame] | 237 | |