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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / fa515ecbca942d44b2700799622b34345ea02852 / . / test / CodeGen / ARM / atomic-op.ll
blob: 03940e38ce86a5a36ba5476d7d63916a2a081947 [file] [log] [blame]
Cameron Zwarichde64aaf2011-05-27 23:54:00 +0000[diff] [blame]1; RUN: llc < %s -mtriple=armv7-apple-darwin10 | FileCheck %s
2; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
3
4define void @func(i32 %argc, i8** %argv) nounwind {
5entry:
6 %argc.addr = alloca i32 ; <i32*> [#uses=1]
7 %argv.addr = alloca i8** ; <i8***> [#uses=1]
8 %val1 = alloca i32 ; <i32*> [#uses=2]
9 %val2 = alloca i32 ; <i32*> [#uses=15]
10 %andt = alloca i32 ; <i32*> [#uses=2]
11 %ort = alloca i32 ; <i32*> [#uses=2]
12 %xort = alloca i32 ; <i32*> [#uses=2]
13 %old = alloca i32 ; <i32*> [#uses=18]
14 %temp = alloca i32 ; <i32*> [#uses=2]
15 store i32 %argc, i32* %argc.addr
16 store i8** %argv, i8*** %argv.addr
17 store i32 0, i32* %val1
18 store i32 31, i32* %val2
19 store i32 3855, i32* %andt
20 store i32 3855, i32* %ort
21 store i32 3855, i32* %xort
22 store i32 4, i32* %temp
23 %tmp = load i32* %temp
24 ; CHECK: ldrex
25 ; CHECK: add
26 ; CHECK: strex
27 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1]
28 store i32 %0, i32* %old
29 ; CHECK: ldrex
30 ; CHECK: sub
31 ; CHECK: strex
32 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1]
33 store i32 %1, i32* %old
34 ; CHECK: ldrex
35 ; CHECK: add
36 ; CHECK: strex
37 call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1]
38 store i32 %2, i32* %old
39 ; CHECK: ldrex
40 ; CHECK: sub
41 ; CHECK: strex
42 call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1]
43 store i32 %3, i32* %old
44 ; CHECK: ldrex
45 ; CHECK: and
46 ; CHECK: strex
47 call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1]
48 store i32 %4, i32* %old
49 ; CHECK: ldrex
50 ; CHECK: or
51 ; CHECK: strex
52 call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1]
53 store i32 %5, i32* %old
54 ; CHECK: ldrex
55 ; CHECK: eor
56 ; CHECK: strex
57 call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1]
58 store i32 %6, i32* %old
59 ; CHECK: ldrex
60 ; CHECK: cmp
61 ; CHECK: strex
62 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1]
63 store i32 %7, i32* %old
64 %neg = sub i32 0, 1 ; <i32> [#uses=1]
65 ; CHECK: ldrex
66 ; CHECK: cmp
67 ; CHECK: strex
68 call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1]
69 store i32 %8, i32* %old
70 ; CHECK: ldrex
71 ; CHECK: cmp
72 ; CHECK: strex
73 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1]
74 store i32 %9, i32* %old
75 ; CHECK: ldrex
76 ; CHECK: cmp
77 ; CHECK: strex
78 call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1]
79 store i32 %10, i32* %old
80 ret void
81}
82
83declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind
84
85declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind
86
87declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind
88
89declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind
90
91declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind
92
93declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind
94
95declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind
96
97declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind
98
99declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind
100
101declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
102
103declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind