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Chris Lattner97f06932009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindola7bc59bc2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner95b2c7d2006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000016#include "ARM.h"
Anton Korobeynikov88ce6672009-05-23 19:51:20 +000017#include "ARMBuildAttrs.h"
Evan Chenga8e29892007-01-19 07:51:42 +000018#include "ARMAddressingModes.h"
19#include "ARMConstantPoolValue.h"
Jim Grosbach7ac16092010-10-01 22:39:28 +000020#include "InstPrinter/ARMInstPrinter.h"
Jim Grosbachbaf120f2010-12-01 03:45:07 +000021#include "ARMAsmPrinter.h"
Chris Lattner97f06932009-10-19 20:20:46 +000022#include "ARMMachineFunctionInfo.h"
Chris Lattner97f06932009-10-19 20:20:46 +000023#include "ARMTargetMachine.h"
Jason W Kim17b443d2010-10-11 23:01:44 +000024#include "ARMTargetObjectFile.h"
Dale Johannesen3f282aa2010-04-26 20:07:31 +000025#include "llvm/Analysis/DebugInfo.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000026#include "llvm/Constants.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000027#include "llvm/Module.h"
Benjamin Kramere55b15f2009-12-28 12:27:56 +000028#include "llvm/Type.h"
Dan Gohmancf20ac42009-08-13 01:36:44 +000029#include "llvm/Assembly/Writer.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000030#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000031#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Chenga8e29892007-01-19 07:51:42 +000032#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000033#include "llvm/MC/MCAsmInfo.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000034#include "llvm/MC/MCAssembler.h"
Chris Lattnerb0f294c2009-10-19 18:38:33 +000035#include "llvm/MC/MCContext.h"
Bill Wendlingbecd83e2010-03-09 00:40:17 +000036#include "llvm/MC/MCExpr.h"
Chris Lattner97f06932009-10-19 20:20:46 +000037#include "llvm/MC/MCInst.h"
Chris Lattnerf9bdedd2009-08-10 18:15:01 +000038#include "llvm/MC/MCSectionMachO.h"
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000039#include "llvm/MC/MCObjectStreamer.h"
Chris Lattner6c2f9e12009-08-19 05:49:37 +000040#include "llvm/MC/MCStreamer.h"
Chris Lattner325d3dc2009-09-13 17:14:04 +000041#include "llvm/MC/MCSymbol.h"
Chris Lattnerd62f1b42010-03-12 21:19:23 +000042#include "llvm/Target/Mangler.h"
Rafael Espindolab01c4bb2006-07-27 11:38:51 +000043#include "llvm/Target/TargetData.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000044#include "llvm/Target/TargetMachine.h"
Evan Cheng5be54b02007-01-19 19:25:36 +000045#include "llvm/Target/TargetOptions.h"
Daniel Dunbar51b198a2009-07-15 20:24:03 +000046#include "llvm/Target/TargetRegistry.h"
Evan Chengc324ecb2009-07-24 18:19:46 +000047#include "llvm/ADT/SmallPtrSet.h"
Jim Grosbachc40d9f92009-09-01 18:49:12 +000048#include "llvm/ADT/SmallString.h"
Bob Wilson54c78ef2009-11-06 23:33:28 +000049#include "llvm/ADT/StringExtras.h"
Chris Lattner97f06932009-10-19 20:20:46 +000050#include "llvm/Support/CommandLine.h"
Devang Patel59135f42010-08-04 22:39:39 +000051#include "llvm/Support/Debug.h"
Torok Edwin30464702009-07-08 20:55:50 +000052#include "llvm/Support/ErrorHandling.h"
Chris Lattnerb23569a2010-04-04 08:18:47 +000053#include "llvm/Support/raw_ostream.h"
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000054#include <cctype>
Rafael Espindola7bc59bc2006-05-14 22:18:28 +000055using namespace llvm;
56
Chris Lattner95b2c7d2006-12-19 22:59:26 +000057namespace {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000058
59 // Per section and per symbol attributes are not supported.
60 // To implement them we would need the ability to delay this emission
61 // until the assembly file is fully parsed/generated as only then do we
62 // know the symbol and section numbers.
63 class AttributeEmitter {
64 public:
65 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
66 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
67 virtual void Finish() = 0;
Rafael Espindola4921e232010-10-25 18:38:32 +000068 virtual ~AttributeEmitter() {}
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000069 };
70
71 class AsmAttributeEmitter : public AttributeEmitter {
72 MCStreamer &Streamer;
73
74 public:
75 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
76 void MaybeSwitchVendor(StringRef Vendor) { }
77
78 void EmitAttribute(unsigned Attribute, unsigned Value) {
79 Streamer.EmitRawText("\t.eabi_attribute " +
80 Twine(Attribute) + ", " + Twine(Value));
81 }
82
83 void Finish() { }
84 };
85
86 class ObjectAttributeEmitter : public AttributeEmitter {
87 MCObjectStreamer &Streamer;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +000088 StringRef CurrentVendor;
89 SmallString<64> Contents;
90
91 public:
92 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
93 Streamer(Streamer_), CurrentVendor("") { }
94
95 void MaybeSwitchVendor(StringRef Vendor) {
96 assert(!Vendor.empty() && "Vendor cannot be empty.");
97
98 if (CurrentVendor.empty())
99 CurrentVendor = Vendor;
100 else if (CurrentVendor == Vendor)
101 return;
102 else
103 Finish();
104
105 CurrentVendor = Vendor;
106
Rafael Espindola33363842010-10-25 22:26:55 +0000107 assert(Contents.size() == 0);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000108 }
109
110 void EmitAttribute(unsigned Attribute, unsigned Value) {
111 // FIXME: should be ULEB
112 Contents += Attribute;
113 Contents += Value;
114 }
115
116 void Finish() {
Rafael Espindola33363842010-10-25 22:26:55 +0000117 const size_t ContentsSize = Contents.size();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000118
Rafael Espindola33363842010-10-25 22:26:55 +0000119 // Vendor size + Vendor name + '\0'
120 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000121
Rafael Espindola33363842010-10-25 22:26:55 +0000122 // Tag + Tag Size
123 const size_t TagHeaderSize = 1 + 4;
124
125 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
126 Streamer.EmitBytes(CurrentVendor, 0);
127 Streamer.EmitIntValue(0, 1); // '\0'
128
129 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
130 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000131
132 Streamer.EmitBytes(Contents, 0);
Rafael Espindola33363842010-10-25 22:26:55 +0000133
134 Contents.clear();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000135 }
136 };
137
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000138} // end of anonymous namespace
139
Jim Grosbachbaf120f2010-12-01 03:45:07 +0000140MachineLocation ARMAsmPrinter::
141getDebugValueLocation(const MachineInstr *MI) const {
142 MachineLocation Location;
143 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
144 // Frame address. Currently handles register +- offset only.
145 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
146 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
147 else {
148 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
149 }
150 return Location;
151}
152
Chris Lattner953ebb72010-01-27 23:58:11 +0000153void ARMAsmPrinter::EmitFunctionEntryLabel() {
154 if (AFI->isThumbFunction()) {
Jim Grosbachce792992010-11-05 22:08:08 +0000155 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
156 OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0);
Chris Lattner953ebb72010-01-27 23:58:11 +0000157 }
Jim Grosbachb0739b72010-09-02 01:02:06 +0000158
Chris Lattner953ebb72010-01-27 23:58:11 +0000159 OutStreamer.EmitLabel(CurrentFnSym);
160}
161
Jim Grosbach2317e402010-09-30 01:57:53 +0000162/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000163/// method to print assembly for each instruction.
164///
165bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Chenga8e29892007-01-19 07:51:42 +0000166 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng6d63a722008-09-18 07:27:23 +0000167 MCP = MF.getConstantPool();
Rafael Espindola4b442b52006-05-23 02:48:20 +0000168
Chris Lattnerd49fe1b2010-01-28 01:28:58 +0000169 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000170}
171
Evan Cheng055b0312009-06-29 07:51:04 +0000172void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner35c33bd2010-04-04 04:47:45 +0000173 raw_ostream &O, const char *Modifier) {
Evan Cheng055b0312009-06-29 07:51:04 +0000174 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000175 unsigned TF = MO.getTargetFlags();
176
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000177 switch (MO.getType()) {
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000178 default:
179 assert(0 && "<unknown operand type>");
Bob Wilson5bafff32009-06-22 23:27:02 +0000180 case MachineOperand::MO_Register: {
181 unsigned Reg = MO.getReg();
Chris Lattner8bc86cb2009-10-19 20:59:55 +0000182 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach35636282010-10-06 21:22:32 +0000183 assert(!MO.getSubReg() && "Subregs should be eliminated!");
184 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000185 break;
Bob Wilson5bafff32009-06-22 23:27:02 +0000186 }
Evan Chenga8e29892007-01-19 07:51:42 +0000187 case MachineOperand::MO_Immediate: {
Evan Cheng5adb66a2009-09-28 09:14:39 +0000188 int64_t Imm = MO.getImm();
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000189 O << '#';
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000190 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jim Grosbach4dea9412010-10-06 16:51:55 +0000191 (TF == ARMII::MO_LO16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000192 O << ":lower16:";
193 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jim Grosbach4dea9412010-10-06 16:51:55 +0000194 (TF == ARMII::MO_HI16))
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000195 O << ":upper16:";
Anton Korobeynikov632606c2009-10-08 20:43:22 +0000196 O << Imm;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000197 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000198 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000199 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner1b2eb0e2010-03-13 21:04:28 +0000200 O << *MO.getMBB()->getSymbol();
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000201 return;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000202 case MachineOperand::MO_GlobalAddress: {
Dan Gohman46510a72010-04-15 01:51:59 +0000203 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov5cdc3a92009-11-24 00:44:37 +0000204 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
205 (TF & ARMII::MO_LO16))
206 O << ":lower16:";
207 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
208 (TF & ARMII::MO_HI16))
209 O << ":upper16:";
Chris Lattnerd62f1b42010-03-12 21:19:23 +0000210 O << *Mang->getSymbol(GV);
Anton Korobeynikov7751ad92008-11-22 16:15:34 +0000211
Chris Lattner0c08d092010-04-03 22:28:33 +0000212 printOffset(MO.getOffset(), O);
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000213 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000214 O << "(PLT)";
Evan Chenga8e29892007-01-19 07:51:42 +0000215 break;
Rafael Espindola84b19be2006-07-16 01:02:57 +0000216 }
Evan Chenga8e29892007-01-19 07:51:42 +0000217 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner10b318b2010-01-17 21:43:43 +0000218 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbach1d6111c2010-10-06 21:36:43 +0000219 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancio0ae4a332007-04-22 00:04:12 +0000220 O << "(PLT)";
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000221 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000222 }
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000223 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000224 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000225 break;
Evan Chenga8e29892007-01-19 07:51:42 +0000226 case MachineOperand::MO_JumpTableIndex:
Chris Lattner1b46f432010-01-23 07:00:21 +0000227 O << *GetJTISymbol(MO.getIndex());
Evan Chenga8e29892007-01-19 07:51:42 +0000228 break;
Rafael Espindola2f99b6b2006-05-25 12:57:06 +0000229 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000230}
231
Evan Cheng055b0312009-06-29 07:51:04 +0000232//===--------------------------------------------------------------------===//
233
Chris Lattner0890cf12010-01-25 19:51:38 +0000234MCSymbol *ARMAsmPrinter::
235GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
236 const MachineBasicBlock *MBB) const {
237 SmallString<60> Name;
238 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000239 << getFunctionNumber() << '_' << uid << '_' << uid2
Chris Lattner0890cf12010-01-25 19:51:38 +0000240 << "_set_" << MBB->getNumber();
Chris Lattner9b97a732010-03-30 18:10:53 +0000241 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner0890cf12010-01-25 19:51:38 +0000242}
243
244MCSymbol *ARMAsmPrinter::
245GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
246 SmallString<60> Name;
247 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner281e7762010-01-25 23:28:03 +0000248 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner9b97a732010-03-30 18:10:53 +0000249 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattnerbfcb0962010-01-25 19:39:52 +0000250}
251
Jim Grosbach433a5782010-09-24 20:47:58 +0000252
253MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel(void) const {
254 SmallString<60> Name;
255 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
256 << getFunctionNumber();
257 return OutContext.GetOrCreateSymbol(Name.str());
258}
259
Evan Cheng055b0312009-06-29 07:51:04 +0000260bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000261 unsigned AsmVariant, const char *ExtraCode,
262 raw_ostream &O) {
Evan Chenga8e29892007-01-19 07:51:42 +0000263 // Does this asm operand have a single letter operand modifier?
264 if (ExtraCode && ExtraCode[0]) {
265 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikov8e9ece72009-08-08 23:10:41 +0000266
Evan Chenga8e29892007-01-19 07:51:42 +0000267 switch (ExtraCode[0]) {
268 default: return true; // Unknown modifier.
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000269 case 'a': // Print as a memory address.
270 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach2f24c4e2010-09-30 15:25:22 +0000271 O << "["
272 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
273 << "]";
Bob Wilson9b4b00a2009-07-09 23:54:51 +0000274 return false;
275 }
276 // Fallthrough
277 case 'c': // Don't print "#" before an immediate operand.
Bob Wilson4f38b382009-08-21 21:58:55 +0000278 if (!MI->getOperand(OpNum).isImm())
279 return true;
Jim Grosbach2317e402010-09-30 01:57:53 +0000280 O << MI->getOperand(OpNum).getImm();
Bob Wilson8f343462009-04-06 21:46:51 +0000281 return false;
Evan Chenge21e3962007-04-04 00:13:29 +0000282 case 'P': // Print a VFP double precision register.
Evan Chengd831cda2009-12-08 23:06:22 +0000283 case 'q': // Print a NEON quad precision register.
Chris Lattner35c33bd2010-04-04 04:47:45 +0000284 printOperand(MI, OpNum, O);
Evan Cheng23a95702007-03-08 22:42:46 +0000285 return false;
Evan Chenga8e29892007-01-19 07:51:42 +0000286 case 'Q':
Bob Wilsond984eb62010-05-27 20:23:42 +0000287 case 'R':
Bob Wilsond984eb62010-05-27 20:23:42 +0000288 case 'H':
Bob Wilson9bb43e12010-12-17 23:06:42 +0000289 // These modifiers are not yet supported.
Bob Wilsond984eb62010-05-27 20:23:42 +0000290 return true;
Evan Cheng84f60b72010-05-27 22:08:38 +0000291 }
Evan Chenga8e29892007-01-19 07:51:42 +0000292 }
Jim Grosbache9952212009-09-04 01:38:51 +0000293
Chris Lattner35c33bd2010-04-04 04:47:45 +0000294 printOperand(MI, OpNum, O);
Evan Chenga8e29892007-01-19 07:51:42 +0000295 return false;
296}
297
Bob Wilson224c2442009-05-19 05:53:42 +0000298bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Cheng055b0312009-06-29 07:51:04 +0000299 unsigned OpNum, unsigned AsmVariant,
Chris Lattnerc75c0282010-04-04 05:29:35 +0000300 const char *ExtraCode,
301 raw_ostream &O) {
Bob Wilson224c2442009-05-19 05:53:42 +0000302 if (ExtraCode && ExtraCode[0])
303 return true; // Unknown modifier.
Bob Wilson765cc0b2009-10-13 20:50:28 +0000304
305 const MachineOperand &MO = MI->getOperand(OpNum);
306 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach2317e402010-09-30 01:57:53 +0000307 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilson224c2442009-05-19 05:53:42 +0000308 return false;
309}
310
Bob Wilson812209a2009-09-30 22:06:26 +0000311void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson0fb34682009-09-30 00:23:42 +0000312 if (Subtarget->isTargetDarwin()) {
313 Reloc::Model RelocM = TM.getRelocationModel();
314 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
315 // Declare all the text sections up front (before the DWARF sections
316 // emitted by AsmPrinter::doInitialization) so the assembler will keep
317 // them together at the beginning of the object file. This helps
318 // avoid out-of-range branches that are due a fundamental limitation of
319 // the way symbol offsets are encoded with the current Darwin ARM
320 // relocations.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000321 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman0d805c32010-04-17 16:44:48 +0000322 static_cast<const TargetLoweringObjectFileMachO &>(
323 getObjFileLowering());
Bob Wilson29e06692009-09-30 22:25:37 +0000324 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
325 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
326 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
327 if (RelocM == Reloc::DynamicNoPIC) {
328 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000329 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
330 MCSectionMachO::S_SYMBOL_STUBS,
331 12, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000332 OutStreamer.SwitchSection(sect);
333 } else {
334 const MCSection *sect =
Chris Lattner22772212010-04-08 20:40:11 +0000335 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
336 MCSectionMachO::S_SYMBOL_STUBS,
337 16, SectionKind::getText());
Bob Wilson29e06692009-09-30 22:25:37 +0000338 OutStreamer.SwitchSection(sect);
339 }
Bob Wilson63db5942010-07-30 19:55:47 +0000340 const MCSection *StaticInitSect =
341 OutContext.getMachOSection("__TEXT", "__StaticInit",
342 MCSectionMachO::S_REGULAR |
343 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
344 SectionKind::getText());
345 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson0fb34682009-09-30 00:23:42 +0000346 }
347 }
348
Jim Grosbache5165492009-11-09 00:11:35 +0000349 // Use unified assembler syntax.
Jason W Kimafd1cc22010-09-30 02:45:56 +0000350 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovd61eca52009-06-17 23:43:18 +0000351
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000352 // Emit ARM Build Attributes
353 if (Subtarget->isTargetELF()) {
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000354
Jason W Kimdef9ac42010-10-06 22:36:46 +0000355 emitAttributes();
Anton Korobeynikov88ce6672009-05-23 19:51:20 +0000356 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000357}
358
Anton Korobeynikov0f3cc652008-08-07 09:54:23 +0000359
Chris Lattner4a071d62009-10-19 17:59:19 +0000360void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng5be54b02007-01-19 19:25:36 +0000361 if (Subtarget->isTargetDarwin()) {
Chris Lattnerf61159b2009-08-03 22:18:15 +0000362 // All darwin targets use mach-o.
Dan Gohman0d805c32010-04-17 16:44:48 +0000363 const TargetLoweringObjectFileMachO &TLOFMacho =
364 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000365 MachineModuleInfoMachO &MMIMacho =
366 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbache9952212009-09-04 01:38:51 +0000367
Evan Chenga8e29892007-01-19 07:51:42 +0000368 // Output non-lazy-pointers for external and common global variables.
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000369 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlingcebae362010-03-10 22:34:10 +0000370
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000371 if (!Stubs.empty()) {
Chris Lattnerff4bc462009-08-10 01:39:42 +0000372 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000373 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattnerc076a972009-08-10 18:01:34 +0000374 EmitAlignment(2);
Chris Lattnerb0f294c2009-10-19 18:38:33 +0000375 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000376 // L_foo$stub:
377 OutStreamer.EmitLabel(Stubs[i].first);
378 // .indirect_symbol _foo
Bill Wendling52a50e52010-03-11 01:18:13 +0000379 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
380 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000381
Bill Wendling52a50e52010-03-11 01:18:13 +0000382 if (MCSym.getInt())
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000383 // External to current translation unit.
384 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
385 else
386 // Internal to current translation unit.
Bill Wendling5e1b55d2010-03-31 18:47:10 +0000387 //
Jim Grosbach1b935a32010-09-22 16:45:13 +0000388 // When we place the LSDA into the TEXT section, the type info
389 // pointers need to be indirect and pc-rel. We accomplish this by
390 // using NLPs; however, sometimes the types are local to the file.
391 // We need to fill in the value for the NLP in those cases.
Bill Wendling52a50e52010-03-11 01:18:13 +0000392 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
393 OutContext),
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000394 4/*size*/, 0/*addrspace*/);
Evan Chengae94e592008-12-05 01:06:39 +0000395 }
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000396
397 Stubs.clear();
398 OutStreamer.AddBlankLine();
Evan Chenga8e29892007-01-19 07:51:42 +0000399 }
400
Chris Lattnere4d9ea82009-10-19 18:44:38 +0000401 Stubs = MMIMacho.GetHiddenGVStubList();
402 if (!Stubs.empty()) {
Chris Lattner6c2f9e12009-08-19 05:49:37 +0000403 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerf3231de2009-08-10 18:02:16 +0000404 EmitAlignment(2);
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000405 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
406 // L_foo$stub:
407 OutStreamer.EmitLabel(Stubs[i].first);
408 // .long _foo
Bill Wendlingcebae362010-03-10 22:34:10 +0000409 OutStreamer.EmitValue(MCSymbolRefExpr::
410 Create(Stubs[i].second.getPointer(),
411 OutContext),
Bill Wendlingbecd83e2010-03-09 00:40:17 +0000412 4/*size*/, 0/*addrspace*/);
413 }
Bill Wendlingcf6f28d2010-03-09 00:43:34 +0000414
415 Stubs.clear();
416 OutStreamer.AddBlankLine();
Evan Chengae94e592008-12-05 01:06:39 +0000417 }
418
Evan Chenga8e29892007-01-19 07:51:42 +0000419 // Funny Darwin hack: This flag tells the linker that no global symbols
420 // contain code that falls through to other global symbols (e.g. the obvious
421 // implementation of multiple entry points). If this doesn't occur, the
422 // linker can safely perform dead code stripping. Since LLVM never
423 // generates code that does this, it is always safe to set.
Chris Lattnera5ad93a2010-01-23 06:39:22 +0000424 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindolab01c4bb2006-07-27 11:38:51 +0000425 }
Rafael Espindola7bc59bc2006-05-14 22:18:28 +0000426}
Anton Korobeynikov0bd89712008-08-17 13:55:10 +0000427
Chris Lattner97f06932009-10-19 20:20:46 +0000428//===----------------------------------------------------------------------===//
Jason W Kimdef9ac42010-10-06 22:36:46 +0000429// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
430// FIXME:
431// The following seem like one-off assembler flags, but they actually need
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000432// to appear in the .ARM.attributes section in ELF.
Jason W Kimdef9ac42010-10-06 22:36:46 +0000433// Instead of subclassing the MCELFStreamer, we do the work here.
434
435void ARMAsmPrinter::emitAttributes() {
Jim Grosbachfa7fb642010-10-06 22:46:47 +0000436
Jason W Kim17b443d2010-10-11 23:01:44 +0000437 emitARMAttributeSection();
438
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000439 AttributeEmitter *AttrEmitter;
440 if (OutStreamer.hasRawTextSupport())
441 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
442 else {
443 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
444 AttrEmitter = new ObjectAttributeEmitter(O);
445 }
446
447 AttrEmitter->MaybeSwitchVendor("aeabi");
448
Jason W Kimdef9ac42010-10-06 22:36:46 +0000449 std::string CPUString = Subtarget->getCPUString();
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000450 if (OutStreamer.hasRawTextSupport()) {
451 if (CPUString != "generic")
452 OutStreamer.EmitRawText(StringRef("\t.cpu ") + CPUString);
453 } else {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000454 assert(CPUString == "generic" && "Unsupported .cpu attribute for ELF/.o");
455 // FIXME: Why these defaults?
456 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
457 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use, 1);
458 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use, 1);
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000459 }
Jason W Kimdef9ac42010-10-06 22:36:46 +0000460
461 // FIXME: Emit FPU type
462 if (Subtarget->hasVFP2())
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000463 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch, 2);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000464
465 // Signal various FP modes.
466 if (!UnsafeFPMath) {
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000467 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal, 1);
468 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000469 }
470
471 if (NoInfsFPMath && NoNaNsFPMath)
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000472 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000473 else
Dale Johannesen7179d1e2010-11-08 19:17:22 +0000474 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model, 3);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000475
476 // 8-bytes alignment stuff.
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000477 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
478 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000479
480 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
481 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) {
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000482 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
483 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimdef9ac42010-10-06 22:36:46 +0000484 }
485 // FIXME: Should we signal R9 usage?
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000486
487 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
488
489 AttrEmitter->Finish();
490 delete AttrEmitter;
Jason W Kimdef9ac42010-10-06 22:36:46 +0000491}
492
Jason W Kim17b443d2010-10-11 23:01:44 +0000493void ARMAsmPrinter::emitARMAttributeSection() {
494 // <format-version>
495 // [ <section-length> "vendor-name"
496 // [ <file-tag> <size> <attribute>*
497 // | <section-tag> <size> <section-number>* 0 <attribute>*
498 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
499 // ]+
500 // ]*
501
502 if (OutStreamer.hasRawTextSupport())
503 return;
504
505 const ARMElfTargetObjectFile &TLOFELF =
506 static_cast<const ARMElfTargetObjectFile &>
507 (getObjFileLowering());
508
509 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim17b443d2010-10-11 23:01:44 +0000510
Rafael Espindolacecbc3d2010-10-25 17:50:35 +0000511 // Format version
512 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim17b443d2010-10-11 23:01:44 +0000513}
514
Jason W Kimdef9ac42010-10-06 22:36:46 +0000515//===----------------------------------------------------------------------===//
Chris Lattner97f06932009-10-19 20:20:46 +0000516
Jim Grosbach988ce092010-09-18 00:05:05 +0000517static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
518 unsigned LabelId, MCContext &Ctx) {
519
520 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
521 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
522 return Label;
523}
524
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000525static MCSymbolRefExpr::VariantKind
526getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
527 switch (Modifier) {
528 default: llvm_unreachable("Unknown modifier!");
529 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
530 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
531 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
532 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
533 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
534 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
535 }
536 return MCSymbolRefExpr::VK_None;
537}
538
Jim Grosbach5df08d82010-11-09 18:45:04 +0000539void ARMAsmPrinter::
540EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
541 int Size = TM.getTargetData()->getTypeAllocSize(MCPV->getType());
542
543 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000544
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000545 MCSymbol *MCSym;
Jim Grosbach5df08d82010-11-09 18:45:04 +0000546 if (ACPV->isLSDA()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000547 SmallString<128> Str;
548 raw_svector_ostream OS(Str);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000549 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000550 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000551 } else if (ACPV->isBlockAddress()) {
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000552 MCSym = GetBlockAddressSymbol(ACPV->getBlockAddress());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000553 } else if (ACPV->isGlobalValue()) {
554 const GlobalValue *GV = ACPV->getGV();
555 bool isIndirect = Subtarget->isTargetDarwin() &&
556 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
557 if (!isIndirect)
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000558 MCSym = Mang->getSymbol(GV);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000559 else {
560 // FIXME: Remove this when Darwin transition to @GOT like syntax.
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000561 MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
Jim Grosbach5df08d82010-11-09 18:45:04 +0000562
563 MachineModuleInfoMachO &MMIMachO =
564 MMI->getObjFileInfo<MachineModuleInfoMachO>();
565 MachineModuleInfoImpl::StubValueTy &StubSym =
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000566 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
567 MMIMachO.getGVStubEntry(MCSym);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000568 if (StubSym.getPointer() == 0)
569 StubSym = MachineModuleInfoImpl::
570 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
571 }
572 } else {
573 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Jim Grosbach7c7ddb22010-11-10 17:59:10 +0000574 MCSym = GetExternalSymbolSymbol(ACPV->getSymbol());
Jim Grosbach5df08d82010-11-09 18:45:04 +0000575 }
576
577 // Create an MCSymbol for the reference.
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000578 const MCExpr *Expr =
579 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
580 OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000581
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000582 if (ACPV->getPCAdjustment()) {
583 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
584 getFunctionNumber(),
585 ACPV->getLabelId(),
586 OutContext);
587 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
588 PCRelExpr =
589 MCBinaryExpr::CreateAdd(PCRelExpr,
590 MCConstantExpr::Create(ACPV->getPCAdjustment(),
591 OutContext),
592 OutContext);
593 if (ACPV->mustAddCurrentAddress()) {
594 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
595 // label, so just emit a local label end reference that instead.
596 MCSymbol *DotSym = OutContext.CreateTempSymbol();
597 OutStreamer.EmitLabel(DotSym);
598 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
599 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000600 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000601 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000602 }
Jim Grosbach2c4d5122010-11-10 03:26:07 +0000603 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach5df08d82010-11-09 18:45:04 +0000604}
605
Jim Grosbacha2244cb2010-09-22 17:39:48 +0000606void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
607 unsigned Opcode = MI->getOpcode();
608 int OpNum = 1;
609 if (Opcode == ARM::BR_JTadd)
610 OpNum = 2;
611 else if (Opcode == ARM::BR_JTm)
612 OpNum = 3;
613
614 const MachineOperand &MO1 = MI->getOperand(OpNum);
615 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
616 unsigned JTI = MO1.getIndex();
617
618 // Emit a label for the jump table.
619 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
620 OutStreamer.EmitLabel(JTISymbol);
621
622 // Emit each entry of the table.
623 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
624 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
625 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
626
627 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
628 MachineBasicBlock *MBB = JTBBs[i];
629 // Construct an MCExpr for the entry. We want a value of the form:
630 // (BasicBlockAddr - TableBeginAddr)
631 //
632 // For example, a table with entries jumping to basic blocks BB0 and BB1
633 // would look like:
634 // LJTI_0_0:
635 // .word (LBB0 - LJTI_0_0)
636 // .word (LBB1 - LJTI_0_0)
637 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
638
639 if (TM.getRelocationModel() == Reloc::PIC_)
640 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
641 OutContext),
642 OutContext);
643 OutStreamer.EmitValue(Expr, 4);
644 }
645}
646
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000647void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
648 unsigned Opcode = MI->getOpcode();
649 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
650 const MachineOperand &MO1 = MI->getOperand(OpNum);
651 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
652 unsigned JTI = MO1.getIndex();
653
654 // Emit a label for the jump table.
655 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
656 OutStreamer.EmitLabel(JTISymbol);
657
658 // Emit each entry of the table.
659 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
660 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
661 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000662 unsigned OffsetWidth = 4;
Jim Grosbachd092a872010-11-29 21:28:32 +0000663 if (MI->getOpcode() == ARM::t2TBB_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000664 OffsetWidth = 1;
Jim Grosbachd092a872010-11-29 21:28:32 +0000665 else if (MI->getOpcode() == ARM::t2TBH_JT)
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000666 OffsetWidth = 2;
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000667
668 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
669 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000670 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
671 OutContext);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000672 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000673 if (OffsetWidth == 4) {
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000674 MCInst BrInst;
675 BrInst.setOpcode(ARM::t2B);
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000676 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000677 OutStreamer.EmitInstruction(BrInst);
678 continue;
679 }
680 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach205a5fa2010-09-22 17:15:35 +0000681 // MCExpr for the entry. We want a value of the form:
682 // (BasicBlockAddr - TableBeginAddr) / 2
683 //
684 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
685 // would look like:
686 // LJTI_0_0:
687 // .byte (LBB0 - LJTI_0_0) / 2
688 // .byte (LBB1 - LJTI_0_0) / 2
689 const MCExpr *Expr =
690 MCBinaryExpr::CreateSub(MBBSymbolExpr,
691 MCSymbolRefExpr::Create(JTISymbol, OutContext),
692 OutContext);
693 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
694 OutContext);
695 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000696 }
697}
698
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000699void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
700 raw_ostream &OS) {
701 unsigned NOps = MI->getNumOperands();
702 assert(NOps==4);
703 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
704 // cast away const; DIetc do not take const operands for some reason.
705 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
706 OS << V.getName();
707 OS << " <- ";
708 // Frame address. Currently handles register +- offset only.
709 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
710 OS << '['; printOperand(MI, 0, OS); OS << '+'; printOperand(MI, 1, OS);
711 OS << ']';
712 OS << "+";
713 printOperand(MI, NOps-2, OS);
714}
715
Jim Grosbach40edf732010-12-14 21:10:47 +0000716static void populateADROperands(MCInst &Inst, unsigned Dest,
717 const MCSymbol *Label,
718 unsigned pred, unsigned ccreg,
719 MCContext &Ctx) {
720 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
721 Inst.addOperand(MCOperand::CreateReg(Dest));
722 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
723 // Add predicate operands.
724 Inst.addOperand(MCOperand::CreateImm(pred));
725 Inst.addOperand(MCOperand::CreateReg(ccreg));
726}
727
Jim Grosbachb454cda2010-09-29 15:23:40 +0000728void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Chris Lattner97f06932009-10-19 20:20:46 +0000729 switch (MI->getOpcode()) {
Chris Lattner4d152222009-10-19 22:23:04 +0000730 default: break;
Jim Grosbach9702e602010-12-09 01:22:19 +0000731 case ARM::t2ADDrSPi:
732 case ARM::t2ADDrSPi12:
733 case ARM::t2SUBrSPi:
734 case ARM::t2SUBrSPi12:
Jim Grosbach766a63d2010-12-09 01:23:51 +0000735 assert ((MI->getOperand(1).getReg() == ARM::SP) &&
736 "Unexpected source register!");
Jim Grosbach9702e602010-12-09 01:22:19 +0000737 break;
738
Chris Lattner112f2392010-11-14 20:31:06 +0000739 case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
Jim Grosbach2d0f53b2010-09-28 17:05:56 +0000740 case ARM::DBG_VALUE: {
741 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
742 SmallString<128> TmpStr;
743 raw_svector_ostream OS(TmpStr);
744 PrintDebugValueComment(MI, OS);
745 OutStreamer.EmitRawText(StringRef(OS.str()));
746 }
747 return;
748 }
Jim Grosbach3efad8f2010-12-16 19:11:16 +0000749 case ARM::tBfar: {
750 MCInst TmpInst;
751 TmpInst.setOpcode(ARM::tBL);
752 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(
753 MI->getOperand(0).getMBB()->getSymbol(), OutContext)));
754 OutStreamer.EmitInstruction(TmpInst);
755 return;
756 }
Jim Grosbach40edf732010-12-14 21:10:47 +0000757 case ARM::LEApcrel:
Jim Grosbachd40963c2010-12-14 22:28:03 +0000758 case ARM::tLEApcrel:
Jim Grosbach40edf732010-12-14 21:10:47 +0000759 case ARM::t2LEApcrel: {
Jim Grosbachdff84b02010-12-02 00:28:45 +0000760 // FIXME: Need to also handle globals and externals
Jim Grosbachdff84b02010-12-02 00:28:45 +0000761 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000762 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
763 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
764 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000765 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
766 GetCPISymbol(MI->getOperand(1).getIndex()),
767 MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
768 OutContext);
Jim Grosbachdff84b02010-12-02 00:28:45 +0000769 OutStreamer.EmitInstruction(TmpInst);
770 return;
771 }
Jim Grosbachd40963c2010-12-14 22:28:03 +0000772 case ARM::LEApcrelJT:
773 case ARM::tLEApcrelJT:
774 case ARM::t2LEApcrelJT: {
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000775 MCInst TmpInst;
Jim Grosbachd40963c2010-12-14 22:28:03 +0000776 TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
777 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
778 : ARM::ADR));
Jim Grosbach40edf732010-12-14 21:10:47 +0000779 populateADROperands(TmpInst, MI->getOperand(0).getReg(),
780 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
781 MI->getOperand(2).getImm()),
782 MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
783 OutContext);
Jim Grosbach5d14f9b2010-12-01 19:47:31 +0000784 OutStreamer.EmitInstruction(TmpInst);
785 return;
786 }
Jim Grosbach2e812e12010-11-30 18:56:36 +0000787 case ARM::MOVPCRX: {
788 MCInst TmpInst;
789 TmpInst.setOpcode(ARM::MOVr);
790 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
791 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
792 // Add predicate operands.
793 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
794 TmpInst.addOperand(MCOperand::CreateReg(0));
795 // Add 's' bit operand (always reg0 for this)
796 TmpInst.addOperand(MCOperand::CreateReg(0));
797 OutStreamer.EmitInstruction(TmpInst);
798 return;
799 }
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +0000800 case ARM::BXr9_CALL:
801 case ARM::BX_CALL: {
802 {
803 MCInst TmpInst;
804 TmpInst.setOpcode(ARM::MOVr);
805 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
806 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
807 // Add predicate operands.
808 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
809 TmpInst.addOperand(MCOperand::CreateReg(0));
810 // Add 's' bit operand (always reg0 for this)
811 TmpInst.addOperand(MCOperand::CreateReg(0));
812 OutStreamer.EmitInstruction(TmpInst);
813 }
814 {
815 MCInst TmpInst;
816 TmpInst.setOpcode(ARM::BX);
817 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
818 OutStreamer.EmitInstruction(TmpInst);
819 }
820 return;
821 }
822 case ARM::BMOVPCRXr9_CALL:
823 case ARM::BMOVPCRX_CALL: {
824 {
825 MCInst TmpInst;
826 TmpInst.setOpcode(ARM::MOVr);
827 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
828 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
829 // Add predicate operands.
830 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
831 TmpInst.addOperand(MCOperand::CreateReg(0));
832 // Add 's' bit operand (always reg0 for this)
833 TmpInst.addOperand(MCOperand::CreateReg(0));
834 OutStreamer.EmitInstruction(TmpInst);
835 }
836 {
837 MCInst TmpInst;
838 TmpInst.setOpcode(ARM::MOVr);
839 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
840 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
841 // Add predicate operands.
842 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
843 TmpInst.addOperand(MCOperand::CreateReg(0));
844 // Add 's' bit operand (always reg0 for this)
845 TmpInst.addOperand(MCOperand::CreateReg(0));
846 OutStreamer.EmitInstruction(TmpInst);
847 }
848 return;
849 }
Jim Grosbachfbd18732010-09-17 23:41:53 +0000850 case ARM::tPICADD: {
851 // This is a pseudo op for a label + instruction sequence, which looks like:
852 // LPC0:
853 // add r0, pc
854 // This adds the address of LPC0 to r0.
855
856 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +0000857 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
858 getFunctionNumber(), MI->getOperand(2).getImm(),
859 OutContext));
Jim Grosbachfbd18732010-09-17 23:41:53 +0000860
861 // Form and emit the add.
862 MCInst AddInst;
863 AddInst.setOpcode(ARM::tADDhirr);
864 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
865 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
866 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
867 // Add predicate operands.
868 AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
869 AddInst.addOperand(MCOperand::CreateReg(0));
870 OutStreamer.EmitInstruction(AddInst);
871 return;
872 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +0000873 case ARM::PICADD: {
Chris Lattner4d152222009-10-19 22:23:04 +0000874 // This is a pseudo op for a label + instruction sequence, which looks like:
875 // LPC0:
876 // add r0, pc, r0
877 // This adds the address of LPC0 to r0.
Jim Grosbachb0739b72010-09-02 01:02:06 +0000878
Chris Lattner4d152222009-10-19 22:23:04 +0000879 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +0000880 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
881 getFunctionNumber(), MI->getOperand(2).getImm(),
882 OutContext));
Jim Grosbachb0739b72010-09-02 01:02:06 +0000883
Jim Grosbachf3f09522010-09-14 21:05:34 +0000884 // Form and emit the add.
Chris Lattner4d152222009-10-19 22:23:04 +0000885 MCInst AddInst;
886 AddInst.setOpcode(ARM::ADDrr);
887 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
888 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
889 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbach5b46d622010-09-14 21:28:17 +0000890 // Add predicate operands.
891 AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
892 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
893 // Add 's' bit operand (always reg0 for this)
894 AddInst.addOperand(MCOperand::CreateReg(0));
Chris Lattner850d2e22010-02-03 01:16:28 +0000895 OutStreamer.EmitInstruction(AddInst);
Chris Lattner4d152222009-10-19 22:23:04 +0000896 return;
897 }
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000898 case ARM::PICSTR:
899 case ARM::PICSTRB:
900 case ARM::PICSTRH:
901 case ARM::PICLDR:
902 case ARM::PICLDRB:
903 case ARM::PICLDRH:
904 case ARM::PICLDRSB:
905 case ARM::PICLDRSH: {
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000906 // This is a pseudo op for a label + instruction sequence, which looks like:
907 // LPC0:
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000908 // OP r0, [pc, r0]
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000909 // The LCP0 label is referenced by a constant pool entry in order to get
910 // a PC-relative address at the ldr instruction.
911
912 // Emit the label.
Jim Grosbach988ce092010-09-18 00:05:05 +0000913 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
914 getFunctionNumber(), MI->getOperand(2).getImm(),
915 OutContext));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000916
917 // Form and emit the load
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000918 unsigned Opcode;
919 switch (MI->getOpcode()) {
920 default:
921 llvm_unreachable("Unexpected opcode!");
Jim Grosbach7e3383c2010-10-27 23:12:14 +0000922 case ARM::PICSTR: Opcode = ARM::STRrs; break;
923 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000924 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach3e556122010-10-26 22:37:02 +0000925 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbachc1d30212010-10-27 00:19:44 +0000926 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000927 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
928 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
929 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
930 }
931 MCInst LdStInst;
932 LdStInst.setOpcode(Opcode);
933 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
934 LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
935 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
936 LdStInst.addOperand(MCOperand::CreateImm(0));
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000937 // Add predicate operands.
Jim Grosbacha28abbe2010-09-17 16:25:52 +0000938 LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
939 LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
940 OutStreamer.EmitInstruction(LdStInst);
Jim Grosbachb74ca9d2010-09-16 17:43:25 +0000941
942 return;
943 }
Jim Grosbacha3fbadf2010-09-30 19:53:58 +0000944 case ARM::CONSTPOOL_ENTRY: {
Chris Lattnera70e6442009-10-19 22:33:05 +0000945 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
946 /// in the function. The first operand is the ID# for this instruction, the
947 /// second is the index into the MachineConstantPool that this is, the third
948 /// is the size in bytes of this constant pool entry.
949 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
950 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
951
952 EmitAlignment(2);
Chris Lattner1b46f432010-01-23 07:00:21 +0000953 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattnera70e6442009-10-19 22:33:05 +0000954
955 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
956 if (MCPE.isMachineConstantPoolEntry())
957 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
958 else
959 EmitGlobalConstant(MCPE.Val.ConstVal);
Jim Grosbachb0739b72010-09-02 01:02:06 +0000960
Chris Lattnera70e6442009-10-19 22:33:05 +0000961 return;
962 }
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000963 case ARM::t2BR_JT: {
964 // Lower and emit the instruction itself, then the jump table following it.
965 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +0000966 TmpInst.setOpcode(ARM::tMOVgpr2gpr);
967 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
968 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
969 // Add predicate operands.
970 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
971 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach882ef2b2010-09-21 23:28:16 +0000972 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbach5ca66692010-11-29 22:37:40 +0000973 // Output the data for the jump table itself
974 EmitJump2Table(MI);
975 return;
976 }
977 case ARM::t2TBB_JT: {
978 // Lower and emit the instruction itself, then the jump table following it.
979 MCInst TmpInst;
980
981 TmpInst.setOpcode(ARM::t2TBB);
982 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
983 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
984 // Add predicate operands.
985 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
986 TmpInst.addOperand(MCOperand::CreateReg(0));
987 OutStreamer.EmitInstruction(TmpInst);
988 // Output the data for the jump table itself
989 EmitJump2Table(MI);
990 // Make sure the next instruction is 2-byte aligned.
991 EmitAlignment(1);
992 return;
993 }
994 case ARM::t2TBH_JT: {
995 // Lower and emit the instruction itself, then the jump table following it.
996 MCInst TmpInst;
997
998 TmpInst.setOpcode(ARM::t2TBH);
999 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1000 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1001 // Add predicate operands.
1002 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1003 TmpInst.addOperand(MCOperand::CreateReg(0));
1004 OutStreamer.EmitInstruction(TmpInst);
1005 // Output the data for the jump table itself
Jim Grosbach882ef2b2010-09-21 23:28:16 +00001006 EmitJump2Table(MI);
1007 return;
1008 }
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001009 case ARM::tBR_JTr:
Jim Grosbach2dc77682010-11-29 18:37:44 +00001010 case ARM::BR_JTr: {
1011 // Lower and emit the instruction itself, then the jump table following it.
1012 // mov pc, target
1013 MCInst TmpInst;
Jim Grosbach5ca66692010-11-29 22:37:40 +00001014 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1015 ARM::MOVr : ARM::tMOVgpr2gpr;
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001016 TmpInst.setOpcode(Opc);
Jim Grosbach2dc77682010-11-29 18:37:44 +00001017 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1018 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1019 // Add predicate operands.
1020 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1021 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbacha0d2c8a2010-11-30 18:30:19 +00001022 // Add 's' bit operand (always reg0 for this)
1023 if (Opc == ARM::MOVr)
1024 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach2dc77682010-11-29 18:37:44 +00001025 OutStreamer.EmitInstruction(TmpInst);
1026
Jim Grosbachf1aa47d2010-11-29 19:32:47 +00001027 // Make sure the Thumb jump table is 4-byte aligned.
1028 if (Opc == ARM::tMOVr)
1029 EmitAlignment(2);
1030
Jim Grosbach2dc77682010-11-29 18:37:44 +00001031 // Output the data for the jump table itself
1032 EmitJumpTable(MI);
1033 return;
1034 }
1035 case ARM::BR_JTm: {
1036 // Lower and emit the instruction itself, then the jump table following it.
1037 // ldr pc, target
1038 MCInst TmpInst;
1039 if (MI->getOperand(1).getReg() == 0) {
1040 // literal offset
1041 TmpInst.setOpcode(ARM::LDRi12);
1042 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1043 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1044 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1045 } else {
1046 TmpInst.setOpcode(ARM::LDRrs);
1047 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1048 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1049 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1050 TmpInst.addOperand(MCOperand::CreateImm(0));
1051 }
1052 // Add predicate operands.
1053 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1054 TmpInst.addOperand(MCOperand::CreateReg(0));
1055 OutStreamer.EmitInstruction(TmpInst);
1056
1057 // Output the data for the jump table itself
Jim Grosbacha2244cb2010-09-22 17:39:48 +00001058 EmitJumpTable(MI);
1059 return;
1060 }
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001061 case ARM::BR_JTadd: {
1062 // Lower and emit the instruction itself, then the jump table following it.
1063 // add pc, target, idx
Jim Grosbach2dc77682010-11-29 18:37:44 +00001064 MCInst TmpInst;
1065 TmpInst.setOpcode(ARM::ADDrr);
1066 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1067 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1068 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001069 // Add predicate operands.
Jim Grosbach2dc77682010-11-29 18:37:44 +00001070 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1071 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001072 // Add 's' bit operand (always reg0 for this)
Jim Grosbach2dc77682010-11-29 18:37:44 +00001073 TmpInst.addOperand(MCOperand::CreateReg(0));
1074 OutStreamer.EmitInstruction(TmpInst);
Jim Grosbachf8dabac2010-11-17 21:05:55 +00001075
1076 // Output the data for the jump table itself
1077 EmitJumpTable(MI);
1078 return;
1079 }
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001080 case ARM::TRAP: {
1081 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1082 // FIXME: Remove this special case when they do.
1083 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001084 //.long 0xe7ffdefe @ trap
Jim Grosbachb2dda4b2010-09-23 19:42:17 +00001085 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001086 OutStreamer.AddComment("trap");
1087 OutStreamer.EmitIntValue(Val, 4);
1088 return;
1089 }
1090 break;
1091 }
1092 case ARM::tTRAP: {
1093 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1094 // FIXME: Remove this special case when they do.
1095 if (!Subtarget->isTargetDarwin()) {
Jim Grosbach78890f42010-10-01 23:21:38 +00001096 //.short 57086 @ trap
Benjamin Kramerc8ab9eb2010-09-23 18:57:26 +00001097 uint16_t Val = 0xdefe;
Jim Grosbach2e6ae132010-09-23 18:05:37 +00001098 OutStreamer.AddComment("trap");
1099 OutStreamer.EmitIntValue(Val, 2);
1100 return;
1101 }
1102 break;
1103 }
Jim Grosbach433a5782010-09-24 20:47:58 +00001104 case ARM::t2Int_eh_sjlj_setjmp:
1105 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001106 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach433a5782010-09-24 20:47:58 +00001107 // Two incoming args: GPR:$src, GPR:$val
1108 // mov $val, pc
1109 // adds $val, #7
1110 // str $val, [$src, #4]
1111 // movs r0, #0
1112 // b 1f
1113 // movs r0, #1
1114 // 1:
1115 unsigned SrcReg = MI->getOperand(0).getReg();
1116 unsigned ValReg = MI->getOperand(1).getReg();
1117 MCSymbol *Label = GetARMSJLJEHLabel();
1118 {
1119 MCInst TmpInst;
1120 TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
1121 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1122 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1123 // 's' bit operand
1124 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1125 OutStreamer.AddComment("eh_setjmp begin");
1126 OutStreamer.EmitInstruction(TmpInst);
1127 }
1128 {
1129 MCInst TmpInst;
1130 TmpInst.setOpcode(ARM::tADDi3);
1131 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1132 // 's' bit operand
1133 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1134 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1135 TmpInst.addOperand(MCOperand::CreateImm(7));
1136 // Predicate.
1137 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1138 TmpInst.addOperand(MCOperand::CreateReg(0));
1139 OutStreamer.EmitInstruction(TmpInst);
1140 }
1141 {
1142 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001143 TmpInst.setOpcode(ARM::tSTRi);
Jim Grosbach433a5782010-09-24 20:47:58 +00001144 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1145 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1146 // The offset immediate is #4. The operand value is scaled by 4 for the
1147 // tSTR instruction.
1148 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach433a5782010-09-24 20:47:58 +00001149 // Predicate.
1150 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1151 TmpInst.addOperand(MCOperand::CreateReg(0));
1152 OutStreamer.EmitInstruction(TmpInst);
1153 }
1154 {
1155 MCInst TmpInst;
1156 TmpInst.setOpcode(ARM::tMOVi8);
1157 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1158 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1159 TmpInst.addOperand(MCOperand::CreateImm(0));
1160 // Predicate.
1161 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1162 TmpInst.addOperand(MCOperand::CreateReg(0));
1163 OutStreamer.EmitInstruction(TmpInst);
1164 }
1165 {
1166 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
1167 MCInst TmpInst;
1168 TmpInst.setOpcode(ARM::tB);
1169 TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
1170 OutStreamer.EmitInstruction(TmpInst);
1171 }
1172 {
1173 MCInst TmpInst;
1174 TmpInst.setOpcode(ARM::tMOVi8);
1175 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1176 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1177 TmpInst.addOperand(MCOperand::CreateImm(1));
1178 // Predicate.
1179 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1180 TmpInst.addOperand(MCOperand::CreateReg(0));
1181 OutStreamer.AddComment("eh_setjmp end");
1182 OutStreamer.EmitInstruction(TmpInst);
1183 }
1184 OutStreamer.EmitLabel(Label);
1185 return;
1186 }
1187
Jim Grosbach45390082010-09-23 23:33:56 +00001188 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbacha3fbadf2010-09-30 19:53:58 +00001189 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbach45390082010-09-23 23:33:56 +00001190 // Two incoming args: GPR:$src, GPR:$val
1191 // add $val, pc, #8
1192 // str $val, [$src, #+4]
1193 // mov r0, #0
1194 // add pc, pc, #0
1195 // mov r0, #1
1196 unsigned SrcReg = MI->getOperand(0).getReg();
1197 unsigned ValReg = MI->getOperand(1).getReg();
1198
1199 {
1200 MCInst TmpInst;
1201 TmpInst.setOpcode(ARM::ADDri);
1202 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1203 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1204 TmpInst.addOperand(MCOperand::CreateImm(8));
1205 // Predicate.
1206 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1207 TmpInst.addOperand(MCOperand::CreateReg(0));
1208 // 's' bit operand (always reg0 for this).
1209 TmpInst.addOperand(MCOperand::CreateReg(0));
1210 OutStreamer.AddComment("eh_setjmp begin");
1211 OutStreamer.EmitInstruction(TmpInst);
1212 }
1213 {
1214 MCInst TmpInst;
Jim Grosbach7e3383c2010-10-27 23:12:14 +00001215 TmpInst.setOpcode(ARM::STRi12);
Jim Grosbach45390082010-09-23 23:33:56 +00001216 TmpInst.addOperand(MCOperand::CreateReg(ValReg));
1217 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach45390082010-09-23 23:33:56 +00001218 TmpInst.addOperand(MCOperand::CreateImm(4));
1219 // Predicate.
1220 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1221 TmpInst.addOperand(MCOperand::CreateReg(0));
1222 OutStreamer.EmitInstruction(TmpInst);
1223 }
1224 {
1225 MCInst TmpInst;
1226 TmpInst.setOpcode(ARM::MOVi);
1227 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1228 TmpInst.addOperand(MCOperand::CreateImm(0));
1229 // Predicate.
1230 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1231 TmpInst.addOperand(MCOperand::CreateReg(0));
1232 // 's' bit operand (always reg0 for this).
1233 TmpInst.addOperand(MCOperand::CreateReg(0));
1234 OutStreamer.EmitInstruction(TmpInst);
1235 }
1236 {
1237 MCInst TmpInst;
1238 TmpInst.setOpcode(ARM::ADDri);
1239 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1240 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1241 TmpInst.addOperand(MCOperand::CreateImm(0));
1242 // Predicate.
1243 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1244 TmpInst.addOperand(MCOperand::CreateReg(0));
1245 // 's' bit operand (always reg0 for this).
1246 TmpInst.addOperand(MCOperand::CreateReg(0));
1247 OutStreamer.EmitInstruction(TmpInst);
1248 }
1249 {
1250 MCInst TmpInst;
1251 TmpInst.setOpcode(ARM::MOVi);
1252 TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
1253 TmpInst.addOperand(MCOperand::CreateImm(1));
1254 // Predicate.
1255 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1256 TmpInst.addOperand(MCOperand::CreateReg(0));
1257 // 's' bit operand (always reg0 for this).
1258 TmpInst.addOperand(MCOperand::CreateReg(0));
1259 OutStreamer.AddComment("eh_setjmp end");
1260 OutStreamer.EmitInstruction(TmpInst);
1261 }
1262 return;
1263 }
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001264 case ARM::Int_eh_sjlj_longjmp: {
1265 // ldr sp, [$src, #8]
1266 // ldr $scratch, [$src, #4]
1267 // ldr r7, [$src]
1268 // bx $scratch
1269 unsigned SrcReg = MI->getOperand(0).getReg();
1270 unsigned ScratchReg = MI->getOperand(1).getReg();
1271 {
1272 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001273 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001274 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1275 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001276 TmpInst.addOperand(MCOperand::CreateImm(8));
1277 // Predicate.
1278 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1279 TmpInst.addOperand(MCOperand::CreateReg(0));
1280 OutStreamer.EmitInstruction(TmpInst);
1281 }
1282 {
1283 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001284 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001285 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1286 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001287 TmpInst.addOperand(MCOperand::CreateImm(4));
1288 // Predicate.
1289 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1290 TmpInst.addOperand(MCOperand::CreateReg(0));
1291 OutStreamer.EmitInstruction(TmpInst);
1292 }
1293 {
1294 MCInst TmpInst;
Jim Grosbach3e556122010-10-26 22:37:02 +00001295 TmpInst.setOpcode(ARM::LDRi12);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001296 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1297 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001298 TmpInst.addOperand(MCOperand::CreateImm(0));
1299 // Predicate.
1300 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1301 TmpInst.addOperand(MCOperand::CreateReg(0));
1302 OutStreamer.EmitInstruction(TmpInst);
1303 }
1304 {
1305 MCInst TmpInst;
Bill Wendling6e46d842010-11-30 00:48:15 +00001306 TmpInst.setOpcode(ARM::BX);
Jim Grosbach5acb3de2010-09-27 21:47:04 +00001307 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1308 // Predicate.
1309 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1310 TmpInst.addOperand(MCOperand::CreateReg(0));
1311 OutStreamer.EmitInstruction(TmpInst);
1312 }
1313 return;
1314 }
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001315 case ARM::tInt_eh_sjlj_longjmp: {
1316 // ldr $scratch, [$src, #8]
1317 // mov sp, $scratch
1318 // ldr $scratch, [$src, #4]
1319 // ldr r7, [$src]
1320 // bx $scratch
1321 unsigned SrcReg = MI->getOperand(0).getReg();
1322 unsigned ScratchReg = MI->getOperand(1).getReg();
1323 {
1324 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001325 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001326 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1327 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1328 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendlingf4caf692010-12-14 03:36:38 +00001329 // tLDR instruction.
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001330 TmpInst.addOperand(MCOperand::CreateImm(2));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001331 // Predicate.
1332 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1333 TmpInst.addOperand(MCOperand::CreateReg(0));
1334 OutStreamer.EmitInstruction(TmpInst);
1335 }
1336 {
1337 MCInst TmpInst;
1338 TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
1339 TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
1340 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1341 // Predicate.
1342 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1343 TmpInst.addOperand(MCOperand::CreateReg(0));
1344 OutStreamer.EmitInstruction(TmpInst);
1345 }
1346 {
1347 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001348 TmpInst.setOpcode(ARM::tLDRi);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001349 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1350 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
1351 TmpInst.addOperand(MCOperand::CreateImm(1));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001352 // Predicate.
1353 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1354 TmpInst.addOperand(MCOperand::CreateReg(0));
1355 OutStreamer.EmitInstruction(TmpInst);
1356 }
1357 {
1358 MCInst TmpInst;
Bill Wendlingf4caf692010-12-14 03:36:38 +00001359 TmpInst.setOpcode(ARM::tLDRr);
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001360 TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
1361 TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
Jim Grosbach385cc5e2010-09-27 22:28:11 +00001362 TmpInst.addOperand(MCOperand::CreateReg(0));
1363 // Predicate.
1364 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1365 TmpInst.addOperand(MCOperand::CreateReg(0));
1366 OutStreamer.EmitInstruction(TmpInst);
1367 }
1368 {
1369 MCInst TmpInst;
1370 TmpInst.setOpcode(ARM::tBX_RET_vararg);
1371 TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
1372 // Predicate.
1373 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1374 TmpInst.addOperand(MCOperand::CreateReg(0));
1375 OutStreamer.EmitInstruction(TmpInst);
1376 }
1377 return;
1378 }
Chris Lattner97f06932009-10-19 20:20:46 +00001379 }
Jim Grosbachb0739b72010-09-02 01:02:06 +00001380
Chris Lattner97f06932009-10-19 20:20:46 +00001381 MCInst TmpInst;
Chris Lattner30e2cc22010-11-14 21:00:02 +00001382 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Chris Lattner850d2e22010-02-03 01:16:28 +00001383 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner97f06932009-10-19 20:20:46 +00001384}
Daniel Dunbar2685a292009-10-20 05:15:36 +00001385
1386//===----------------------------------------------------------------------===//
1387// Target Registry Stuff
1388//===----------------------------------------------------------------------===//
1389
1390static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1391 unsigned SyntaxVariant,
Chris Lattnerd3740872010-04-04 05:04:31 +00001392 const MCAsmInfo &MAI) {
Daniel Dunbar2685a292009-10-20 05:15:36 +00001393 if (SyntaxVariant == 0)
Jim Grosbach74d7e6c2010-09-17 21:33:25 +00001394 return new ARMInstPrinter(MAI);
Daniel Dunbar2685a292009-10-20 05:15:36 +00001395 return 0;
1396}
1397
1398// Force static initialization.
1399extern "C" void LLVMInitializeARMAsmPrinter() {
1400 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1401 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1402
1403 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1404 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
1405}
1406