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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 9e36843964abce1e4f2db23b0b2c3ec8490fe601 / . / lib / Target / PowerPC / Makefile
blob: 693b25d8f8ab9c344ac7e0fb214f071ca6c3fd22 [file] [log] [blame]
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]1##===- lib/Target/PowerPC/Makefile -------------------------*- Makefile -*-===##
2#
3# The LLVM Compiler Infrastructure
4#
5# This file was developed by the LLVM research group and is distributed under
6# the University of Illinois Open Source License. See LICENSE.TXT for details.
7#
8##===----------------------------------------------------------------------===##
9LEVEL = ../../..
Chris Lattner017fdcb2004-07-15 02:33:38 +0000[diff] [blame]10LIBRARYNAME = powerpc
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]11include $(LEVEL)/Makefile.common
12
Misha Brukman2f947862004-08-05 18:34:15 +0000[diff] [blame]13TARGET = PowerPC
14
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]15# Make sure that tblgen is run, first thing.
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]16$(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
17 PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \
18 PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
19 PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]20
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]21TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
Misha Brukman2f947862004-08-05 18:34:15 +0000[diff] [blame]22
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]23%GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
24 @echo "Building PowerPC register names with tblgen"
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]25 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
26
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]27%GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
28 @echo "Building `basename $<` register information header with tblgen"
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]29 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
30
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]31%GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
32 @echo "Building `basename $<` register information implementation with tblgen"
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]33 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
34
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]35$(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
36 @echo "Building $(TARGET) instruction names with tblgen"
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]37 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
38
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]39%GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
40 @echo "Building $(TARGET) instruction information with tblgen"
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]41 $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
42
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]43$(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
44 @echo "Building $(TARGET) code emitter"
Misha Brukmanf5885482004-08-09 17:24:32 +0000[diff] [blame]45 $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
46
Misha Brukman9e368432004-08-17 05:11:54 +0000[diff] [blame^]47$(TARGET)GenAsmWriter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
Nate Begeman14d89d62004-08-14 22:06:38 +0000[diff] [blame]48 @echo "Building $(TARGET).td assembly writer with tblgen"
49 $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@
50
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000[diff] [blame]51clean::
52 $(VERB) rm -f *.inc