Misha Brukman | a85d6bc | 2002-11-22 22:42:50 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 2 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by the LLVM research group and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 7 | // |
John Criswell | b576c94 | 2003-10-20 19:43:21 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Chris Lattner | 055c965 | 2002-10-29 21:05:24 +0000 | [diff] [blame] | 14 | #include "X86InstrInfo.h" |
Chris Lattner | 4ce42a7 | 2002-12-03 05:42:53 +0000 | [diff] [blame] | 15 | #include "X86.h" |
Chris Lattner | abf05b2 | 2003-08-03 21:55:55 +0000 | [diff] [blame] | 16 | #include "X86GenInstrInfo.inc" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 17 | #include "X86InstrBuilder.h" |
| 18 | #include "X86Subtarget.h" |
| 19 | #include "X86TargetMachine.h" |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/STLExtras.h" |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 22 | #include "llvm/CodeGen/LiveVariables.h" |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 23 | #include "llvm/CodeGen/SSARegMap.h" |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 24 | using namespace llvm; |
| 25 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 26 | X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) |
Owen Anderson | 718cb66 | 2007-09-07 04:06:50 +0000 | [diff] [blame] | 27 | : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)), |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 28 | TM(tm), RI(tm, *this) { |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 29 | } |
| 30 | |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 31 | bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, |
| 32 | unsigned& sourceReg, |
| 33 | unsigned& destReg) const { |
| 34 | MachineOpCode oc = MI.getOpcode(); |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 35 | if (oc == X86::MOV8rr || oc == X86::MOV16rr || |
| 36 | oc == X86::MOV32rr || oc == X86::MOV64rr || |
Evan Cheng | 403be7e | 2006-05-08 08:01:26 +0000 | [diff] [blame] | 37 | oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 38 | oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || |
| 39 | oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 || |
Evan Cheng | fe5cb19 | 2006-02-16 22:45:17 +0000 | [diff] [blame] | 40 | oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || |
Evan Cheng | 82521dd | 2006-03-21 07:09:35 +0000 | [diff] [blame] | 41 | oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || |
Evan Cheng | 11e15b3 | 2006-04-03 20:53:28 +0000 | [diff] [blame] | 42 | oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || |
Bill Wendling | 2f88dcd | 2007-03-08 22:09:11 +0000 | [diff] [blame] | 43 | oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || |
Bill Wendling | 6dd29e0 | 2007-04-24 21:17:46 +0000 | [diff] [blame] | 44 | oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { |
Evan Cheng | 1e341729 | 2007-04-25 07:12:14 +0000 | [diff] [blame] | 45 | assert(MI.getNumOperands() >= 2 && |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 46 | MI.getOperand(0).isRegister() && |
| 47 | MI.getOperand(1).isRegister() && |
| 48 | "invalid register-register move instruction"); |
Alkis Evlogimenos | be766c7 | 2004-02-13 21:01:20 +0000 | [diff] [blame] | 49 | sourceReg = MI.getOperand(1).getReg(); |
| 50 | destReg = MI.getOperand(0).getReg(); |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 51 | return true; |
| 52 | } |
| 53 | return false; |
| 54 | } |
Alkis Evlogimenos | 36f506e | 2004-07-31 09:38:47 +0000 | [diff] [blame] | 55 | |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 56 | unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, |
| 57 | int &FrameIndex) const { |
| 58 | switch (MI->getOpcode()) { |
| 59 | default: break; |
| 60 | case X86::MOV8rm: |
| 61 | case X86::MOV16rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 62 | case X86::MOV16_rm: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 63 | case X86::MOV32rm: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 64 | case X86::MOV32_rm: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 65 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 66 | case X86::LD_Fp64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 67 | case X86::MOVSSrm: |
| 68 | case X86::MOVSDrm: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 69 | case X86::MOVAPSrm: |
| 70 | case X86::MOVAPDrm: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 71 | case X86::MMX_MOVD64rm: |
| 72 | case X86::MMX_MOVQ64rm: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 73 | if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && |
| 74 | MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && |
| 75 | MI->getOperand(2).getImmedValue() == 1 && |
| 76 | MI->getOperand(3).getReg() == 0 && |
| 77 | MI->getOperand(4).getImmedValue() == 0) { |
| 78 | FrameIndex = MI->getOperand(1).getFrameIndex(); |
| 79 | return MI->getOperand(0).getReg(); |
| 80 | } |
| 81 | break; |
| 82 | } |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, |
| 87 | int &FrameIndex) const { |
| 88 | switch (MI->getOpcode()) { |
| 89 | default: break; |
| 90 | case X86::MOV8mr: |
| 91 | case X86::MOV16mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 92 | case X86::MOV16_mr: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 93 | case X86::MOV32mr: |
Evan Cheng | f4df680 | 2006-05-11 07:33:49 +0000 | [diff] [blame] | 94 | case X86::MOV32_mr: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 95 | case X86::MOV64mr: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 96 | case X86::ST_FpP64m: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 97 | case X86::MOVSSmr: |
| 98 | case X86::MOVSDmr: |
Chris Lattner | 993c897 | 2006-04-18 16:44:51 +0000 | [diff] [blame] | 99 | case X86::MOVAPSmr: |
| 100 | case X86::MOVAPDmr: |
Bill Wendling | 823efee | 2007-04-03 06:00:37 +0000 | [diff] [blame] | 101 | case X86::MMX_MOVD64mr: |
| 102 | case X86::MMX_MOVQ64mr: |
Bill Wendling | 71bfd11 | 2007-04-03 23:48:32 +0000 | [diff] [blame] | 103 | case X86::MMX_MOVNTQmr: |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 104 | if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && |
| 105 | MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && |
Chris Lattner | 1c07e72 | 2006-02-02 20:38:12 +0000 | [diff] [blame] | 106 | MI->getOperand(1).getImmedValue() == 1 && |
| 107 | MI->getOperand(2).getReg() == 0 && |
| 108 | MI->getOperand(3).getImmedValue() == 0) { |
| 109 | FrameIndex = MI->getOperand(0).getFrameIndex(); |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 110 | return MI->getOperand(4).getReg(); |
| 111 | } |
| 112 | break; |
| 113 | } |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 118 | bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 119 | switch (MI->getOpcode()) { |
| 120 | default: break; |
| 121 | case X86::MOV8rm: |
| 122 | case X86::MOV16rm: |
| 123 | case X86::MOV16_rm: |
| 124 | case X86::MOV32rm: |
| 125 | case X86::MOV32_rm: |
| 126 | case X86::MOV64rm: |
Dale Johannesen | e377d4d | 2007-07-04 21:07:47 +0000 | [diff] [blame] | 127 | case X86::LD_Fp64m: |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 128 | case X86::MOVSSrm: |
| 129 | case X86::MOVSDrm: |
| 130 | case X86::MOVAPSrm: |
| 131 | case X86::MOVAPDrm: |
| 132 | case X86::MMX_MOVD64rm: |
| 133 | case X86::MMX_MOVQ64rm: |
Dan Gohman | 82a87a0 | 2007-06-19 01:48:05 +0000 | [diff] [blame] | 134 | // Loads from constant pools are trivially rematerializable. |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 135 | return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && |
| 136 | MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && |
| 137 | MI->getOperand(1).getReg() == 0 && |
| 138 | MI->getOperand(2).getImmedValue() == 1 && |
| 139 | MI->getOperand(3).getReg() == 0; |
| 140 | } |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 141 | // All other instructions marked M_REMATERIALIZABLE are always trivially |
| 142 | // rematerializable. |
| 143 | return true; |
Dan Gohman | c101e95 | 2007-06-14 20:50:44 +0000 | [diff] [blame] | 144 | } |
| 145 | |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 146 | /// convertToThreeAddress - This method must be implemented by targets that |
| 147 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
| 148 | /// may be able to convert a two-address instruction into a true |
| 149 | /// three-address instruction on demand. This allows the X86 target (for |
| 150 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
| 151 | /// would require register copies due to two-addressness. |
| 152 | /// |
| 153 | /// This method returns a null pointer if the transformation cannot be |
| 154 | /// performed, otherwise it returns the new instruction. |
| 155 | /// |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 156 | MachineInstr * |
| 157 | X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, |
| 158 | MachineBasicBlock::iterator &MBBI, |
| 159 | LiveVariables &LV) const { |
| 160 | MachineInstr *MI = MBBI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 161 | // All instructions input are two-addr instructions. Get the known operands. |
| 162 | unsigned Dest = MI->getOperand(0).getReg(); |
| 163 | unsigned Src = MI->getOperand(1).getReg(); |
| 164 | |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 165 | MachineInstr *NewMI = NULL; |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 166 | // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 167 | // we have better subtarget support, enable the 16-bit LEA generation here. |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 168 | bool DisableLEA16 = true; |
| 169 | |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 170 | switch (MI->getOpcode()) { |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 171 | default: return 0; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 172 | case X86::SHUFPSrri: { |
| 173 | assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 174 | if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; |
| 175 | |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 176 | unsigned A = MI->getOperand(0).getReg(); |
| 177 | unsigned B = MI->getOperand(1).getReg(); |
| 178 | unsigned C = MI->getOperand(2).getReg(); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 179 | unsigned M = MI->getOperand(3).getImm(); |
| 180 | if (B != C) return 0; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 181 | NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 182 | break; |
| 183 | } |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 184 | case X86::SHL64ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 185 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | 995f550 | 2007-03-28 18:12:31 +0000 | [diff] [blame] | 186 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 187 | // the flags produced by a shift yet, so this is safe. |
| 188 | unsigned Dest = MI->getOperand(0).getReg(); |
| 189 | unsigned Src = MI->getOperand(1).getReg(); |
| 190 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 191 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 192 | |
| 193 | NewMI = BuildMI(get(X86::LEA64r), Dest) |
| 194 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 195 | break; |
| 196 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 197 | case X86::SHL32ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 198 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 199 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 200 | // the flags produced by a shift yet, so this is safe. |
| 201 | unsigned Dest = MI->getOperand(0).getReg(); |
| 202 | unsigned Src = MI->getOperand(1).getReg(); |
| 203 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 204 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
| 205 | |
Chris Lattner | f2177b8 | 2007-03-28 00:58:40 +0000 | [diff] [blame] | 206 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? |
| 207 | X86::LEA64_32r : X86::LEA32r; |
| 208 | NewMI = BuildMI(get(Opc), Dest) |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 209 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 210 | break; |
| 211 | } |
| 212 | case X86::SHL16ri: { |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 213 | assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 214 | // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses |
| 215 | // the flags produced by a shift yet, so this is safe. |
| 216 | unsigned Dest = MI->getOperand(0).getReg(); |
| 217 | unsigned Src = MI->getOperand(1).getReg(); |
| 218 | unsigned ShAmt = MI->getOperand(2).getImm(); |
| 219 | if (ShAmt == 0 || ShAmt >= 4) return 0; |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 220 | |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 221 | if (DisableLEA16) { |
| 222 | // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. |
| 223 | SSARegMap *RegMap = MFI->getParent()->getSSARegMap(); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 224 | unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() |
| 225 | ? X86::LEA64_32r : X86::LEA32r; |
| 226 | unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass); |
| 227 | unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 228 | |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 229 | MachineInstr *Ins = |
| 230 | BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 231 | Ins->copyKillDeadInfo(MI); |
| 232 | |
| 233 | NewMI = BuildMI(get(Opc), leaOutReg) |
| 234 | .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0); |
| 235 | |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 236 | MachineInstr *Ext = |
| 237 | BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2); |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 238 | Ext->copyKillDeadInfo(MI); |
| 239 | |
| 240 | MFI->insert(MBBI, Ins); // Insert the insert_subreg |
| 241 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 242 | LV.addVirtualRegisterKilled(leaInReg, NewMI); |
| 243 | MFI->insert(MBBI, NewMI); // Insert the new inst |
| 244 | LV.addVirtualRegisterKilled(leaOutReg, Ext); |
Evan Cheng | 61d9c86 | 2007-09-06 00:14:41 +0000 | [diff] [blame] | 245 | MFI->insert(MBBI, Ext); // Insert the extract_subreg |
Christopher Lamb | b813371 | 2007-08-10 21:18:25 +0000 | [diff] [blame] | 246 | return Ext; |
| 247 | } else { |
| 248 | NewMI = BuildMI(get(X86::LEA16r), Dest) |
| 249 | .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); |
| 250 | } |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 251 | break; |
Evan Cheng | ccba76b | 2006-05-30 20:26:50 +0000 | [diff] [blame] | 252 | } |
| 253 | } |
| 254 | |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 255 | // FIXME: None of these instructions are promotable to LEAs without |
| 256 | // additional information. In particular, LEA doesn't set the flags that |
Chris Lattner | 5aee0b9 | 2005-01-02 04:18:17 +0000 | [diff] [blame] | 257 | // add and inc do. :( |
Chris Lattner | a16b7cb | 2007-03-20 06:08:29 +0000 | [diff] [blame] | 258 | if (0) |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 259 | switch (MI->getOpcode()) { |
| 260 | case X86::INC32r: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 261 | case X86::INC64_32r: |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 262 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 263 | NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 264 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 265 | case X86::INC16r: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 266 | case X86::INC64_16r: |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 267 | if (DisableLEA16) return 0; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 268 | assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 269 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 270 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 271 | case X86::DEC32r: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 272 | case X86::DEC64_32r: |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 273 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 274 | NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 275 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 276 | case X86::DEC16r: |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 277 | case X86::DEC64_16r: |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 278 | if (DisableLEA16) return 0; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 279 | assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 280 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 281 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 282 | case X86::ADD32rr: |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 283 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 284 | NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src, |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 285 | MI->getOperand(2).getReg()); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 286 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 287 | case X86::ADD16rr: |
| 288 | if (DisableLEA16) return 0; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 289 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 290 | NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 291 | MI->getOperand(2).getReg()); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 292 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 293 | case X86::ADD32ri: |
Evan Cheng | 6de0163 | 2006-05-19 18:43:41 +0000 | [diff] [blame] | 294 | case X86::ADD32ri8: |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 295 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 296 | if (MI->getOperand(2).isImmediate()) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 297 | NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 298 | MI->getOperand(2).getImmedValue()); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 299 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 300 | case X86::ADD16ri: |
Evan Cheng | 6de0163 | 2006-05-19 18:43:41 +0000 | [diff] [blame] | 301 | case X86::ADD16ri8: |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 302 | if (DisableLEA16) return 0; |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 303 | assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 304 | if (MI->getOperand(2).isImmediate()) |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 305 | NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 306 | MI->getOperand(2).getImmedValue()); |
| 307 | break; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 308 | case X86::SHL16ri: |
| 309 | if (DisableLEA16) return 0; |
| 310 | case X86::SHL32ri: |
Evan Cheng | 24f2ea3 | 2007-09-14 21:48:26 +0000 | [diff] [blame] | 311 | assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() && |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 312 | "Unknown shl instruction!"); |
| 313 | unsigned ShAmt = MI->getOperand(2).getImmedValue(); |
| 314 | if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { |
| 315 | X86AddressMode AM; |
| 316 | AM.Scale = 1 << ShAmt; |
| 317 | AM.IndexReg = Src; |
| 318 | unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 319 | NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 320 | } |
| 321 | break; |
| 322 | } |
| 323 | |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 324 | if (NewMI) { |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 325 | NewMI->copyKillDeadInfo(MI); |
Evan Cheng | 258ff67 | 2006-12-01 21:52:41 +0000 | [diff] [blame] | 326 | LV.instructionChanged(MI, NewMI); // Update live variables |
| 327 | MFI->insert(MBBI, NewMI); // Insert the new inst |
| 328 | } |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 329 | return NewMI; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 330 | } |
| 331 | |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 332 | /// commuteInstruction - We have a few instructions that must be hacked on to |
| 333 | /// commute them. |
| 334 | /// |
| 335 | MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { |
Chris Lattner | 6458f18 | 2006-09-28 23:33:12 +0000 | [diff] [blame] | 336 | // FIXME: Can commute cmoves by changing the condition! |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 337 | switch (MI->getOpcode()) { |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 338 | case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) |
| 339 | case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 340 | case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 341 | case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) |
| 342 | case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) |
| 343 | case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 344 | unsigned Opc; |
| 345 | unsigned Size; |
| 346 | switch (MI->getOpcode()) { |
| 347 | default: assert(0 && "Unreachable!"); |
| 348 | case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; |
| 349 | case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; |
| 350 | case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; |
| 351 | case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; |
Dan Gohman | e47f1f9 | 2007-09-14 23:17:45 +0000 | [diff] [blame] | 352 | case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; |
| 353 | case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; |
Chris Lattner | 0df53d2 | 2005-01-19 07:31:24 +0000 | [diff] [blame] | 354 | } |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 355 | unsigned Amt = MI->getOperand(3).getImmedValue(); |
| 356 | unsigned A = MI->getOperand(0).getReg(); |
| 357 | unsigned B = MI->getOperand(1).getReg(); |
| 358 | unsigned C = MI->getOperand(2).getReg(); |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 359 | bool BisKill = MI->getOperand(1).isKill(); |
| 360 | bool CisKill = MI->getOperand(2).isKill(); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 361 | return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) |
Evan Cheng | 6ce7dc2 | 2006-11-15 20:58:11 +0000 | [diff] [blame] | 362 | .addReg(B, false, false, BisKill).addImm(Size-Amt); |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 363 | } |
| 364 | default: |
| 365 | return TargetInstrInfo::commuteInstruction(MI); |
| 366 | } |
| 367 | } |
| 368 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 369 | static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { |
| 370 | switch (BrOpc) { |
| 371 | default: return X86::COND_INVALID; |
| 372 | case X86::JE: return X86::COND_E; |
| 373 | case X86::JNE: return X86::COND_NE; |
| 374 | case X86::JL: return X86::COND_L; |
| 375 | case X86::JLE: return X86::COND_LE; |
| 376 | case X86::JG: return X86::COND_G; |
| 377 | case X86::JGE: return X86::COND_GE; |
| 378 | case X86::JB: return X86::COND_B; |
| 379 | case X86::JBE: return X86::COND_BE; |
| 380 | case X86::JA: return X86::COND_A; |
| 381 | case X86::JAE: return X86::COND_AE; |
| 382 | case X86::JS: return X86::COND_S; |
| 383 | case X86::JNS: return X86::COND_NS; |
| 384 | case X86::JP: return X86::COND_P; |
| 385 | case X86::JNP: return X86::COND_NP; |
| 386 | case X86::JO: return X86::COND_O; |
| 387 | case X86::JNO: return X86::COND_NO; |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { |
| 392 | switch (CC) { |
| 393 | default: assert(0 && "Illegal condition code!"); |
| 394 | case X86::COND_E: return X86::JE; |
| 395 | case X86::COND_NE: return X86::JNE; |
| 396 | case X86::COND_L: return X86::JL; |
| 397 | case X86::COND_LE: return X86::JLE; |
| 398 | case X86::COND_G: return X86::JG; |
| 399 | case X86::COND_GE: return X86::JGE; |
| 400 | case X86::COND_B: return X86::JB; |
| 401 | case X86::COND_BE: return X86::JBE; |
| 402 | case X86::COND_A: return X86::JA; |
| 403 | case X86::COND_AE: return X86::JAE; |
| 404 | case X86::COND_S: return X86::JS; |
| 405 | case X86::COND_NS: return X86::JNS; |
| 406 | case X86::COND_P: return X86::JP; |
| 407 | case X86::COND_NP: return X86::JNP; |
| 408 | case X86::COND_O: return X86::JO; |
| 409 | case X86::COND_NO: return X86::JNO; |
| 410 | } |
| 411 | } |
| 412 | |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 413 | /// GetOppositeBranchCondition - Return the inverse of the specified condition, |
| 414 | /// e.g. turning COND_E to COND_NE. |
| 415 | X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { |
| 416 | switch (CC) { |
| 417 | default: assert(0 && "Illegal condition code!"); |
| 418 | case X86::COND_E: return X86::COND_NE; |
| 419 | case X86::COND_NE: return X86::COND_E; |
| 420 | case X86::COND_L: return X86::COND_GE; |
| 421 | case X86::COND_LE: return X86::COND_G; |
| 422 | case X86::COND_G: return X86::COND_LE; |
| 423 | case X86::COND_GE: return X86::COND_L; |
| 424 | case X86::COND_B: return X86::COND_AE; |
| 425 | case X86::COND_BE: return X86::COND_A; |
| 426 | case X86::COND_A: return X86::COND_BE; |
| 427 | case X86::COND_AE: return X86::COND_B; |
| 428 | case X86::COND_S: return X86::COND_NS; |
| 429 | case X86::COND_NS: return X86::COND_S; |
| 430 | case X86::COND_P: return X86::COND_NP; |
| 431 | case X86::COND_NP: return X86::COND_P; |
| 432 | case X86::COND_O: return X86::COND_NO; |
| 433 | case X86::COND_NO: return X86::COND_O; |
| 434 | } |
| 435 | } |
| 436 | |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 437 | bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { |
Evan Cheng | 14c4655 | 2007-07-06 23:22:03 +0000 | [diff] [blame] | 438 | const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); |
| 439 | if (TID->Flags & M_TERMINATOR_FLAG) { |
| 440 | // Conditional branch is a special case. |
| 441 | if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0) |
| 442 | return true; |
| 443 | if ((TID->Flags & M_PREDICABLE) == 0) |
| 444 | return true; |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 445 | return !isPredicated(MI); |
Evan Cheng | 14c4655 | 2007-07-06 23:22:03 +0000 | [diff] [blame] | 446 | } |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 447 | return false; |
| 448 | } |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 449 | |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 450 | // For purposes of branch analysis do not count FP_REG_KILL as a terminator. |
| 451 | static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, |
| 452 | const X86InstrInfo &TII) { |
| 453 | if (MI->getOpcode() == X86::FP_REG_KILL) |
| 454 | return false; |
| 455 | return TII.isUnpredicatedTerminator(MI); |
| 456 | } |
| 457 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 458 | bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, |
| 459 | MachineBasicBlock *&TBB, |
| 460 | MachineBasicBlock *&FBB, |
| 461 | std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 462 | // If the block has no terminators, it just falls into the block after it. |
| 463 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 464 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 465 | return false; |
| 466 | |
| 467 | // Get the last instruction in the block. |
| 468 | MachineInstr *LastInst = I; |
| 469 | |
| 470 | // If there is only one terminator instruction, process it. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 471 | if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 472 | if (!isBranch(LastInst->getOpcode())) |
| 473 | return true; |
| 474 | |
| 475 | // If the block ends with a branch there are 3 possibilities: |
| 476 | // it's an unconditional, conditional, or indirect branch. |
| 477 | |
| 478 | if (LastInst->getOpcode() == X86::JMP) { |
| 479 | TBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 480 | return false; |
| 481 | } |
| 482 | X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); |
| 483 | if (BranchCode == X86::COND_INVALID) |
| 484 | return true; // Can't handle indirect branch. |
| 485 | |
| 486 | // Otherwise, block ends with fall-through condbranch. |
| 487 | TBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 488 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
| 489 | return false; |
| 490 | } |
| 491 | |
| 492 | // Get the instruction before it if it's a terminator. |
| 493 | MachineInstr *SecondLastInst = I; |
| 494 | |
| 495 | // If there are three terminators, we don't know what sort of block this is. |
Evan Cheng | 85dce6c | 2007-07-26 17:32:14 +0000 | [diff] [blame] | 496 | if (SecondLastInst && I != MBB.begin() && |
| 497 | isBrAnalysisUnpredicatedTerminator(--I, *this)) |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 498 | return true; |
| 499 | |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 500 | // If the block ends with X86::JMP and a conditional branch, handle it. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 501 | X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); |
| 502 | if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { |
Chris Lattner | 6ce6443 | 2006-10-30 22:27:23 +0000 | [diff] [blame] | 503 | TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); |
| 504 | Cond.push_back(MachineOperand::CreateImm(BranchCode)); |
| 505 | FBB = LastInst->getOperand(0).getMachineBasicBlock(); |
| 506 | return false; |
| 507 | } |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 508 | |
Dale Johannesen | 13e8b51 | 2007-06-13 17:59:52 +0000 | [diff] [blame] | 509 | // If the block ends with two X86::JMPs, handle it. The second one is not |
| 510 | // executed, so remove it. |
| 511 | if (SecondLastInst->getOpcode() == X86::JMP && |
| 512 | LastInst->getOpcode() == X86::JMP) { |
| 513 | TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); |
| 514 | I = LastInst; |
| 515 | I->eraseFromParent(); |
| 516 | return false; |
| 517 | } |
| 518 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 519 | // Otherwise, can't handle this. |
| 520 | return true; |
| 521 | } |
| 522 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 523 | unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 524 | MachineBasicBlock::iterator I = MBB.end(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 525 | if (I == MBB.begin()) return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 526 | --I; |
| 527 | if (I->getOpcode() != X86::JMP && |
| 528 | GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 529 | return 0; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 530 | |
| 531 | // Remove the branch. |
| 532 | I->eraseFromParent(); |
| 533 | |
| 534 | I = MBB.end(); |
| 535 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 536 | if (I == MBB.begin()) return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 537 | --I; |
| 538 | if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 539 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 540 | |
| 541 | // Remove the branch. |
| 542 | I->eraseFromParent(); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 543 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 544 | } |
| 545 | |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 546 | unsigned |
| 547 | X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 548 | MachineBasicBlock *FBB, |
| 549 | const std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 550 | // Shouldn't be a fall through. |
| 551 | assert(TBB && "InsertBranch must not be told to insert a fallthrough"); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 552 | assert((Cond.size() == 1 || Cond.size() == 0) && |
| 553 | "X86 branch conditions have one component!"); |
| 554 | |
| 555 | if (FBB == 0) { // One way branch. |
| 556 | if (Cond.empty()) { |
| 557 | // Unconditional branch? |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 558 | BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 559 | } else { |
| 560 | // Conditional branch. |
| 561 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 562 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
Chris Lattner | 34a84ac | 2006-10-21 05:34:23 +0000 | [diff] [blame] | 563 | } |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 564 | return 1; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 565 | } |
| 566 | |
Chris Lattner | 879d09c | 2006-10-21 05:42:09 +0000 | [diff] [blame] | 567 | // Two-way Conditional branch. |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 568 | unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); |
Evan Cheng | c0f64ff | 2006-11-27 23:37:22 +0000 | [diff] [blame] | 569 | BuildMI(&MBB, get(Opc)).addMBB(TBB); |
| 570 | BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 571 | return 2; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 574 | bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { |
| 575 | if (MBB.empty()) return false; |
| 576 | |
| 577 | switch (MBB.back().getOpcode()) { |
Evan Cheng | 126f17a | 2007-05-21 18:44:17 +0000 | [diff] [blame] | 578 | case X86::RET: // Return. |
| 579 | case X86::RETI: |
| 580 | case X86::TAILJMPd: |
| 581 | case X86::TAILJMPr: |
| 582 | case X86::TAILJMPm: |
Chris Lattner | c24ff8e | 2006-10-28 17:29:57 +0000 | [diff] [blame] | 583 | case X86::JMP: // Uncond branch. |
| 584 | case X86::JMP32r: // Indirect branch. |
| 585 | case X86::JMP32m: // Indirect branch through mem. |
| 586 | return true; |
| 587 | default: return false; |
| 588 | } |
| 589 | } |
| 590 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 591 | bool X86InstrInfo:: |
| 592 | ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 593 | assert(Cond.size() == 1 && "Invalid X86 branch condition!"); |
| 594 | Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); |
| 595 | return false; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 596 | } |
| 597 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 598 | const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { |
| 599 | const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); |
| 600 | if (Subtarget->is64Bit()) |
| 601 | return &X86::GR64RegClass; |
| 602 | else |
| 603 | return &X86::GR32RegClass; |
| 604 | } |