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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnerf8c68f62006-06-28 22:17:39 +000029#include "llvm/Support/Visibility.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Chris Lattner2c2c6c62006-01-22 23:41:00 +000033#include <iostream>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000034using namespace llvm;
35
36namespace {
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000037 static Statistic<> NumSpills("spiller", "Number of register spills");
38 static Statistic<> NumStores("spiller", "Number of stores added");
39 static Statistic<> NumLoads ("spiller", "Number of loads added");
40 static Statistic<> NumReused("spiller", "Number of values reused");
41 static Statistic<> NumDSE ("spiller", "Number of dead stores elided");
42 static Statistic<> NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattner8c4d88d2004-09-30 01:54:45 +000044 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000045
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000046 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000048 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 cl::Prefix,
50 cl::values(clEnumVal(simple, " simple spiller"),
51 clEnumVal(local, " local spiller"),
52 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000053 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000054}
55
Chris Lattner8c4d88d2004-09-30 01:54:45 +000056//===----------------------------------------------------------------------===//
57// VirtRegMap implementation
58//===----------------------------------------------------------------------===//
59
60void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000061 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
62 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000063}
64
Chris Lattner8c4d88d2004-09-30 01:54:45 +000065int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
66 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000067 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000068 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000069 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
70 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
71 RC->getAlignment());
72 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000073 ++NumSpills;
74 return frameIndex;
75}
76
77void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
78 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000079 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000080 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000081 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000082}
83
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000084void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000085 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000086 // Move previous memory references folded to new instruction.
87 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000088 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000089 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
90 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000091 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000092 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000093
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000094 ModRef MRInfo;
95 if (!OldMI->getOperand(OpNo).isDef()) {
96 assert(OldMI->getOperand(OpNo).isUse() && "Operand is not use or def?");
97 MRInfo = isRef;
98 } else {
99 MRInfo = OldMI->getOperand(OpNo).isUse() ? isModRef : isMod;
100 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000101
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000102 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000103 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000104}
105
Chris Lattner7f690e62004-09-30 02:15:18 +0000106void VirtRegMap::print(std::ostream &OS) const {
107 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000108
Chris Lattner7f690e62004-09-30 02:15:18 +0000109 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000110 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000111 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
112 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
113 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000114
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000115 }
116
117 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000118 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
119 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
120 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
121 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000122}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000123
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124void VirtRegMap::dump() const { print(std::cerr); }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000125
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000126
127//===----------------------------------------------------------------------===//
128// Simple Spiller Implementation
129//===----------------------------------------------------------------------===//
130
131Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000132
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000133namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000134 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000135 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000136 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000137}
138
Chris Lattner35f27052006-05-01 21:16:03 +0000139bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000140 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
141 DEBUG(std::cerr << "********** Function: "
142 << MF.getFunction()->getName() << '\n');
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000143 const TargetMachine &TM = MF.getTarget();
144 const MRegisterInfo &MRI = *TM.getRegisterInfo();
145 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000146
Chris Lattner4ea1b822004-09-30 02:33:48 +0000147 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
148 // each vreg once (in the case where a spilled vreg is used by multiple
149 // operands). This is always smaller than the number of operands to the
150 // current machine instr, so it should be small.
151 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000152
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000153 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
154 MBBI != E; ++MBBI) {
155 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
156 MachineBasicBlock &MBB = *MBBI;
157 for (MachineBasicBlock::iterator MII = MBB.begin(),
158 E = MBB.end(); MII != E; ++MII) {
159 MachineInstr &MI = *MII;
160 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000161 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000162 if (MO.isRegister() && MO.getReg())
163 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
164 unsigned VirtReg = MO.getReg();
165 unsigned PhysReg = VRM.getPhys(VirtReg);
166 if (VRM.hasStackSlot(VirtReg)) {
167 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000168 const TargetRegisterClass* RC =
169 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000170
Chris Lattner886dd912005-04-04 21:35:34 +0000171 if (MO.isUse() &&
172 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
173 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000174 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000175 LoadedRegs.push_back(VirtReg);
176 ++NumLoads;
177 DEBUG(std::cerr << '\t' << *prior(MII));
178 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000179
Chris Lattner886dd912005-04-04 21:35:34 +0000180 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000181 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000182 ++NumStores;
183 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000184 }
Chris Lattner886dd912005-04-04 21:35:34 +0000185 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000186 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000187 } else {
188 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000189 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000190 }
Chris Lattner886dd912005-04-04 21:35:34 +0000191
Chris Lattner477e4552004-09-30 16:10:45 +0000192 DEBUG(std::cerr << '\t' << MI);
Chris Lattner4ea1b822004-09-30 02:33:48 +0000193 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000194 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000195 }
196 return true;
197}
198
199//===----------------------------------------------------------------------===//
200// Local Spiller Implementation
201//===----------------------------------------------------------------------===//
202
203namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000204 /// LocalSpiller - This spiller does a simple pass over the machine basic
205 /// block to attempt to keep spills in registers as much as possible for
206 /// blocks that have low register pressure (the vreg may be spilled due to
207 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000208 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000209 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000210 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000211 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000212 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000213 MRI = MF.getTarget().getRegisterInfo();
214 TII = MF.getTarget().getInstrInfo();
215 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
216 << MF.getFunction()->getName() << "':\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000217
Chris Lattner7fb64342004-10-01 19:04:51 +0000218 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
219 MBB != E; ++MBB)
220 RewriteMBB(*MBB, VRM);
221 return true;
222 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000224 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000225 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000226 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000228 std::multimap<unsigned, int> &PhysRegs);
229 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
230 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 };
232}
233
Chris Lattner66cf80f2006-02-03 23:13:58 +0000234/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
235/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000236///
237/// Note that not all physregs are created equal here. In particular, some
238/// physregs are reloads that we are allowed to clobber or ignore at any time.
239/// Other physregs are values that the register allocated program is using that
240/// we cannot CHANGE, but we can read if we like. We keep track of this on a
241/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
242/// entries. The predicate 'canClobberPhysReg()' checks this bit and
243/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000244namespace {
245class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000246 const MRegisterInfo *MRI;
247 const TargetInstrInfo *TII;
248
249 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
250 // register values that are still available, due to being loaded or stored to,
251 // but not invalidated yet.
252 std::map<int, unsigned> SpillSlotsAvailable;
253
254 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
255 // which stack slot values are currently held by a physreg. This is used to
256 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
257 std::multimap<unsigned, int> PhysRegsAvailable;
258
259 void ClobberPhysRegOnly(unsigned PhysReg);
260public:
261 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
262 : MRI(mri), TII(tii) {
263 }
264
265 /// getSpillSlotPhysReg - If the specified stack slot is available in a
266 /// physical register, return that PhysReg, otherwise return 0.
267 unsigned getSpillSlotPhysReg(int Slot) const {
268 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
269 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000270 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000271 return 0;
272 }
Chris Lattner540fec62006-02-25 01:51:33 +0000273
274 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000275
276 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000277 /// specified physreg. If CanClobber is true, the physreg can be modified at
278 /// any time without changing the semantics of the program.
279 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000280 // If this stack slot is thought to be available in some other physreg,
281 // remove its record.
282 ModifyStackSlot(Slot);
283
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000285 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000286
287 DEBUG(std::cerr << "Remembering SS#" << Slot << " in physreg "
288 << MRI->getName(Reg) << "\n");
289 }
290
Chris Lattner593c9582006-02-03 23:28:46 +0000291 /// canClobberPhysReg - Return true if the spiller is allowed to change the
292 /// value of the specified stackslot register if it desires. The specified
293 /// stack slot must be available in a physreg for this query to make sense.
294 bool canClobberPhysReg(int Slot) const {
295 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
296 return SpillSlotsAvailable.find(Slot)->second & 1;
297 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298
299 /// ClobberPhysReg - This is called when the specified physreg changes
300 /// value. We use this to invalidate any info about stuff we thing lives in
301 /// it and any of its aliases.
302 void ClobberPhysReg(unsigned PhysReg);
303
304 /// ModifyStackSlot - This method is called when the value in a stack slot
305 /// changes. This removes information about which register the previous value
306 /// for this slot lives in (as the previous value is dead now).
307 void ModifyStackSlot(int Slot);
308};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000309}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000310
311/// ClobberPhysRegOnly - This is called when the specified physreg changes
312/// value. We use this to invalidate any info about stuff we thing lives in it.
313void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
314 std::multimap<unsigned, int>::iterator I =
315 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000316 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000317 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000318 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000319 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000320 "Bidirectional map mismatch!");
321 SpillSlotsAvailable.erase(Slot);
Chris Lattner7fb64342004-10-01 19:04:51 +0000322 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
Chris Lattner07cf1412006-02-03 00:36:31 +0000323 << " clobbered, invalidating SS#" << Slot << "\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000324 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000325}
326
Chris Lattner66cf80f2006-02-03 23:13:58 +0000327/// ClobberPhysReg - This is called when the specified physreg changes
328/// value. We use this to invalidate any info about stuff we thing lives in
329/// it and any of its aliases.
330void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000331 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000332 ClobberPhysRegOnly(*AS);
333 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000334}
335
Chris Lattner07cf1412006-02-03 00:36:31 +0000336/// ModifyStackSlot - This method is called when the value in a stack slot
337/// changes. This removes information about which register the previous value
338/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000339void AvailableSpills::ModifyStackSlot(int Slot) {
340 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
341 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000342 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000343 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000344
345 // This register may hold the value of multiple stack slots, only remove this
346 // stack slot from the set of values the register contains.
347 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
348 for (; ; ++I) {
349 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
350 "Map inverse broken!");
351 if (I->second == Slot) break;
352 }
353 PhysRegsAvailable.erase(I);
354}
355
356
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000357
Chris Lattner7fb64342004-10-01 19:04:51 +0000358// ReusedOp - For each reused operand, we keep track of a bit of information, in
359// case we need to rollback upon processing a new operand. See comments below.
360namespace {
361 struct ReusedOp {
362 // The MachineInstr operand that reused an available value.
363 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000364
Chris Lattner7fb64342004-10-01 19:04:51 +0000365 // StackSlot - The spill slot of the value being reused.
366 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000367
Chris Lattner7fb64342004-10-01 19:04:51 +0000368 // PhysRegReused - The physical register the value was available in.
369 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000370
Chris Lattner7fb64342004-10-01 19:04:51 +0000371 // AssignedPhysReg - The physreg that was assigned for use by the reload.
372 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000373
374 // VirtReg - The virtual register itself.
375 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000376
Chris Lattner8a61a752005-10-06 17:19:06 +0000377 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
378 unsigned vreg)
379 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
380 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000381 };
Chris Lattner540fec62006-02-25 01:51:33 +0000382
383 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
384 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000385 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000386 MachineInstr &MI;
387 std::vector<ReusedOp> Reuses;
388 public:
389 ReuseInfo(MachineInstr &mi) : MI(mi) {}
390
391 bool hasReuses() const {
392 return !Reuses.empty();
393 }
394
395 /// addReuse - If we choose to reuse a virtual register that is already
396 /// available instead of reloading it, remember that we did so.
397 void addReuse(unsigned OpNo, unsigned StackSlot,
398 unsigned PhysRegReused, unsigned AssignedPhysReg,
399 unsigned VirtReg) {
400 // If the reload is to the assigned register anyway, no undo will be
401 // required.
402 if (PhysRegReused == AssignedPhysReg) return;
403
404 // Otherwise, remember this.
405 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
406 AssignedPhysReg, VirtReg));
407 }
408
409 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
410 /// is some other operand that is using the specified register, either pick
411 /// a new register to use, or evict the previous reload and use this reg.
412 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
413 AvailableSpills &Spills,
414 std::map<int, MachineInstr*> &MaybeDeadStores) {
415 if (Reuses.empty()) return PhysReg; // This is most often empty.
416
417 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
418 ReusedOp &Op = Reuses[ro];
419 // If we find some other reuse that was supposed to use this register
420 // exactly for its reload, we can change this reload to use ITS reload
421 // register.
422 if (Op.PhysRegReused == PhysReg) {
423 // Yup, use the reload register that we didn't use before.
Chris Lattner47cb7172006-02-25 02:03:40 +0000424 unsigned NewReg = Op.AssignedPhysReg;
425
426 // Remove the record for the previous reuse. We know it can never be
427 // invalidated now.
428 Reuses.erase(Reuses.begin()+ro);
429 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000430 } else {
431 // Otherwise, we might also have a problem if a previously reused
432 // value aliases the new register. If so, codegen the previous reload
433 // and use this one.
434 unsigned PRRU = Op.PhysRegReused;
435 const MRegisterInfo *MRI = Spills.getRegInfo();
436 if (MRI->areAliases(PRRU, PhysReg)) {
437 // Okay, we found out that an alias of a reused register
438 // was used. This isn't good because it means we have
439 // to undo a previous reuse.
440 MachineBasicBlock *MBB = MI->getParent();
441 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000442 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
443
444 // Copy Op out of the vector and remove it, we're going to insert an
445 // explicit load for it.
446 ReusedOp NewOp = Op;
447 Reuses.erase(Reuses.begin()+ro);
448
449 // Ok, we're going to try to reload the assigned physreg into the
450 // slot that we were supposed to in the first place. However, that
451 // register could hold a reuse. Check to see if it conflicts or
452 // would prefer us to use a different register.
453 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
454 MI, Spills, MaybeDeadStores);
455
456 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
457 NewOp.StackSlot, AliasRC);
458 Spills.ClobberPhysReg(NewPhysReg);
459 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000460
461 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000462 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000463
Chris Lattnere53f4a02006-05-04 17:52:23 +0000464 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000465
Chris Lattner28bad082006-02-25 02:17:31 +0000466 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000467 ++NumLoads;
468 DEBUG(MachineBasicBlock::iterator MII = MI;
469 std::cerr << '\t' << *prior(MII));
470
471 DEBUG(std::cerr << "Reuse undone!\n");
Chris Lattner540fec62006-02-25 01:51:33 +0000472 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000473
474 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000475 return PhysReg;
476 }
477 }
478 }
479 return PhysReg;
480 }
481 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000482}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000483
Chris Lattner7fb64342004-10-01 19:04:51 +0000484
485/// rewriteMBB - Keep track of which spills are available even after the
486/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000487void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000488
Chris Lattner7fb64342004-10-01 19:04:51 +0000489 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
490
Chris Lattner66cf80f2006-02-03 23:13:58 +0000491 // Spills - Keep track of which spilled values are available in physregs so
492 // that we can choose to reuse the physregs instead of emitting reloads.
493 AvailableSpills Spills(MRI, TII);
494
Chris Lattner7fb64342004-10-01 19:04:51 +0000495 // DefAndUseVReg - When we see a def&use operand that is spilled, keep track
496 // of it. ".first" is the machine operand index (should always be 0 for now),
497 // and ".second" is the virtual register that is spilled.
498 std::vector<std::pair<unsigned, unsigned> > DefAndUseVReg;
499
Chris Lattner52b25db2004-10-01 19:47:12 +0000500 // MaybeDeadStores - When we need to write a value back into a stack slot,
501 // keep track of the inserted store. If the stack slot value is never read
502 // (because the value was used from some available register, for example), and
503 // subsequently stored to, the original store is dead. This map keeps track
504 // of inserted stores that are not used. If we see a subsequent store to the
505 // same stack slot, the original store is deleted.
506 std::map<int, MachineInstr*> MaybeDeadStores;
507
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000508 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
509
Chris Lattner7fb64342004-10-01 19:04:51 +0000510 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
511 MII != E; ) {
512 MachineInstr &MI = *MII;
513 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
514
Chris Lattner540fec62006-02-25 01:51:33 +0000515 /// ReusedOperands - Keep track of operand reuse in case we need to undo
516 /// reuse.
517 ReuseInfo ReusedOperands(MI);
518
Chris Lattner7fb64342004-10-01 19:04:51 +0000519 DefAndUseVReg.clear();
520
521 // Process all of the spilled uses and all non spilled reg references.
522 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
523 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000524 if (!MO.isRegister() || MO.getReg() == 0)
525 continue; // Ignore non-register operands.
526
527 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
528 // Ignore physregs for spilling, but remember that it is used by this
529 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000530 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner50ea01e2005-09-09 20:29:51 +0000531 continue;
532 }
533
534 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
535 "Not a virtual or a physical register?");
536
537 unsigned VirtReg = MO.getReg();
538 if (!VRM.hasStackSlot(VirtReg)) {
539 // This virtual register was assigned a physreg!
540 unsigned Phys = VRM.getPhys(VirtReg);
541 PhysRegsUsed[Phys] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000542 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000543 continue;
544 }
545
546 // This virtual register is now known to be a spilled value.
547 if (!MO.isUse())
548 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000549
Chris Lattner50ea01e2005-09-09 20:29:51 +0000550 // If this is both a def and a use, we need to emit a store to the
551 // stack slot after the instruction. Keep track of D&U operands
552 // because we are about to change it to a physreg here.
553 if (MO.isDef()) {
554 // Remember that this was a def-and-use operand, and that the
555 // stack slot is live after this instruction executes.
556 DefAndUseVReg.push_back(std::make_pair(i, VirtReg));
557 }
558
559 int StackSlot = VRM.getStackSlot(VirtReg);
560 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000561
Chris Lattner50ea01e2005-09-09 20:29:51 +0000562 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000563 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000564
Chris Lattneraddc55a2006-04-28 01:46:50 +0000565 // Don't reuse it for a def&use operand if we aren't allowed to change
566 // the physreg!
567 if (!MO.isDef() || Spills.canClobberPhysReg(StackSlot)) {
568 // If this stack slot value is already available, reuse it!
569 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
570 << MRI->getName(PhysReg) << " for vreg"
571 << VirtReg <<" instead of reloading into physreg "
572 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000573 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000574
575 // The only technical detail we have is that we don't know that
576 // PhysReg won't be clobbered by a reloaded stack slot that occurs
577 // later in the instruction. In particular, consider 'op V1, V2'.
578 // If V1 is available in physreg R0, we would choose to reuse it
579 // here, instead of reloading it into the register the allocator
580 // indicated (say R1). However, V2 might have to be reloaded
581 // later, and it might indicate that it needs to live in R0. When
582 // this occurs, we need to have information available that
583 // indicates it is safe to use R1 for the reload instead of R0.
584 //
585 // To further complicate matters, we might conflict with an alias,
586 // or R0 and R1 might not be compatible with each other. In this
587 // case, we actually insert a reload for V1 in R1, ensuring that
588 // we can get at R0 or its alias.
589 ReusedOperands.addReuse(i, StackSlot, PhysReg,
590 VRM.getPhys(VirtReg), VirtReg);
591 ++NumReused;
592 continue;
593 }
594
595 // Otherwise we have a situation where we have a two-address instruction
596 // whose mod/ref operand needs to be reloaded. This reload is already
597 // available in some register "PhysReg", but if we used PhysReg as the
598 // operand to our 2-addr instruction, the instruction would modify
599 // PhysReg. This isn't cool if something later uses PhysReg and expects
600 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000601 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000602 // To avoid this problem, and to avoid doing a load right after a store,
603 // we emit a copy from PhysReg into the designated register for this
604 // operand.
605 unsigned DesignatedReg = VRM.getPhys(VirtReg);
606 assert(DesignatedReg && "Must map virtreg to physreg!");
607
608 // Note that, if we reused a register for a previous operand, the
609 // register we want to reload into might not actually be
610 // available. If this occurs, use the register indicated by the
611 // reuser.
612 if (ReusedOperands.hasReuses())
613 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
614 Spills, MaybeDeadStores);
615
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000616 // If the mapped designated register is actually the physreg we have
617 // incoming, we don't need to inserted a dead copy.
618 if (DesignatedReg == PhysReg) {
619 // If this stack slot value is already available, reuse it!
620 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
621 << MRI->getName(PhysReg) << " for vreg"
622 << VirtReg
623 << " instead of reloading into same physreg.\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000624 MI.getOperand(i).setReg(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000625 ++NumReused;
626 continue;
627 }
628
Chris Lattneraddc55a2006-04-28 01:46:50 +0000629 const TargetRegisterClass* RC =
630 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
631
632 PhysRegsUsed[DesignatedReg] = true;
633 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
634
635 // This invalidates DesignatedReg.
636 Spills.ClobberPhysReg(DesignatedReg);
637
638 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000639 MI.getOperand(i).setReg(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000640 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner50ea01e2005-09-09 20:29:51 +0000641 ++NumReused;
642 continue;
643 }
644
645 // Otherwise, reload it and remember that we have it.
646 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000647 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000648 const TargetRegisterClass* RC =
649 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000650
Chris Lattner50ea01e2005-09-09 20:29:51 +0000651 // Note that, if we reused a register for a previous operand, the
652 // register we want to reload into might not actually be
653 // available. If this occurs, use the register indicated by the
654 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000655 if (ReusedOperands.hasReuses())
656 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
657 Spills, MaybeDeadStores);
658
Chris Lattner50ea01e2005-09-09 20:29:51 +0000659 PhysRegsUsed[PhysReg] = true;
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000660 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000661 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000662 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000663
664 // Any stores to this stack slot are not dead anymore.
665 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000666 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000667 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000668 MI.getOperand(i).setReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000669 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000670 }
671
Chris Lattner7fb64342004-10-01 19:04:51 +0000672 // Loop over all of the implicit defs, clearing them from our available
673 // sets.
Jim Laskeycd4317e2006-07-21 21:15:20 +0000674 const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
675 if (ImpDef) {
676 for ( ; *ImpDef; ++ImpDef) {
677 PhysRegsUsed[*ImpDef] = true;
678 Spills.ClobberPhysReg(*ImpDef);
679 }
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000680 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000681
Chris Lattner7fb64342004-10-01 19:04:51 +0000682 DEBUG(std::cerr << '\t' << MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000683
Chris Lattner7fb64342004-10-01 19:04:51 +0000684 // If we have folded references to memory operands, make sure we clear all
685 // physical registers that may contain the value of the spilled virtual
686 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000687 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
688 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000689 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
690 << I->second.second);
691 unsigned VirtReg = I->second.first;
692 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000693 if (!VRM.hasStackSlot(VirtReg)) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000694 DEBUG(std::cerr << ": No stack slot!\n");
Chris Lattnercea86882005-09-19 06:56:21 +0000695 continue;
696 }
697 int SS = VRM.getStackSlot(VirtReg);
698 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
699
700 // If this folded instruction is just a use, check to see if it's a
701 // straight load from the virt reg slot.
702 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
703 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000704 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
705 // If this spill slot is available, turn it into a copy (or nothing)
706 // instead of leaving it as a load!
Chris Lattner66cf80f2006-02-03 23:13:58 +0000707 unsigned InReg;
708 if (FrameIdx == SS && (InReg = Spills.getSpillSlotPhysReg(SS))) {
Chris Lattnercea86882005-09-19 06:56:21 +0000709 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
710 MachineFunction &MF = *MBB.getParent();
Chris Lattner66cf80f2006-02-03 23:13:58 +0000711 if (DestReg != InReg) {
712 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
Chris Lattnercea86882005-09-19 06:56:21 +0000713 MF.getSSARegMap()->getRegClass(VirtReg));
Chris Lattner22480c42005-10-05 18:30:19 +0000714 // Revisit the copy so we make sure to notice the effects of the
715 // operation on the destreg (either needing to RA it if it's
716 // virtual or needing to clobber any values if it's physical).
717 NextMII = &MI;
718 --NextMII; // backtrack to the copy.
Chris Lattnercea86882005-09-19 06:56:21 +0000719 }
Chris Lattner8a18c132006-05-01 21:17:10 +0000720 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattnercea86882005-09-19 06:56:21 +0000721 MBB.erase(&MI);
722 goto ProcessNextInst;
723 }
724 }
725 }
726
727 // If this reference is not a use, any previous store is now dead.
728 // Otherwise, the store to this stack slot is not dead anymore.
729 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
730 if (MDSI != MaybeDeadStores.end()) {
731 if (MR & VirtRegMap::isRef) // Previous store is not dead.
732 MaybeDeadStores.erase(MDSI);
733 else {
734 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000735 assert(VirtRegMap::isMod && "Can't be modref!");
736 DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second);
737 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000738 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000739 MaybeDeadStores.erase(MDSI);
740 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000741 }
742 }
743
744 // If the spill slot value is available, and this is a new definition of
745 // the value, the value is not available anymore.
746 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000747 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000748 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000749
750 // If this is *just* a mod of the value, check to see if this is just a
751 // store to the spill slot (i.e. the spill got merged into the copy). If
752 // so, realize that the vreg is available now, and add the store to the
753 // MaybeDeadStore info.
754 int StackSlot;
755 if (!(MR & VirtRegMap::isRef)) {
756 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
757 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
758 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000759 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000760 // this as a potentially dead store in case there is a subsequent
761 // store into the stack slot without a read from it.
762 MaybeDeadStores[StackSlot] = &MI;
763
Chris Lattnercd816392006-02-02 23:29:36 +0000764 // If the stack slot value was previously available in some other
765 // register, change it now. Otherwise, make the register available,
766 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000767 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000768 }
769 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000770 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000771 }
772
Chris Lattner7fb64342004-10-01 19:04:51 +0000773 // Process all of the spilled defs.
774 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
775 MachineOperand &MO = MI.getOperand(i);
776 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
777 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000778
Chris Lattner7fb64342004-10-01 19:04:51 +0000779 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
780 // Check to see if this is a def-and-use vreg operand that we do need
781 // to insert a store for.
782 bool OpTakenCareOf = false;
783 if (MO.isUse() && !DefAndUseVReg.empty()) {
784 for (unsigned dau = 0, e = DefAndUseVReg.size(); dau != e; ++dau)
785 if (DefAndUseVReg[dau].first == i) {
786 VirtReg = DefAndUseVReg[dau].second;
787 OpTakenCareOf = true;
788 break;
789 }
790 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000791
Chris Lattner7fb64342004-10-01 19:04:51 +0000792 if (!OpTakenCareOf) {
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000793 // Check to see if this is a noop copy. If so, eliminate the
794 // instruction before considering the dest reg to be changed.
Chris Lattner109afed2006-02-03 03:16:14 +0000795 unsigned Src, Dst;
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000796 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
797 ++NumDCE;
798 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
799 MBB.erase(&MI);
800 VRM.RemoveFromFoldedVirtMap(&MI);
801 goto ProcessNextInst;
Chris Lattner109afed2006-02-03 03:16:14 +0000802 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000803 Spills.ClobberPhysReg(VirtReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000804 continue;
Chris Lattner7fb64342004-10-01 19:04:51 +0000805 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000806 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000807
Chris Lattner84e752a2006-02-03 03:06:49 +0000808 // The only vregs left are stack slot definitions.
809 int StackSlot = VRM.getStackSlot(VirtReg);
810 const TargetRegisterClass *RC =
811 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
812 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000813
Chris Lattner84e752a2006-02-03 03:06:49 +0000814 // If this is a def&use operand, and we used a different physreg for
815 // it than the one assigned, make sure to execute the store from the
816 // correct physical register.
817 if (MO.getReg() == VirtReg)
818 PhysReg = VRM.getPhys(VirtReg);
819 else
820 PhysReg = MO.getReg();
Chris Lattner7fb64342004-10-01 19:04:51 +0000821
Chris Lattner84e752a2006-02-03 03:06:49 +0000822 PhysRegsUsed[PhysReg] = true;
823 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
824 DEBUG(std::cerr << "Store:\t" << *next(MII));
Chris Lattnere53f4a02006-05-04 17:52:23 +0000825 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000826
Chris Lattner109afed2006-02-03 03:16:14 +0000827 // Check to see if this is a noop copy. If so, eliminate the
828 // instruction before considering the dest reg to be changed.
829 {
830 unsigned Src, Dst;
831 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
832 ++NumDCE;
833 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
834 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000835 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000836 goto ProcessNextInst;
837 }
838 }
839
Chris Lattner84e752a2006-02-03 03:06:49 +0000840 // If there is a dead store to this stack slot, nuke it now.
841 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
842 if (LastStore) {
Chris Lattner35f27052006-05-01 21:16:03 +0000843 DEBUG(std::cerr << "Removed dead store:\t" << *LastStore);
Chris Lattner84e752a2006-02-03 03:06:49 +0000844 ++NumDSE;
845 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000846 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000847 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000848 LastStore = next(MII);
849
850 // If the stack slot value was previously available in some other
851 // register, change it now. Otherwise, make the register available,
852 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000853 Spills.ModifyStackSlot(StackSlot);
854 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000855 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000856 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000857 }
858 }
Chris Lattnercea86882005-09-19 06:56:21 +0000859 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000860 MII = NextMII;
861 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000862}
863
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000864
865
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000866llvm::Spiller* llvm::createSpiller() {
867 switch (SpillerOpt) {
868 default: assert(0 && "Unreachable!");
869 case local:
870 return new LocalSpiller();
871 case simple:
872 return new SimpleSpiller();
873 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000874}