Blame - lib/CodeGen/SelectionDAG/TargetLowering.cpp - fp2-dev/platform/external/llvm

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Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	1	//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	2	//
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	3	// The LLVM Compiler Infrastructure
				4	//
Chris Lattner	4ee451d	2007-12-29 20:36:04 +0000	[diff] [blame]	5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	7	//
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	8	//===----------------------------------------------------------------------===//
				9	//
				10	// This implements the TargetLowering class.
				11	//
				12	//===----------------------------------------------------------------------===//
				13
				14	#include "llvm/Target/TargetLowering.h"
Chris Lattner	af76e59	2009-08-22 20:48:53 +0000	[diff] [blame]	15	#include "llvm/MC/MCAsmInfo.h"
Chris Lattner	beeb93e	2010-01-26 05:58:28 +0000	[diff] [blame]	16	#include "llvm/MC/MCExpr.h"
Owen Anderson	07000c6	2006-05-12 06:33:49 +0000	[diff] [blame]	17	#include "llvm/Target/TargetData.h"
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	18	#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	19	#include "llvm/Target/TargetMachine.h"
Dan Gohman	6f0d024	2008-02-10 18:45:23 +0000	[diff] [blame]	20	#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman	707e018	2008-04-12 04:36:06 +0000	[diff] [blame]	21	#include "llvm/GlobalVariable.h"
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	22	#include "llvm/DerivedTypes.h"
Dan Gohman	84023e0	2010-07-10 09:00:22 +0000	[diff] [blame]	23	#include "llvm/CodeGen/Analysis.h"
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	24	#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	25	#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	26	#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	27	#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson	718cb66	2007-09-07 04:06:50 +0000	[diff] [blame]	28	#include "llvm/ADT/STLExtras.h"
Torok Edwin	c25e758	2009-07-11 20:10:48 +0000	[diff] [blame]	29	#include "llvm/Support/ErrorHandling.h"
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	30	#include "llvm/Support/MathExtras.h"
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	31	using namespace llvm;
				32
Rafael Espindola	9a58023	2009-02-27 13:37:18 +0000	[diff] [blame]	33	namespace llvm {
				34	TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
				35	bool isLocal = GV->hasLocalLinkage();
				36	bool isDeclaration = GV->isDeclaration();
				37	// FIXME: what should we do for protected and internal visibility?
				38	// For variables, is internal different from hidden?
				39	bool isHidden = GV->hasHiddenVisibility();
				40
				41	if (reloc == Reloc::PIC_) {
				42	if (isLocal \|\| isHidden)
				43	return TLSModel::LocalDynamic;
				44	else
				45	return TLSModel::GeneralDynamic;
				46	} else {
				47	if (!isDeclaration \|\| isHidden)
				48	return TLSModel::LocalExec;
				49	else
				50	return TLSModel::InitialExec;
				51	}
				52	}
				53	}
				54
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	55	/// InitLibcallNames - Set default libcall names.
				56	///
Evan Cheng	79cca50	2007-01-12 22:51:10 +0000	[diff] [blame]	57	static void InitLibcallNames(const char **Names) {
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	58	Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	59	Names[RTLIB::SHL_I32] = "__ashlsi3";
				60	Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	61	Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	62	Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	63	Names[RTLIB::SRL_I32] = "__lshrsi3";
				64	Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	65	Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	66	Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	67	Names[RTLIB::SRA_I32] = "__ashrsi3";
				68	Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sands	dddc629	2008-07-11 16:52:29 +0000	[diff] [blame]	69	Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	70	Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikov	c31642f	2009-05-03 13:14:08 +0000	[diff] [blame]	71	Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	72	Names[RTLIB::MUL_I32] = "__mulsi3";
				73	Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	74	Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	75	Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov	813090c	2009-05-03 13:18:16 +0000	[diff] [blame]	76	Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	77	Names[RTLIB::SDIV_I32] = "__divsi3";
				78	Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	79	Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	80	Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikov	fb3f84f	2009-05-08 18:50:54 +0000	[diff] [blame]	81	Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	82	Names[RTLIB::UDIV_I32] = "__udivsi3";
				83	Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	84	Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	85	Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov	813090c	2009-05-03 13:18:16 +0000	[diff] [blame]	86	Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	87	Names[RTLIB::SREM_I32] = "__modsi3";
				88	Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	89	Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov	8983da7	2009-11-07 17:14:39 +0000	[diff] [blame]	90	Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov	9fe9c8e	2009-05-03 13:19:57 +0000	[diff] [blame]	91	Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	92	Names[RTLIB::UREM_I32] = "__umodsi3";
				93	Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands	5ac319a	2008-07-10 15:35:05 +0000	[diff] [blame]	94	Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	95	Names[RTLIB::NEG_I32] = "__negsi2";
				96	Names[RTLIB::NEG_I64] = "__negdi2";
				97	Names[RTLIB::ADD_F32] = "__addsf3";
				98	Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	99	Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	100	Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	101	Names[RTLIB::SUB_F32] = "__subsf3";
				102	Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	103	Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	104	Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	105	Names[RTLIB::MUL_F32] = "__mulsf3";
				106	Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	107	Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	108	Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	109	Names[RTLIB::DIV_F32] = "__divsf3";
				110	Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	111	Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	112	Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	113	Names[RTLIB::REM_F32] = "fmodf";
				114	Names[RTLIB::REM_F64] = "fmod";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	115	Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	116	Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	117	Names[RTLIB::POWI_F32] = "__powisf2";
				118	Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	119	Names[RTLIB::POWI_F80] = "__powixf2";
				120	Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	121	Names[RTLIB::SQRT_F32] = "sqrtf";
				122	Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	123	Names[RTLIB::SQRT_F80] = "sqrtl";
				124	Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen	7794f2a	2008-09-04 00:47:13 +0000	[diff] [blame]	125	Names[RTLIB::LOG_F32] = "logf";
				126	Names[RTLIB::LOG_F64] = "log";
				127	Names[RTLIB::LOG_F80] = "logl";
				128	Names[RTLIB::LOG_PPCF128] = "logl";
				129	Names[RTLIB::LOG2_F32] = "log2f";
				130	Names[RTLIB::LOG2_F64] = "log2";
				131	Names[RTLIB::LOG2_F80] = "log2l";
				132	Names[RTLIB::LOG2_PPCF128] = "log2l";
				133	Names[RTLIB::LOG10_F32] = "log10f";
				134	Names[RTLIB::LOG10_F64] = "log10";
				135	Names[RTLIB::LOG10_F80] = "log10l";
				136	Names[RTLIB::LOG10_PPCF128] = "log10l";
				137	Names[RTLIB::EXP_F32] = "expf";
				138	Names[RTLIB::EXP_F64] = "exp";
				139	Names[RTLIB::EXP_F80] = "expl";
				140	Names[RTLIB::EXP_PPCF128] = "expl";
				141	Names[RTLIB::EXP2_F32] = "exp2f";
				142	Names[RTLIB::EXP2_F64] = "exp2";
				143	Names[RTLIB::EXP2_F80] = "exp2l";
				144	Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	145	Names[RTLIB::SIN_F32] = "sinf";
				146	Names[RTLIB::SIN_F64] = "sin";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	147	Names[RTLIB::SIN_F80] = "sinl";
				148	Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	149	Names[RTLIB::COS_F32] = "cosf";
				150	Names[RTLIB::COS_F64] = "cos";
Duncan Sands	007f984	2008-01-10 10:28:30 +0000	[diff] [blame]	151	Names[RTLIB::COS_F80] = "cosl";
				152	Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohman	e54be10	2007-10-11 23:09:10 +0000	[diff] [blame]	153	Names[RTLIB::POW_F32] = "powf";
				154	Names[RTLIB::POW_F64] = "pow";
				155	Names[RTLIB::POW_F80] = "powl";
				156	Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman	2bb1e3e	2008-08-21 18:38:14 +0000	[diff] [blame]	157	Names[RTLIB::CEIL_F32] = "ceilf";
				158	Names[RTLIB::CEIL_F64] = "ceil";
				159	Names[RTLIB::CEIL_F80] = "ceill";
				160	Names[RTLIB::CEIL_PPCF128] = "ceill";
				161	Names[RTLIB::TRUNC_F32] = "truncf";
				162	Names[RTLIB::TRUNC_F64] = "trunc";
				163	Names[RTLIB::TRUNC_F80] = "truncl";
				164	Names[RTLIB::TRUNC_PPCF128] = "truncl";
				165	Names[RTLIB::RINT_F32] = "rintf";
				166	Names[RTLIB::RINT_F64] = "rint";
				167	Names[RTLIB::RINT_F80] = "rintl";
				168	Names[RTLIB::RINT_PPCF128] = "rintl";
				169	Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
				170	Names[RTLIB::NEARBYINT_F64] = "nearbyint";
				171	Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
				172	Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
				173	Names[RTLIB::FLOOR_F32] = "floorf";
				174	Names[RTLIB::FLOOR_F64] = "floor";
				175	Names[RTLIB::FLOOR_F80] = "floorl";
				176	Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sands	d2c817e	2010-03-14 21:08:40 +0000	[diff] [blame]	177	Names[RTLIB::COPYSIGN_F32] = "copysignf";
				178	Names[RTLIB::COPYSIGN_F64] = "copysign";
				179	Names[RTLIB::COPYSIGN_F80] = "copysignl";
				180	Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	181	Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	182	Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
				183	Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	184	Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	185	Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
				186	Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
				187	Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
				188	Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	189	Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
				190	Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	191	Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
				192	Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	193	Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	194	Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
				195	Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	196	Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
				197	Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	198	Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sands	be1ad4d	2008-07-10 15:33:02 +0000	[diff] [blame]	199	Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	200	Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	201	Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands	041cde2	2008-06-25 20:24:48 +0000	[diff] [blame]	202	Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	203	Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	204	Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	205	Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
				206	Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	207	Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
				208	Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	209	Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	210	Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
				211	Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	212	Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
				213	Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	214	Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	215	Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
				216	Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	217	Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands	041cde2	2008-06-25 20:24:48 +0000	[diff] [blame]	218	Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	219	Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohman	a2e9485	2008-03-10 23:03:31 +0000	[diff] [blame]	220	Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	221	Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
				222	Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands	9bed0f5	2008-07-11 16:57:02 +0000	[diff] [blame]	223	Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
				224	Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	225	Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
				226	Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	227	Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
				228	Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohman	d91446d	2008-03-05 01:08:17 +0000	[diff] [blame]	229	Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
				230	Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
				231	Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
				232	Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	233	Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
				234	Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sands	ac6cece	2008-07-11 17:00:14 +0000	[diff] [blame]	235	Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
				236	Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	237	Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
				238	Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sands	ac6cece	2008-07-11 17:00:14 +0000	[diff] [blame]	239	Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
				240	Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
				241	Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
				242	Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
				243	Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
				244	Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	245	Names[RTLIB::OEQ_F32] = "__eqsf2";
				246	Names[RTLIB::OEQ_F64] = "__eqdf2";
				247	Names[RTLIB::UNE_F32] = "__nesf2";
				248	Names[RTLIB::UNE_F64] = "__nedf2";
				249	Names[RTLIB::OGE_F32] = "__gesf2";
				250	Names[RTLIB::OGE_F64] = "__gedf2";
				251	Names[RTLIB::OLT_F32] = "__ltsf2";
				252	Names[RTLIB::OLT_F64] = "__ltdf2";
				253	Names[RTLIB::OLE_F32] = "__lesf2";
				254	Names[RTLIB::OLE_F64] = "__ledf2";
				255	Names[RTLIB::OGT_F32] = "__gtsf2";
				256	Names[RTLIB::OGT_F64] = "__gtdf2";
				257	Names[RTLIB::UO_F32] = "__unordsf2";
				258	Names[RTLIB::UO_F64] = "__unorddf2";
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	259	Names[RTLIB::O_F32] = "__unordsf2";
				260	Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Gupta	a114baa	2009-07-30 09:12:56 +0000	[diff] [blame]	261	Names[RTLIB::MEMCPY] = "memcpy";
				262	Names[RTLIB::MEMMOVE] = "memmove";
				263	Names[RTLIB::MEMSET] = "memset";
Duncan Sands	b0f1e17	2009-05-22 20:36:31 +0000	[diff] [blame]	264	Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbach	e03262f	2010-06-18 21:43:38 +0000	[diff] [blame]	265	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
				266	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
				267	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
				268	Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbach	ef6eb9c	2010-06-18 23:03:10 +0000	[diff] [blame]	269	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
				270	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
				271	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
				272	Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbach	e03262f	2010-06-18 21:43:38 +0000	[diff] [blame]	273	Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
				274	Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
				275	Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
				276	Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
				277	Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
				278	Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
				279	Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
				280	Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
				281	Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
				282	Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
				283	Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
				284	Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
				285	Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
				286	Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
				287	Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
				288	Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
				289	Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
				290	Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
				291	Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
				292	Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
				293	Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
				294	Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
				295	Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
				296	Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	297	}
				298
Anton Korobeynikov	72977a4	2009-08-14 20:10:52 +0000	[diff] [blame]	299	/// InitLibcallCallingConvs - Set default libcall CallingConvs.
				300	///
				301	static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
				302	for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
				303	CCs[i] = CallingConv::C;
				304	}
				305	}
				306
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	307	/// getFPEXT - Return the FPEXT__ value for the given types, or
				308	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	309	RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	310	if (OpVT == MVT::f32) {
				311	if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	312	return FPEXT_F32_F64;
				313	}
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	314
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	315	return UNKNOWN_LIBCALL;
				316	}
				317
				318	/// getFPROUND - Return the FPROUND__ value for the given types, or
				319	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	320	RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	321	if (RetVT == MVT::f32) {
				322	if (OpVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	323	return FPROUND_F64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	324	if (OpVT == MVT::f80)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	325	return FPROUND_F80_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	326	if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	327	return FPROUND_PPCF128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	328	} else if (RetVT == MVT::f64) {
				329	if (OpVT == MVT::f80)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	330	return FPROUND_F80_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	331	if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopes	e36bfe6	2008-08-07 19:01:24 +0000	[diff] [blame]	332	return FPROUND_PPCF128_F64;
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	333	}
Anton Korobeynikov	927411b	2010-03-14 18:42:24 +0000	[diff] [blame]	334
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	335	return UNKNOWN_LIBCALL;
				336	}
				337
				338	/// getFPTOSINT - Return the FPTOSINT__ value for the given types, or
				339	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	340	RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	341	if (OpVT == MVT::f32) {
				342	if (RetVT == MVT::i8)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	343	return FPTOSINT_F32_I8;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	344	if (RetVT == MVT::i16)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	345	return FPTOSINT_F32_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	346	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	347	return FPTOSINT_F32_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	348	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	349	return FPTOSINT_F32_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	350	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	351	return FPTOSINT_F32_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	352	} else if (OpVT == MVT::f64) {
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	353	if (RetVT == MVT::i8)
				354	return FPTOSINT_F64_I8;
				355	if (RetVT == MVT::i16)
				356	return FPTOSINT_F64_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	357	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	358	return FPTOSINT_F64_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	359	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	360	return FPTOSINT_F64_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	361	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	362	return FPTOSINT_F64_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	363	} else if (OpVT == MVT::f80) {
				364	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	365	return FPTOSINT_F80_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	366	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	367	return FPTOSINT_F80_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	368	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	369	return FPTOSINT_F80_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	370	} else if (OpVT == MVT::ppcf128) {
				371	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	372	return FPTOSINT_PPCF128_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	373	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	374	return FPTOSINT_PPCF128_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	375	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	376	return FPTOSINT_PPCF128_I128;
				377	}
				378	return UNKNOWN_LIBCALL;
				379	}
				380
				381	/// getFPTOUINT - Return the FPTOUINT__ value for the given types, or
				382	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	383	RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	384	if (OpVT == MVT::f32) {
				385	if (RetVT == MVT::i8)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	386	return FPTOUINT_F32_I8;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	387	if (RetVT == MVT::i16)
Sanjiv Gupta	8aa207e	2009-06-16 09:03:58 +0000	[diff] [blame]	388	return FPTOUINT_F32_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	389	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	390	return FPTOUINT_F32_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	391	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	392	return FPTOUINT_F32_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	393	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	394	return FPTOUINT_F32_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	395	} else if (OpVT == MVT::f64) {
Anton Korobeynikov	de0118c	2010-03-26 21:32:14 +0000	[diff] [blame]	396	if (RetVT == MVT::i8)
				397	return FPTOUINT_F64_I8;
				398	if (RetVT == MVT::i16)
				399	return FPTOUINT_F64_I16;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	400	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	401	return FPTOUINT_F64_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	402	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	403	return FPTOUINT_F64_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	404	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	405	return FPTOUINT_F64_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	406	} else if (OpVT == MVT::f80) {
				407	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	408	return FPTOUINT_F80_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	409	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	410	return FPTOUINT_F80_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	411	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	412	return FPTOUINT_F80_I128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	413	} else if (OpVT == MVT::ppcf128) {
				414	if (RetVT == MVT::i32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	415	return FPTOUINT_PPCF128_I32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	416	if (RetVT == MVT::i64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	417	return FPTOUINT_PPCF128_I64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	418	if (RetVT == MVT::i128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	419	return FPTOUINT_PPCF128_I128;
				420	}
				421	return UNKNOWN_LIBCALL;
				422	}
				423
				424	/// getSINTTOFP - Return the SINTTOFP__ value for the given types, or
				425	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	426	RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	427	if (OpVT == MVT::i32) {
				428	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	429	return SINTTOFP_I32_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	430	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	431	return SINTTOFP_I32_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	432	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	433	return SINTTOFP_I32_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	434	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	435	return SINTTOFP_I32_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	436	} else if (OpVT == MVT::i64) {
				437	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	438	return SINTTOFP_I64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	439	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	440	return SINTTOFP_I64_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	441	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	442	return SINTTOFP_I64_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	443	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	444	return SINTTOFP_I64_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	445	} else if (OpVT == MVT::i128) {
				446	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	447	return SINTTOFP_I128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	448	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	449	return SINTTOFP_I128_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	450	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	451	return SINTTOFP_I128_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	452	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	453	return SINTTOFP_I128_PPCF128;
				454	}
				455	return UNKNOWN_LIBCALL;
				456	}
				457
				458	/// getUINTTOFP - Return the UINTTOFP__ value for the given types, or
				459	/// UNKNOWN_LIBCALL if there is none.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	460	RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	461	if (OpVT == MVT::i32) {
				462	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	463	return UINTTOFP_I32_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	464	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	465	return UINTTOFP_I32_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	466	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	467	return UINTTOFP_I32_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	468	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	469	return UINTTOFP_I32_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	470	} else if (OpVT == MVT::i64) {
				471	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	472	return UINTTOFP_I64_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	473	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	474	return UINTTOFP_I64_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	475	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	476	return UINTTOFP_I64_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	477	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	478	return UINTTOFP_I64_PPCF128;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	479	} else if (OpVT == MVT::i128) {
				480	if (RetVT == MVT::f32)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	481	return UINTTOFP_I128_F32;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	482	else if (RetVT == MVT::f64)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	483	return UINTTOFP_I128_F64;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	484	else if (RetVT == MVT::f80)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	485	return UINTTOFP_I128_F80;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	486	else if (RetVT == MVT::ppcf128)
Duncan Sands	b2ff885	2008-07-17 02:36:29 +0000	[diff] [blame]	487	return UINTTOFP_I128_PPCF128;
				488	}
				489	return UNKNOWN_LIBCALL;
				490	}
				491
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	492	/// InitCmpLibcallCCs - Set default comparison libcall CC.
				493	///
				494	static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
				495	memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
				496	CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
				497	CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
				498	CCs[RTLIB::UNE_F32] = ISD::SETNE;
				499	CCs[RTLIB::UNE_F64] = ISD::SETNE;
				500	CCs[RTLIB::OGE_F32] = ISD::SETGE;
				501	CCs[RTLIB::OGE_F64] = ISD::SETGE;
				502	CCs[RTLIB::OLT_F32] = ISD::SETLT;
				503	CCs[RTLIB::OLT_F64] = ISD::SETLT;
				504	CCs[RTLIB::OLE_F32] = ISD::SETLE;
				505	CCs[RTLIB::OLE_F64] = ISD::SETLE;
				506	CCs[RTLIB::OGT_F32] = ISD::SETGT;
				507	CCs[RTLIB::OGT_F64] = ISD::SETGT;
				508	CCs[RTLIB::UO_F32] = ISD::SETNE;
				509	CCs[RTLIB::UO_F64] = ISD::SETNE;
				510	CCs[RTLIB::O_F32] = ISD::SETEQ;
				511	CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	512	}
				513
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	514	/// NOTE: The constructor takes ownership of TLOF.
Dan Gohman	f0757b0	2010-04-21 01:34:56 +0000	[diff] [blame]	515	TargetLowering::TargetLowering(const TargetMachine &tm,
				516	const TargetLoweringObjectFile *tlof)
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	517	: TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	518	// All operations default to being supported.
				519	memset(OpActions, 0, sizeof(OpActions));
Evan Cheng	0329466	2008-10-14 21:26:46 +0000	[diff] [blame]	520	memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattner	ddf8956	2008-01-17 19:59:44 +0000	[diff] [blame]	521	memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattner	c9133f9	2008-01-18 19:36:20 +0000	[diff] [blame]	522	memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng	7f04268	2008-10-15 02:05:31 +0000	[diff] [blame]	523	memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman	93f81e2	2007-07-09 20:49:44 +0000	[diff] [blame]	524
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	525	// Set default actions for various operations.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	526	for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	527	// Default all indexed load / store to expand.
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	528	for (unsigned IM = (unsigned)ISD::PRE_INC;
				529	IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	530	setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
				531	setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	532	}
Chris Lattner	1a3048b	2007-12-22 20:47:56 +0000	[diff] [blame]	533
				534	// These operations default to expand.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	535	setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
				536	setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng	5ff839f	2006-11-09 18:56:43 +0000	[diff] [blame]	537	}
Evan Cheng	d2cde68	2008-03-10 19:38:10 +0000	[diff] [blame]	538
				539	// Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	540	setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begeman	e179584	2008-02-14 08:57:00 +0000	[diff] [blame]	541
				542	// ConstantFP nodes default to expand. Targets can either change this to
Evan Cheng	eb2f969	2009-10-27 19:56:55 +0000	[diff] [blame]	543	// Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begeman	e179584	2008-02-14 08:57:00 +0000	[diff] [blame]	544	// to optimize expansions for certain constants.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	545	setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
				546	setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
				547	setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	548
Dale Johannesen	0bb4160	2008-09-22 21:57:32 +0000	[diff] [blame]	549	// These library functions default to expand.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	550	setOperationAction(ISD::FLOG , MVT::f64, Expand);
				551	setOperationAction(ISD::FLOG2, MVT::f64, Expand);
				552	setOperationAction(ISD::FLOG10,MVT::f64, Expand);
				553	setOperationAction(ISD::FEXP , MVT::f64, Expand);
				554	setOperationAction(ISD::FEXP2, MVT::f64, Expand);
				555	setOperationAction(ISD::FLOG , MVT::f32, Expand);
				556	setOperationAction(ISD::FLOG2, MVT::f32, Expand);
				557	setOperationAction(ISD::FLOG10,MVT::f32, Expand);
				558	setOperationAction(ISD::FEXP , MVT::f32, Expand);
				559	setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen	0bb4160	2008-09-22 21:57:32 +0000	[diff] [blame]	560
Chris Lattner	41bab0b	2008-01-15 21:58:08 +0000	[diff] [blame]	561	// Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	562	setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattner	41bab0b	2008-01-15 21:58:08 +0000	[diff] [blame]	563
Owen Anderson	a69571c	2006-05-03 01:29:57 +0000	[diff] [blame]	564	IsLittleEndian = TD->isLittleEndian();
Owen Anderson	1d0be15	2009-08-13 21:58:54 +0000	[diff] [blame]	565	ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	566	memset(RegClassForVT, 0,MVT::LAST_VALUETYPEsizeof(TargetRegisterClass));
Owen Anderson	718cb66	2007-09-07 04:06:50 +0000	[diff] [blame]	567	memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Cheng	a03a5dc	2006-02-14 08:38:30 +0000	[diff] [blame]	568	maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng	6ebf7bc	2009-05-13 21:42:09 +0000	[diff] [blame]	569	benefitFromCodePlacementOpt = false;
Anton Korobeynikov	d27a258	2006-12-10 23:12:42 +0000	[diff] [blame]	570	UseUnderscoreSetJmp = false;
				571	UseUnderscoreLongJmp = false;
Chris Lattner	6618039	2007-02-25 01:28:05 +0000	[diff] [blame]	572	SelectIsExpensive = false;
Nate Begeman	405e3ec	2005-10-21 00:02:42 +0000	[diff] [blame]	573	IntDivIsCheap = false;
				574	Pow2DivIsCheap = false;
Chris Lattner	ee4a765	2006-01-25 18:57:15 +0000	[diff] [blame]	575	StackPointerRegisterToSaveRestore = 0;
Jim Laskey	9bb3c93	2007-02-22 18:04:49 +0000	[diff] [blame]	576	ExceptionPointerRegister = 0;
				577	ExceptionSelectorRegister = 0;
Duncan Sands	0322808	2008-11-23 15:47:28 +0000	[diff] [blame]	578	BooleanContents = UndefinedBooleanContent;
Evan Cheng	211ffa1	2010-05-19 20:19:50 +0000	[diff] [blame]	579	SchedPreferenceInfo = Sched::Latency;
Chris Lattner	7acf5f3	2006-09-05 17:39:15 +0000	[diff] [blame]	580	JumpBufSize = 0;
Duraid Madina	0c9e0ff	2006-09-04 07:44:11 +0000	[diff] [blame]	581	JumpBufAlignment = 0;
Evan Cheng	fb8075d	2008-02-28 00:43:03 +0000	[diff] [blame]	582	PrefLoopAlignment = 0;
Rafael Espindola	cbeeae2	2010-07-11 04:01:49 +0000	[diff] [blame]	583	MinStackArgumentAlignment = 1;
Jim Grosbach	9a52649	2010-06-23 16:07:42 +0000	[diff] [blame]	584	ShouldFoldAtomicFences = false;
Evan Cheng	5696622	2007-01-12 02:11:51 +0000	[diff] [blame]	585
				586	InitLibcallNames(LibcallRoutineNames);
Evan Cheng	d385fd6	2007-01-31 09:29:11 +0000	[diff] [blame]	587	InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov	72977a4	2009-08-14 20:10:52 +0000	[diff] [blame]	588	InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	589	}
				590
Chris Lattner	f014412	2009-07-28 03:13:23 +0000	[diff] [blame]	591	TargetLowering::~TargetLowering() {
				592	delete &TLOF;
				593	}
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	594
Mon P Wang	f7ea6c3	2010-02-10 23:37:45 +0000	[diff] [blame]	595	/// canOpTrap - Returns true if the operation can trap for the value type.
				596	/// VT must be a legal type.
				597	bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
				598	assert(isTypeLegal(VT));
				599	switch (Op) {
				600	default:
				601	return false;
				602	case ISD::FDIV:
				603	case ISD::FREM:
				604	case ISD::SDIV:
				605	case ISD::UDIV:
				606	case ISD::SREM:
				607	case ISD::UREM:
				608	return true;
				609	}
				610	}
				611
				612
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	613	static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	614	unsigned &NumIntermediates,
				615	EVT &RegisterVT,
				616	TargetLowering *TLI) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	617	// Figure out the right, legal destination reg to copy into.
				618	unsigned NumElts = VT.getVectorNumElements();
				619	MVT EltTy = VT.getVectorElementType();
				620
				621	unsigned NumVectorRegs = 1;
				622
				623	// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
				624	// could break down into LHS/RHS like LegalizeDAG does.
				625	if (!isPowerOf2_32(NumElts)) {
				626	NumVectorRegs = NumElts;
				627	NumElts = 1;
				628	}
				629
				630	// Divide the input until we get to a supported size. This will always
				631	// end with a scalar if the target doesn't support vectors.
				632	while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
				633	NumElts >>= 1;
				634	NumVectorRegs <<= 1;
				635	}
				636
				637	NumIntermediates = NumVectorRegs;
				638
				639	MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
				640	if (!TLI->isTypeLegal(NewVT))
				641	NewVT = EltTy;
				642	IntermediateVT = NewVT;
				643
				644	EVT DestVT = TLI->getRegisterType(NewVT);
				645	RegisterVT = DestVT;
Chris Lattner	32b4b5a	2010-07-05 05:53:14 +0000	[diff] [blame]	646	if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	647	return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	648
Chris Lattner	32b4b5a	2010-07-05 05:53:14 +0000	[diff] [blame]	649	// Otherwise, promotion or legal types use the same number of registers as
				650	// the vector decimated to the appropriate level.
				651	return NumVectorRegs;
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	652	}
				653
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	654	/// isLegalRC - Return true if the value types that can be represented by the
				655	/// specified register class are all legal.
				656	bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
				657	for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
				658	I != E; ++I) {
				659	if (isTypeLegal(*I))
				660	return true;
				661	}
				662	return false;
				663	}
				664
				665	/// hasLegalSuperRegRegClasses - Return true if the specified register class
				666	/// has one or more super-reg register classes that are legal.
Evan Cheng	d70f57b	2010-07-19 22:15:08 +0000	[diff] [blame]	667	bool
				668	TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	669	if (*RC->superregclasses_begin() == 0)
				670	return false;
				671	for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
				672	E = RC->superregclasses_end(); I != E; ++I) {
				673	const TargetRegisterClass RRC = I;
				674	if (isLegalRC(RRC))
				675	return true;
				676	}
				677	return false;
				678	}
				679
				680	/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	681	/// of the register class for the specified type and its associated "cost".
				682	std::pair<const TargetRegisterClass*, uint8_t>
				683	TargetLowering::findRepresentativeClass(EVT VT) const {
				684	const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
				685	if (!RC)
				686	return std::make_pair(RC, 0);
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	687	const TargetRegisterClass *BestRC = RC;
				688	for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
				689	E = RC->superregclasses_end(); I != E; ++I) {
				690	const TargetRegisterClass RRC = I;
				691	if (RRC->isASubClass() \|\| !isLegalRC(RRC))
				692	continue;
				693	if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	694	return std::make_pair(RRC, 1);
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	695	BestRC = RRC;
				696	}
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	697	return std::make_pair(BestRC, 1);
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	698	}
				699
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	700	/// computeRegisterProperties - Once all of the register classes are added,
				701	/// this allows us to compute derived properties we expose.
				702	void TargetLowering::computeRegisterProperties() {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	703	assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattner	bb97d81	2005-01-16 01:10:58 +0000	[diff] [blame]	704	"Too many value types for ValueTypeActions to hold!");
				705
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	706	// Everything defaults to needing one register.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	707	for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohman	b9f1019	2007-06-21 14:42:22 +0000	[diff] [blame]	708	NumRegistersForVT[i] = 1;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	709	RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	710	}
				711	// ...except isVoid, which doesn't need any registers.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	712	NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukman	f976c85	2005-04-21 22:55:34 +0000	[diff] [blame]	713
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	714	// Find the largest integer register class.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	715	unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	716	for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	717	assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner	310968c	2005-01-07 07:44:53 +0000	[diff] [blame]	718
				719	// Every integer value type larger than this largest register takes twice as
				720	// many registers to represent as the previous ValueType.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	721	for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman	8a55ce4	2009-09-23 21:02:20 +0000	[diff] [blame]	722	EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
				723	if (!ExpandedVT.isInteger())
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	724	break;
Dan Gohman	b9f1019	2007-06-21 14:42:22 +0000	[diff] [blame]	725	NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	726	RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
				727	TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman	8a55ce4	2009-09-23 21:02:20 +0000	[diff] [blame]	728	ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng	1a8f1fe	2006-12-09 02:42:38 +0000	[diff] [blame]	729	}
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	730
				731	// Inspect all of the ValueType's smaller than the largest integer
				732	// register to see which ones need promotion.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	733	unsigned LegalIntReg = LargestIntReg;
				734	for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	735	IntReg >= (unsigned)MVT::i1; --IntReg) {
				736	EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	737	if (isTypeLegal(IVT)) {
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	738	LegalIntReg = IntReg;
				739	} else {
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	740	RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	741	(MVT::SimpleValueType)LegalIntReg;
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	742	ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	743	}
				744	}
				745
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	746	// ppcf128 type is really two f64's.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	747	if (!isTypeLegal(MVT::ppcf128)) {
				748	NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
				749	RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
				750	TransformToType[MVT::ppcf128] = MVT::f64;
				751	ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesen	161e897	2007-10-05 20:04:43 +0000	[diff] [blame]	752	}
				753
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	754	// Decide how to handle f64. If the target does not have native f64 support,
				755	// expand it to i64 and we will be generating soft float library calls.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	756	if (!isTypeLegal(MVT::f64)) {
				757	NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
				758	RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
				759	TransformToType[MVT::f64] = MVT::i64;
				760	ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	761	}
				762
				763	// Decide how to handle f32. If the target does not have native support for
				764	// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	765	if (!isTypeLegal(MVT::f32)) {
				766	if (isTypeLegal(MVT::f64)) {
				767	NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
				768	RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
				769	TransformToType[MVT::f32] = MVT::f64;
				770	ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	771	} else {
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	772	NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
				773	RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
				774	TransformToType[MVT::f32] = MVT::i32;
				775	ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	776	}
Evan Cheng	1a8f1fe	2006-12-09 02:42:38 +0000	[diff] [blame]	777	}
Nate Begeman	4ef3b81	2005-11-22 01:29:36 +0000	[diff] [blame]	778
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	779	// Loop over all of the vector value types to see which need transformations.
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	780	for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
				781	i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	782	MVT VT = (MVT::SimpleValueType)i;
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	783	if (isTypeLegal(VT)) continue;
				784
				785	MVT IntermediateVT;
				786	EVT RegisterVT;
				787	unsigned NumIntermediates;
				788	NumRegistersForVT[i] =
				789	getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
				790	RegisterVT, this);
				791	RegisterTypeForVT[i] = RegisterVT;
				792
				793	// Determine if there is a legal wider type.
				794	bool IsLegalWiderType = false;
				795	EVT EltVT = VT.getVectorElementType();
				796	unsigned NElts = VT.getVectorNumElements();
				797	for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
				798	EVT SVT = (MVT::SimpleValueType)nVT;
				799	if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT &&
				800	SVT.getVectorNumElements() > NElts && NElts != 1) {
				801	TransformToType[i] = SVT;
				802	ValueTypeActions.setTypeAction(VT, Promote);
				803	IsLegalWiderType = true;
				804	break;
Mon P Wang	87c8a8f	2008-12-18 20:03:17 +0000	[diff] [blame]	805	}
Chris Lattner	598751e	2010-07-05 05:36:21 +0000	[diff] [blame]	806	}
				807	if (!IsLegalWiderType) {
				808	EVT NVT = VT.getPow2VectorType();
				809	if (NVT == VT) {
				810	// Type is already a power of 2. The default action is to split.
				811	TransformToType[i] = MVT::Other;
				812	ValueTypeActions.setTypeAction(VT, Expand);
				813	} else {
				814	TransformToType[i] = NVT;
				815	ValueTypeActions.setTypeAction(VT, Promote);
Mon P Wang	87c8a8f	2008-12-18 20:03:17 +0000	[diff] [blame]	816	}
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	817	}
Chris Lattner	3a593584	2006-03-16 19:50:01 +0000	[diff] [blame]	818	}
Evan Cheng	46dcb57	2010-07-19 18:47:01 +0000	[diff] [blame]	819
				820	// Determine the 'representative' register class for each value type.
				821	// An representative register class is the largest (meaning one which is
				822	// not a sub-register class / subreg register class) legal register class for
				823	// a group of value types. For example, on i386, i8, i16, and i32
				824	// representative would be GR32; while on x86_64 it's GR64.
Evan Cheng	d70f57b	2010-07-19 22:15:08 +0000	[diff] [blame]	825	for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng	4f6b467	2010-07-21 06:09:07 +0000	[diff] [blame]	826	const TargetRegisterClass* RRC;
				827	uint8_t Cost;
				828	tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
				829	RepRegClassForVT[i] = RRC;
				830	RepRegClassCostForVT[i] = Cost;
Evan Cheng	d70f57b	2010-07-19 22:15:08 +0000	[diff] [blame]	831	}
Chris Lattner	bb97d81	2005-01-16 01:10:58 +0000	[diff] [blame]	832	}
Chris Lattner	cba82f9	2005-01-16 07:28:11 +0000	[diff] [blame]	833
Evan Cheng	7226158	2005-12-20 06:22:03 +0000	[diff] [blame]	834	const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
				835	return NULL;
				836	}
Evan Cheng	3a03ebb	2005-12-21 23:05:39 +0000	[diff] [blame]	837
Scott Michel	5b8f82e	2008-03-10 15:42:14 +0000	[diff] [blame]	838
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	839	MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson	1d0be15	2009-08-13 21:58:54 +0000	[diff] [blame]	840	return PointerTy.SimpleTy;
Scott Michel	5b8f82e	2008-03-10 15:42:14 +0000	[diff] [blame]	841	}
				842
Sanjiv Gupta	8f17a36	2009-12-28 02:40:33 +0000	[diff] [blame]	843	MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
				844	return MVT::i32; // return the default value
				845	}
				846
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	847	/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	848	/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
				849	/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
				850	/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	851	///
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	852	/// This method returns the number of registers needed, and the VT for each
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	853	/// register. It also returns the VT and quantity of the intermediate values
				854	/// before they are promoted/expanded.
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	855	///
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	856	unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	857	EVT &IntermediateVT,
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	858	unsigned &NumIntermediates,
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	859	EVT &RegisterVT) const {
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	860	// Figure out the right, legal destination reg to copy into.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	861	unsigned NumElts = VT.getVectorNumElements();
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	862	EVT EltTy = VT.getVectorElementType();
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	863
				864	unsigned NumVectorRegs = 1;
				865
Nate Begeman	d73ab88	2007-11-27 19:28:48 +0000	[diff] [blame]	866	// FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
				867	// could break down into LHS/RHS like LegalizeDAG does.
				868	if (!isPowerOf2_32(NumElts)) {
				869	NumVectorRegs = NumElts;
				870	NumElts = 1;
				871	}
				872
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	873	// Divide the input until we get to a supported size. This will always
				874	// end with a scalar if the target doesn't support vectors.
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	875	while (NumElts > 1 && !isTypeLegal(
				876	EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	877	NumElts >>= 1;
				878	NumVectorRegs <<= 1;
				879	}
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	880
				881	NumIntermediates = NumVectorRegs;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	882
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	883	EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman	7f32156	2007-06-25 16:23:39 +0000	[diff] [blame]	884	if (!isTypeLegal(NewVT))
				885	NewVT = EltTy;
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	886	IntermediateVT = NewVT;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	887
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	888	EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohman	b6f5b00	2007-06-28 23:29:44 +0000	[diff] [blame]	889	RegisterVT = DestVT;
Duncan Sands	8e4eb09	2008-06-08 20:54:56 +0000	[diff] [blame]	890	if (DestVT.bitsLT(NewVT)) {
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	891	// Value is expanded, e.g. i64 -> i16.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	892	return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	893	} else {
				894	// Otherwise, promotion or legal types use the same number of registers as
				895	// the vector decimated to the appropriate level.
Chris Lattner	79227e2	2006-03-31 00:46:36 +0000	[diff] [blame]	896	return NumVectorRegs;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	897	}
				898
Evan Cheng	e9b3da1	2006-05-17 18:10:06 +0000	[diff] [blame]	899	return 1;
Chris Lattner	dc87929	2006-03-31 00:28:56 +0000	[diff] [blame]	900	}
				901
Dan Gohman	84023e0	2010-07-10 09:00:22 +0000	[diff] [blame]	902	/// Get the EVTs and ArgFlags collections that represent the legalized return
				903	/// type of the given function. This does not require a DAG or a return value,
				904	/// and is suitable for use before any DAGs for the function are constructed.
				905	/// TODO: Move this out of TargetLowering.cpp.
				906	void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
				907	SmallVectorImpl<ISD::OutputArg> &Outs,
				908	const TargetLowering &TLI,
				909	SmallVectorImpl<uint64_t> *Offsets) {
				910	SmallVector<EVT, 4> ValueVTs;
				911	ComputeValueVTs(TLI, ReturnType, ValueVTs);
				912	unsigned NumValues = ValueVTs.size();
				913	if (NumValues == 0) return;
				914	unsigned Offset = 0;
				915
				916	for (unsigned j = 0, f = NumValues; j != f; ++j) {
				917	EVT VT = ValueVTs[j];
				918	ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
				919
				920	if (attr & Attribute::SExt)
				921	ExtendKind = ISD::SIGN_EXTEND;
				922	else if (attr & Attribute::ZExt)
				923	ExtendKind = ISD::ZERO_EXTEND;
				924
				925	// FIXME: C calling convention requires the return type to be promoted to
				926	// at least 32-bit. But this is not necessary for non-C calling
				927	// conventions. The frontend should mark functions whose return values
				928	// require promoting with signext or zeroext attributes.
				929	if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
				930	EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
				931	if (VT.bitsLT(MinVT))
				932	VT = MinVT;
				933	}
				934
				935	unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
				936	EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
				937	unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
				938	PartVT.getTypeForEVT(ReturnType->getContext()));
				939
				940	// 'inreg' on function refers to return value
				941	ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
				942	if (attr & Attribute::InReg)
				943	Flags.setInReg();
				944
				945	// Propagate extension type if any
				946	if (attr & Attribute::SExt)
				947	Flags.setSExt();
				948	else if (attr & Attribute::ZExt)
				949	Flags.setZExt();
				950
				951	for (unsigned i = 0; i < NumParts; ++i) {
				952	Outs.push_back(ISD::OutputArg(Flags, PartVT, /isFixed=/true));
				953	if (Offsets) {
				954	Offsets->push_back(Offset);
				955	Offset += PartSize;
				956	}
				957	}
				958	}
				959	}
				960
Evan Cheng	3ae0543	2008-01-24 00:22:01 +0000	[diff] [blame]	961	/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen	28d08fd	2008-02-28 22:31:51 +0000	[diff] [blame]	962	/// function arguments in the caller parameter area. This is the actual
				963	/// alignment, not its logarithm.
Evan Cheng	3ae0543	2008-01-24 00:22:01 +0000	[diff] [blame]	964	unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen	28d08fd	2008-02-28 22:31:51 +0000	[diff] [blame]	965	return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng	3ae0543	2008-01-24 00:22:01 +0000	[diff] [blame]	966	}
				967
Chris Lattner	071c62f	2010-01-25 23:26:13 +0000	[diff] [blame]	968	/// getJumpTableEncoding - Return the entry encoding for a jump table in the
				969	/// current function. The returned value is a member of the
				970	/// MachineJumpTableInfo::JTEntryKind enum.
				971	unsigned TargetLowering::getJumpTableEncoding() const {
				972	// In non-pic modes, just use the address of a block.
				973	if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
				974	return MachineJumpTableInfo::EK_BlockAddress;
				975
				976	// In PIC mode, if the target supports a GPRel32 directive, use it.
				977	if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
				978	return MachineJumpTableInfo::EK_GPRel32BlockAddress;
				979
				980	// Otherwise, use a label difference.
				981	return MachineJumpTableInfo::EK_LabelDifference32;
				982	}
				983
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	984	SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
				985	SelectionDAG &DAG) const {
Chris Lattner	f1214cb	2010-01-26 06:53:37 +0000	[diff] [blame]	986	// If our PIC model is GP relative, use the global offset table as the base.
				987	if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesen	b300d2a	2009-02-07 00:55:49 +0000	[diff] [blame]	988	return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Cheng	cc41586	2007-11-09 01:32:10 +0000	[diff] [blame]	989	return Table;
				990	}
				991
Chris Lattner	13e97a2	2010-01-26 05:30:30 +0000	[diff] [blame]	992	/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
				993	/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
				994	/// MCExpr.
				995	const MCExpr *
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	996	TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
				997	unsigned JTI,MCContext &Ctx) const{
Chris Lattner	beeb93e	2010-01-26 05:58:28 +0000	[diff] [blame]	998	// The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner	589c6f6	2010-01-26 06:28:43 +0000	[diff] [blame]	999	return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner	13e97a2	2010-01-26 05:30:30 +0000	[diff] [blame]	1000	}
				1001
Dan Gohman	6520e20	2008-10-18 02:06:02 +0000	[diff] [blame]	1002	bool
				1003	TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
				1004	// Assume that everything is safe in static mode.
				1005	if (getTargetMachine().getRelocationModel() == Reloc::Static)
				1006	return true;
				1007
				1008	// In dynamic-no-pic mode, assume that known defined values are safe.
				1009	if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
				1010	GA &&
				1011	!GA->getGlobal()->isDeclaration() &&
Duncan Sands	667d4b8	2009-03-07 15:45:40 +0000	[diff] [blame]	1012	!GA->getGlobal()->isWeakForLinker())
Dan Gohman	6520e20	2008-10-18 02:06:02 +0000	[diff] [blame]	1013	return true;
				1014
				1015	// Otherwise assume nothing is safe.
				1016	return false;
				1017	}
				1018
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	1019	//===----------------------------------------------------------------------===//
				1020	// Optimization Methods
				1021	//===----------------------------------------------------------------------===//
				1022
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1023	/// ShrinkDemandedConstant - Check to see if the specified operand of the
				1024	/// specified instruction is a constant integer. If so, check to see if there
				1025	/// are any bits set in the constant that are not demanded. If so, shrink the
				1026	/// constant and return true.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1027	bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1028	const APInt &Demanded) {
Dale Johannesen	de06470	2009-02-06 21:50:26 +0000	[diff] [blame]	1029	DebugLoc dl = Op.getDebugLoc();
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1030
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1031	// FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1032	switch (Op.getOpcode()) {
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1033	default: break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1034	case ISD::XOR:
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1035	case ISD::AND:
				1036	case ISD::OR: {
				1037	ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
				1038	if (!C) return false;
				1039
				1040	if (Op.getOpcode() == ISD::XOR &&
				1041	(C->getAPIntValue() \| (~Demanded)).isAllOnesValue())
				1042	return false;
				1043
				1044	// if we can expand it to have all bits set, do it
				1045	if (C->getAPIntValue().intersects(~Demanded)) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1046	EVT VT = Op.getValueType();
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1047	SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
				1048	DAG.getConstant(Demanded &
				1049	C->getAPIntValue(),
				1050	VT));
				1051	return CombineTo(Op, New);
				1052	}
				1053
Nate Begeman	de99629	2006-02-03 22:24:05 +0000	[diff] [blame]	1054	break;
				1055	}
Bill Wendling	36ae6c1	2009-03-04 00:18:06 +0000	[diff] [blame]	1056	}
				1057
Nate Begeman	de99629	2006-02-03 22:24:05 +0000	[diff] [blame]	1058	return false;
				1059	}
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1060
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1061	/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
				1062	/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
				1063	/// cast, but it could be generalized for targets with other types of
				1064	/// implicit widening casts.
				1065	bool
				1066	TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
				1067	unsigned BitWidth,
				1068	const APInt &Demanded,
				1069	DebugLoc dl) {
				1070	assert(Op.getNumOperands() == 2 &&
				1071	"ShrinkDemandedOp only supports binary operators!");
				1072	assert(Op.getNode()->getNumValues() == 1 &&
				1073	"ShrinkDemandedOp only supports nodes with one result!");
				1074
				1075	// Don't do this if the node has another user, which may require the
				1076	// full value.
				1077	if (!Op.getNode()->hasOneUse())
				1078	return false;
				1079
				1080	// Search for the smallest integer type with free casts to and from
				1081	// Op's type. For expedience, just check power-of-2 integer types.
				1082	const TargetLowering &TLI = DAG.getTargetLoweringInfo();
				1083	unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
				1084	if (!isPowerOf2_32(SmallVTBits))
				1085	SmallVTBits = NextPowerOf2(SmallVTBits);
				1086	for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	1087	EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1088	if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
				1089	TLI.isZExtFree(SmallVT, Op.getValueType())) {
				1090	// We found a type with free casts.
				1091	SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
				1092	DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
				1093	Op.getNode()->getOperand(0)),
				1094	DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
				1095	Op.getNode()->getOperand(1)));
				1096	SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
				1097	return CombineTo(Op, Z);
				1098	}
				1099	}
				1100	return false;
				1101	}
				1102
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1103	/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
				1104	/// DemandedMask bits of the result of Op are ever used downstream. If we can
				1105	/// use this information to simplify Op, create a new simplified DAG node and
				1106	/// return true, returning the original and new nodes in Old and New. Otherwise,
				1107	/// analyze the expression and return a mask of KnownOne and KnownZero bits for
				1108	/// the expression (used to simplify the caller). The KnownZero/One bits may
				1109	/// only be accurate for those bits in the DemandedMask.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1110	bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1111	const APInt &DemandedMask,
				1112	APInt &KnownZero,
				1113	APInt &KnownOne,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1114	TargetLoweringOpt &TLO,
				1115	unsigned Depth) const {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1116	unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman	87862e7	2009-12-11 21:31:27 +0000	[diff] [blame]	1117	assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1118	"Mask size mismatches value type size!");
				1119	APInt NewMask = DemandedMask;
Dale Johannesen	6f38cb6	2009-02-07 19:59:05 +0000	[diff] [blame]	1120	DebugLoc dl = Op.getDebugLoc();
Chris Lattner	3fc5b01	2007-05-17 18:19:23 +0000	[diff] [blame]	1121
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1122	// Don't know anything.
				1123	KnownZero = KnownOne = APInt(BitWidth, 0);
				1124
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1125	// Other users may use these bits.
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	1126	if (!Op.getNode()->hasOneUse()) {
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1127	if (Depth != 0) {
				1128	// If not at the root, Just compute the KnownZero/KnownOne bits to
				1129	// simplify things downstream.
Dan Gohman	ea859be	2007-06-22 14:59:07 +0000	[diff] [blame]	1130	TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1131	return false;
				1132	}
				1133	// If this is the root being simplified, allow it to have multiple uses,
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1134	// just set the NewMask to all bits.
				1135	NewMask = APInt::getAllOnesValue(BitWidth);
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1136	} else if (DemandedMask == 0) {
				1137	// Not demanding any bits from Op.
				1138	if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesen	e8d7230	2009-02-06 23:05:02 +0000	[diff] [blame]	1139	return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1140	return false;
				1141	} else if (Depth == 6) { // Limit search depth.
				1142	return false;
				1143	}
				1144
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1145	APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1146	switch (Op.getOpcode()) {
				1147	case ISD::Constant:
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1148	// We know all of the bits for a constant!
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1149	KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
				1150	KnownZero = ~KnownOne & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1151	return false; // Don't fall through, will infinitely loop.
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1152	case ISD::AND:
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1153	// If the RHS is a constant, check to see if the LHS would be zero without
				1154	// using the bits from the RHS. Below, we use knowledge about the RHS to
				1155	// simplify the LHS, here we're using information from the LHS to simplify
				1156	// the RHS.
				1157	if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1158	APInt LHSZero, LHSOne;
				1159	TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohman	ea859be	2007-06-22 14:59:07 +0000	[diff] [blame]	1160	LHSZero, LHSOne, Depth+1);
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1161	// If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1162	if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1163	return TLO.CombineTo(Op, Op.getOperand(0));
				1164	// If any of the set bits in the RHS are known zero on the LHS, shrink
				1165	// the constant.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1166	if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner	81cd355	2006-02-27 00:36:27 +0000	[diff] [blame]	1167	return true;
				1168	}
				1169
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1170	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1171	KnownOne, TLO, Depth+1))
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1172	return true;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1173	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1174	if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1175	KnownZero2, KnownOne2, TLO, Depth+1))
				1176	return true;
				1177	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1178
				1179	// If all of the demanded bits are known one on one side, return the other.
				1180	// These bits cannot contribute to the result of the 'and'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1181	if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1182	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1183	if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1184	return TLO.CombineTo(Op, Op.getOperand(1));
				1185	// If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1186	if ((NewMask & (KnownZero\|KnownZero2)) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1187	return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
				1188	// If the RHS is a constant, see if we can simplify it.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1189	if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1190	return true;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1191	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1192	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1193	return true;
				1194
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1195	// Output known-1 bits are only known if set in both the LHS & RHS.
				1196	KnownOne &= KnownOne2;
				1197	// Output known-0 are known to be clear if zero in either the LHS \| RHS.
				1198	KnownZero \|= KnownZero2;
				1199	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1200	case ISD::OR:
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1201	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1202	KnownOne, TLO, Depth+1))
				1203	return true;
				1204	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1205	if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1206	KnownZero2, KnownOne2, TLO, Depth+1))
				1207	return true;
				1208	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1209
				1210	// If all of the demanded bits are known zero on one side, return the other.
				1211	// These bits cannot contribute to the result of the 'or'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1212	if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1213	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1214	if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1215	return TLO.CombineTo(Op, Op.getOperand(1));
				1216	// If all of the potentially set bits on one side are known to be set on
				1217	// the other side, just use the 'other' side.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1218	if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1219	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1220	if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1221	return TLO.CombineTo(Op, Op.getOperand(1));
				1222	// If the RHS is a constant, see if we can simplify it.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1223	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1224	return true;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1225	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1226	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1227	return true;
				1228
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1229	// Output known-0 bits are only known if clear in both the LHS & RHS.
				1230	KnownZero &= KnownZero2;
				1231	// Output known-1 are known to be set if set in either the LHS \| RHS.
				1232	KnownOne \|= KnownOne2;
				1233	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1234	case ISD::XOR:
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1235	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1236	KnownOne, TLO, Depth+1))
				1237	return true;
				1238	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1239	if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1240	KnownOne2, TLO, Depth+1))
				1241	return true;
				1242	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1243
				1244	// If all of the demanded bits are known zero on one side, return the other.
				1245	// These bits cannot contribute to the result of the 'xor'.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1246	if ((KnownZero & NewMask) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1247	return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1248	if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1249	return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1250	// If the operation can be done in a smaller type, do so.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1251	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1252	return true;
				1253
Chris Lattner	3687c1a	2006-11-27 21:50:02 +0000	[diff] [blame]	1254	// If all of the unknown bits are known to be zero on one side or the other
				1255	// (but not both) turn this into an inclusive or.
				1256	// e.g. (A & C1)^(B & C2) -> (A & C1)\|(B & C2) iff C1&C2 == 0
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1257	if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesen	de06470	2009-02-06 21:50:26 +0000	[diff] [blame]	1258	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner	3687c1a	2006-11-27 21:50:02 +0000	[diff] [blame]	1259	Op.getOperand(0),
				1260	Op.getOperand(1)));
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1261
				1262	// Output known-0 bits are known if clear or set in both the LHS & RHS.
				1263	KnownZeroOut = (KnownZero & KnownZero2) \| (KnownOne & KnownOne2);
				1264	// Output known-1 are known to be set if set in only one of the LHS, RHS.
				1265	KnownOneOut = (KnownZero & KnownOne2) \| (KnownOne & KnownZero2);
				1266
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1267	// If all of the demanded bits on one side are known, and all of the set
				1268	// bits on that side are also known to be set on the other side, turn this
				1269	// into an AND, as we know the bits will be cleared.
				1270	// e.g. (X \| C1) ^ C2 --> (X \| C1) & ~C2 iff (C1&C2) == C2
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1271	if ((NewMask & (KnownZero\|KnownOne)) == NewMask) { // all known
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1272	if ((KnownOne & KnownOne2) == KnownOne) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1273	EVT VT = Op.getValueType();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1274	SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1275	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
				1276	Op.getOperand(0), ANDC));
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1277	}
				1278	}
				1279
				1280	// If the RHS is a constant, see if we can simplify it.
Torok Edwin	4fea2e9	2008-04-06 21:23:02 +0000	[diff] [blame]	1281	// for XOR, we prefer to force bits to 1 if they will make a -1.
				1282	// if we can't force bits, try to shrink constant
				1283	if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
				1284	APInt Expanded = C->getAPIntValue() \| (~NewMask);
				1285	// if we can expand it to have all bits set, do it
				1286	if (Expanded.isAllOnesValue()) {
				1287	if (Expanded != C->getAPIntValue()) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1288	EVT VT = Op.getValueType();
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1289	SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin	4fea2e9	2008-04-06 21:23:02 +0000	[diff] [blame]	1290	TLO.DAG.getConstant(Expanded, VT));
				1291	return TLO.CombineTo(Op, New);
				1292	}
				1293	// if it already has all the bits set, nothing to change
				1294	// but don't shrink either!
				1295	} else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
				1296	return true;
				1297	}
				1298	}
				1299
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1300	KnownZero = KnownZeroOut;
				1301	KnownOne = KnownOneOut;
				1302	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1303	case ISD::SELECT:
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1304	if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1305	KnownOne, TLO, Depth+1))
				1306	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1307	if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1308	KnownOne2, TLO, Depth+1))
				1309	return true;
				1310	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
				1311	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1312
				1313	// If the operands are constants, see if we can simplify them.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1314	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1315	return true;
				1316
				1317	// Only known if known in both the LHS and RHS.
				1318	KnownOne &= KnownOne2;
				1319	KnownZero &= KnownZero2;
				1320	break;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1321	case ISD::SELECT_CC:
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1322	if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1323	KnownOne, TLO, Depth+1))
				1324	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1325	if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1326	KnownOne2, TLO, Depth+1))
				1327	return true;
				1328	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
				1329	assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
				1330
				1331	// If the operands are constants, see if we can simplify them.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1332	if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1333	return true;
				1334
				1335	// Only known if known in both the LHS and RHS.
				1336	KnownOne &= KnownOne2;
				1337	KnownZero &= KnownZero2;
				1338	break;
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1339	case ISD::SHL:
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1340	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1341	unsigned ShAmt = SA->getZExtValue();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1342	SDValue InOp = Op.getOperand(0);
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1343
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1344	// If the shift count is an invalid immediate, don't do anything.
				1345	if (ShAmt >= BitWidth)
				1346	break;
				1347
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1348	// If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
				1349	// single shift. We can do this if the bottom bits (which are shifted
				1350	// out) are never demanded.
				1351	if (InOp.getOpcode() == ISD::SRL &&
				1352	isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1353	if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1354	unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1355	unsigned Opc = ISD::SHL;
				1356	int Diff = ShAmt-C1;
				1357	if (Diff < 0) {
				1358	Diff = -Diff;
				1359	Opc = ISD::SRL;
				1360	}
				1361
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1362	SDValue NewSA =
Chris Lattner	4e7e6cd	2007-05-30 16:30:06 +0000	[diff] [blame]	1363	TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1364	EVT VT = Op.getValueType();
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1365	return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1366	InOp.getOperand(0), NewSA));
				1367	}
				1368	}
				1369
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1370	if (SimplifyDemandedBits(Op.getOperand(0), NewMask.lshr(ShAmt),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1371	KnownZero, KnownOne, TLO, Depth+1))
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1372	return true;
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1373	KnownZero <<= SA->getZExtValue();
				1374	KnownOne <<= SA->getZExtValue();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1375	// low bits known zero.
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1376	KnownZero \|= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1377	}
				1378	break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1379	case ISD::SRL:
				1380	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1381	EVT VT = Op.getValueType();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1382	unsigned ShAmt = SA->getZExtValue();
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	1383	unsigned VTSize = VT.getSizeInBits();
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1384	SDValue InOp = Op.getOperand(0);
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1385
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1386	// If the shift count is an invalid immediate, don't do anything.
				1387	if (ShAmt >= BitWidth)
				1388	break;
				1389
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1390	// If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
				1391	// single shift. We can do this if the top bits (which are shifted out)
				1392	// are never demanded.
				1393	if (InOp.getOpcode() == ISD::SHL &&
				1394	isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1395	if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1396	unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1397	unsigned Opc = ISD::SRL;
				1398	int Diff = ShAmt-C1;
				1399	if (Diff < 0) {
				1400	Diff = -Diff;
				1401	Opc = ISD::SHL;
				1402	}
				1403
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1404	SDValue NewSA =
Chris Lattner	8c7d2d5	2007-04-17 22:53:02 +0000	[diff] [blame]	1405	TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1406	return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner	895c4ab	2007-04-17 21:14:16 +0000	[diff] [blame]	1407	InOp.getOperand(0), NewSA));
				1408	}
				1409	}
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1410
				1411	// Compute the new bits that are at the top now.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1412	if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1413	KnownZero, KnownOne, TLO, Depth+1))
				1414	return true;
				1415	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1416	KnownZero = KnownZero.lshr(ShAmt);
				1417	KnownOne = KnownOne.lshr(ShAmt);
Chris Lattner	c4fa603	2006-06-13 16:52:37 +0000	[diff] [blame]	1418
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1419	APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattner	c4fa603	2006-06-13 16:52:37 +0000	[diff] [blame]	1420	KnownZero \|= HighBits; // High bits known zero.
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1421	}
				1422	break;
				1423	case ISD::SRA:
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1424	// If this is an arithmetic shift right and only the low-bit is set, we can
				1425	// always convert this into a logical shr, even if the shift amount is
				1426	// variable. The low bit of the shift cannot be an input sign bit unless
				1427	// the shift amount is >= the size of the datatype, which is undefined.
				1428	if (DemandedMask == 1)
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1429	return TLO.CombineTo(Op,
				1430	TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
				1431	Op.getOperand(0), Op.getOperand(1)));
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1432
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1433	if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1434	EVT VT = Op.getValueType();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	1435	unsigned ShAmt = SA->getZExtValue();
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1436
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1437	// If the shift count is an invalid immediate, don't do anything.
				1438	if (ShAmt >= BitWidth)
				1439	break;
				1440
				1441	APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner	1b73713	2006-05-08 17:22:53 +0000	[diff] [blame]	1442
				1443	// If any of the demanded bits are produced by the sign extension, we also
				1444	// demand the input sign bit.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1445	APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
				1446	if (HighBits.intersects(NewMask))
Dan Gohman	87862e7	2009-12-11 21:31:27 +0000	[diff] [blame]	1447	InDemandedMask \|= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Chris Lattner	1b73713	2006-05-08 17:22:53 +0000	[diff] [blame]	1448
				1449	if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1450	KnownZero, KnownOne, TLO, Depth+1))
				1451	return true;
				1452	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1453	KnownZero = KnownZero.lshr(ShAmt);
				1454	KnownOne = KnownOne.lshr(ShAmt);
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1455
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1456	// Handle the sign bit, adjusted to where it is now in the mask.
				1457	APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1458
				1459	// If the input sign bit is known to be zero, or if none of the top bits
				1460	// are demanded, turn this into an unsigned shift right.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1461	if (KnownZero.intersects(SignBit) \|\| (HighBits & ~NewMask) == HighBits) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1462	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
				1463	Op.getOperand(0),
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1464	Op.getOperand(1)));
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1465	} else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1466	KnownOne \|= HighBits;
				1467	}
				1468	}
				1469	break;
				1470	case ISD::SIGN_EXTEND_INREG: {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1471	EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1472
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1473	// Sign extension. Compute the demanded bits in the result that are not
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1474	// present in the input.
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1475	APInt NewBits =
				1476	APInt::getHighBitsSet(BitWidth,
				1477	BitWidth - EVT.getScalarType().getSizeInBits()) &
				1478	NewMask;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1479
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1480	// If none of the extended bits are demanded, eliminate the sextinreg.
				1481	if (NewBits == 0)
				1482	return TLO.CombineTo(Op, Op.getOperand(0));
				1483
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1484	APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1485	InSignBit.zext(BitWidth);
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1486	APInt InputDemandedBits =
				1487	APInt::getLowBitsSet(BitWidth,
				1488	EVT.getScalarType().getSizeInBits()) &
				1489	NewMask;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1490
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1491	// Since the sign extended bits are demanded, we know that the sign
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1492	// bit is demanded.
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1493	InputDemandedBits \|= InSignBit;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1494
				1495	if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
				1496	KnownZero, KnownOne, TLO, Depth+1))
				1497	return true;
				1498	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
				1499
				1500	// If the sign bit of the input is known set or clear, then we know the
				1501	// top bits of the result.
				1502
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1503	// If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1504	if (KnownZero.intersects(InSignBit))
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1505	return TLO.CombineTo(Op,
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1506	TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1507
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1508	if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1509	KnownOne \|= NewBits;
				1510	KnownZero &= ~NewBits;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1511	} else { // Input sign bit unknown
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1512	KnownZero &= ~NewBits;
				1513	KnownOne &= ~NewBits;
				1514	}
				1515	break;
				1516	}
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1517	case ISD::ZERO_EXTEND: {
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1518	unsigned OperandBitWidth =
				1519	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1520	APInt InMask = NewMask;
				1521	InMask.trunc(OperandBitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1522
				1523	// If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1524	APInt NewBits =
				1525	APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
				1526	if (!NewBits.intersects(NewMask))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1527	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1528	Op.getValueType(),
				1529	Op.getOperand(0)));
				1530
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1531	if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1532	KnownZero, KnownOne, TLO, Depth+1))
				1533	return true;
				1534	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1535	KnownZero.zext(BitWidth);
				1536	KnownOne.zext(BitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1537	KnownZero \|= NewBits;
				1538	break;
				1539	}
				1540	case ISD::SIGN_EXTEND: {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1541	EVT InVT = Op.getOperand(0).getValueType();
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1542	unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1543	APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman	9736028	2008-03-11 21:29:43 +0000	[diff] [blame]	1544	APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1545	APInt NewBits = ~InMask & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1546
				1547	// If none of the top bits are demanded, convert this into an any_extend.
				1548	if (NewBits == 0)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1549	return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
				1550	Op.getValueType(),
				1551	Op.getOperand(0)));
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1552
				1553	// Since some of the sign extended bits are demanded, we know that the sign
				1554	// bit is demanded.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1555	APInt InDemandedBits = InMask & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1556	InDemandedBits \|= InSignBit;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1557	InDemandedBits.trunc(InBits);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1558
				1559	if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
				1560	KnownOne, TLO, Depth+1))
				1561	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1562	KnownZero.zext(BitWidth);
				1563	KnownOne.zext(BitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1564
				1565	// If the sign bit is known zero, convert this to a zero extend.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1566	if (KnownZero.intersects(InSignBit))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1567	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1568	Op.getValueType(),
				1569	Op.getOperand(0)));
				1570
				1571	// If the sign bit is known one, the top bits match.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1572	if (KnownOne.intersects(InSignBit)) {
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1573	KnownOne \|= NewBits;
				1574	KnownZero &= ~NewBits;
				1575	} else { // Otherwise, top bits aren't known.
				1576	KnownOne &= ~NewBits;
				1577	KnownZero &= ~NewBits;
				1578	}
				1579	break;
				1580	}
				1581	case ISD::ANY_EXTEND: {
Dan Gohman	d199636	2010-01-09 02:13:55 +0000	[diff] [blame]	1582	unsigned OperandBitWidth =
				1583	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1584	APInt InMask = NewMask;
				1585	InMask.trunc(OperandBitWidth);
				1586	if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1587	KnownZero, KnownOne, TLO, Depth+1))
				1588	return true;
				1589	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1590	KnownZero.zext(BitWidth);
				1591	KnownOne.zext(BitWidth);
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1592	break;
				1593	}
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1594	case ISD::TRUNCATE: {
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1595	// Simplify the input, using demanded bit information, and compute the known
				1596	// zero/one bits live out.
Dan Gohman	042919c	2010-03-01 17:59:21 +0000	[diff] [blame]	1597	unsigned OperandBitWidth =
				1598	Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1599	APInt TruncMask = NewMask;
Dan Gohman	042919c	2010-03-01 17:59:21 +0000	[diff] [blame]	1600	TruncMask.zext(OperandBitWidth);
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1601	if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1602	KnownZero, KnownOne, TLO, Depth+1))
				1603	return true;
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1604	KnownZero.trunc(BitWidth);
				1605	KnownOne.trunc(BitWidth);
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1606
				1607	// If the input is only used by this truncate, see if we can shrink it based
				1608	// on the known demanded bits.
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	1609	if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1610	SDValue In = Op.getOperand(0);
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1611	switch (In.getOpcode()) {
				1612	default: break;
				1613	case ISD::SRL:
				1614	// Shrink SRL by a constant if none of the high bits shifted in are
				1615	// demanded.
Evan Cheng	e5b51ac	2010-04-17 06:13:15 +0000	[diff] [blame]	1616	if (TLO.LegalTypes() &&
				1617	!isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
				1618	// Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
				1619	// undesirable.
				1620	break;
				1621	ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
				1622	if (!ShAmt)
				1623	break;
				1624	APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
				1625	OperandBitWidth - BitWidth);
				1626	HighBits = HighBits.lshr(ShAmt->getZExtValue());
				1627	HighBits.trunc(BitWidth);
				1628
				1629	if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
				1630	// None of the shifted in bits are needed. Add a truncate of the
				1631	// shift input, then shift it.
				1632	SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
				1633	Op.getValueType(),
				1634	In.getOperand(0));
				1635	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
				1636	Op.getValueType(),
				1637	NewTrunc,
				1638	In.getOperand(1)));
Chris Lattner	c93dfda	2006-05-06 00:11:52 +0000	[diff] [blame]	1639	}
				1640	break;
				1641	}
				1642	}
				1643
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1644	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattner	fe8babf	2006-05-05 22:32:12 +0000	[diff] [blame]	1645	break;
				1646	}
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1647	case ISD::AssertZext: {
Dan Gohman	400f75c	2010-06-03 20:21:33 +0000	[diff] [blame]	1648	// Demand all the bits of the input that are demanded in the output.
				1649	// The low bits are obvious; the high bits are demanded because we're
				1650	// asserting that they're zero here.
				1651	if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1652	KnownZero, KnownOne, TLO, Depth+1))
				1653	return true;
				1654	assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman	400f75c	2010-06-03 20:21:33 +0000	[diff] [blame]	1655
				1656	EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
				1657	APInt InMask = APInt::getLowBitsSet(BitWidth,
				1658	VT.getSizeInBits());
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1659	KnownZero \|= ~InMask & NewMask;
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1660	break;
				1661	}
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1662	case ISD::BIT_CONVERT:
				1663	#if 0
				1664	// If this is an FP->Int bitcast and if the sign bit is the only thing that
				1665	// is demanded, turn this into a FGETSIGN.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1666	if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	1667	MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
				1668	!MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1669	// Only do this xform if FGETSIGN is valid or if before legalize.
				1670	if (!TLO.AfterLegalize \|\|
				1671	isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
				1672	// Make a FGETSIGN + SHL to move the sign bit into the appropriate
				1673	// place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1674	SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1675	Op.getOperand(0));
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	1676	unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1677	SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner	2ceb2cf	2007-12-22 21:35:38 +0000	[diff] [blame]	1678	return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
				1679	Sign, ShAmt));
				1680	}
				1681	}
				1682	#endif
				1683	break;
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1684	case ISD::ADD:
				1685	case ISD::MUL:
				1686	case ISD::SUB: {
				1687	// Add, Sub, and Mul don't demand any bits in positions beyond that
				1688	// of the highest bit demanded of them.
				1689	APInt LoMask = APInt::getLowBitsSet(BitWidth,
				1690	BitWidth - NewMask.countLeadingZeros());
				1691	if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
				1692	KnownOne2, TLO, Depth+1))
				1693	return true;
				1694	if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
				1695	KnownOne2, TLO, Depth+1))
				1696	return true;
				1697	// See if the operation should be performed at a smaller bit width.
Dan Gohman	4e39e9d	2010-06-24 14:30:44 +0000	[diff] [blame]	1698	if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman	97121ba	2009-04-08 00:15:30 +0000	[diff] [blame]	1699	return true;
				1700	}
				1701	// FALL THROUGH
Dan Gohman	54eed37	2008-05-06 00:53:29 +0000	[diff] [blame]	1702	default:
Chris Lattner	1482b5f	2006-04-02 06:15:09 +0000	[diff] [blame]	1703	// Just use ComputeMaskedBits to compute output bits.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1704	TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattner	a6bc5a4	2006-02-27 01:00:42 +0000	[diff] [blame]	1705	break;
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1706	}
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1707
				1708	// If we know the value of all of the demanded bits, return this as a
				1709	// constant.
Dan Gohman	7b8d4a9	2008-02-27 00:25:32 +0000	[diff] [blame]	1710	if ((NewMask & (KnownZero\|KnownOne)) == NewMask)
Chris Lattner	ec66515	2006-02-26 23:36:02 +0000	[diff] [blame]	1711	return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
				1712
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1713	return false;
				1714	}
				1715
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1716	/// computeMaskedBitsForTargetNode - Determine which of the bits specified
				1717	/// in Mask are known to be either zero or one and return them in the
				1718	/// KnownZero/KnownOne bitsets.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1719	void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman	977a76f	2008-02-13 22:28:48 +0000	[diff] [blame]	1720	const APInt &Mask,
Dan Gohman	fd29e0e	2008-02-13 00:35:47 +0000	[diff] [blame]	1721	APInt &KnownZero,
				1722	APInt &KnownOne,
Dan Gohman	ea859be	2007-06-22 14:59:07 +0000	[diff] [blame]	1723	const SelectionDAG &DAG,
Nate Begeman	368e18d	2006-02-16 21:11:51 +0000	[diff] [blame]	1724	unsigned Depth) const {
Chris Lattner	1b5232a	2006-04-02 06:19:46 +0000	[diff] [blame]	1725	assert((Op.getOpcode() >= ISD::BUILTIN_OP_END \|\|
				1726	Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN \|\|
				1727	Op.getOpcode() == ISD::INTRINSIC_W_CHAIN \|\|
				1728	Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattner	c6fd6cd	2006-01-30 04:09:27 +0000	[diff] [blame]	1729	"Should use MaskedValueIsZero if you don't know whether Op"
				1730	" is a target node!");
Dan Gohman	977a76f	2008-02-13 22:28:48 +0000	[diff] [blame]	1731	KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng	3a03ebb	2005-12-21 23:05:39 +0000	[diff] [blame]	1732	}
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	1733
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1734	/// ComputeNumSignBitsForTargetNode - This method can be implemented by
				1735	/// targets that want to expose additional information about sign bits to the
				1736	/// DAG Combiner.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1737	unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1738	unsigned Depth) const {
				1739	assert((Op.getOpcode() >= ISD::BUILTIN_OP_END \|\|
				1740	Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN \|\|
				1741	Op.getOpcode() == ISD::INTRINSIC_W_CHAIN \|\|
				1742	Op.getOpcode() == ISD::INTRINSIC_VOID) &&
				1743	"Should use ComputeNumSignBits if you don't know whether Op"
				1744	" is a target node!");
				1745	return 1;
				1746	}
				1747
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1748	/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
				1749	/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
				1750	/// determine which bit is set.
				1751	///
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	1752	static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1753	// A left-shift of a constant one will have exactly one bit set, because
				1754	// shifting the bit off the end is undefined.
				1755	if (Val.getOpcode() == ISD::SHL)
				1756	if (ConstantSDNode *C =
				1757	dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
				1758	if (C->getAPIntValue() == 1)
				1759	return true;
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1760
Dan Gohman	97d1163	2009-02-15 23:59:32 +0000	[diff] [blame]	1761	// Similarly, a right-shift of a constant sign-bit will have exactly
				1762	// one bit set.
				1763	if (Val.getOpcode() == ISD::SRL)
				1764	if (ConstantSDNode *C =
				1765	dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
				1766	if (C->getAPIntValue().isSignBit())
				1767	return true;
				1768
				1769	// More could be done here, though the above checks are enough
				1770	// to handle some common cases.
				1771
				1772	// Fall back to ComputeMaskedBits to catch other known cases.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1773	EVT OpVT = Val.getValueType();
Dan Gohman	5b870af	2010-03-02 02:14:38 +0000	[diff] [blame]	1774	unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1775	APInt Mask = APInt::getAllOnesValue(BitWidth);
				1776	APInt KnownZero, KnownOne;
				1777	DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	1778	return (KnownZero.countPopulation() == BitWidth - 1) &&
				1779	(KnownOne.countPopulation() == 1);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	1780	}
Chris Lattner	5c3e21d	2006-05-06 09:27:13 +0000	[diff] [blame]	1781
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1782	/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	1783	/// and cc. If it is unable to simplify it, return a null SDValue.
				1784	SDValue
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1785	TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1786	ISD::CondCode Cond, bool foldBooleans,
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	1787	DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1788	SelectionDAG &DAG = DCI.DAG;
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	1789	LLVMContext &Context = *DAG.getContext();
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1790
				1791	// These setcc operations always fold.
				1792	switch (Cond) {
				1793	default: break;
				1794	case ISD::SETFALSE:
				1795	case ISD::SETFALSE2: return DAG.getConstant(0, VT);
				1796	case ISD::SETTRUE:
				1797	case ISD::SETTRUE2: return DAG.getConstant(1, VT);
				1798	}
				1799
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1800	if (isa<ConstantSDNode>(N0.getNode())) {
				1801	// Ensure that the constant occurs on the RHS, and fold constant
				1802	// comparisons.
				1803	return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
				1804	}
				1805
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	1806	if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman	6c6cd1c	2008-03-03 22:22:56 +0000	[diff] [blame]	1807	const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	1808
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1809	// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
				1810	// equality comparison, then we're just comparing whether X itself is
				1811	// zero.
				1812	if (N0.getOpcode() == ISD::SRL && (C1 == 0 \|\| C1 == 1) &&
				1813	N0.getOperand(0).getOpcode() == ISD::CTLZ &&
				1814	N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1815	const APInt &ShAmt
				1816	= cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1817	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
				1818	ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
				1819	if ((C1 == 0) == (Cond == ISD::SETEQ)) {
				1820	// (srl (ctlz x), 5) == 0 -> X != 0
				1821	// (srl (ctlz x), 5) != 1 -> X != 0
				1822	Cond = ISD::SETNE;
				1823	} else {
				1824	// (srl (ctlz x), 5) != 0 -> X == 0
				1825	// (srl (ctlz x), 5) == 1 -> X == 0
				1826	Cond = ISD::SETEQ;
				1827	}
				1828	SDValue Zero = DAG.getConstant(0, N0.getValueType());
				1829	return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
				1830	Zero, Cond);
				1831	}
				1832	}
				1833
				1834	// If the LHS is '(and load, const)', the RHS is 0,
				1835	// the test is for equality or unsigned, and all 1 bits of the const are
				1836	// in the same partial word, see if we can shorten the load.
				1837	if (DCI.isBeforeLegalize() &&
				1838	N0.getOpcode() == ISD::AND && C1 == 0 &&
				1839	N0.getNode()->hasOneUse() &&
				1840	isa<LoadSDNode>(N0.getOperand(0)) &&
				1841	N0.getOperand(0).getNode()->hasOneUse() &&
				1842	isa<ConstantSDNode>(N0.getOperand(1))) {
				1843	LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1844	APInt bestMask;
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1845	unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1846	if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1847	unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1848	unsigned maskWidth = origWidth;
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1849	// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
				1850	// 8 bits, but have to be careful...
				1851	if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
				1852	origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1853	const APInt &Mask =
				1854	cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1855	for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1856	APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1857	for (unsigned offset=0; offset<origWidth/width; offset++) {
				1858	if ((newMask & Mask) == Mask) {
				1859	if (!TD->isLittleEndian())
				1860	bestOffset = (origWidth/width - offset - 1) * (width/8);
				1861	else
				1862	bestOffset = (uint64_t)offset * (width/8);
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1863	bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1864	bestWidth = width;
				1865	break;
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	1866	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1867	newMask = newMask << width;
Dale Johannesen	89217a6	2008-11-07 01:28:02 +0000	[diff] [blame]	1868	}
				1869	}
				1870	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1871	if (bestWidth) {
Owen Anderson	23b9b19	2009-08-12 00:36:31 +0000	[diff] [blame]	1872	EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1873	if (newVT.isRound()) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1874	EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1875	SDValue Ptr = Lod->getBasePtr();
				1876	if (bestOffset != 0)
				1877	Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
				1878	DAG.getConstant(bestOffset, PtrType));
				1879	unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
				1880	SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
				1881	Lod->getSrcValue(),
				1882	Lod->getSrcValueOffset() + bestOffset,
David Greene	1e55944	2010-02-15 17:00:31 +0000	[diff] [blame]	1883	false, false, NewAlign);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1884	return DAG.getSetCC(dl, VT,
				1885	DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1886	DAG.getConstant(bestMask.trunc(bestWidth),
				1887	newVT)),
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1888	DAG.getConstant(0LL, newVT), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1889	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1890	}
				1891	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1892
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1893	// If the LHS is a ZERO_EXTEND, perform the comparison on the input.
				1894	if (N0.getOpcode() == ISD::ZERO_EXTEND) {
				1895	unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
				1896
				1897	// If the comparison constant has bits in the upper part, the
				1898	// zero-extended value could never match.
				1899	if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
				1900	C1.getBitWidth() - InSize))) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1901	switch (Cond) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1902	case ISD::SETUGT:
				1903	case ISD::SETUGE:
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1904	case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1905	case ISD::SETULT:
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1906	case ISD::SETULE:
				1907	case ISD::SETNE: return DAG.getConstant(1, VT);
				1908	case ISD::SETGT:
				1909	case ISD::SETGE:
				1910	// True if the sign bit of C1 is set.
				1911	return DAG.getConstant(C1.isNegative(), VT);
				1912	case ISD::SETLT:
				1913	case ISD::SETLE:
				1914	// True if the sign bit of C1 isn't set.
				1915	return DAG.getConstant(C1.isNonNegative(), VT);
				1916	default:
Jakob Stoklund Olesen	78d1264	2009-07-24 18:22:59 +0000	[diff] [blame]	1917	break;
				1918	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1919	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1920
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1921	// Otherwise, we can perform the comparison with the low bits.
				1922	switch (Cond) {
				1923	case ISD::SETEQ:
				1924	case ISD::SETNE:
				1925	case ISD::SETUGT:
				1926	case ISD::SETUGE:
				1927	case ISD::SETULT:
				1928	case ISD::SETULE: {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1929	EVT newVT = N0.getOperand(0).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1930	if (DCI.isBeforeLegalizeOps() \|\|
				1931	(isOperationLegal(ISD::SETCC, newVT) &&
				1932	getCondCodeAction(Cond, newVT)==Legal))
				1933	return DAG.getSetCC(dl, VT, N0.getOperand(0),
				1934	DAG.getConstant(APInt(C1).trunc(InSize), newVT),
				1935	Cond);
				1936	break;
				1937	}
				1938	default:
				1939	break; // todo, be more careful with signed comparisons
				1940	}
				1941	} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	1942	(Cond == ISD::SETEQ \|\| Cond == ISD::SETNE)) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1943	EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1944	unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1945	EVT ExtDstTy = N0.getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1946	unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
				1947
				1948	// If the extended part has any inconsistent bits, it cannot ever
				1949	// compare equal. In other words, they have to be all ones or all
				1950	// zeros.
				1951	APInt ExtBits =
				1952	APInt::getHighBitsSet(ExtDstTyBits, ExtDstTyBits - ExtSrcTyBits);
				1953	if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
				1954	return DAG.getConstant(Cond == ISD::SETNE, VT);
				1955
				1956	SDValue ZextOp;
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	1957	EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1958	if (Op0Ty == ExtSrcTy) {
				1959	ZextOp = N0.getOperand(0);
				1960	} else {
				1961	APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
				1962	ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
				1963	DAG.getConstant(Imm, Op0Ty));
				1964	}
				1965	if (!DCI.isCalledByLegalizer())
				1966	DCI.AddToWorklist(ZextOp.getNode());
				1967	// Otherwise, make this a use of a zext.
				1968	return DAG.getSetCC(dl, VT, ZextOp,
				1969	DAG.getConstant(C1 & APInt::getLowBitsSet(
				1970	ExtDstTyBits,
				1971	ExtSrcTyBits),
				1972	ExtDstTy),
				1973	Cond);
				1974	} else if ((N1C->isNullValue() \|\| N1C->getAPIntValue() == 1) &&
				1975	(Cond == ISD::SETEQ \|\| Cond == ISD::SETNE)) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1976	// SETCC (SETCC), [0\|1], [EQ\|NE] -> SETCC
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	1977	if (N0.getOpcode() == ISD::SETCC &&
				1978	isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	1979	bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1980	if (TrueWhenTrue)
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	1981	return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1982	// Invert the condition.
				1983	ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
				1984	CC = ISD::getSetCCInverse(CC,
				1985	N0.getOperand(0).getValueType().isInteger());
				1986	return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	1987	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	1988
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1989	if ((N0.getOpcode() == ISD::XOR \|\|
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	1990	(N0.getOpcode() == ISD::AND &&
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	1991	N0.getOperand(0).getOpcode() == ISD::XOR &&
				1992	N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
				1993	isa<ConstantSDNode>(N0.getOperand(1)) &&
				1994	cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
				1995	// If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
				1996	// can only do this if the top bits are known zero.
				1997	unsigned BitWidth = N0.getValueSizeInBits();
				1998	if (DAG.MaskedValueIsZero(N0,
				1999	APInt::getHighBitsSet(BitWidth,
				2000	BitWidth-1))) {
				2001	// Okay, get the un-inverted input value.
				2002	SDValue Val;
				2003	if (N0.getOpcode() == ISD::XOR)
				2004	Val = N0.getOperand(0);
				2005	else {
				2006	assert(N0.getOpcode() == ISD::AND &&
				2007	N0.getOperand(0).getOpcode() == ISD::XOR);
				2008	// ((X^1)&1)^1 -> X & 1
				2009	Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
				2010	N0.getOperand(0).getOperand(0),
				2011	N0.getOperand(1));
				2012	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2013
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2014	return DAG.getSetCC(dl, VT, Val, N1,
				2015	Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
				2016	}
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2017	} else if (N1C->getAPIntValue() == 1 &&
				2018	(VT == MVT::i1 \|\|
				2019	getBooleanContents() == ZeroOrOneBooleanContent)) {
				2020	SDValue Op0 = N0;
				2021	if (Op0.getOpcode() == ISD::TRUNCATE)
				2022	Op0 = Op0.getOperand(0);
				2023
				2024	if ((Op0.getOpcode() == ISD::XOR) &&
				2025	Op0.getOperand(0).getOpcode() == ISD::SETCC &&
				2026	Op0.getOperand(1).getOpcode() == ISD::SETCC) {
				2027	// (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
				2028	Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
				2029	return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
				2030	Cond);
				2031	} else if (Op0.getOpcode() == ISD::AND &&
				2032	isa<ConstantSDNode>(Op0.getOperand(1)) &&
				2033	cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
				2034	// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov	17458a7	2010-05-01 12:52:34 +0000	[diff] [blame]	2035	if (Op0.getValueType().bitsGT(VT))
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2036	Op0 = DAG.getNode(ISD::AND, dl, VT,
				2037	DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
				2038	DAG.getConstant(1, VT));
Anton Korobeynikov	17458a7	2010-05-01 12:52:34 +0000	[diff] [blame]	2039	else if (Op0.getValueType().bitsLT(VT))
				2040	Op0 = DAG.getNode(ISD::AND, dl, VT,
				2041	DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
				2042	DAG.getConstant(1, VT));
				2043
Evan Cheng	2c755ba	2010-02-27 07:36:59 +0000	[diff] [blame]	2044	return DAG.getSetCC(dl, VT, Op0,
				2045	DAG.getConstant(0, Op0.getValueType()),
				2046	Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
				2047	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2048	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2049	}
				2050
				2051	APInt MinVal, MaxVal;
				2052	unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
				2053	if (ISD::isSignedIntSetCC(Cond)) {
				2054	MinVal = APInt::getSignedMinValue(OperandBitSize);
				2055	MaxVal = APInt::getSignedMaxValue(OperandBitSize);
				2056	} else {
				2057	MinVal = APInt::getMinValue(OperandBitSize);
				2058	MaxVal = APInt::getMaxValue(OperandBitSize);
				2059	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2060
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2061	// Canonicalize GE/LE comparisons to use GT/LT comparisons.
				2062	if (Cond == ISD::SETGE \|\| Cond == ISD::SETUGE) {
				2063	if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
				2064	// X >= C0 --> X > (C0-1)
				2065	return DAG.getSetCC(dl, VT, N0,
				2066	DAG.getConstant(C1-1, N1.getValueType()),
				2067	(Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
				2068	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2069
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2070	if (Cond == ISD::SETLE \|\| Cond == ISD::SETULE) {
				2071	if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
				2072	// X <= C0 --> X < (C0+1)
				2073	return DAG.getSetCC(dl, VT, N0,
				2074	DAG.getConstant(C1+1, N1.getValueType()),
				2075	(Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
				2076	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2077
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2078	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MinVal)
				2079	return DAG.getConstant(0, VT); // X < MIN --> false
				2080	if ((Cond == ISD::SETGE \|\| Cond == ISD::SETUGE) && C1 == MinVal)
				2081	return DAG.getConstant(1, VT); // X >= MIN --> true
				2082	if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MaxVal)
				2083	return DAG.getConstant(0, VT); // X > MAX --> false
				2084	if ((Cond == ISD::SETLE \|\| Cond == ISD::SETULE) && C1 == MaxVal)
				2085	return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2086
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2087	// Canonicalize setgt X, Min --> setne X, Min
				2088	if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MinVal)
				2089	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
				2090	// Canonicalize setlt X, Max --> setne X, Max
				2091	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MaxVal)
				2092	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2093
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2094	// If we have setult X, 1, turn it into seteq X, 0
				2095	if ((Cond == ISD::SETLT \|\| Cond == ISD::SETULT) && C1 == MinVal+1)
				2096	return DAG.getSetCC(dl, VT, N0,
				2097	DAG.getConstant(MinVal, N0.getValueType()),
				2098	ISD::SETEQ);
				2099	// If we have setugt X, Max-1, turn it into seteq X, Max
				2100	else if ((Cond == ISD::SETGT \|\| Cond == ISD::SETUGT) && C1 == MaxVal-1)
				2101	return DAG.getSetCC(dl, VT, N0,
				2102	DAG.getConstant(MaxVal, N0.getValueType()),
				2103	ISD::SETEQ);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2104
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2105	// If we have "setcc X, C0", check to see if we can shrink the immediate
				2106	// by changing cc.
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2107
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2108	// SETUGT X, SINTMAX -> SETLT X, 0
				2109	if (Cond == ISD::SETUGT &&
				2110	C1 == APInt::getSignedMaxValue(OperandBitSize))
				2111	return DAG.getSetCC(dl, VT, N0,
				2112	DAG.getConstant(0, N1.getValueType()),
				2113	ISD::SETLT);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2114
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2115	// SETULT X, SINTMIN -> SETGT X, -1
				2116	if (Cond == ISD::SETULT &&
				2117	C1 == APInt::getSignedMinValue(OperandBitSize)) {
				2118	SDValue ConstMinusOne =
				2119	DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
				2120	N1.getValueType());
				2121	return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
				2122	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2123
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2124	// Fold bit comparisons when we can.
				2125	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2126	(VT == N0.getValueType() \|\|
				2127	(isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
				2128	N0.getOpcode() == ISD::AND)
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2129	if (ConstantSDNode *AndRHS =
				2130	dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2131	EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2132	getPointerTy() : getShiftAmountTy();
				2133	if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
				2134	// Perform the xform if the AND RHS is a single bit.
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2135	if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2136	return DAG.getNode(ISD::TRUNCATE, dl, VT,
				2137	DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2138	DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2139	}
Evan Cheng	347a9cb	2010-01-07 20:58:44 +0000	[diff] [blame]	2140	} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2141	// (X & 8) == 8 --> (X & 8) >> 3
				2142	// Perform the xform if C1 is a single bit.
				2143	if (C1.isPowerOf2()) {
Evan Cheng	d40d03e	2010-01-06 19:38:29 +0000	[diff] [blame]	2144	return DAG.getNode(ISD::TRUNCATE, dl, VT,
				2145	DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
				2146	DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2147	}
				2148	}
Eli Friedman	b101b0b	2009-07-26 23:47:17 +0000	[diff] [blame]	2149	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2150	}
				2151
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2152	if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2153	// Constant fold or commute setcc.
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2154	SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2155	if (O.getNode()) return O;
				2156	} else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2157	// If the RHS of an FP comparison is a constant, simplify it away in
				2158	// some cases.
				2159	if (CFP->getValueAPF().isNaN()) {
				2160	// If an operand is known to be a nan, we can fold it.
				2161	switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwin	c23197a	2009-07-14 16:55:14 +0000	[diff] [blame]	2162	default: llvm_unreachable("Unknown flavor!");
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2163	case 0: // Known false.
				2164	return DAG.getConstant(0, VT);
				2165	case 1: // Known true.
				2166	return DAG.getConstant(1, VT);
Chris Lattner	1c3e1e2	2007-12-30 21:21:10 +0000	[diff] [blame]	2167	case 2: // Undefined.
Dale Johannesen	e8d7230	2009-02-06 23:05:02 +0000	[diff] [blame]	2168	return DAG.getUNDEF(VT);
Chris Lattner	63079f0	2007-12-29 08:37:08 +0000	[diff] [blame]	2169	}
				2170	}
				2171
				2172	// Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
				2173	// constant if knowing that the operand is non-nan is enough. We prefer to
				2174	// have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
				2175	// materialize 0.0.
				2176	if (Cond == ISD::SETO \|\| Cond == ISD::SETUO)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2177	return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman	11eab02	2009-09-26 15:24:17 +0000	[diff] [blame]	2178
				2179	// If the condition is not legal, see if we can find an equivalent one
				2180	// which is legal.
				2181	if (!isCondCodeLegal(Cond, N0.getValueType())) {
				2182	// If the comparison was an awkward floating-point == or != and one of
				2183	// the comparison operands is infinity or negative infinity, convert the
				2184	// condition to a less-awkward <= or >=.
				2185	if (CFP->getValueAPF().isInfinity()) {
				2186	if (CFP->getValueAPF().isNegative()) {
				2187	if (Cond == ISD::SETOEQ &&
				2188	isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
				2189	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
				2190	if (Cond == ISD::SETUEQ &&
				2191	isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
				2192	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
				2193	if (Cond == ISD::SETUNE &&
				2194	isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
				2195	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
				2196	if (Cond == ISD::SETONE &&
				2197	isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
				2198	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
				2199	} else {
				2200	if (Cond == ISD::SETOEQ &&
				2201	isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
				2202	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
				2203	if (Cond == ISD::SETUEQ &&
				2204	isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
				2205	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
				2206	if (Cond == ISD::SETUNE &&
				2207	isCondCodeLegal(ISD::SETULT, N0.getValueType()))
				2208	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
				2209	if (Cond == ISD::SETONE &&
				2210	isCondCodeLegal(ISD::SETULT, N0.getValueType()))
				2211	return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
				2212	}
				2213	}
				2214	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2215	}
				2216
				2217	if (N0 == N1) {
				2218	// We can always fold X == X for integer setcc's.
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2219	if (N0.getValueType().isInteger())
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2220	return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
				2221	unsigned UOF = ISD::getUnorderedFlavor(Cond);
				2222	if (UOF == 2) // FP operators that are undefined on NaNs.
				2223	return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
				2224	if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
				2225	return DAG.getConstant(UOF, VT);
				2226	// Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
				2227	// if it is not already.
				2228	ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
				2229	if (NewCond != Cond)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2230	return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2231	}
				2232
				2233	if ((Cond == ISD::SETEQ \|\| Cond == ISD::SETNE) &&
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2234	N0.getValueType().isInteger()) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2235	if (N0.getOpcode() == ISD::ADD \|\| N0.getOpcode() == ISD::SUB \|\|
				2236	N0.getOpcode() == ISD::XOR) {
				2237	// Simplify (X+Y) == (X+Z) --> Y == Z
				2238	if (N0.getOpcode() == N1.getOpcode()) {
				2239	if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2240	return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2241	if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2242	return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2243	if (DAG.isCommutativeBinOp(N0.getOpcode())) {
				2244	// If X op Y == Y op X, try other combinations.
				2245	if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2246	return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
				2247	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2248	if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2249	return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
				2250	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2251	}
				2252	}
				2253
				2254	if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
				2255	if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
				2256	// Turn (X+C1) == C2 --> X == C2-C1
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2257	if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2258	return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	2259	DAG.getConstant(RHSC->getAPIntValue()-
				2260	LHSR->getAPIntValue(),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2261	N0.getValueType()), Cond);
				2262	}
				2263
				2264	// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
				2265	if (N0.getOpcode() == ISD::XOR)
				2266	// If we know that all of the inverted bits are zero, don't bother
				2267	// performing the inversion.
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2268	if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
				2269	return
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2270	DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2271	DAG.getConstant(LHSR->getAPIntValue() ^
				2272	RHSC->getAPIntValue(),
				2273	N0.getValueType()),
				2274	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2275	}
				2276
				2277	// Turn (C1-X) == C2 --> X == C1-C2
				2278	if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2279	if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2280	return
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2281	DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman	2e68b6f	2008-02-25 21:11:39 +0000	[diff] [blame]	2282	DAG.getConstant(SUBC->getAPIntValue() -
				2283	RHSC->getAPIntValue(),
				2284	N0.getValueType()),
				2285	Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2286	}
				2287	}
				2288	}
				2289
				2290	// Simplify (X+Z) == X --> Z == 0
				2291	if (N0.getOperand(0) == N1)
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2292	return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2293	DAG.getConstant(0, N0.getValueType()), Cond);
				2294	if (N0.getOperand(1) == N1) {
				2295	if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2296	return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2297	DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2298	else if (N0.getNode()->hasOneUse()) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2299	assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
				2300	// (Z-X) == X --> Z == X<<1
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2301	SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2302	N1,
				2303	DAG.getConstant(1, getShiftAmountTy()));
				2304	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2305	DCI.AddToWorklist(SH.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2306	return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2307	}
				2308	}
				2309	}
				2310
				2311	if (N1.getOpcode() == ISD::ADD \|\| N1.getOpcode() == ISD::SUB \|\|
				2312	N1.getOpcode() == ISD::XOR) {
				2313	// Simplify X == (X+Z) --> Z == 0
				2314	if (N1.getOperand(0) == N0) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2315	return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2316	DAG.getConstant(0, N1.getValueType()), Cond);
				2317	} else if (N1.getOperand(1) == N0) {
				2318	if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2319	return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2320	DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2321	} else if (N1.getNode()->hasOneUse()) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2322	assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
				2323	// X == (Z-X) --> X<<1 == Z
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2324	SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2325	DAG.getConstant(1, getShiftAmountTy()));
				2326	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2327	DCI.AddToWorklist(SH.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2328	return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2329	}
				2330	}
				2331	}
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2332
Dan Gohman	2c65c3d	2009-01-29 16:18:12 +0000	[diff] [blame]	2333	// Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2334	// Note that where y is variable and is known to have at most
				2335	// one bit set (for example, if it is z&1) we cannot do this;
				2336	// the expressions are not equivalent when y==0.
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2337	if (N0.getOpcode() == ISD::AND)
				2338	if (N0.getOperand(0) == N1 \|\| N0.getOperand(1) == N1) {
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2339	if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2340	Cond = ISD::getSetCCInverse(Cond, /isInteger=/true);
				2341	SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2342	return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2343	}
				2344	}
				2345	if (N1.getOpcode() == ISD::AND)
				2346	if (N1.getOperand(0) == N0 \|\| N1.getOperand(1) == N0) {
Dale Johannesen	85b0ede	2009-02-11 19:19:41 +0000	[diff] [blame]	2347	if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2348	Cond = ISD::getSetCCInverse(Cond, /isInteger=/true);
				2349	SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2350	return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohman	e5af2d3	2009-01-29 01:59:02 +0000	[diff] [blame]	2351	}
				2352	}
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2353	}
				2354
				2355	// Fold away ALL boolean setcc's.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2356	SDValue Temp;
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2357	if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2358	switch (Cond) {
Torok Edwin	c23197a	2009-07-14 16:55:14 +0000	[diff] [blame]	2359	default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2360	case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2361	Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
				2362	N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2363	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2364	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2365	break;
				2366	case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2367	N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2368	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2369	case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
				2370	case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2371	Temp = DAG.getNOT(dl, N0, MVT::i1);
				2372	N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2373	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2374	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2375	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2376	case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
				2377	case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2378	Temp = DAG.getNOT(dl, N1, MVT::i1);
				2379	N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2380	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2381	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2382	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2383	case ISD::SETULE: // X <=u Y --> X == 0 \| Y == 1 --> ~X \| Y
				2384	case ISD::SETGE: // X >=s Y --> X == 0 \| Y == 1 --> ~X \| Y
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2385	Temp = DAG.getNOT(dl, N0, MVT::i1);
				2386	N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2387	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2388	DCI.AddToWorklist(Temp.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2389	break;
Bob Wilson	4c24546	2009-01-22 17:39:32 +0000	[diff] [blame]	2390	case ISD::SETUGE: // X >=u Y --> X == 1 \| Y == 0 --> ~Y \| X
				2391	case ISD::SETLE: // X <=s Y --> X == 1 \| Y == 0 --> ~Y \| X
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2392	Temp = DAG.getNOT(dl, N1, MVT::i1);
				2393	N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2394	break;
				2395	}
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2396	if (VT != MVT::i1) {
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2397	if (!DCI.isCalledByLegalizer())
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2398	DCI.AddToWorklist(N0.getNode());
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2399	// FIXME: If running after legalize, we probably can't do this.
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2400	N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2401	}
				2402	return N0;
				2403	}
				2404
				2405	// Could not fold it.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2406	return SDValue();
Evan Cheng	fa1eb27	2007-02-08 22:13:59 +0000	[diff] [blame]	2407	}
				2408
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2409	/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
				2410	/// node is a GlobalAddress + offset.
Dan Gohman	46510a7	2010-04-15 01:51:59 +0000	[diff] [blame]	2411	bool TargetLowering::isGAPlusOffset(SDNode N, const GlobalValue &GA,
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2412	int64_t &Offset) const {
				2413	if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman	9ea3f56	2008-06-09 22:05:52 +0000	[diff] [blame]	2414	GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
				2415	GA = GASD->getGlobal();
				2416	Offset += GASD->getOffset();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2417	return true;
				2418	}
				2419
				2420	if (N->getOpcode() == ISD::ADD) {
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2421	SDValue N1 = N->getOperand(0);
				2422	SDValue N2 = N->getOperand(1);
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2423	if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2424	ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
				2425	if (V) {
Dan Gohman	7810bfe	2008-09-26 21:54:37 +0000	[diff] [blame]	2426	Offset += V->getSExtValue();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2427	return true;
				2428	}
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2429	} else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2430	ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
				2431	if (V) {
Dan Gohman	7810bfe	2008-09-26 21:54:37 +0000	[diff] [blame]	2432	Offset += V->getSExtValue();
Evan Cheng	ad4196b	2008-05-12 19:56:52 +0000	[diff] [blame]	2433	return true;
				2434	}
				2435	}
				2436	}
				2437	return false;
				2438	}
				2439
				2440
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2441	SDValue TargetLowering::
Chris Lattner	00ffed0	2006-03-01 04:52:55 +0000	[diff] [blame]	2442	PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
				2443	// Default implementation: no optimization.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2444	return SDValue();
Chris Lattner	00ffed0	2006-03-01 04:52:55 +0000	[diff] [blame]	2445	}
				2446
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2447	//===----------------------------------------------------------------------===//
				2448	// Inline Assembler Implementation Methods
				2449	//===----------------------------------------------------------------------===//
				2450
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2451
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2452	TargetLowering::ConstraintType
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2453	TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2454	// FIXME: lots more standard ones to handle.
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2455	if (Constraint.size() == 1) {
				2456	switch (Constraint[0]) {
				2457	default: break;
				2458	case 'r': return C_RegisterClass;
				2459	case 'm': // memory
				2460	case 'o': // offsetable
				2461	case 'V': // not offsetable
				2462	return C_Memory;
				2463	case 'i': // Simple Integer or Relocatable Constant
				2464	case 'n': // Simple Integer
				2465	case 's': // Relocatable Constant
Chris Lattner	c13dd1c	2007-03-25 04:35:41 +0000	[diff] [blame]	2466	case 'X': // Allow ANY value.
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2467	case 'I': // Target registers.
				2468	case 'J':
				2469	case 'K':
				2470	case 'L':
				2471	case 'M':
				2472	case 'N':
				2473	case 'O':
				2474	case 'P':
				2475	return C_Other;
				2476	}
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2477	}
Chris Lattner	065421f	2007-03-25 02:18:14 +0000	[diff] [blame]	2478
				2479	if (Constraint.size() > 1 && Constraint[0] == '{' &&
				2480	Constraint[Constraint.size()-1] == '}')
				2481	return C_Register;
Chris Lattner	4234f57	2007-03-25 02:14:49 +0000	[diff] [blame]	2482	return C_Unknown;
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2483	}
				2484
Dale Johannesen	ba2a0b9	2008-01-29 02:21:21 +0000	[diff] [blame]	2485	/// LowerXConstraint - try to replace an X constraint, which matches anything,
				2486	/// with another that has more specific requirements based on the type of the
				2487	/// corresponding operand.
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2488	const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2489	if (ConstraintVT.isInteger())
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2490	return "r";
Duncan Sands	83ec4b6	2008-06-06 12:08:01 +0000	[diff] [blame]	2491	if (ConstraintVT.isFloatingPoint())
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2492	return "f"; // works for many targets
				2493	return 0;
Dale Johannesen	ba2a0b9	2008-01-29 02:21:21 +0000	[diff] [blame]	2494	}
				2495
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2496	/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
				2497	/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2498	void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2499	char ConstraintLetter,
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2500	std::vector<SDValue> &Ops,
Chris Lattner	5e76423	2008-04-26 23:02:14 +0000	[diff] [blame]	2501	SelectionDAG &DAG) const {
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2502	switch (ConstraintLetter) {
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2503	default: break;
Dale Johannesen	eb57ea7	2007-11-05 21:20:28 +0000	[diff] [blame]	2504	case 'X': // Allows any operand; labels (basic block) use this.
				2505	if (Op.getOpcode() == ISD::BasicBlock) {
				2506	Ops.push_back(Op);
				2507	return;
				2508	}
				2509	// fall through
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2510	case 'i': // Simple Integer or Relocatable Constant
				2511	case 'n': // Simple Integer
Dale Johannesen	eb57ea7	2007-11-05 21:20:28 +0000	[diff] [blame]	2512	case 's': { // Relocatable Constant
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2513	// These operands are interested in values of the form (GV+C), where C may
				2514	// be folded in as an offset of GV, or it may be explicitly added. Also, it
				2515	// is possible and fine if either GV or C are missing.
				2516	ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
				2517	GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
				2518
				2519	// If we have "(add GV, C)", pull out GV/C
				2520	if (Op.getOpcode() == ISD::ADD) {
				2521	C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
				2522	GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
				2523	if (C == 0 \|\| GA == 0) {
				2524	C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
				2525	GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
				2526	}
				2527	if (C == 0 \|\| GA == 0)
				2528	C = 0, GA = 0;
				2529	}
				2530
				2531	// If we find a valid operand, map to the TargetXXX version so that the
				2532	// value itself doesn't get selected.
				2533	if (GA) { // Either &GV or &GV+C
				2534	if (ConstraintLetter != 'n') {
				2535	int64_t Offs = GA->getOffset();
Dan Gohman	f5aeb1a	2008-09-12 16:56:44 +0000	[diff] [blame]	2536	if (C) Offs += C->getZExtValue();
Devang Patel	0d881da	2010-07-06 22:08:15 +0000	[diff] [blame]	2537	Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel	07538ad	2010-07-15 18:45:27 +0000	[diff] [blame]	2538	C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2539	Op.getValueType(), Offs));
				2540	return;
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2541	}
				2542	}
				2543	if (C) { // just C, no GV.
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2544	// Simple constants are not allowed for 's'.
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2545	if (ConstraintLetter != 's') {
Dale Johannesen	78e3e52	2009-02-12 20:58:09 +0000	[diff] [blame]	2546	// gcc prints these as sign extended. Sign extend value to 64 bits
				2547	// now; without this it would get ZExt'd later in
				2548	// ScheduleDAGSDNodes::EmitNode, which is very generic.
				2549	Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson	825b72b	2009-08-11 20:47:22 +0000	[diff] [blame]	2550	MVT::i64));
Chris Lattner	48884cd	2007-08-25 00:47:38 +0000	[diff] [blame]	2551	return;
				2552	}
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2553	}
Chris Lattner	9ff6ee8	2007-02-17 06:00:35 +0000	[diff] [blame]	2554	break;
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2555	}
Chris Lattner	75c7d2b	2007-05-03 16:54:34 +0000	[diff] [blame]	2556	}
Chris Lattner	eb8146b	2006-02-04 02:13:02 +0000	[diff] [blame]	2557	}
				2558
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	2559	std::vector<unsigned> TargetLowering::
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2560	getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2561	EVT VT) const {
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2562	return std::vector<unsigned>();
				2563	}
				2564
				2565
				2566	std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner	4217ca8dc	2006-02-21 23:11:00 +0000	[diff] [blame]	2567	getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2568	EVT VT) const {
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2569	if (Constraint[0] != '{')
Douglas Gregor	7d9663c	2010-05-11 06:17:44 +0000	[diff] [blame]	2570	return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattner	a55079a	2006-02-01 01:29:47 +0000	[diff] [blame]	2571	assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
				2572
				2573	// Remove the braces from around the name.
Benjamin Kramer	05872ea	2009-11-12 20:36:59 +0000	[diff] [blame]	2574	StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2575
				2576	// Figure out which register class contains this reg.
Dan Gohman	6f0d024	2008-02-10 18:45:23 +0000	[diff] [blame]	2577	const TargetRegisterInfo *RI = TM.getRegisterInfo();
				2578	for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2579	E = RI->regclass_end(); RCI != E; ++RCI) {
				2580	const TargetRegisterClass RC = RCI;
Chris Lattner	b3befd4	2006-02-22 23:00:51 +0000	[diff] [blame]	2581
Dan Gohman	f451cb8	2010-02-10 16:03:48 +0000	[diff] [blame]	2582	// If none of the value types for this register class are valid, we
Chris Lattner	b3befd4	2006-02-22 23:00:51 +0000	[diff] [blame]	2583	// can't use it. For example, 64-bit reg classes on 32-bit targets.
				2584	bool isLegal = false;
				2585	for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
				2586	I != E; ++I) {
				2587	if (isTypeLegal(*I)) {
				2588	isLegal = true;
				2589	break;
				2590	}
				2591	}
				2592
				2593	if (!isLegal) continue;
				2594
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2595	for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
				2596	I != E; ++I) {
Benjamin Kramer	05872ea	2009-11-12 20:36:59 +0000	[diff] [blame]	2597	if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2598	return std::make_pair(*I, RC);
Chris Lattner	1efa40f	2006-02-22 00:56:39 +0000	[diff] [blame]	2599	}
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	2600	}
Chris Lattner	a55079a	2006-02-01 01:29:47 +0000	[diff] [blame]	2601
Douglas Gregor	7d9663c	2010-05-11 06:17:44 +0000	[diff] [blame]	2602	return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner	4ccb070	2006-01-26 20:37:03 +0000	[diff] [blame]	2603	}
Evan Cheng	30b37b5	2006-03-13 23:18:16 +0000	[diff] [blame]	2604
				2605	//===----------------------------------------------------------------------===//
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2606	// Constraint Selection.
				2607
Chris Lattner	6bdcda3	2008-10-17 16:47:46 +0000	[diff] [blame]	2608	/// isMatchingInputConstraint - Return true of this is an input operand that is
				2609	/// a matching constraint like "4".
				2610	bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner	58f15c4	2008-10-17 16:21:11 +0000	[diff] [blame]	2611	assert(!ConstraintCode.empty() && "No known constraint!");
				2612	return isdigit(ConstraintCode[0]);
				2613	}
				2614
				2615	/// getMatchedOperand - If this is an input matching constraint, this method
				2616	/// returns the output operand it matches.
				2617	unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
				2618	assert(!ConstraintCode.empty() && "No known constraint!");
				2619	return atoi(ConstraintCode.c_str());
				2620	}
				2621
				2622
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2623	/// getConstraintGenerality - Return an integer indicating how general CT
				2624	/// is.
				2625	static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
				2626	switch (CT) {
Torok Edwin	c23197a	2009-07-14 16:55:14 +0000	[diff] [blame]	2627	default: llvm_unreachable("Unknown constraint type!");
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2628	case TargetLowering::C_Other:
				2629	case TargetLowering::C_Unknown:
				2630	return 0;
				2631	case TargetLowering::C_Register:
				2632	return 1;
				2633	case TargetLowering::C_RegisterClass:
				2634	return 2;
				2635	case TargetLowering::C_Memory:
				2636	return 3;
				2637	}
				2638	}
				2639
				2640	/// ChooseConstraint - If there are multiple different constraints that we
				2641	/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner	24e1a9d	2008-04-27 01:49:46 +0000	[diff] [blame]	2642	/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2643	/// Other -> immediates and magic values
				2644	/// Register -> one specific register
				2645	/// RegisterClass -> a group of regs
				2646	/// Memory -> memory
				2647	/// Ideally, we would pick the most specific constraint possible: if we have
				2648	/// something that fits into a register, we would pick it. The problem here
				2649	/// is that if we have something that could either be in a register or in
				2650	/// memory that use of the register could cause selection of other
				2651	/// operands to fail: they might only succeed if we pick memory. Because of
				2652	/// this the heuristic we use is:
				2653	///
				2654	/// 1) If there is an 'other' constraint, and if the operand is valid for
				2655	/// that constraint, use it. This makes us take advantage of 'i'
				2656	/// constraints when available.
				2657	/// 2) Otherwise, pick the most general constraint present. This prefers
				2658	/// 'm' over 'r', for example.
				2659	///
				2660	static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen	1784d16	2010-06-25 21:55:36 +0000	[diff] [blame]	2661	const TargetLowering &TLI,
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2662	SDValue Op, SelectionDAG *DAG) {
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2663	assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
				2664	unsigned BestIdx = 0;
				2665	TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
				2666	int BestGenerality = -1;
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	2667
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2668	// Loop over the options, keeping track of the most general one.
				2669	for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
				2670	TargetLowering::ConstraintType CType =
				2671	TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	2672
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	2673	// If this is an 'other' constraint, see if the operand is valid for it.
				2674	// For example, on X86 we might have an 'rI' constraint. If the operand
				2675	// is an integer in the range [0..31] we want to use I (saving a load
				2676	// of a register), otherwise we must use 'r'.
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2677	if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	2678	assert(OpInfo.Codes[i].size() == 1 &&
				2679	"Unhandled multi-letter 'other' constraint");
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2680	std::vector<SDValue> ResultOps;
Dale Johannesen	1784d16	2010-06-25 21:55:36 +0000	[diff] [blame]	2681	TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	2682	ResultOps, *DAG);
				2683	if (!ResultOps.empty()) {
				2684	BestType = CType;
				2685	BestIdx = i;
				2686	break;
				2687	}
				2688	}
				2689
Dale Johannesen	a5989f8	2010-06-28 22:09:45 +0000	[diff] [blame]	2690	// Things with matching constraints can only be registers, per gcc
				2691	// documentation. This mainly affects "g" constraints.
				2692	if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
				2693	continue;
				2694
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2695	// This constraint letter is more general than the previous one, use it.
				2696	int Generality = getConstraintGenerality(CType);
				2697	if (Generality > BestGenerality) {
				2698	BestType = CType;
				2699	BestIdx = i;
				2700	BestGenerality = Generality;
				2701	}
				2702	}
				2703
				2704	OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
				2705	OpInfo.ConstraintType = BestType;
				2706	}
				2707
				2708	/// ComputeConstraintToUse - Determines the constraint code and constraint
				2709	/// type to use for the specific AsmOperandInfo, setting
				2710	/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	2711	void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2712	SDValue Op,
Chris Lattner	5a09690	2008-04-27 00:37:18 +0000	[diff] [blame]	2713	SelectionDAG *DAG) const {
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2714	assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
				2715
				2716	// Single-letter constraints ('r') are very common.
				2717	if (OpInfo.Codes.size() == 1) {
				2718	OpInfo.ConstraintCode = OpInfo.Codes[0];
				2719	OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
				2720	} else {
Dale Johannesen	1784d16	2010-06-25 21:55:36 +0000	[diff] [blame]	2721	ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2722	}
				2723
				2724	// 'X' matches anything.
				2725	if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
				2726	// Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	2727	// that matches labels). For Functions, the type here is the type of
Dale Johannesen	5339c55	2009-07-20 23:27:39 +0000	[diff] [blame]	2728	// the result, which is not what we want to look at; leave them alone.
				2729	Value *v = OpInfo.CallOperandVal;
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	2730	if (isa<BasicBlock>(v) \|\| isa<ConstantInt>(v) \|\| isa<Function>(v)) {
				2731	OpInfo.CallOperandVal = v;
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2732	return;
Dale Johannesen	8ea5ec6	2009-07-07 23:26:33 +0000	[diff] [blame]	2733	}
Chris Lattner	4376fea	2008-04-27 00:09:47 +0000	[diff] [blame]	2734
				2735	// Otherwise, try to resolve it to something we know about by looking at
				2736	// the actual operand type.
				2737	if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
				2738	OpInfo.ConstraintCode = Repl;
				2739	OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
				2740	}
				2741	}
				2742	}
				2743
				2744	//===----------------------------------------------------------------------===//
Evan Cheng	30b37b5	2006-03-13 23:18:16 +0000	[diff] [blame]	2745	// Loop Strength Reduction hooks
				2746	//===----------------------------------------------------------------------===//
				2747
Chris Lattner	1436bb6	2007-03-30 23:14:50 +0000	[diff] [blame]	2748	/// isLegalAddressingMode - Return true if the addressing mode represented
				2749	/// by AM is legal for this target, for a load/store of the specified type.
				2750	bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
				2751	const Type *Ty) const {
				2752	// The default implementation of this implements a conservative RISCy, r+r and
				2753	// r+i addr mode.
				2754
				2755	// Allows a sign-extended 16-bit immediate field.
				2756	if (AM.BaseOffs <= -(1LL << 16) \|\| AM.BaseOffs >= (1LL << 16)-1)
				2757	return false;
				2758
				2759	// No global is ever allowed as a base.
				2760	if (AM.BaseGV)
				2761	return false;
				2762
				2763	// Only support r+r,
				2764	switch (AM.Scale) {
				2765	case 0: // "r+i" or just "i", depending on HasBaseReg.
				2766	break;
				2767	case 1:
				2768	if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
				2769	return false;
				2770	// Otherwise we have r+r or r+i.
				2771	break;
				2772	case 2:
				2773	if (AM.HasBaseReg \|\| AM.BaseOffs) // 2r+r or 2r+i is not allowed.
				2774	return false;
				2775	// Allow 2*r as r+r.
				2776	break;
				2777	}
				2778
				2779	return true;
				2780	}
				2781
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2782	/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
				2783	/// return a DAG expression to select that will generate the same value by
				2784	/// multiplying by a magic number. See:
				2785	/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2786	SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
				2787	std::vector<SDNode> Created) const {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2788	EVT VT = N->getValueType(0);
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2789	DebugLoc dl= N->getDebugLoc();
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2790
				2791	// Check to see if we can do this.
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	2792	// FIXME: We should be more aggressive here.
				2793	if (!isTypeLegal(VT))
				2794	return SDValue();
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2795
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	2796	APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad	4e5ea55	2009-04-30 10:15:35 +0000	[diff] [blame]	2797	APInt::ms magics = d.magic();
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2798
				2799	// Multiply the numerator (operand 0) by the magic value
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	2800	// FIXME: We should support doing a MUL in a wider type
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2801	SDValue Q;
Dan Gohman	f560ffa	2009-01-28 17:46:25 +0000	[diff] [blame]	2802	if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2803	Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2804	DAG.getConstant(magics.m, VT));
Dan Gohman	f560ffa	2009-01-28 17:46:25 +0000	[diff] [blame]	2805	else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2806	Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2807	N->getOperand(0),
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2808	DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2809	else
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2810	return SDValue(); // No mulhs or equvialent
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2811	// If d > 0 and m < 0, add the numerator
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	2812	if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2813	Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2814	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2815	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2816	}
				2817	// If d < 0 and m > 0, subtract the numerator.
Eli Friedman	fc69cb4	2008-11-30 06:35:39 +0000	[diff] [blame]	2818	if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2819	Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2820	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2821	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2822	}
				2823	// Shift right algebraic if shift value is nonzero
				2824	if (magics.s > 0) {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2825	Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2826	DAG.getConstant(magics.s, getShiftAmountTy()));
				2827	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2828	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2829	}
				2830	// Extract the sign bit and add it to the quotient
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2831	SDValue T =
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2832	DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2833	getShiftAmountTy()));
				2834	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2835	Created->push_back(T.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2836	return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2837	}
				2838
				2839	/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
				2840	/// return a DAG expression to select that will generate the same value by
				2841	/// multiplying by a magic number. See:
				2842	/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2843	SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
				2844	std::vector<SDNode> Created) const {
Owen Anderson	e50ed30	2009-08-10 22:56:29 +0000	[diff] [blame]	2845	EVT VT = N->getValueType(0);
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2846	DebugLoc dl = N->getDebugLoc();
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	2847
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2848	// Check to see if we can do this.
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	2849	// FIXME: We should be more aggressive here.
				2850	if (!isTypeLegal(VT))
				2851	return SDValue();
				2852
				2853	// FIXME: We should use a narrower constant when the upper
				2854	// bits are known to be zero.
				2855	ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad	4e5ea55	2009-04-30 10:15:35 +0000	[diff] [blame]	2856	APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	2857
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2858	// Multiply the numerator (operand 0) by the magic value
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	2859	// FIXME: We should support doing a MUL in a wider type
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2860	SDValue Q;
Dan Gohman	f560ffa	2009-01-28 17:46:25 +0000	[diff] [blame]	2861	if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2862	Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2863	DAG.getConstant(magics.m, VT));
Dan Gohman	f560ffa	2009-01-28 17:46:25 +0000	[diff] [blame]	2864	else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2865	Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2866	N->getOperand(0),
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2867	DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman	525178c	2007-10-08 18:33:35 +0000	[diff] [blame]	2868	else
Dan Gohman	475871a	2008-07-27 21:46:04 +0000	[diff] [blame]	2869	return SDValue(); // No mulhu or equvialent
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2870	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2871	Created->push_back(Q.getNode());
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2872
				2873	if (magics.a == 0) {
Eli Friedman	201c977	2008-11-30 06:02:26 +0000	[diff] [blame]	2874	assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
				2875	"We shouldn't generate an undefined shift!");
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2876	return DAG.getNode(ISD::SRL, dl, VT, Q,
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2877	DAG.getConstant(magics.s, getShiftAmountTy()));
				2878	} else {
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2879	SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2880	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2881	Created->push_back(NPQ.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2882	NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2883	DAG.getConstant(1, getShiftAmountTy()));
				2884	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2885	Created->push_back(NPQ.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2886	NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2887	if (Created)
Gabor Greif	ba36cb5	2008-08-28 21:40:38 +0000	[diff] [blame]	2888	Created->push_back(NPQ.getNode());
Dale Johannesen	ff97d4f	2009-02-03 00:47:48 +0000	[diff] [blame]	2889	return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharth	dae9cbe	2006-05-16 17:42:15 +0000	[diff] [blame]	2890	DAG.getConstant(magics.s-1, getShiftAmountTy()));
				2891	}
				2892	}