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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
38STATISTIC(NumStores, "Number of stores added");
39STATISTIC(NumLoads , "Number of loads added");
40STATISTIC(NumReused, "Number of values reused");
41STATISTIC(NumDSE , "Number of dead stores elided");
42STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattnercd3245a2006-12-19 22:41:21 +000044namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000045 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000046
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000047 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000049 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000050 cl::Prefix,
51 cl::values(clEnumVal(simple, " simple spiller"),
52 clEnumVal(local, " local spiller"),
53 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000054 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000055}
56
Chris Lattner8c4d88d2004-09-30 01:54:45 +000057//===----------------------------------------------------------------------===//
58// VirtRegMap implementation
59//===----------------------------------------------------------------------===//
60
Chris Lattner29268692006-09-05 02:12:02 +000061VirtRegMap::VirtRegMap(MachineFunction &mf)
62 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
63 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
64 grow();
65}
66
Chris Lattner8c4d88d2004-09-30 01:54:45 +000067void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000068 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
69 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000070}
71
Chris Lattner8c4d88d2004-09-30 01:54:45 +000072int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
73 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000074 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000075 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000076 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
77 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
78 RC->getAlignment());
79 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000080 ++NumSpills;
81 return frameIndex;
82}
83
84void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
85 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000086 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000087 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000088 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000089}
90
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000092 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000093 // Move previous memory references folded to new instruction.
94 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000095 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000096 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
97 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000098 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000099 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000100
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000101 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000102 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
103 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000104 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000105 // Folded a two-address operand.
106 MRInfo = isModRef;
107 } else if (OldMI->getOperand(OpNo).isDef()) {
108 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000110 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000112
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000113 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000114 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000115}
116
Chris Lattner7f690e62004-09-30 02:15:18 +0000117void VirtRegMap::print(std::ostream &OS) const {
118 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000119
Chris Lattner7f690e62004-09-30 02:15:18 +0000120 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000121 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000122 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
123 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
124 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000125
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000126 }
127
128 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000129 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
130 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
131 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
132 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000133}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000134
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000135void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000136 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000137}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000138
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000139
140//===----------------------------------------------------------------------===//
141// Simple Spiller Implementation
142//===----------------------------------------------------------------------===//
143
144Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000145
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000146namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000147 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000148 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000149 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000150}
151
Chris Lattner35f27052006-05-01 21:16:03 +0000152bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000153 DOUT << "********** REWRITE MACHINE CODE **********\n";
154 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000155 const TargetMachine &TM = MF.getTarget();
156 const MRegisterInfo &MRI = *TM.getRegisterInfo();
157 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000158
Chris Lattner4ea1b822004-09-30 02:33:48 +0000159 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
160 // each vreg once (in the case where a spilled vreg is used by multiple
161 // operands). This is always smaller than the number of operands to the
162 // current machine instr, so it should be small.
163 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000164
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000165 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
166 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000167 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000168 MachineBasicBlock &MBB = *MBBI;
169 for (MachineBasicBlock::iterator MII = MBB.begin(),
170 E = MBB.end(); MII != E; ++MII) {
171 MachineInstr &MI = *MII;
172 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000173 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000174 if (MO.isRegister() && MO.getReg())
175 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
176 unsigned VirtReg = MO.getReg();
177 unsigned PhysReg = VRM.getPhys(VirtReg);
178 if (VRM.hasStackSlot(VirtReg)) {
179 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000180 const TargetRegisterClass* RC =
181 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000182
Chris Lattner886dd912005-04-04 21:35:34 +0000183 if (MO.isUse() &&
184 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
185 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000186 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000187 LoadedRegs.push_back(VirtReg);
188 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000189 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000190 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000191
Chris Lattner886dd912005-04-04 21:35:34 +0000192 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000193 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000194 ++NumStores;
195 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000196 }
Chris Lattner886dd912005-04-04 21:35:34 +0000197 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000198 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000199 } else {
200 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000201 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000202 }
Chris Lattner886dd912005-04-04 21:35:34 +0000203
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000204 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000205 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000206 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000207 }
208 return true;
209}
210
211//===----------------------------------------------------------------------===//
212// Local Spiller Implementation
213//===----------------------------------------------------------------------===//
214
215namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000216 /// LocalSpiller - This spiller does a simple pass over the machine basic
217 /// block to attempt to keep spills in registers as much as possible for
218 /// blocks that have low register pressure (the vreg may be spilled due to
219 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000220 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000222 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000223 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000224 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000225 MRI = MF.getTarget().getRegisterInfo();
226 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000227 DOUT << "\n**** Local spiller rewriting function '"
228 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000229
Chris Lattner7fb64342004-10-01 19:04:51 +0000230 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
231 MBB != E; ++MBB)
232 RewriteMBB(*MBB, VRM);
233 return true;
234 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000235 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000236 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000237 };
238}
239
Chris Lattner66cf80f2006-02-03 23:13:58 +0000240/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
241/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000242///
243/// Note that not all physregs are created equal here. In particular, some
244/// physregs are reloads that we are allowed to clobber or ignore at any time.
245/// Other physregs are values that the register allocated program is using that
246/// we cannot CHANGE, but we can read if we like. We keep track of this on a
247/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
248/// entries. The predicate 'canClobberPhysReg()' checks this bit and
249/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000250namespace {
251class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000252 const MRegisterInfo *MRI;
253 const TargetInstrInfo *TII;
254
255 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
256 // register values that are still available, due to being loaded or stored to,
Evan Cheng6b448092007-03-02 08:52:00 +0000257 // but not invalidated yet. It also tracks the instructions that defined
Evan Chengde4e9422007-02-25 09:51:27 +0000258 // or used the register.
Evan Cheng6b448092007-03-02 08:52:00 +0000259 typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo;
Evan Cheng91e23902007-02-23 01:13:26 +0000260 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000261
262 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
263 // which stack slot values are currently held by a physreg. This is used to
264 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
265 std::multimap<unsigned, int> PhysRegsAvailable;
266
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000267 void disallowClobberPhysRegOnly(unsigned PhysReg);
268
Chris Lattner66cf80f2006-02-03 23:13:58 +0000269 void ClobberPhysRegOnly(unsigned PhysReg);
270public:
271 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
272 : MRI(mri), TII(tii) {
273 }
274
Evan Cheng91e23902007-02-23 01:13:26 +0000275 const MRegisterInfo *getRegInfo() const { return MRI; }
276
Chris Lattner66cf80f2006-02-03 23:13:58 +0000277 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000278 /// physical register, return that PhysReg, otherwise return 0. It also
279 /// returns by reference the instruction that either defines or last uses
280 /// the register.
281 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
282 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
283 if (I != SpillSlotsAvailable.end()) {
Evan Cheng6b448092007-03-02 08:52:00 +0000284 if (!I->second.second.empty())
285 SSMI = I->second.second.back();
Evan Cheng91e23902007-02-23 01:13:26 +0000286 return I->second.first >> 1; // Remove the CanClobber bit.
287 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000288 return 0;
289 }
Evan Chengde4e9422007-02-25 09:51:27 +0000290
Evan Cheng6b448092007-03-02 08:52:00 +0000291 /// addLastUse - Add the last use information of all stack slots whose
Evan Chengde4e9422007-02-25 09:51:27 +0000292 /// values are available in the specific register.
Evan Cheng6b448092007-03-02 08:52:00 +0000293 void addLastUse(unsigned PhysReg, MachineInstr *Use) {
Evan Chengde4e9422007-02-25 09:51:27 +0000294 std::multimap<unsigned, int>::iterator I =
295 PhysRegsAvailable.lower_bound(PhysReg);
296 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
297 int Slot = I->second;
298 I++;
299
300 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
301 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
302 unsigned Val = II->second.first;
303 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
Evan Cheng6b448092007-03-02 08:52:00 +0000304 II->second.second.push_back(Use);
305 }
306 }
307
308 /// removeLastUse - Remove the last use information of all stack slots whose
309 /// values are available in the specific register.
310 void removeLastUse(unsigned PhysReg, MachineInstr *Use) {
311 std::multimap<unsigned, int>::iterator I =
312 PhysRegsAvailable.lower_bound(PhysReg);
313 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
314 int Slot = I->second;
315 I++;
316
317 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
318 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
319 unsigned Val = II->second.first;
320 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
321 if (II->second.second.back() == Use)
322 II->second.second.pop_back();
Evan Chengde4e9422007-02-25 09:51:27 +0000323 }
324 }
Chris Lattner540fec62006-02-25 01:51:33 +0000325
Chris Lattner66cf80f2006-02-03 23:13:58 +0000326 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000327 /// specified physreg. If CanClobber is true, the physreg can be modified at
328 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000329 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
330 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000331 // If this stack slot is thought to be available in some other physreg,
332 // remove its record.
333 ModifyStackSlot(Slot);
334
Chris Lattner66cf80f2006-02-03 23:13:58 +0000335 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng6b448092007-03-02 08:52:00 +0000336 std::vector<MachineInstr*> DefUses;
337 DefUses.push_back(MI);
Evan Cheng91e23902007-02-23 01:13:26 +0000338 SpillSlotsAvailable[Slot] =
Evan Cheng6b448092007-03-02 08:52:00 +0000339 std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000340
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000341 DOUT << "Remembering SS#" << Slot << " in physreg "
342 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000343 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000344
Chris Lattner593c9582006-02-03 23:28:46 +0000345 /// canClobberPhysReg - Return true if the spiller is allowed to change the
346 /// value of the specified stackslot register if it desires. The specified
347 /// stack slot must be available in a physreg for this query to make sense.
348 bool canClobberPhysReg(int Slot) const {
349 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000350 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000351 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000352
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000353 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
354 /// stackslot register. The register is still available but is no longer
355 /// allowed to be modifed.
356 void disallowClobberPhysReg(unsigned PhysReg);
357
Chris Lattner66cf80f2006-02-03 23:13:58 +0000358 /// ClobberPhysReg - This is called when the specified physreg changes
359 /// value. We use this to invalidate any info about stuff we thing lives in
360 /// it and any of its aliases.
361 void ClobberPhysReg(unsigned PhysReg);
362
363 /// ModifyStackSlot - This method is called when the value in a stack slot
364 /// changes. This removes information about which register the previous value
365 /// for this slot lives in (as the previous value is dead now).
366 void ModifyStackSlot(int Slot);
367};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000368}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000369
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000370/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
371/// stackslot register. The register is still available but is no longer
372/// allowed to be modifed.
373void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
374 std::multimap<unsigned, int>::iterator I =
375 PhysRegsAvailable.lower_bound(PhysReg);
376 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
377 int Slot = I->second;
378 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000379 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000380 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000381 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000382 DOUT << "PhysReg " << MRI->getName(PhysReg)
383 << " copied, it is available for use but can no longer be modified\n";
384 }
385}
386
387/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
388/// stackslot register and its aliases. The register and its aliases may
389/// still available but is no longer allowed to be modifed.
390void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
391 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
392 disallowClobberPhysRegOnly(*AS);
393 disallowClobberPhysRegOnly(PhysReg);
394}
395
Chris Lattner66cf80f2006-02-03 23:13:58 +0000396/// ClobberPhysRegOnly - This is called when the specified physreg changes
397/// value. We use this to invalidate any info about stuff we thing lives in it.
398void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
399 std::multimap<unsigned, int>::iterator I =
400 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000401 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000402 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000403 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000404 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000405 "Bidirectional map mismatch!");
406 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000407 DOUT << "PhysReg " << MRI->getName(PhysReg)
408 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000409 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000410}
411
Chris Lattner66cf80f2006-02-03 23:13:58 +0000412/// ClobberPhysReg - This is called when the specified physreg changes
413/// value. We use this to invalidate any info about stuff we thing lives in
414/// it and any of its aliases.
415void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000416 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000417 ClobberPhysRegOnly(*AS);
418 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000419}
420
Chris Lattner07cf1412006-02-03 00:36:31 +0000421/// ModifyStackSlot - This method is called when the value in a stack slot
422/// changes. This removes information about which register the previous value
423/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000424void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000425 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000426 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000427 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000428 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000429
430 // This register may hold the value of multiple stack slots, only remove this
431 // stack slot from the set of values the register contains.
432 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
433 for (; ; ++I) {
434 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
435 "Map inverse broken!");
436 if (I->second == Slot) break;
437 }
438 PhysRegsAvailable.erase(I);
439}
440
441
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000442
Chris Lattner7fb64342004-10-01 19:04:51 +0000443// ReusedOp - For each reused operand, we keep track of a bit of information, in
444// case we need to rollback upon processing a new operand. See comments below.
445namespace {
446 struct ReusedOp {
447 // The MachineInstr operand that reused an available value.
448 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000449
Chris Lattner7fb64342004-10-01 19:04:51 +0000450 // StackSlot - The spill slot of the value being reused.
451 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000452
Chris Lattner7fb64342004-10-01 19:04:51 +0000453 // PhysRegReused - The physical register the value was available in.
454 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000455
Chris Lattner7fb64342004-10-01 19:04:51 +0000456 // AssignedPhysReg - The physreg that was assigned for use by the reload.
457 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000458
459 // VirtReg - The virtual register itself.
460 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000461
Chris Lattner8a61a752005-10-06 17:19:06 +0000462 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
463 unsigned vreg)
464 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
465 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000466 };
Chris Lattner540fec62006-02-25 01:51:33 +0000467
468 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
469 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000470 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000471 MachineInstr &MI;
472 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000473 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000474 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000475 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000476 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000477 }
Chris Lattner540fec62006-02-25 01:51:33 +0000478
479 bool hasReuses() const {
480 return !Reuses.empty();
481 }
482
483 /// addReuse - If we choose to reuse a virtual register that is already
484 /// available instead of reloading it, remember that we did so.
485 void addReuse(unsigned OpNo, unsigned StackSlot,
486 unsigned PhysRegReused, unsigned AssignedPhysReg,
487 unsigned VirtReg) {
488 // If the reload is to the assigned register anyway, no undo will be
489 // required.
490 if (PhysRegReused == AssignedPhysReg) return;
491
492 // Otherwise, remember this.
493 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
494 AssignedPhysReg, VirtReg));
495 }
Evan Chenge077ef62006-11-04 00:21:55 +0000496
497 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000498 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000499 }
500
501 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000502 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000503 }
Chris Lattner540fec62006-02-25 01:51:33 +0000504
505 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
506 /// is some other operand that is using the specified register, either pick
507 /// a new register to use, or evict the previous reload and use this reg.
508 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
509 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000510 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000511 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000512 if (Reuses.empty()) return PhysReg; // This is most often empty.
513
514 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
515 ReusedOp &Op = Reuses[ro];
516 // If we find some other reuse that was supposed to use this register
517 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000518 // register. That is, unless its reload register has already been
519 // considered and subsequently rejected because it has also been reused
520 // by another operand.
521 if (Op.PhysRegReused == PhysReg &&
522 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000523 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000524 unsigned NewReg = Op.AssignedPhysReg;
525 Rejected.insert(PhysReg);
526 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000527 } else {
528 // Otherwise, we might also have a problem if a previously reused
529 // value aliases the new register. If so, codegen the previous reload
530 // and use this one.
531 unsigned PRRU = Op.PhysRegReused;
532 const MRegisterInfo *MRI = Spills.getRegInfo();
533 if (MRI->areAliases(PRRU, PhysReg)) {
534 // Okay, we found out that an alias of a reused register
535 // was used. This isn't good because it means we have
536 // to undo a previous reuse.
537 MachineBasicBlock *MBB = MI->getParent();
538 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000539 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
540
541 // Copy Op out of the vector and remove it, we're going to insert an
542 // explicit load for it.
543 ReusedOp NewOp = Op;
544 Reuses.erase(Reuses.begin()+ro);
545
546 // Ok, we're going to try to reload the assigned physreg into the
547 // slot that we were supposed to in the first place. However, that
548 // register could hold a reuse. Check to see if it conflicts or
549 // would prefer us to use a different register.
550 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000551 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000552
553 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
554 NewOp.StackSlot, AliasRC);
555 Spills.ClobberPhysReg(NewPhysReg);
556 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000557
558 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000559 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000560
Chris Lattnere53f4a02006-05-04 17:52:23 +0000561 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000562
Evan Cheng91e23902007-02-23 01:13:26 +0000563 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000564 ++NumLoads;
565 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000566 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000567
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000568 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000569 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000570
571 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000572 return PhysReg;
573 }
574 }
575 }
576 return PhysReg;
577 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000578
579 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
580 /// 'Rejected' set to remember which registers have been considered and
581 /// rejected for the reload. This avoids infinite looping in case like
582 /// this:
583 /// t1 := op t2, t3
584 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
585 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
586 /// t1 <- desires r1
587 /// sees r1 is taken by t2, tries t2's reload register r0
588 /// sees r0 is taken by t3, tries t3's reload register r1
589 /// sees r1 is taken by t2, tries t2's reload register r0 ...
590 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
591 AvailableSpills &Spills,
592 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000593 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000594 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
595 }
Chris Lattner540fec62006-02-25 01:51:33 +0000596 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000597}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000598
Chris Lattner7fb64342004-10-01 19:04:51 +0000599
600/// rewriteMBB - Keep track of which spills are available even after the
601/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000602void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000603
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000604 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000605
Chris Lattner66cf80f2006-02-03 23:13:58 +0000606 // Spills - Keep track of which spilled values are available in physregs so
607 // that we can choose to reuse the physregs instead of emitting reloads.
608 AvailableSpills Spills(MRI, TII);
609
Chris Lattner52b25db2004-10-01 19:47:12 +0000610 // MaybeDeadStores - When we need to write a value back into a stack slot,
611 // keep track of the inserted store. If the stack slot value is never read
612 // (because the value was used from some available register, for example), and
613 // subsequently stored to, the original store is dead. This map keeps track
614 // of inserted stores that are not used. If we see a subsequent store to the
615 // same stack slot, the original store is deleted.
616 std::map<int, MachineInstr*> MaybeDeadStores;
617
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000618 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
619
Chris Lattner7fb64342004-10-01 19:04:51 +0000620 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
621 MII != E; ) {
622 MachineInstr &MI = *MII;
623 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
624
Chris Lattner540fec62006-02-25 01:51:33 +0000625 /// ReusedOperands - Keep track of operand reuse in case we need to undo
626 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000627 ReuseInfo ReusedOperands(MI, MRI);
628
629 // Loop over all of the implicit defs, clearing them from our available
630 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000631 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
632 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000633 if (ImpDef) {
634 for ( ; *ImpDef; ++ImpDef) {
635 PhysRegsUsed[*ImpDef] = true;
636 ReusedOperands.markClobbered(*ImpDef);
637 Spills.ClobberPhysReg(*ImpDef);
638 }
639 }
640
Chris Lattner7fb64342004-10-01 19:04:51 +0000641 // Process all of the spilled uses and all non spilled reg references.
642 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
643 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000644 if (!MO.isRegister() || MO.getReg() == 0)
645 continue; // Ignore non-register operands.
646
647 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
648 // Ignore physregs for spilling, but remember that it is used by this
649 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000650 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000651 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000652 continue;
653 }
654
655 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
656 "Not a virtual or a physical register?");
657
658 unsigned VirtReg = MO.getReg();
659 if (!VRM.hasStackSlot(VirtReg)) {
660 // This virtual register was assigned a physreg!
661 unsigned Phys = VRM.getPhys(VirtReg);
662 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000663 if (MO.isDef())
664 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000665 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000666 continue;
667 }
668
669 // This virtual register is now known to be a spilled value.
670 if (!MO.isUse())
671 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000672
Chris Lattner50ea01e2005-09-09 20:29:51 +0000673 int StackSlot = VRM.getStackSlot(VirtReg);
674 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000675
Chris Lattner50ea01e2005-09-09 20:29:51 +0000676 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000677 MachineInstr *SSMI = NULL;
678 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000679 // This spilled operand might be part of a two-address operand. If this
680 // is the case, then changing it will necessarily require changing the
681 // def part of the instruction as well. However, in some cases, we
682 // aren't allowed to modify the reused register. If none of these cases
683 // apply, reuse it.
684 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000685 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000686 if (ti != -1 &&
687 MI.getOperand(ti).isReg() &&
688 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000689 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000690 // long as we are allowed to clobber the value and there isn't an
691 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000692 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
693 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000694 }
695
696 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000697 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000698 DOUT << "Reusing SS#" << StackSlot << " from physreg "
699 << MRI->getName(PhysReg) << " for vreg"
700 << VirtReg <<" instead of reloading into physreg "
701 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000702 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000703
Evan Cheng91e23902007-02-23 01:13:26 +0000704 // Extend the live range of the MI that last kill the register if
705 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000706 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000707 if (SSMI) {
708 MachineOperand *MOK = SSMI->findRegisterUseOperand(PhysReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000709 if (MOK) {
710 WasKill = MOK->isKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000711 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000712 }
Evan Cheng6b448092007-03-02 08:52:00 +0000713 }
714 if (ti == -1) {
715 // Unless it's the use of a two-address code, transfer the kill
716 // of the reused register to this use.
Evan Chenga7288df2007-03-03 06:32:37 +0000717 if (WasKill)
718 MI.getOperand(i).setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000719 Spills.addLastUse(PhysReg, &MI);
Evan Cheng50d25d72007-02-23 21:47:50 +0000720 }
Evan Cheng91e23902007-02-23 01:13:26 +0000721
Chris Lattneraddc55a2006-04-28 01:46:50 +0000722 // The only technical detail we have is that we don't know that
723 // PhysReg won't be clobbered by a reloaded stack slot that occurs
724 // later in the instruction. In particular, consider 'op V1, V2'.
725 // If V1 is available in physreg R0, we would choose to reuse it
726 // here, instead of reloading it into the register the allocator
727 // indicated (say R1). However, V2 might have to be reloaded
728 // later, and it might indicate that it needs to live in R0. When
729 // this occurs, we need to have information available that
730 // indicates it is safe to use R1 for the reload instead of R0.
731 //
732 // To further complicate matters, we might conflict with an alias,
733 // or R0 and R1 might not be compatible with each other. In this
734 // case, we actually insert a reload for V1 in R1, ensuring that
735 // we can get at R0 or its alias.
736 ReusedOperands.addReuse(i, StackSlot, PhysReg,
737 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000738 if (ti != -1)
739 // Only mark it clobbered if this is a use&def operand.
740 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000741 ++NumReused;
742 continue;
743 }
744
745 // Otherwise we have a situation where we have a two-address instruction
746 // whose mod/ref operand needs to be reloaded. This reload is already
747 // available in some register "PhysReg", but if we used PhysReg as the
748 // operand to our 2-addr instruction, the instruction would modify
749 // PhysReg. This isn't cool if something later uses PhysReg and expects
750 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000751 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000752 // To avoid this problem, and to avoid doing a load right after a store,
753 // we emit a copy from PhysReg into the designated register for this
754 // operand.
755 unsigned DesignatedReg = VRM.getPhys(VirtReg);
756 assert(DesignatedReg && "Must map virtreg to physreg!");
757
758 // Note that, if we reused a register for a previous operand, the
759 // register we want to reload into might not actually be
760 // available. If this occurs, use the register indicated by the
761 // reuser.
762 if (ReusedOperands.hasReuses())
763 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
764 Spills, MaybeDeadStores);
765
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000766 // If the mapped designated register is actually the physreg we have
767 // incoming, we don't need to inserted a dead copy.
768 if (DesignatedReg == PhysReg) {
769 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000770 DOUT << "Reusing SS#" << StackSlot << " from physreg "
771 << MRI->getName(PhysReg) << " for vreg"
772 << VirtReg
773 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000774 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000775 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000776 ++NumReused;
777 continue;
778 }
779
Chris Lattneraddc55a2006-04-28 01:46:50 +0000780 const TargetRegisterClass* RC =
781 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
782
783 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000784 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000785 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000786
787 // Extend the live range of the MI that last kill the register if
788 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000789 bool WasKill = false;
Evan Chengde4e9422007-02-25 09:51:27 +0000790 if (SSMI) {
791 MachineOperand *MOK = SSMI->findRegisterUseOperand(PhysReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000792 if (MOK) {
793 WasKill = MOK->isKill();
Evan Chengde4e9422007-02-25 09:51:27 +0000794 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000795 }
Evan Chengde4e9422007-02-25 09:51:27 +0000796 }
Evan Cheng6b448092007-03-02 08:52:00 +0000797 MachineInstr *CopyMI = prior(MII);
Evan Chenga7288df2007-03-03 06:32:37 +0000798 if (WasKill) {
799 // Transfer kill to the next use.
800 MachineOperand *MOU = CopyMI->findRegisterUseOperand(PhysReg);
801 MOU->setIsKill();
802 }
803 Spills.addLastUse(PhysReg, CopyMI);
Evan Chengde4e9422007-02-25 09:51:27 +0000804
Chris Lattneraddc55a2006-04-28 01:46:50 +0000805 // This invalidates DesignatedReg.
806 Spills.ClobberPhysReg(DesignatedReg);
807
Evan Cheng91e23902007-02-23 01:13:26 +0000808 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000809 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000810 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000811 ++NumReused;
812 continue;
813 }
814
815 // Otherwise, reload it and remember that we have it.
816 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000817 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000818 const TargetRegisterClass* RC =
819 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000820
Chris Lattner50ea01e2005-09-09 20:29:51 +0000821 // Note that, if we reused a register for a previous operand, the
822 // register we want to reload into might not actually be
823 // available. If this occurs, use the register indicated by the
824 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000825 if (ReusedOperands.hasReuses())
826 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
827 Spills, MaybeDeadStores);
828
Chris Lattner50ea01e2005-09-09 20:29:51 +0000829 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000830 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000831 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000832 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000833 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000834
835 // Any stores to this stack slot are not dead anymore.
836 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000837 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000838 // Assumes this is the last use. IsKill will be unset if reg is reused
839 // unless it's a two-address operand.
840 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
841 MI.getOperand(i).setIsKill();
Chris Lattner50ea01e2005-09-09 20:29:51 +0000842 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000843 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000844 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000845 }
846
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000847 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000848
Chris Lattner7fb64342004-10-01 19:04:51 +0000849 // If we have folded references to memory operands, make sure we clear all
850 // physical registers that may contain the value of the spilled virtual
851 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000852 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
853 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000854 DOUT << "Folded vreg: " << I->second.first << " MR: "
855 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000856 unsigned VirtReg = I->second.first;
857 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000858 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000859 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000860 continue;
861 }
862 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000863 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000864
865 // If this folded instruction is just a use, check to see if it's a
866 // straight load from the virt reg slot.
867 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
868 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000869 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000870 if (FrameIdx == SS) {
871 // If this spill slot is available, turn it into a copy (or nothing)
872 // instead of leaving it as a load!
Evan Chengde4e9422007-02-25 09:51:27 +0000873 MachineInstr *SSMI = NULL;
874 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000875 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000876 MachineFunction &MF = *MBB.getParent();
877 if (DestReg != InReg) {
878 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
879 MF.getSSARegMap()->getRegClass(VirtReg));
880 // Revisit the copy so we make sure to notice the effects of the
881 // operation on the destreg (either needing to RA it if it's
882 // virtual or needing to clobber any values if it's physical).
883 NextMII = &MI;
884 --NextMII; // backtrack to the copy.
Evan Chengde4e9422007-02-25 09:51:27 +0000885 } else
886 DOUT << "Removing now-noop copy: " << MI;
887
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000888 // Either way, the live range of the last kill of InReg has been
889 // extended. Remove its kill.
Evan Chenga7288df2007-03-03 06:32:37 +0000890 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000891 if (SSMI) {
892 MachineOperand *MOK = SSMI->findRegisterUseOperand(InReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000893 if (MOK) {
894 WasKill = MOK->isKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000895 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000896 }
Evan Cheng6b448092007-03-02 08:52:00 +0000897 }
898 if (NextMII != MBB.end()) {
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000899 // If NextMII uses InReg (must be the copy?), mark it killed.
Evan Chengde4e9422007-02-25 09:51:27 +0000900 MachineOperand *MOU = NextMII->findRegisterUseOperand(InReg);
901 if (MOU) {
Evan Chenga7288df2007-03-03 06:32:37 +0000902 if (WasKill)
903 MOU->setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000904 Spills.addLastUse(InReg, &(*NextMII));
Evan Chengde4e9422007-02-25 09:51:27 +0000905 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000906 }
Evan Chengde4e9422007-02-25 09:51:27 +0000907
Chris Lattner6ec36262006-10-12 17:45:38 +0000908 VRM.RemoveFromFoldedVirtMap(&MI);
909 MBB.erase(&MI);
910 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000911 }
Chris Lattnercea86882005-09-19 06:56:21 +0000912 }
913 }
914 }
915
916 // If this reference is not a use, any previous store is now dead.
917 // Otherwise, the store to this stack slot is not dead anymore.
918 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
919 if (MDSI != MaybeDeadStores.end()) {
920 if (MR & VirtRegMap::isRef) // Previous store is not dead.
921 MaybeDeadStores.erase(MDSI);
922 else {
923 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000924 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000925 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000926 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000927 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000928 MaybeDeadStores.erase(MDSI);
929 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000930 }
931 }
932
933 // If the spill slot value is available, and this is a new definition of
934 // the value, the value is not available anymore.
935 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000936 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000937 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000938
939 // If this is *just* a mod of the value, check to see if this is just a
940 // store to the spill slot (i.e. the spill got merged into the copy). If
941 // so, realize that the vreg is available now, and add the store to the
942 // MaybeDeadStore info.
943 int StackSlot;
944 if (!(MR & VirtRegMap::isRef)) {
945 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
946 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
947 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000948 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000949 // this as a potentially dead store in case there is a subsequent
950 // store into the stack slot without a read from it.
951 MaybeDeadStores[StackSlot] = &MI;
952
Chris Lattnercd816392006-02-02 23:29:36 +0000953 // If the stack slot value was previously available in some other
954 // register, change it now. Otherwise, make the register available,
955 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +0000956 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000957 }
958 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000959 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000960 }
961
Chris Lattner7fb64342004-10-01 19:04:51 +0000962 // Process all of the spilled defs.
963 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
964 MachineOperand &MO = MI.getOperand(i);
965 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
966 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000967
Chris Lattner7fb64342004-10-01 19:04:51 +0000968 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000969 // Check to see if this is a noop copy. If so, eliminate the
970 // instruction before considering the dest reg to be changed.
971 unsigned Src, Dst;
972 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
973 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000974 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng6b448092007-03-02 08:52:00 +0000975 Spills.removeLastUse(Src, &MI);
Chris Lattner29268692006-09-05 02:12:02 +0000976 MBB.erase(&MI);
977 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000978 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000979 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000980 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000981
982 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000983 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000984 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000985
986 // Check to see if this instruction is a load from a stack slot into
987 // a register. If so, this provides the stack slot value in the reg.
988 int FrameIdx;
989 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
990 assert(DestReg == VirtReg && "Unknown load situation!");
991
992 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +0000993 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000994 goto ProcessNextInst;
995 }
996
Chris Lattner29268692006-09-05 02:12:02 +0000997 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000998 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000999
Chris Lattner84e752a2006-02-03 03:06:49 +00001000 // The only vregs left are stack slot definitions.
1001 int StackSlot = VRM.getStackSlot(VirtReg);
1002 const TargetRegisterClass *RC =
1003 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001004
Chris Lattner29268692006-09-05 02:12:02 +00001005 // If this def is part of a two-address operand, make sure to execute
1006 // the store from the correct physical register.
1007 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001008 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001009 if (TiedOp != -1)
1010 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001011 else {
Chris Lattner29268692006-09-05 02:12:02 +00001012 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001013 if (ReusedOperands.isClobbered(PhysReg)) {
1014 // Another def has taken the assigned physreg. It must have been a
1015 // use&def which got it due to reuse. Undo the reuse!
1016 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1017 Spills, MaybeDeadStores);
1018 }
1019 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001020
Chris Lattner84e752a2006-02-03 03:06:49 +00001021 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +00001022 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001023 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001024 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001025 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001026
Chris Lattner84e752a2006-02-03 03:06:49 +00001027 // If there is a dead store to this stack slot, nuke it now.
1028 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1029 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001030 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001031 ++NumDSE;
1032 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001033 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001034 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001035 LastStore = next(MII);
1036
1037 // If the stack slot value was previously available in some other
1038 // register, change it now. Otherwise, make the register available,
1039 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001040 Spills.ModifyStackSlot(StackSlot);
1041 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001042 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001043 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001044
1045 // Check to see if this is a noop copy. If so, eliminate the
1046 // instruction before considering the dest reg to be changed.
1047 {
1048 unsigned Src, Dst;
1049 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1050 ++NumDCE;
1051 DOUT << "Removing now-noop copy: " << MI;
1052 MBB.erase(&MI);
1053 VRM.RemoveFromFoldedVirtMap(&MI);
1054 goto ProcessNextInst;
1055 }
1056 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001057 }
1058 }
Chris Lattnercea86882005-09-19 06:56:21 +00001059 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +00001060 MII = NextMII;
1061 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001062}
1063
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001064
1065
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001066llvm::Spiller* llvm::createSpiller() {
1067 switch (SpillerOpt) {
1068 default: assert(0 && "Unreachable!");
1069 case local:
1070 return new LocalSpiller();
1071 case simple:
1072 return new SimpleSpiller();
1073 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001074}