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Dan Gohmanb0cf29c2008-08-13 20:19:35 +00001///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the implementation of the FastISel class.
11//
12//===----------------------------------------------------------------------===//
13
Dan Gohman6f2766d2008-08-19 22:31:46 +000014#include "llvm/Instructions.h"
Dan Gohmanb0cf29c2008-08-13 20:19:35 +000015#include "llvm/CodeGen/FastISel.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/Target/TargetInstrInfo.h"
19using namespace llvm;
20
Dan Gohmanbdedd442008-08-20 00:11:48 +000021/// SelectBinaryOp - Select and emit code for a binary operator instruction,
22/// which has an opcode which directly corresponds to the given ISD opcode.
23///
24bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
25 DenseMap<const Value*, unsigned> &ValueMap) {
26 unsigned Op0 = ValueMap[I->getOperand(0)];
27 unsigned Op1 = ValueMap[I->getOperand(1)];
Dan Gohmana7f2dff2008-08-20 00:35:17 +000028 if (Op0 == 0 || Op1 == 0)
29 // Unhandled operand. Halt "fast" selection and bail.
30 return false;
31
Dan Gohmanbdedd442008-08-20 00:11:48 +000032 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
33 if (VT == MVT::Other || !VT.isSimple())
34 // Unhandled type. Halt "fast" selection and bail.
35 return false;
36
37 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
38 if (ResultReg == 0)
39 // Target-specific code wasn't able to find a machine opcode for
40 // the given ISD opcode and type. Halt "fast" selection and bail.
41 return false;
42
Dan Gohman8014e862008-08-20 00:23:20 +000043 // We successfully emitted code for the given LLVM Instruction.
Dan Gohmanbdedd442008-08-20 00:11:48 +000044 ValueMap[I] = ResultReg;
45 return true;
46}
47
48bool FastISel::SelectGetElementPtr(Instruction *I,
49 DenseMap<const Value*, unsigned> &ValueMap) {
50 // TODO: implement me
51 return false;
52}
53
Dan Gohmanb0cf29c2008-08-13 20:19:35 +000054BasicBlock::iterator
55FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
56 DenseMap<const Value*, unsigned> &ValueMap) {
57 BasicBlock::iterator I = Begin;
58
59 for (; I != End; ++I) {
60 switch (I->getOpcode()) {
Dan Gohman8014e862008-08-20 00:23:20 +000061 case Instruction::Add: {
62 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
63 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
64 }
65 case Instruction::Sub: {
66 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
67 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
68 }
69 case Instruction::Mul: {
70 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
71 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
72 }
Dan Gohmanbdedd442008-08-20 00:11:48 +000073 case Instruction::SDiv:
74 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
75 case Instruction::UDiv:
76 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
77 case Instruction::FDiv:
78 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
79 case Instruction::SRem:
80 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
81 case Instruction::URem:
82 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
83 case Instruction::FRem:
84 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
85 case Instruction::Shl:
86 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
87 case Instruction::LShr:
88 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
89 case Instruction::AShr:
90 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
91 case Instruction::And:
92 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
93 case Instruction::Or:
94 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
95 case Instruction::Xor:
96 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
97
98 case Instruction::GetElementPtr:
99 if (!SelectGetElementPtr(I, ValueMap)) return I;
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000100 break;
Dan Gohmanbdedd442008-08-20 00:11:48 +0000101
Dan Gohman6f2766d2008-08-19 22:31:46 +0000102 case Instruction::Br: {
103 BranchInst *BI = cast<BranchInst>(I);
104
105 // For now, check for and handle just the most trivial case: an
106 // unconditional fall-through branch.
107 if (BI->isUnconditional() &&
108 next(MachineFunction::iterator(MBB))->getBasicBlock() ==
109 BI->getSuccessor(0)) {
110 MBB->addSuccessor(next(MachineFunction::iterator(MBB)));
111 break;
112 }
113
114 // Something more complicated. Halt "fast" selection and bail.
115 return I;
116 }
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000117 default:
118 // Unhandled instruction. Halt "fast" selection and bail.
119 return I;
120 }
121 }
122
123 return I;
124}
125
Dan Gohmane285a742008-08-14 21:51:29 +0000126FastISel::~FastISel() {}
127
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000128unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
129 return 0;
130}
131
132unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
133 unsigned /*Op0*/) {
134 return 0;
135}
136
137unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
138 unsigned /*Op0*/, unsigned /*Op0*/) {
139 return 0;
140}
141
142unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
143 const TargetRegisterClass* RC) {
144 MachineRegisterInfo &MRI = MF->getRegInfo();
145 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000146 unsigned ResultReg = MRI.createVirtualRegister(RC);
147
Dan Gohman8133a522008-08-19 20:46:54 +0000148 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000149
150 MBB->push_back(MI);
151 return ResultReg;
152}
153
154unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
155 const TargetRegisterClass *RC,
156 unsigned Op0) {
157 MachineRegisterInfo &MRI = MF->getRegInfo();
158 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000159 unsigned ResultReg = MRI.createVirtualRegister(RC);
160
Dan Gohman8133a522008-08-19 20:46:54 +0000161 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000162 MI->addOperand(MachineOperand::CreateReg(Op0, false));
163
164 MBB->push_back(MI);
165 return ResultReg;
166}
167
168unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
169 const TargetRegisterClass *RC,
170 unsigned Op0, unsigned Op1) {
171 MachineRegisterInfo &MRI = MF->getRegInfo();
172 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000173 unsigned ResultReg = MRI.createVirtualRegister(RC);
174
Dan Gohman8133a522008-08-19 20:46:54 +0000175 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
Dan Gohmanb0cf29c2008-08-13 20:19:35 +0000176 MI->addOperand(MachineOperand::CreateReg(Op0, false));
177 MI->addOperand(MachineOperand::CreateReg(Op1, false));
178
179 MBB->push_back(MI);
180 return ResultReg;
181}