Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / aafe626c7fa9f99150cccd27d0151a2cf7c8c00b / . / lib / CodeGen / SelectionDAG / TargetLowering.cpp
blob: b74f600cfa2db964ef62ae2de38c5bc65f117341 [file] [log] [blame]
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]1//===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]2//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]7//
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
Chris Lattneraf76e592009-08-22 20:48:53 +0000[diff] [blame]15#include "llvm/MC/MCAsmInfo.h"
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]16#include "llvm/MC/MCExpr.h"
Owen Anderson07000c62006-05-12 06:33:49 +0000[diff] [blame]17#include "llvm/Target/TargetData.h"
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]18#include "llvm/Target/TargetLoweringObjectFile.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]19#include "llvm/Target/TargetMachine.h"
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]21#include "llvm/GlobalVariable.h"
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]22#include "llvm/DerivedTypes.h"
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]23#include "llvm/CodeGen/Analysis.h"
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]25#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunction.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]27#include "llvm/CodeGen/SelectionDAG.h"
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]28#include "llvm/ADT/STLExtras.h"
Torok Edwinc25e7582009-07-11 20:10:48 +0000[diff] [blame]29#include "llvm/Support/ErrorHandling.h"
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]30#include "llvm/Support/MathExtras.h"
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]31using namespace llvm;
32
Rafael Espindola9a580232009-02-27 13:37:18 +0000[diff] [blame]33namespace llvm {
34TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
35 bool isLocal = GV->hasLocalLinkage();
36 bool isDeclaration = GV->isDeclaration();
37 // FIXME: what should we do for protected and internal visibility?
38 // For variables, is internal different from hidden?
39 bool isHidden = GV->hasHiddenVisibility();
40
41 if (reloc == Reloc::PIC_) {
42 if (isLocal || isHidden)
43 return TLSModel::LocalDynamic;
44 else
45 return TLSModel::GeneralDynamic;
46 } else {
47 if (!isDeclaration || isHidden)
48 return TLSModel::LocalExec;
49 else
50 return TLSModel::InitialExec;
51 }
52}
53}
54
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]55/// InitLibcallNames - Set default libcall names.
56///
Evan Cheng79cca502007-01-12 22:51:10 +0000[diff] [blame]57static void InitLibcallNames(const char **Names) {
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]58 Names[RTLIB::SHL_I16] = "__ashlhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]59 Names[RTLIB::SHL_I32] = "__ashlsi3";
60 Names[RTLIB::SHL_I64] = "__ashldi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]61 Names[RTLIB::SHL_I128] = "__ashlti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]62 Names[RTLIB::SRL_I16] = "__lshrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]63 Names[RTLIB::SRL_I32] = "__lshrsi3";
64 Names[RTLIB::SRL_I64] = "__lshrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]65 Names[RTLIB::SRL_I128] = "__lshrti3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]66 Names[RTLIB::SRA_I16] = "__ashrhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]67 Names[RTLIB::SRA_I32] = "__ashrsi3";
68 Names[RTLIB::SRA_I64] = "__ashrdi3";
Duncan Sandsdddc6292008-07-11 16:52:29 +0000[diff] [blame]69 Names[RTLIB::SRA_I128] = "__ashrti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]70 Names[RTLIB::MUL_I8] = "__mulqi3";
Anton Korobeynikovc31642f2009-05-03 13:14:08 +0000[diff] [blame]71 Names[RTLIB::MUL_I16] = "__mulhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]72 Names[RTLIB::MUL_I32] = "__mulsi3";
73 Names[RTLIB::MUL_I64] = "__muldi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]74 Names[RTLIB::MUL_I128] = "__multi3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]75 Names[RTLIB::SDIV_I8] = "__divqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]76 Names[RTLIB::SDIV_I16] = "__divhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]77 Names[RTLIB::SDIV_I32] = "__divsi3";
78 Names[RTLIB::SDIV_I64] = "__divdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]79 Names[RTLIB::SDIV_I128] = "__divti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]80 Names[RTLIB::UDIV_I8] = "__udivqi3";
Anton Korobeynikovfb3f84f2009-05-08 18:50:54 +0000[diff] [blame]81 Names[RTLIB::UDIV_I16] = "__udivhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]82 Names[RTLIB::UDIV_I32] = "__udivsi3";
83 Names[RTLIB::UDIV_I64] = "__udivdi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]84 Names[RTLIB::UDIV_I128] = "__udivti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]85 Names[RTLIB::SREM_I8] = "__modqi3";
Anton Korobeynikov813090c2009-05-03 13:18:16 +0000[diff] [blame]86 Names[RTLIB::SREM_I16] = "__modhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]87 Names[RTLIB::SREM_I32] = "__modsi3";
88 Names[RTLIB::SREM_I64] = "__moddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]89 Names[RTLIB::SREM_I128] = "__modti3";
Anton Korobeynikov8983da72009-11-07 17:14:39 +0000[diff] [blame]90 Names[RTLIB::UREM_I8] = "__umodqi3";
Anton Korobeynikov9fe9c8e2009-05-03 13:19:57 +0000[diff] [blame]91 Names[RTLIB::UREM_I16] = "__umodhi3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]92 Names[RTLIB::UREM_I32] = "__umodsi3";
93 Names[RTLIB::UREM_I64] = "__umoddi3";
Duncan Sands5ac319a2008-07-10 15:35:05 +0000[diff] [blame]94 Names[RTLIB::UREM_I128] = "__umodti3";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]95 Names[RTLIB::NEG_I32] = "__negsi2";
96 Names[RTLIB::NEG_I64] = "__negdi2";
97 Names[RTLIB::ADD_F32] = "__addsf3";
98 Names[RTLIB::ADD_F64] = "__adddf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]99 Names[RTLIB::ADD_F80] = "__addxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]100 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]101 Names[RTLIB::SUB_F32] = "__subsf3";
102 Names[RTLIB::SUB_F64] = "__subdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]103 Names[RTLIB::SUB_F80] = "__subxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]104 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]105 Names[RTLIB::MUL_F32] = "__mulsf3";
106 Names[RTLIB::MUL_F64] = "__muldf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]107 Names[RTLIB::MUL_F80] = "__mulxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]109 Names[RTLIB::DIV_F32] = "__divsf3";
110 Names[RTLIB::DIV_F64] = "__divdf3";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]111 Names[RTLIB::DIV_F80] = "__divxf3";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]112 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]113 Names[RTLIB::REM_F32] = "fmodf";
114 Names[RTLIB::REM_F64] = "fmod";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]115 Names[RTLIB::REM_F80] = "fmodl";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]116 Names[RTLIB::REM_PPCF128] = "fmodl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]117 Names[RTLIB::POWI_F32] = "__powisf2";
118 Names[RTLIB::POWI_F64] = "__powidf2";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]119 Names[RTLIB::POWI_F80] = "__powixf2";
120 Names[RTLIB::POWI_PPCF128] = "__powitf2";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]121 Names[RTLIB::SQRT_F32] = "sqrtf";
122 Names[RTLIB::SQRT_F64] = "sqrt";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]123 Names[RTLIB::SQRT_F80] = "sqrtl";
124 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
Dale Johannesen7794f2a2008-09-04 00:47:13 +0000[diff] [blame]125 Names[RTLIB::LOG_F32] = "logf";
126 Names[RTLIB::LOG_F64] = "log";
127 Names[RTLIB::LOG_F80] = "logl";
128 Names[RTLIB::LOG_PPCF128] = "logl";
129 Names[RTLIB::LOG2_F32] = "log2f";
130 Names[RTLIB::LOG2_F64] = "log2";
131 Names[RTLIB::LOG2_F80] = "log2l";
132 Names[RTLIB::LOG2_PPCF128] = "log2l";
133 Names[RTLIB::LOG10_F32] = "log10f";
134 Names[RTLIB::LOG10_F64] = "log10";
135 Names[RTLIB::LOG10_F80] = "log10l";
136 Names[RTLIB::LOG10_PPCF128] = "log10l";
137 Names[RTLIB::EXP_F32] = "expf";
138 Names[RTLIB::EXP_F64] = "exp";
139 Names[RTLIB::EXP_F80] = "expl";
140 Names[RTLIB::EXP_PPCF128] = "expl";
141 Names[RTLIB::EXP2_F32] = "exp2f";
142 Names[RTLIB::EXP2_F64] = "exp2";
143 Names[RTLIB::EXP2_F80] = "exp2l";
144 Names[RTLIB::EXP2_PPCF128] = "exp2l";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]145 Names[RTLIB::SIN_F32] = "sinf";
146 Names[RTLIB::SIN_F64] = "sin";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]147 Names[RTLIB::SIN_F80] = "sinl";
148 Names[RTLIB::SIN_PPCF128] = "sinl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]149 Names[RTLIB::COS_F32] = "cosf";
150 Names[RTLIB::COS_F64] = "cos";
Duncan Sands007f9842008-01-10 10:28:30 +0000[diff] [blame]151 Names[RTLIB::COS_F80] = "cosl";
152 Names[RTLIB::COS_PPCF128] = "cosl";
Dan Gohmane54be102007-10-11 23:09:10 +0000[diff] [blame]153 Names[RTLIB::POW_F32] = "powf";
154 Names[RTLIB::POW_F64] = "pow";
155 Names[RTLIB::POW_F80] = "powl";
156 Names[RTLIB::POW_PPCF128] = "powl";
Dan Gohman2bb1e3e2008-08-21 18:38:14 +0000[diff] [blame]157 Names[RTLIB::CEIL_F32] = "ceilf";
158 Names[RTLIB::CEIL_F64] = "ceil";
159 Names[RTLIB::CEIL_F80] = "ceill";
160 Names[RTLIB::CEIL_PPCF128] = "ceill";
161 Names[RTLIB::TRUNC_F32] = "truncf";
162 Names[RTLIB::TRUNC_F64] = "trunc";
163 Names[RTLIB::TRUNC_F80] = "truncl";
164 Names[RTLIB::TRUNC_PPCF128] = "truncl";
165 Names[RTLIB::RINT_F32] = "rintf";
166 Names[RTLIB::RINT_F64] = "rint";
167 Names[RTLIB::RINT_F80] = "rintl";
168 Names[RTLIB::RINT_PPCF128] = "rintl";
169 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
170 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
171 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
172 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
173 Names[RTLIB::FLOOR_F32] = "floorf";
174 Names[RTLIB::FLOOR_F64] = "floor";
175 Names[RTLIB::FLOOR_F80] = "floorl";
176 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Duncan Sandsd2c817e2010-03-14 21:08:40 +0000[diff] [blame]177 Names[RTLIB::COPYSIGN_F32] = "copysignf";
178 Names[RTLIB::COPYSIGN_F64] = "copysign";
179 Names[RTLIB::COPYSIGN_F80] = "copysignl";
180 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]181 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]182 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
183 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]184 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]185 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
186 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
187 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
188 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]189 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
190 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]191 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
192 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]193 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]194 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
195 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]196 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
197 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]198 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
Duncan Sandsbe1ad4d2008-07-10 15:33:02 +0000[diff] [blame]199 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]200 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]201 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]202 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]203 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]204 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]205 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
206 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]207 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
208 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]209 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]210 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
211 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]212 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
213 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]214 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]215 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
216 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]217 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
Duncan Sands041cde22008-06-25 20:24:48 +0000[diff] [blame]218 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]219 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
Dan Gohmana2e94852008-03-10 23:03:31 +0000[diff] [blame]220 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]221 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
222 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
Duncan Sands9bed0f52008-07-11 16:57:02 +0000[diff] [blame]223 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
224 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]225 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
226 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]227 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
228 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
Dan Gohmand91446d2008-03-05 01:08:17 +0000[diff] [blame]229 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
230 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
231 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
232 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]233 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
234 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]235 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
236 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]237 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
238 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
Duncan Sandsac6cece2008-07-11 17:00:14 +0000[diff] [blame]239 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
240 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
241 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
242 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
243 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
244 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]245 Names[RTLIB::OEQ_F32] = "__eqsf2";
246 Names[RTLIB::OEQ_F64] = "__eqdf2";
247 Names[RTLIB::UNE_F32] = "__nesf2";
248 Names[RTLIB::UNE_F64] = "__nedf2";
249 Names[RTLIB::OGE_F32] = "__gesf2";
250 Names[RTLIB::OGE_F64] = "__gedf2";
251 Names[RTLIB::OLT_F32] = "__ltsf2";
252 Names[RTLIB::OLT_F64] = "__ltdf2";
253 Names[RTLIB::OLE_F32] = "__lesf2";
254 Names[RTLIB::OLE_F64] = "__ledf2";
255 Names[RTLIB::OGT_F32] = "__gtsf2";
256 Names[RTLIB::OGT_F64] = "__gtdf2";
257 Names[RTLIB::UO_F32] = "__unordsf2";
258 Names[RTLIB::UO_F64] = "__unorddf2";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]259 Names[RTLIB::O_F32] = "__unordsf2";
260 Names[RTLIB::O_F64] = "__unorddf2";
Sanjiv Guptaa114baa2009-07-30 09:12:56 +0000[diff] [blame]261 Names[RTLIB::MEMCPY] = "memcpy";
262 Names[RTLIB::MEMMOVE] = "memmove";
263 Names[RTLIB::MEMSET] = "memset";
Duncan Sandsb0f1e172009-05-22 20:36:31 +0000[diff] [blame]264 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]265 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
Jim Grosbachef6eb9c2010-06-18 23:03:10 +0000[diff] [blame]269 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
Jim Grosbache03262f2010-06-18 21:43:38 +0000[diff] [blame]273 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
277 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
281 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
282 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
283 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
284 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
285 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
286 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
287 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
288 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
289 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and-xor_4";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
293 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]297}
298
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]299/// InitLibcallCallingConvs - Set default libcall CallingConvs.
300///
301static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
302 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
303 CCs[i] = CallingConv::C;
304 }
305}
306
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]307/// getFPEXT - Return the FPEXT_*_* value for the given types, or
308/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]309RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]310 if (OpVT == MVT::f32) {
311 if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]312 return FPEXT_F32_F64;
313 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]314
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]315 return UNKNOWN_LIBCALL;
316}
317
318/// getFPROUND - Return the FPROUND_*_* value for the given types, or
319/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]320RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]321 if (RetVT == MVT::f32) {
322 if (OpVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]323 return FPROUND_F64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]324 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]325 return FPROUND_F80_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]326 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]327 return FPROUND_PPCF128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]328 } else if (RetVT == MVT::f64) {
329 if (OpVT == MVT::f80)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]330 return FPROUND_F80_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]331 if (OpVT == MVT::ppcf128)
Bruno Cardoso Lopese36bfe62008-08-07 19:01:24 +0000[diff] [blame]332 return FPROUND_PPCF128_F64;
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]333 }
Anton Korobeynikov927411b2010-03-14 18:42:24 +0000[diff] [blame]334
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]335 return UNKNOWN_LIBCALL;
336}
337
338/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
339/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]340RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]341 if (OpVT == MVT::f32) {
342 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]343 return FPTOSINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]344 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]345 return FPTOSINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]346 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]347 return FPTOSINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]348 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]349 return FPTOSINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]350 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]351 return FPTOSINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]352 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]353 if (RetVT == MVT::i8)
354 return FPTOSINT_F64_I8;
355 if (RetVT == MVT::i16)
356 return FPTOSINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]357 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]358 return FPTOSINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]359 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]360 return FPTOSINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]361 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]362 return FPTOSINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]363 } else if (OpVT == MVT::f80) {
364 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]365 return FPTOSINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]366 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]367 return FPTOSINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]368 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]369 return FPTOSINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]370 } else if (OpVT == MVT::ppcf128) {
371 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]372 return FPTOSINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]373 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]374 return FPTOSINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]375 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]376 return FPTOSINT_PPCF128_I128;
377 }
378 return UNKNOWN_LIBCALL;
379}
380
381/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
382/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]383RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]384 if (OpVT == MVT::f32) {
385 if (RetVT == MVT::i8)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]386 return FPTOUINT_F32_I8;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]387 if (RetVT == MVT::i16)
Sanjiv Gupta8aa207e2009-06-16 09:03:58 +0000[diff] [blame]388 return FPTOUINT_F32_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]389 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]390 return FPTOUINT_F32_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]391 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]392 return FPTOUINT_F32_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]393 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]394 return FPTOUINT_F32_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]395 } else if (OpVT == MVT::f64) {
Anton Korobeynikovde0118c2010-03-26 21:32:14 +0000[diff] [blame]396 if (RetVT == MVT::i8)
397 return FPTOUINT_F64_I8;
398 if (RetVT == MVT::i16)
399 return FPTOUINT_F64_I16;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]400 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]401 return FPTOUINT_F64_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]402 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]403 return FPTOUINT_F64_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]404 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]405 return FPTOUINT_F64_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]406 } else if (OpVT == MVT::f80) {
407 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]408 return FPTOUINT_F80_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]409 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]410 return FPTOUINT_F80_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]411 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]412 return FPTOUINT_F80_I128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]413 } else if (OpVT == MVT::ppcf128) {
414 if (RetVT == MVT::i32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]415 return FPTOUINT_PPCF128_I32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]416 if (RetVT == MVT::i64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]417 return FPTOUINT_PPCF128_I64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]418 if (RetVT == MVT::i128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]419 return FPTOUINT_PPCF128_I128;
420 }
421 return UNKNOWN_LIBCALL;
422}
423
424/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
425/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]426RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]427 if (OpVT == MVT::i32) {
428 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]429 return SINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]430 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]431 return SINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]432 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]433 return SINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]434 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]435 return SINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]436 } else if (OpVT == MVT::i64) {
437 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]438 return SINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]439 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]440 return SINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]441 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]442 return SINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]443 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]444 return SINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]445 } else if (OpVT == MVT::i128) {
446 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]447 return SINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]448 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]449 return SINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]450 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]451 return SINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]452 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]453 return SINTTOFP_I128_PPCF128;
454 }
455 return UNKNOWN_LIBCALL;
456}
457
458/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
459/// UNKNOWN_LIBCALL if there is none.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]460RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]461 if (OpVT == MVT::i32) {
462 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]463 return UINTTOFP_I32_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]464 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]465 return UINTTOFP_I32_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]466 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]467 return UINTTOFP_I32_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]468 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]469 return UINTTOFP_I32_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]470 } else if (OpVT == MVT::i64) {
471 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]472 return UINTTOFP_I64_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]473 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]474 return UINTTOFP_I64_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]475 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]476 return UINTTOFP_I64_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]477 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]478 return UINTTOFP_I64_PPCF128;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]479 } else if (OpVT == MVT::i128) {
480 if (RetVT == MVT::f32)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]481 return UINTTOFP_I128_F32;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]482 else if (RetVT == MVT::f64)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]483 return UINTTOFP_I128_F64;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]484 else if (RetVT == MVT::f80)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]485 return UINTTOFP_I128_F80;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]486 else if (RetVT == MVT::ppcf128)
Duncan Sandsb2ff8852008-07-17 02:36:29 +0000[diff] [blame]487 return UINTTOFP_I128_PPCF128;
488 }
489 return UNKNOWN_LIBCALL;
490}
491
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]492/// InitCmpLibcallCCs - Set default comparison libcall CC.
493///
494static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
495 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
496 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
497 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
498 CCs[RTLIB::UNE_F32] = ISD::SETNE;
499 CCs[RTLIB::UNE_F64] = ISD::SETNE;
500 CCs[RTLIB::OGE_F32] = ISD::SETGE;
501 CCs[RTLIB::OGE_F64] = ISD::SETGE;
502 CCs[RTLIB::OLT_F32] = ISD::SETLT;
503 CCs[RTLIB::OLT_F64] = ISD::SETLT;
504 CCs[RTLIB::OLE_F32] = ISD::SETLE;
505 CCs[RTLIB::OLE_F64] = ISD::SETLE;
506 CCs[RTLIB::OGT_F32] = ISD::SETGT;
507 CCs[RTLIB::OGT_F64] = ISD::SETGT;
508 CCs[RTLIB::UO_F32] = ISD::SETNE;
509 CCs[RTLIB::UO_F64] = ISD::SETNE;
510 CCs[RTLIB::O_F32] = ISD::SETEQ;
511 CCs[RTLIB::O_F64] = ISD::SETEQ;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]512}
513
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]514/// NOTE: The constructor takes ownership of TLOF.
Dan Gohmanf0757b02010-04-21 01:34:56 +0000[diff] [blame]515TargetLowering::TargetLowering(const TargetMachine &tm,
516 const TargetLoweringObjectFile *tlof)
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]517 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]518 // All operations default to being supported.
519 memset(OpActions, 0, sizeof(OpActions));
Evan Cheng03294662008-10-14 21:26:46 +0000[diff] [blame]520 memset(LoadExtActions, 0, sizeof(LoadExtActions));
Chris Lattnerddf89562008-01-17 19:59:44 +0000[diff] [blame]521 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
Chris Lattnerc9133f92008-01-18 19:36:20 +0000[diff] [blame]522 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
Evan Cheng7f042682008-10-15 02:05:31 +0000[diff] [blame]523 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Dan Gohman93f81e22007-07-09 20:49:44 +0000[diff] [blame]524
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]525 // Set default actions for various operations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]526 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]527 // Default all indexed load / store to expand.
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]528 for (unsigned IM = (unsigned)ISD::PRE_INC;
529 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]530 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
531 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]532 }
Chris Lattner1a3048b2007-12-22 20:47:56 +0000[diff] [blame]533
534 // These operations default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]535 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
Evan Cheng5ff839f2006-11-09 18:56:43 +0000[diff] [blame]537 }
Evan Chengd2cde682008-03-10 19:38:10 +0000[diff] [blame]538
539 // Most targets ignore the @llvm.prefetch intrinsic.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]540 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]541
542 // ConstantFP nodes default to expand. Targets can either change this to
Evan Chengeb2f9692009-10-27 19:56:55 +0000[diff] [blame]543 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
Nate Begemane1795842008-02-14 08:57:00 +0000[diff] [blame]544 // to optimize expansions for certain constants.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]545 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
546 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]548
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]549 // These library functions default to expand.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]550 setOperationAction(ISD::FLOG , MVT::f64, Expand);
551 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
552 setOperationAction(ISD::FLOG10,MVT::f64, Expand);
553 setOperationAction(ISD::FEXP , MVT::f64, Expand);
554 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
555 setOperationAction(ISD::FLOG , MVT::f32, Expand);
556 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
557 setOperationAction(ISD::FLOG10,MVT::f32, Expand);
558 setOperationAction(ISD::FEXP , MVT::f32, Expand);
559 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
Dale Johannesen0bb41602008-09-22 21:57:32 +0000[diff] [blame]560
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]561 // Default ISD::TRAP to expand (which turns it into abort).
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]562 setOperationAction(ISD::TRAP, MVT::Other, Expand);
Chris Lattner41bab0b2008-01-15 21:58:08 +0000[diff] [blame]563
Owen Andersona69571c2006-05-03 01:29:57 +0000[diff] [blame]564 IsLittleEndian = TD->isLittleEndian();
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]565 ShiftAmountTy = PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]566 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
Owen Anderson718cb662007-09-07 04:06:50 +0000[diff] [blame]567 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Evan Chenga03a5dc2006-02-14 08:38:30 +0000[diff] [blame]568 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
Evan Cheng6ebf7bc2009-05-13 21:42:09 +0000[diff] [blame]569 benefitFromCodePlacementOpt = false;
Anton Korobeynikovd27a2582006-12-10 23:12:42 +0000[diff] [blame]570 UseUnderscoreSetJmp = false;
571 UseUnderscoreLongJmp = false;
Chris Lattner66180392007-02-25 01:28:05 +0000[diff] [blame]572 SelectIsExpensive = false;
Nate Begeman405e3ec2005-10-21 00:02:42 +0000[diff] [blame]573 IntDivIsCheap = false;
574 Pow2DivIsCheap = false;
Chris Lattneree4a7652006-01-25 18:57:15 +0000[diff] [blame]575 StackPointerRegisterToSaveRestore = 0;
Jim Laskey9bb3c932007-02-22 18:04:49 +0000[diff] [blame]576 ExceptionPointerRegister = 0;
577 ExceptionSelectorRegister = 0;
Duncan Sands03228082008-11-23 15:47:28 +0000[diff] [blame]578 BooleanContents = UndefinedBooleanContent;
Evan Cheng211ffa12010-05-19 20:19:50 +0000[diff] [blame]579 SchedPreferenceInfo = Sched::Latency;
Chris Lattner7acf5f32006-09-05 17:39:15 +0000[diff] [blame]580 JumpBufSize = 0;
Duraid Madina0c9e0ff2006-09-04 07:44:11 +0000[diff] [blame]581 JumpBufAlignment = 0;
Evan Chengfb8075d2008-02-28 00:43:03 +0000[diff] [blame]582 PrefLoopAlignment = 0;
Rafael Espindolacbeeae22010-07-11 04:01:49 +0000[diff] [blame]583 MinStackArgumentAlignment = 1;
Jim Grosbach9a526492010-06-23 16:07:42 +0000[diff] [blame]584 ShouldFoldAtomicFences = false;
Evan Cheng56966222007-01-12 02:11:51 +0000[diff] [blame]585
586 InitLibcallNames(LibcallRoutineNames);
Evan Chengd385fd62007-01-31 09:29:11 +0000[diff] [blame]587 InitCmpLibcallCCs(CmpLibcallCCs);
Anton Korobeynikov72977a42009-08-14 20:10:52 +0000[diff] [blame]588 InitLibcallCallingConvs(LibcallCallingConvs);
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]589}
590
Chris Lattnerf0144122009-07-28 03:13:23 +0000[diff] [blame]591TargetLowering::~TargetLowering() {
592 delete &TLOF;
593}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]594
Mon P Wangf7ea6c32010-02-10 23:37:45 +0000[diff] [blame]595/// canOpTrap - Returns true if the operation can trap for the value type.
596/// VT must be a legal type.
597bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
598 assert(isTypeLegal(VT));
599 switch (Op) {
600 default:
601 return false;
602 case ISD::FDIV:
603 case ISD::FREM:
604 case ISD::SDIV:
605 case ISD::UDIV:
606 case ISD::SREM:
607 case ISD::UREM:
608 return true;
609 }
610}
611
612
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]613static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]614 unsigned &NumIntermediates,
615 EVT &RegisterVT,
616 TargetLowering *TLI) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]617 // Figure out the right, legal destination reg to copy into.
618 unsigned NumElts = VT.getVectorNumElements();
619 MVT EltTy = VT.getVectorElementType();
620
621 unsigned NumVectorRegs = 1;
622
623 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
624 // could break down into LHS/RHS like LegalizeDAG does.
625 if (!isPowerOf2_32(NumElts)) {
626 NumVectorRegs = NumElts;
627 NumElts = 1;
628 }
629
630 // Divide the input until we get to a supported size. This will always
631 // end with a scalar if the target doesn't support vectors.
632 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
633 NumElts >>= 1;
634 NumVectorRegs <<= 1;
635 }
636
637 NumIntermediates = NumVectorRegs;
638
639 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
640 if (!TLI->isTypeLegal(NewVT))
641 NewVT = EltTy;
642 IntermediateVT = NewVT;
643
644 EVT DestVT = TLI->getRegisterType(NewVT);
645 RegisterVT = DestVT;
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]646 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]647 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]648
Chris Lattner32b4b5a2010-07-05 05:53:14 +0000[diff] [blame]649 // Otherwise, promotion or legal types use the same number of registers as
650 // the vector decimated to the appropriate level.
651 return NumVectorRegs;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]652}
653
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]654/// isLegalRC - Return true if the value types that can be represented by the
655/// specified register class are all legal.
656bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
657 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
658 I != E; ++I) {
659 if (isTypeLegal(*I))
660 return true;
661 }
662 return false;
663}
664
665/// hasLegalSuperRegRegClasses - Return true if the specified register class
666/// has one or more super-reg register classes that are legal.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]667bool
668TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]669 if (*RC->superregclasses_begin() == 0)
670 return false;
671 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
672 E = RC->superregclasses_end(); I != E; ++I) {
673 const TargetRegisterClass *RRC = *I;
674 if (isLegalRC(RRC))
675 return true;
676 }
677 return false;
678}
679
680/// findRepresentativeClass - Return the largest legal super-reg register class
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]681/// of the register class for the specified type and its associated "cost".
682std::pair<const TargetRegisterClass*, uint8_t>
683TargetLowering::findRepresentativeClass(EVT VT) const {
684 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
685 if (!RC)
686 return std::make_pair(RC, 0);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]687 const TargetRegisterClass *BestRC = RC;
688 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
689 E = RC->superregclasses_end(); I != E; ++I) {
690 const TargetRegisterClass *RRC = *I;
691 if (RRC->isASubClass() || !isLegalRC(RRC))
692 continue;
693 if (!hasLegalSuperRegRegClasses(RRC))
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]694 return std::make_pair(RRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]695 BestRC = RRC;
696 }
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]697 return std::make_pair(BestRC, 1);
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]698}
699
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]700
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]701/// computeRegisterProperties - Once all of the register classes are added,
702/// this allows us to compute derived properties we expose.
703void TargetLowering::computeRegisterProperties() {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]704 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]705 "Too many value types for ValueTypeActions to hold!");
706
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]707 // Everything defaults to needing one register.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]708 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]709 NumRegistersForVT[i] = 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]710 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]711 }
712 // ...except isVoid, which doesn't need any registers.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]713 NumRegistersForVT[MVT::isVoid] = 0;
Misha Brukmanf976c852005-04-21 22:55:34 +0000[diff] [blame]714
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]715 // Find the largest integer register class.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]716 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]717 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]718 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
Chris Lattner310968c2005-01-07 07:44:53 +0000[diff] [blame]719
720 // Every integer value type larger than this largest register takes twice as
721 // many registers to represent as the previous ValueType.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]722 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]723 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
724 if (!ExpandedVT.isInteger())
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]725 break;
Dan Gohmanb9f10192007-06-21 14:42:22 +0000[diff] [blame]726 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]727 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
728 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
Dan Gohman8a55ce42009-09-23 21:02:20 +0000[diff] [blame]729 ValueTypeActions.setTypeAction(ExpandedVT, Expand);
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]730 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]731
732 // Inspect all of the ValueType's smaller than the largest integer
733 // register to see which ones need promotion.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]734 unsigned LegalIntReg = LargestIntReg;
735 for (unsigned IntReg = LargestIntReg - 1;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]736 IntReg >= (unsigned)MVT::i1; --IntReg) {
737 EVT IVT = (MVT::SimpleValueType)IntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]738 if (isTypeLegal(IVT)) {
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]739 LegalIntReg = IntReg;
740 } else {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]741 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]742 (MVT::SimpleValueType)LegalIntReg;
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]743 ValueTypeActions.setTypeAction(IVT, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]744 }
745 }
746
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]747 // ppcf128 type is really two f64's.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]748 if (!isTypeLegal(MVT::ppcf128)) {
749 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
750 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
751 TransformToType[MVT::ppcf128] = MVT::f64;
752 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
Dale Johannesen161e8972007-10-05 20:04:43 +0000[diff] [blame]753 }
754
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]755 // Decide how to handle f64. If the target does not have native f64 support,
756 // expand it to i64 and we will be generating soft float library calls.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]757 if (!isTypeLegal(MVT::f64)) {
758 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
759 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
760 TransformToType[MVT::f64] = MVT::i64;
761 ValueTypeActions.setTypeAction(MVT::f64, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]762 }
763
764 // Decide how to handle f32. If the target does not have native support for
765 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]766 if (!isTypeLegal(MVT::f32)) {
767 if (isTypeLegal(MVT::f64)) {
768 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
769 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
770 TransformToType[MVT::f32] = MVT::f64;
771 ValueTypeActions.setTypeAction(MVT::f32, Promote);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]772 } else {
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]773 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
774 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
775 TransformToType[MVT::f32] = MVT::i32;
776 ValueTypeActions.setTypeAction(MVT::f32, Expand);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]777 }
Evan Cheng1a8f1fe2006-12-09 02:42:38 +0000[diff] [blame]778 }
Nate Begeman4ef3b812005-11-22 01:29:36 +0000[diff] [blame]779
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]780 // Loop over all of the vector value types to see which need transformations.
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]781 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
782 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]783 MVT VT = (MVT::SimpleValueType)i;
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]784 if (isTypeLegal(VT)) continue;
785
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]786 // Determine if there is a legal wider type. If so, we should promote to
787 // that wider vector type.
788 EVT EltVT = VT.getVectorElementType();
789 unsigned NElts = VT.getVectorNumElements();
790 if (NElts != 1) {
791 bool IsLegalWiderType = false;
792 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
793 EVT SVT = (MVT::SimpleValueType)nVT;
794 if (SVT.getVectorElementType() == EltVT &&
795 SVT.getVectorNumElements() > NElts &&
796 isTypeSynthesizable(SVT)) {
797 TransformToType[i] = SVT;
798 RegisterTypeForVT[i] = SVT;
799 NumRegistersForVT[i] = 1;
800 ValueTypeActions.setTypeAction(VT, Promote);
801 IsLegalWiderType = true;
802 break;
803 }
804 }
805 if (IsLegalWiderType) continue;
806 }
807
Chris Lattner598751e2010-07-05 05:36:21 +0000[diff] [blame]808 MVT IntermediateVT;
809 EVT RegisterVT;
810 unsigned NumIntermediates;
811 NumRegistersForVT[i] =
812 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
813 RegisterVT, this);
814 RegisterTypeForVT[i] = RegisterVT;
815
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]816 EVT NVT = VT.getPow2VectorType();
817 if (NVT == VT) {
818 // Type is already a power of 2. The default action is to split.
819 TransformToType[i] = MVT::Other;
820 ValueTypeActions.setTypeAction(VT, Expand);
821 } else {
822 TransformToType[i] = NVT;
823 ValueTypeActions.setTypeAction(VT, Promote);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]824 }
Chris Lattner3a5935842006-03-16 19:50:01 +0000[diff] [blame]825 }
Evan Cheng46dcb572010-07-19 18:47:01 +0000[diff] [blame]826
827 // Determine the 'representative' register class for each value type.
828 // An representative register class is the largest (meaning one which is
829 // not a sub-register class / subreg register class) legal register class for
830 // a group of value types. For example, on i386, i8, i16, and i32
831 // representative would be GR32; while on x86_64 it's GR64.
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]832 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]833 const TargetRegisterClass* RRC;
834 uint8_t Cost;
835 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
836 RepRegClassForVT[i] = RRC;
837 RepRegClassCostForVT[i] = Cost;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]838 }
Chris Lattnerbb97d812005-01-16 01:10:58 +0000[diff] [blame]839}
Chris Lattnercba82f92005-01-16 07:28:11 +0000[diff] [blame]840
Evan Cheng72261582005-12-20 06:22:03 +0000[diff] [blame]841const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
842 return NULL;
843}
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]844
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]845
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]846MVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
Owen Anderson1d0be152009-08-13 21:58:54 +0000[diff] [blame]847 return PointerTy.SimpleTy;
Scott Michel5b8f82e2008-03-10 15:42:14 +0000[diff] [blame]848}
849
Sanjiv Gupta8f17a362009-12-28 02:40:33 +0000[diff] [blame]850MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
851 return MVT::i32; // return the default value
852}
853
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]854/// getVectorTypeBreakdown - Vector types are broken down into some number of
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]855/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
856/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
857/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]858///
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]859/// This method returns the number of registers needed, and the VT for each
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]860/// register. It also returns the VT and quantity of the intermediate values
861/// before they are promoted/expanded.
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]862///
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]863unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]864 EVT &IntermediateVT,
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]865 unsigned &NumIntermediates,
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]866 EVT &RegisterVT) const {
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]867 unsigned NumElts = VT.getVectorNumElements();
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]868
869 // If there is a wider vector type with the same element type as this one,
870 // we should widen to that legal vector type. This handles things like
871 // <2 x float> -> <4 x float>.
Chris Lattneraafe6262010-08-25 23:00:45 +0000[diff] [blame^]872 if (NumElts != 1 && getTypeAction(VT) == Promote) {
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]873 RegisterVT = getTypeToTransformTo(Context, VT);
874 if (isTypeLegal(RegisterVT)) {
875 IntermediateVT = RegisterVT;
876 NumIntermediates = 1;
877 return 1;
878 }
879 }
880
881 // Figure out the right, legal destination reg to copy into.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]882 EVT EltTy = VT.getVectorElementType();
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]883
884 unsigned NumVectorRegs = 1;
885
Nate Begemand73ab882007-11-27 19:28:48 +0000[diff] [blame]886 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
887 // could break down into LHS/RHS like LegalizeDAG does.
888 if (!isPowerOf2_32(NumElts)) {
889 NumVectorRegs = NumElts;
890 NumElts = 1;
891 }
892
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]893 // Divide the input until we get to a supported size. This will always
894 // end with a scalar if the target doesn't support vectors.
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]895 while (NumElts > 1 && !isTypeLegal(
896 EVT::getVectorVT(Context, EltTy, NumElts))) {
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]897 NumElts >>= 1;
898 NumVectorRegs <<= 1;
899 }
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]900
901 NumIntermediates = NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]902
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]903 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
Dan Gohman7f321562007-06-25 16:23:39 +0000[diff] [blame]904 if (!isTypeLegal(NewVT))
905 NewVT = EltTy;
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]906 IntermediateVT = NewVT;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]907
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]908 EVT DestVT = getRegisterType(Context, NewVT);
Dan Gohmanb6f5b002007-06-28 23:29:44 +0000[diff] [blame]909 RegisterVT = DestVT;
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]910 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]911 return NumVectorRegs*(NewVT.getSizeInBits()/DestVT.getSizeInBits());
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]912
Chris Lattnere6f7c262010-08-25 22:49:25 +0000[diff] [blame]913 // Otherwise, promotion or legal types use the same number of registers as
914 // the vector decimated to the appropriate level.
915 return NumVectorRegs;
Chris Lattnerdc879292006-03-31 00:28:56 +0000[diff] [blame]916}
917
Dan Gohman84023e02010-07-10 09:00:22 +0000[diff] [blame]918/// Get the EVTs and ArgFlags collections that represent the legalized return
919/// type of the given function. This does not require a DAG or a return value,
920/// and is suitable for use before any DAGs for the function are constructed.
921/// TODO: Move this out of TargetLowering.cpp.
922void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
923 SmallVectorImpl<ISD::OutputArg> &Outs,
924 const TargetLowering &TLI,
925 SmallVectorImpl<uint64_t> *Offsets) {
926 SmallVector<EVT, 4> ValueVTs;
927 ComputeValueVTs(TLI, ReturnType, ValueVTs);
928 unsigned NumValues = ValueVTs.size();
929 if (NumValues == 0) return;
930 unsigned Offset = 0;
931
932 for (unsigned j = 0, f = NumValues; j != f; ++j) {
933 EVT VT = ValueVTs[j];
934 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
935
936 if (attr & Attribute::SExt)
937 ExtendKind = ISD::SIGN_EXTEND;
938 else if (attr & Attribute::ZExt)
939 ExtendKind = ISD::ZERO_EXTEND;
940
941 // FIXME: C calling convention requires the return type to be promoted to
942 // at least 32-bit. But this is not necessary for non-C calling
943 // conventions. The frontend should mark functions whose return values
944 // require promoting with signext or zeroext attributes.
945 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
946 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
947 if (VT.bitsLT(MinVT))
948 VT = MinVT;
949 }
950
951 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
952 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
953 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
954 PartVT.getTypeForEVT(ReturnType->getContext()));
955
956 // 'inreg' on function refers to return value
957 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
958 if (attr & Attribute::InReg)
959 Flags.setInReg();
960
961 // Propagate extension type if any
962 if (attr & Attribute::SExt)
963 Flags.setSExt();
964 else if (attr & Attribute::ZExt)
965 Flags.setZExt();
966
967 for (unsigned i = 0; i < NumParts; ++i) {
968 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
969 if (Offsets) {
970 Offsets->push_back(Offset);
971 Offset += PartSize;
972 }
973 }
974 }
975}
976
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]977/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]978/// function arguments in the caller parameter area. This is the actual
979/// alignment, not its logarithm.
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]980unsigned TargetLowering::getByValTypeAlignment(const Type *Ty) const {
Dale Johannesen28d08fd2008-02-28 22:31:51 +0000[diff] [blame]981 return TD->getCallFrameTypeAlignment(Ty);
Evan Cheng3ae05432008-01-24 00:22:01 +0000[diff] [blame]982}
983
Chris Lattner071c62f2010-01-25 23:26:13 +0000[diff] [blame]984/// getJumpTableEncoding - Return the entry encoding for a jump table in the
985/// current function. The returned value is a member of the
986/// MachineJumpTableInfo::JTEntryKind enum.
987unsigned TargetLowering::getJumpTableEncoding() const {
988 // In non-pic modes, just use the address of a block.
989 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
990 return MachineJumpTableInfo::EK_BlockAddress;
991
992 // In PIC mode, if the target supports a GPRel32 directive, use it.
993 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
994 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
995
996 // Otherwise, use a label difference.
997 return MachineJumpTableInfo::EK_LabelDifference32;
998}
999
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1000SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1001 SelectionDAG &DAG) const {
Chris Lattnerf1214cb2010-01-26 06:53:37 +0000[diff] [blame]1002 // If our PIC model is GP relative, use the global offset table as the base.
1003 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
Dale Johannesenb300d2a2009-02-07 00:55:49 +0000[diff] [blame]1004 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
Evan Chengcc415862007-11-09 01:32:10 +0000[diff] [blame]1005 return Table;
1006}
1007
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1008/// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1009/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1010/// MCExpr.
1011const MCExpr *
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1012TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1013 unsigned JTI,MCContext &Ctx) const{
Chris Lattnerbeeb93e2010-01-26 05:58:28 +0000[diff] [blame]1014 // The normal PIC reloc base is the label at the start of the jump table.
Chris Lattner589c6f62010-01-26 06:28:43 +0000[diff] [blame]1015 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
Chris Lattner13e97a22010-01-26 05:30:30 +0000[diff] [blame]1016}
1017
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1018bool
1019TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1020 // Assume that everything is safe in static mode.
1021 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1022 return true;
1023
1024 // In dynamic-no-pic mode, assume that known defined values are safe.
1025 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1026 GA &&
1027 !GA->getGlobal()->isDeclaration() &&
Duncan Sands667d4b82009-03-07 15:45:40 +0000[diff] [blame]1028 !GA->getGlobal()->isWeakForLinker())
Dan Gohman6520e202008-10-18 02:06:02 +0000[diff] [blame]1029 return true;
1030
1031 // Otherwise assume nothing is safe.
1032 return false;
1033}
1034
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]1035//===----------------------------------------------------------------------===//
1036// Optimization Methods
1037//===----------------------------------------------------------------------===//
1038
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1039/// ShrinkDemandedConstant - Check to see if the specified operand of the
1040/// specified instruction is a constant integer. If so, check to see if there
1041/// are any bits set in the constant that are not demanded. If so, shrink the
1042/// constant and return true.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1043bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1044 const APInt &Demanded) {
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1045 DebugLoc dl = Op.getDebugLoc();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1046
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1047 // FIXME: ISD::SELECT, ISD::SELECT_CC
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1048 switch (Op.getOpcode()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1049 default: break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1050 case ISD::XOR:
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1051 case ISD::AND:
1052 case ISD::OR: {
1053 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1054 if (!C) return false;
1055
1056 if (Op.getOpcode() == ISD::XOR &&
1057 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1058 return false;
1059
1060 // if we can expand it to have all bits set, do it
1061 if (C->getAPIntValue().intersects(~Demanded)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1062 EVT VT = Op.getValueType();
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1063 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1064 DAG.getConstant(Demanded &
1065 C->getAPIntValue(),
1066 VT));
1067 return CombineTo(Op, New);
1068 }
1069
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1070 break;
1071 }
Bill Wendling36ae6c12009-03-04 00:18:06 +0000[diff] [blame]1072 }
1073
Nate Begemande996292006-02-03 22:24:05 +0000[diff] [blame]1074 return false;
1075}
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1076
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1077/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1078/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1079/// cast, but it could be generalized for targets with other types of
1080/// implicit widening casts.
1081bool
1082TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1083 unsigned BitWidth,
1084 const APInt &Demanded,
1085 DebugLoc dl) {
1086 assert(Op.getNumOperands() == 2 &&
1087 "ShrinkDemandedOp only supports binary operators!");
1088 assert(Op.getNode()->getNumValues() == 1 &&
1089 "ShrinkDemandedOp only supports nodes with one result!");
1090
1091 // Don't do this if the node has another user, which may require the
1092 // full value.
1093 if (!Op.getNode()->hasOneUse())
1094 return false;
1095
1096 // Search for the smallest integer type with free casts to and from
1097 // Op's type. For expedience, just check power-of-2 integer types.
1098 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1099 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1100 if (!isPowerOf2_32(SmallVTBits))
1101 SmallVTBits = NextPowerOf2(SmallVTBits);
1102 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1103 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1104 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1105 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1106 // We found a type with free casts.
1107 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1108 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1109 Op.getNode()->getOperand(0)),
1110 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1111 Op.getNode()->getOperand(1)));
1112 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1113 return CombineTo(Op, Z);
1114 }
1115 }
1116 return false;
1117}
1118
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1119/// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1120/// DemandedMask bits of the result of Op are ever used downstream. If we can
1121/// use this information to simplify Op, create a new simplified DAG node and
1122/// return true, returning the original and new nodes in Old and New. Otherwise,
1123/// analyze the expression and return a mask of KnownOne and KnownZero bits for
1124/// the expression (used to simplify the caller). The KnownZero/One bits may
1125/// only be accurate for those bits in the DemandedMask.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1126bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1127 const APInt &DemandedMask,
1128 APInt &KnownZero,
1129 APInt &KnownOne,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1130 TargetLoweringOpt &TLO,
1131 unsigned Depth) const {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1132 unsigned BitWidth = DemandedMask.getBitWidth();
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1133 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1134 "Mask size mismatches value type size!");
1135 APInt NewMask = DemandedMask;
Dale Johannesen6f38cb62009-02-07 19:59:05 +0000[diff] [blame]1136 DebugLoc dl = Op.getDebugLoc();
Chris Lattner3fc5b012007-05-17 18:19:23 +0000[diff] [blame]1137
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1138 // Don't know anything.
1139 KnownZero = KnownOne = APInt(BitWidth, 0);
1140
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1141 // Other users may use these bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1142 if (!Op.getNode()->hasOneUse()) {
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1143 if (Depth != 0) {
1144 // If not at the root, Just compute the KnownZero/KnownOne bits to
1145 // simplify things downstream.
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1146 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1147 return false;
1148 }
1149 // If this is the root being simplified, allow it to have multiple uses,
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1150 // just set the NewMask to all bits.
1151 NewMask = APInt::getAllOnesValue(BitWidth);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1152 } else if (DemandedMask == 0) {
1153 // Not demanding any bits from Op.
1154 if (Op.getOpcode() != ISD::UNDEF)
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]1155 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1156 return false;
1157 } else if (Depth == 6) { // Limit search depth.
1158 return false;
1159 }
1160
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1161 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1162 switch (Op.getOpcode()) {
1163 case ISD::Constant:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1164 // We know all of the bits for a constant!
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1165 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue() & NewMask;
1166 KnownZero = ~KnownOne & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1167 return false; // Don't fall through, will infinitely loop.
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1168 case ISD::AND:
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1169 // If the RHS is a constant, check to see if the LHS would be zero without
1170 // using the bits from the RHS. Below, we use knowledge about the RHS to
1171 // simplify the LHS, here we're using information from the LHS to simplify
1172 // the RHS.
1173 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1174 APInt LHSZero, LHSOne;
1175 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1176 LHSZero, LHSOne, Depth+1);
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1177 // If the LHS already has zeros where RHSC does, this and is dead.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1178 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1179 return TLO.CombineTo(Op, Op.getOperand(0));
1180 // If any of the set bits in the RHS are known zero on the LHS, shrink
1181 // the constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1182 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
Chris Lattner81cd3552006-02-27 00:36:27 +0000[diff] [blame]1183 return true;
1184 }
1185
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1186 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1187 KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1188 return true;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1189 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1190 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1191 KnownZero2, KnownOne2, TLO, Depth+1))
1192 return true;
1193 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1194
1195 // If all of the demanded bits are known one on one side, return the other.
1196 // These bits cannot contribute to the result of the 'and'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1197 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1198 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1199 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1200 return TLO.CombineTo(Op, Op.getOperand(1));
1201 // If all of the demanded bits in the inputs are known zeros, return zero.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1202 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1203 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1204 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1205 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1206 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1207 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1208 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1209 return true;
1210
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1211 // Output known-1 bits are only known if set in both the LHS & RHS.
1212 KnownOne &= KnownOne2;
1213 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1214 KnownZero |= KnownZero2;
1215 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1216 case ISD::OR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1217 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1218 KnownOne, TLO, Depth+1))
1219 return true;
1220 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1221 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1222 KnownZero2, KnownOne2, TLO, Depth+1))
1223 return true;
1224 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1225
1226 // If all of the demanded bits are known zero on one side, return the other.
1227 // These bits cannot contribute to the result of the 'or'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1228 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1229 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1230 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1231 return TLO.CombineTo(Op, Op.getOperand(1));
1232 // If all of the potentially set bits on one side are known to be set on
1233 // the other side, just use the 'other' side.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1234 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1235 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1236 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1237 return TLO.CombineTo(Op, Op.getOperand(1));
1238 // If the RHS is a constant, see if we can simplify it.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1239 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1240 return true;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1241 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1242 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1243 return true;
1244
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1245 // Output known-0 bits are only known if clear in both the LHS & RHS.
1246 KnownZero &= KnownZero2;
1247 // Output known-1 are known to be set if set in either the LHS | RHS.
1248 KnownOne |= KnownOne2;
1249 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1250 case ISD::XOR:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1251 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1252 KnownOne, TLO, Depth+1))
1253 return true;
1254 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1255 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1256 KnownOne2, TLO, Depth+1))
1257 return true;
1258 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1259
1260 // If all of the demanded bits are known zero on one side, return the other.
1261 // These bits cannot contribute to the result of the 'xor'.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1262 if ((KnownZero & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1263 return TLO.CombineTo(Op, Op.getOperand(0));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1264 if ((KnownZero2 & NewMask) == NewMask)
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1265 return TLO.CombineTo(Op, Op.getOperand(1));
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1266 // If the operation can be done in a smaller type, do so.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1267 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1268 return true;
1269
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1270 // If all of the unknown bits are known to be zero on one side or the other
1271 // (but not both) turn this into an *inclusive* or.
1272 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1273 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
Dale Johannesende064702009-02-06 21:50:26 +0000[diff] [blame]1274 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Chris Lattner3687c1a2006-11-27 21:50:02 +0000[diff] [blame]1275 Op.getOperand(0),
1276 Op.getOperand(1)));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1277
1278 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1279 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1280 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1281 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1282
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1283 // If all of the demanded bits on one side are known, and all of the set
1284 // bits on that side are also known to be set on the other side, turn this
1285 // into an AND, as we know the bits will be cleared.
1286 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1287 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1288 if ((KnownOne & KnownOne2) == KnownOne) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1289 EVT VT = Op.getValueType();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1290 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1291 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1292 Op.getOperand(0), ANDC));
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1293 }
1294 }
1295
1296 // If the RHS is a constant, see if we can simplify it.
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1297 // for XOR, we prefer to force bits to 1 if they will make a -1.
1298 // if we can't force bits, try to shrink constant
1299 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1300 APInt Expanded = C->getAPIntValue() | (~NewMask);
1301 // if we can expand it to have all bits set, do it
1302 if (Expanded.isAllOnesValue()) {
1303 if (Expanded != C->getAPIntValue()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1304 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1305 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
Torok Edwin4fea2e92008-04-06 21:23:02 +0000[diff] [blame]1306 TLO.DAG.getConstant(Expanded, VT));
1307 return TLO.CombineTo(Op, New);
1308 }
1309 // if it already has all the bits set, nothing to change
1310 // but don't shrink either!
1311 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1312 return true;
1313 }
1314 }
1315
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1316 KnownZero = KnownZeroOut;
1317 KnownOne = KnownOneOut;
1318 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1319 case ISD::SELECT:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1320 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1321 KnownOne, TLO, Depth+1))
1322 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1323 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1324 KnownOne2, TLO, Depth+1))
1325 return true;
1326 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1327 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1328
1329 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1330 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1331 return true;
1332
1333 // Only known if known in both the LHS and RHS.
1334 KnownOne &= KnownOne2;
1335 KnownZero &= KnownZero2;
1336 break;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1337 case ISD::SELECT_CC:
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1338 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1339 KnownOne, TLO, Depth+1))
1340 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1341 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1342 KnownOne2, TLO, Depth+1))
1343 return true;
1344 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1345 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1346
1347 // If the operands are constants, see if we can simplify them.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1348 if (TLO.ShrinkDemandedConstant(Op, NewMask))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1349 return true;
1350
1351 // Only known if known in both the LHS and RHS.
1352 KnownOne &= KnownOne2;
1353 KnownZero &= KnownZero2;
1354 break;
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1355 case ISD::SHL:
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1356 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1357 unsigned ShAmt = SA->getZExtValue();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1358 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1359
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1360 // If the shift count is an invalid immediate, don't do anything.
1361 if (ShAmt >= BitWidth)
1362 break;
1363
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1364 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1365 // single shift. We can do this if the bottom bits (which are shifted
1366 // out) are never demanded.
1367 if (InOp.getOpcode() == ISD::SRL &&
1368 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1369 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1370 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1371 unsigned Opc = ISD::SHL;
1372 int Diff = ShAmt-C1;
1373 if (Diff < 0) {
1374 Diff = -Diff;
1375 Opc = ISD::SRL;
1376 }
1377
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1378 SDValue NewSA =
Chris Lattner4e7e6cd2007-05-30 16:30:06 +0000[diff] [blame]1379 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1380 EVT VT = Op.getValueType();
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1381 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1382 InOp.getOperand(0), NewSA));
1383 }
1384 }
1385
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1386 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1387 KnownZero, KnownOne, TLO, Depth+1))
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1388 return true;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1389
1390 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1391 // are not demanded. This will likely allow the anyext to be folded away.
1392 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1393 SDValue InnerOp = InOp.getNode()->getOperand(0);
1394 EVT InnerVT = InnerOp.getValueType();
1395 if ((APInt::getHighBitsSet(BitWidth,
1396 BitWidth - InnerVT.getSizeInBits()) &
1397 DemandedMask) == 0 &&
1398 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1399 EVT ShTy = getShiftAmountTy();
1400 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1401 ShTy = InnerVT;
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1402 SDValue NarrowShl =
1403 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
Dan Gohmancd20c6f2010-07-23 21:08:12 +0000[diff] [blame]1404 TLO.DAG.getConstant(ShAmt, ShTy));
Dan Gohmana4f4d692010-07-23 18:03:30 +0000[diff] [blame]1405 return
1406 TLO.CombineTo(Op,
1407 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1408 NarrowShl));
1409 }
1410 }
1411
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1412 KnownZero <<= SA->getZExtValue();
1413 KnownOne <<= SA->getZExtValue();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1414 // low bits known zero.
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1415 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1416 }
1417 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1418 case ISD::SRL:
1419 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1420 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1421 unsigned ShAmt = SA->getZExtValue();
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1422 unsigned VTSize = VT.getSizeInBits();
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1423 SDValue InOp = Op.getOperand(0);
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1424
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1425 // If the shift count is an invalid immediate, don't do anything.
1426 if (ShAmt >= BitWidth)
1427 break;
1428
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1429 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1430 // single shift. We can do this if the top bits (which are shifted out)
1431 // are never demanded.
1432 if (InOp.getOpcode() == ISD::SHL &&
1433 isa<ConstantSDNode>(InOp.getOperand(1))) {
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1434 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1435 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1436 unsigned Opc = ISD::SRL;
1437 int Diff = ShAmt-C1;
1438 if (Diff < 0) {
1439 Diff = -Diff;
1440 Opc = ISD::SHL;
1441 }
1442
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1443 SDValue NewSA =
Chris Lattner8c7d2d52007-04-17 22:53:02 +0000[diff] [blame]1444 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1445 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
Chris Lattner895c4ab2007-04-17 21:14:16 +0000[diff] [blame]1446 InOp.getOperand(0), NewSA));
1447 }
1448 }
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1449
1450 // Compute the new bits that are at the top now.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1451 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1452 KnownZero, KnownOne, TLO, Depth+1))
1453 return true;
1454 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1455 KnownZero = KnownZero.lshr(ShAmt);
1456 KnownOne = KnownOne.lshr(ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1457
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1458 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
Chris Lattnerc4fa6032006-06-13 16:52:37 +0000[diff] [blame]1459 KnownZero |= HighBits; // High bits known zero.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1460 }
1461 break;
1462 case ISD::SRA:
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1463 // If this is an arithmetic shift right and only the low-bit is set, we can
1464 // always convert this into a logical shr, even if the shift amount is
1465 // variable. The low bit of the shift cannot be an input sign bit unless
1466 // the shift amount is >= the size of the datatype, which is undefined.
1467 if (DemandedMask == 1)
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1468 return TLO.CombineTo(Op,
1469 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1470 Op.getOperand(0), Op.getOperand(1)));
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1471
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1472 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1473 EVT VT = Op.getValueType();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]1474 unsigned ShAmt = SA->getZExtValue();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1475
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1476 // If the shift count is an invalid immediate, don't do anything.
1477 if (ShAmt >= BitWidth)
1478 break;
1479
1480 APInt InDemandedMask = (NewMask << ShAmt);
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1481
1482 // If any of the demanded bits are produced by the sign extension, we also
1483 // demand the input sign bit.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1484 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1485 if (HighBits.intersects(NewMask))
Dan Gohman87862e72009-12-11 21:31:27 +0000[diff] [blame]1486 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
Chris Lattner1b737132006-05-08 17:22:53 +0000[diff] [blame]1487
1488 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1489 KnownZero, KnownOne, TLO, Depth+1))
1490 return true;
1491 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1492 KnownZero = KnownZero.lshr(ShAmt);
1493 KnownOne = KnownOne.lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1494
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1495 // Handle the sign bit, adjusted to where it is now in the mask.
1496 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1497
1498 // If the input sign bit is known to be zero, or if none of the top bits
1499 // are demanded, turn this into an unsigned shift right.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1500 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1501 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1502 Op.getOperand(0),
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1503 Op.getOperand(1)));
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1504 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1505 KnownOne |= HighBits;
1506 }
1507 }
1508 break;
1509 case ISD::SIGN_EXTEND_INREG: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1510 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1511
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1512 // Sign extension. Compute the demanded bits in the result that are not
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1513 // present in the input.
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1514 APInt NewBits =
1515 APInt::getHighBitsSet(BitWidth,
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1516 BitWidth - EVT.getScalarType().getSizeInBits());
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1517
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1518 // If none of the extended bits are demanded, eliminate the sextinreg.
Eli Friedman1d17d192010-08-02 04:42:25 +0000[diff] [blame]1519 if ((NewBits & NewMask) == 0)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1520 return TLO.CombineTo(Op, Op.getOperand(0));
1521
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1522 APInt InSignBit = APInt::getSignBit(EVT.getScalarType().getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1523 InSignBit.zext(BitWidth);
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1524 APInt InputDemandedBits =
1525 APInt::getLowBitsSet(BitWidth,
1526 EVT.getScalarType().getSizeInBits()) &
1527 NewMask;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1528
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1529 // Since the sign extended bits are demanded, we know that the sign
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1530 // bit is demanded.
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1531 InputDemandedBits |= InSignBit;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1532
1533 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1534 KnownZero, KnownOne, TLO, Depth+1))
1535 return true;
1536 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1537
1538 // If the sign bit of the input is known set or clear, then we know the
1539 // top bits of the result.
1540
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1541 // If the input sign bit is known zero, convert this into a zero extension.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1542 if (KnownZero.intersects(InSignBit))
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1543 return TLO.CombineTo(Op,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1544 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,EVT));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1545
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1546 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1547 KnownOne |= NewBits;
1548 KnownZero &= ~NewBits;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1549 } else { // Input sign bit unknown
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1550 KnownZero &= ~NewBits;
1551 KnownOne &= ~NewBits;
1552 }
1553 break;
1554 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1555 case ISD::ZERO_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1556 unsigned OperandBitWidth =
1557 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1558 APInt InMask = NewMask;
1559 InMask.trunc(OperandBitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1560
1561 // If none of the top bits are demanded, convert this into an any_extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1562 APInt NewBits =
1563 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1564 if (!NewBits.intersects(NewMask))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1565 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1566 Op.getValueType(),
1567 Op.getOperand(0)));
1568
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1569 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1570 KnownZero, KnownOne, TLO, Depth+1))
1571 return true;
1572 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1573 KnownZero.zext(BitWidth);
1574 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1575 KnownZero |= NewBits;
1576 break;
1577 }
1578 case ISD::SIGN_EXTEND: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1579 EVT InVT = Op.getOperand(0).getValueType();
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1580 unsigned InBits = InVT.getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1581 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
Dan Gohman97360282008-03-11 21:29:43 +0000[diff] [blame]1582 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1583 APInt NewBits = ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1584
1585 // If none of the top bits are demanded, convert this into an any_extend.
1586 if (NewBits == 0)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1587 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1588 Op.getValueType(),
1589 Op.getOperand(0)));
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1590
1591 // Since some of the sign extended bits are demanded, we know that the sign
1592 // bit is demanded.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1593 APInt InDemandedBits = InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1594 InDemandedBits |= InSignBit;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1595 InDemandedBits.trunc(InBits);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1596
1597 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1598 KnownOne, TLO, Depth+1))
1599 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1600 KnownZero.zext(BitWidth);
1601 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1602
1603 // If the sign bit is known zero, convert this to a zero extend.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1604 if (KnownZero.intersects(InSignBit))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1605 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1606 Op.getValueType(),
1607 Op.getOperand(0)));
1608
1609 // If the sign bit is known one, the top bits match.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1610 if (KnownOne.intersects(InSignBit)) {
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1611 KnownOne |= NewBits;
1612 KnownZero &= ~NewBits;
1613 } else { // Otherwise, top bits aren't known.
1614 KnownOne &= ~NewBits;
1615 KnownZero &= ~NewBits;
1616 }
1617 break;
1618 }
1619 case ISD::ANY_EXTEND: {
Dan Gohmand1996362010-01-09 02:13:55 +0000[diff] [blame]1620 unsigned OperandBitWidth =
1621 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1622 APInt InMask = NewMask;
1623 InMask.trunc(OperandBitWidth);
1624 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1625 KnownZero, KnownOne, TLO, Depth+1))
1626 return true;
1627 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1628 KnownZero.zext(BitWidth);
1629 KnownOne.zext(BitWidth);
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1630 break;
1631 }
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1632 case ISD::TRUNCATE: {
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1633 // Simplify the input, using demanded bit information, and compute the known
1634 // zero/one bits live out.
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1635 unsigned OperandBitWidth =
1636 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1637 APInt TruncMask = NewMask;
Dan Gohman042919c2010-03-01 17:59:21 +0000[diff] [blame]1638 TruncMask.zext(OperandBitWidth);
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1639 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1640 KnownZero, KnownOne, TLO, Depth+1))
1641 return true;
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1642 KnownZero.trunc(BitWidth);
1643 KnownOne.trunc(BitWidth);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1644
1645 // If the input is only used by this truncate, see if we can shrink it based
1646 // on the known demanded bits.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1647 if (Op.getOperand(0).getNode()->hasOneUse()) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1648 SDValue In = Op.getOperand(0);
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1649 switch (In.getOpcode()) {
1650 default: break;
1651 case ISD::SRL:
1652 // Shrink SRL by a constant if none of the high bits shifted in are
1653 // demanded.
Evan Chenge5b51ac2010-04-17 06:13:15 +0000[diff] [blame]1654 if (TLO.LegalTypes() &&
1655 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1656 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1657 // undesirable.
1658 break;
1659 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1660 if (!ShAmt)
1661 break;
1662 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1663 OperandBitWidth - BitWidth);
1664 HighBits = HighBits.lshr(ShAmt->getZExtValue());
1665 HighBits.trunc(BitWidth);
1666
1667 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1668 // None of the shifted in bits are needed. Add a truncate of the
1669 // shift input, then shift it.
1670 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1671 Op.getValueType(),
1672 In.getOperand(0));
1673 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1674 Op.getValueType(),
1675 NewTrunc,
1676 In.getOperand(1)));
Chris Lattnerc93dfda2006-05-06 00:11:52 +0000[diff] [blame]1677 }
1678 break;
1679 }
1680 }
1681
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1682 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Chris Lattnerfe8babf2006-05-05 22:32:12 +0000[diff] [blame]1683 break;
1684 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1685 case ISD::AssertZext: {
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1686 // Demand all the bits of the input that are demanded in the output.
1687 // The low bits are obvious; the high bits are demanded because we're
1688 // asserting that they're zero here.
1689 if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1690 KnownZero, KnownOne, TLO, Depth+1))
1691 return true;
1692 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
Dan Gohman400f75c2010-06-03 20:21:33 +0000[diff] [blame]1693
1694 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1695 APInt InMask = APInt::getLowBitsSet(BitWidth,
1696 VT.getSizeInBits());
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1697 KnownZero |= ~InMask & NewMask;
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1698 break;
1699 }
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1700 case ISD::BIT_CONVERT:
1701#if 0
1702 // If this is an FP->Int bitcast and if the sign bit is the only thing that
1703 // is demanded, turn this into a FGETSIGN.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1704 if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]1705 MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
1706 !MVT::isVector(Op.getOperand(0).getValueType())) {
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1707 // Only do this xform if FGETSIGN is valid or if before legalize.
1708 if (!TLO.AfterLegalize ||
1709 isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
1710 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1711 // place. We expect the SHL to be eliminated by other optimizations.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1712 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, Op.getValueType(),
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1713 Op.getOperand(0));
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]1714 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1715 SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy());
Chris Lattner2ceb2cf2007-12-22 21:35:38 +0000[diff] [blame]1716 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, Op.getValueType(),
1717 Sign, ShAmt));
1718 }
1719 }
1720#endif
1721 break;
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1722 case ISD::ADD:
1723 case ISD::MUL:
1724 case ISD::SUB: {
1725 // Add, Sub, and Mul don't demand any bits in positions beyond that
1726 // of the highest bit demanded of them.
1727 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1728 BitWidth - NewMask.countLeadingZeros());
1729 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1730 KnownOne2, TLO, Depth+1))
1731 return true;
1732 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1733 KnownOne2, TLO, Depth+1))
1734 return true;
1735 // See if the operation should be performed at a smaller bit width.
Dan Gohman4e39e9d2010-06-24 14:30:44 +0000[diff] [blame]1736 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
Dan Gohman97121ba2009-04-08 00:15:30 +0000[diff] [blame]1737 return true;
1738 }
1739 // FALL THROUGH
Dan Gohman54eed372008-05-06 00:53:29 +0000[diff] [blame]1740 default:
Chris Lattner1482b5f2006-04-02 06:15:09 +0000[diff] [blame]1741 // Just use ComputeMaskedBits to compute output bits.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1742 TLO.DAG.ComputeMaskedBits(Op, NewMask, KnownZero, KnownOne, Depth);
Chris Lattnera6bc5a42006-02-27 01:00:42 +0000[diff] [blame]1743 break;
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1744 }
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1745
1746 // If we know the value of all of the demanded bits, return this as a
1747 // constant.
Dan Gohman7b8d4a92008-02-27 00:25:32 +0000[diff] [blame]1748 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
Chris Lattnerec665152006-02-26 23:36:02 +0000[diff] [blame]1749 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1750
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1751 return false;
1752}
1753
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1754/// computeMaskedBitsForTargetNode - Determine which of the bits specified
1755/// in Mask are known to be either zero or one and return them in the
1756/// KnownZero/KnownOne bitsets.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1757void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1758 const APInt &Mask,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]1759 APInt &KnownZero,
1760 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]1761 const SelectionDAG &DAG,
Nate Begeman368e18d2006-02-16 21:11:51 +0000[diff] [blame]1762 unsigned Depth) const {
Chris Lattner1b5232a2006-04-02 06:19:46 +0000[diff] [blame]1763 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1764 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1765 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1766 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
Chris Lattnerc6fd6cd2006-01-30 04:09:27 +0000[diff] [blame]1767 "Should use MaskedValueIsZero if you don't know whether Op"
1768 " is a target node!");
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]1769 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
Evan Cheng3a03ebb2005-12-21 23:05:39 +0000[diff] [blame]1770}
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]1771
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1772/// ComputeNumSignBitsForTargetNode - This method can be implemented by
1773/// targets that want to expose additional information about sign bits to the
1774/// DAG Combiner.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1775unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1776 unsigned Depth) const {
1777 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1778 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1779 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1780 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1781 "Should use ComputeNumSignBits if you don't know whether Op"
1782 " is a target node!");
1783 return 1;
1784}
1785
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1786/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1787/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1788/// determine which bit is set.
1789///
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1790static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1791 // A left-shift of a constant one will have exactly one bit set, because
1792 // shifting the bit off the end is undefined.
1793 if (Val.getOpcode() == ISD::SHL)
1794 if (ConstantSDNode *C =
1795 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1796 if (C->getAPIntValue() == 1)
1797 return true;
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1798
Dan Gohman97d11632009-02-15 23:59:32 +0000[diff] [blame]1799 // Similarly, a right-shift of a constant sign-bit will have exactly
1800 // one bit set.
1801 if (Val.getOpcode() == ISD::SRL)
1802 if (ConstantSDNode *C =
1803 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1804 if (C->getAPIntValue().isSignBit())
1805 return true;
1806
1807 // More could be done here, though the above checks are enough
1808 // to handle some common cases.
1809
1810 // Fall back to ComputeMaskedBits to catch other known cases.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1811 EVT OpVT = Val.getValueType();
Dan Gohman5b870af2010-03-02 02:14:38 +0000[diff] [blame]1812 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1813 APInt Mask = APInt::getAllOnesValue(BitWidth);
1814 APInt KnownZero, KnownOne;
1815 DAG.ComputeMaskedBits(Val, Mask, KnownZero, KnownOne);
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]1816 return (KnownZero.countPopulation() == BitWidth - 1) &&
1817 (KnownOne.countPopulation() == 1);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]1818}
Chris Lattner5c3e21d2006-05-06 09:27:13 +0000[diff] [blame]1819
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1820/// SimplifySetCC - Try to simplify a setcc built with the specified operands
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]1821/// and cc. If it is unable to simplify it, return a null SDValue.
1822SDValue
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1823TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1824 ISD::CondCode Cond, bool foldBooleans,
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]1825 DAGCombinerInfo &DCI, DebugLoc dl) const {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1826 SelectionDAG &DAG = DCI.DAG;
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1827 LLVMContext &Context = *DAG.getContext();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1828
1829 // These setcc operations always fold.
1830 switch (Cond) {
1831 default: break;
1832 case ISD::SETFALSE:
1833 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1834 case ISD::SETTRUE:
1835 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1836 }
1837
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1838 if (isa<ConstantSDNode>(N0.getNode())) {
1839 // Ensure that the constant occurs on the RHS, and fold constant
1840 // comparisons.
1841 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1842 }
1843
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]1844 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
Dan Gohman6c6cd1c2008-03-03 22:22:56 +0000[diff] [blame]1845 const APInt &C1 = N1C->getAPIntValue();
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1846
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1847 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1848 // equality comparison, then we're just comparing whether X itself is
1849 // zero.
1850 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1851 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1852 N0.getOperand(1).getOpcode() == ISD::Constant) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1853 const APInt &ShAmt
1854 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1855 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1856 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1857 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1858 // (srl (ctlz x), 5) == 0 -> X != 0
1859 // (srl (ctlz x), 5) != 1 -> X != 0
1860 Cond = ISD::SETNE;
1861 } else {
1862 // (srl (ctlz x), 5) != 0 -> X == 0
1863 // (srl (ctlz x), 5) == 1 -> X == 0
1864 Cond = ISD::SETEQ;
1865 }
1866 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1867 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1868 Zero, Cond);
1869 }
1870 }
1871
1872 // If the LHS is '(and load, const)', the RHS is 0,
1873 // the test is for equality or unsigned, and all 1 bits of the const are
1874 // in the same partial word, see if we can shorten the load.
1875 if (DCI.isBeforeLegalize() &&
1876 N0.getOpcode() == ISD::AND && C1 == 0 &&
1877 N0.getNode()->hasOneUse() &&
1878 isa<LoadSDNode>(N0.getOperand(0)) &&
1879 N0.getOperand(0).getNode()->hasOneUse() &&
1880 isa<ConstantSDNode>(N0.getOperand(1))) {
1881 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1882 APInt bestMask;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1883 unsigned bestWidth = 0, bestOffset = 0;
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1884 if (!Lod->isVolatile() && Lod->isUnindexed()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1885 unsigned origWidth = N0.getValueType().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1886 unsigned maskWidth = origWidth;
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1887 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1888 // 8 bits, but have to be careful...
1889 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1890 origWidth = Lod->getMemoryVT().getSizeInBits();
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1891 const APInt &Mask =
1892 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1893 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1894 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1895 for (unsigned offset=0; offset<origWidth/width; offset++) {
1896 if ((newMask & Mask) == Mask) {
1897 if (!TD->isLittleEndian())
1898 bestOffset = (origWidth/width - offset - 1) * (width/8);
1899 else
1900 bestOffset = (uint64_t)offset * (width/8);
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1901 bestMask = Mask.lshr(offset * (width/8) * 8);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1902 bestWidth = width;
1903 break;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1904 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1905 newMask = newMask << width;
Dale Johannesen89217a62008-11-07 01:28:02 +0000[diff] [blame]1906 }
1907 }
1908 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1909 if (bestWidth) {
Owen Anderson23b9b192009-08-12 00:36:31 +0000[diff] [blame]1910 EVT newVT = EVT::getIntegerVT(Context, bestWidth);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1911 if (newVT.isRound()) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1912 EVT PtrType = Lod->getOperand(1).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1913 SDValue Ptr = Lod->getBasePtr();
1914 if (bestOffset != 0)
1915 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1916 DAG.getConstant(bestOffset, PtrType));
1917 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1918 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1919 Lod->getSrcValue(),
1920 Lod->getSrcValueOffset() + bestOffset,
David Greene1e559442010-02-15 17:00:31 +0000[diff] [blame]1921 false, false, NewAlign);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1922 return DAG.getSetCC(dl, VT,
1923 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]1924 DAG.getConstant(bestMask.trunc(bestWidth),
1925 newVT)),
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1926 DAG.getConstant(0LL, newVT), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1927 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1928 }
1929 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1930
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1931 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1932 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1933 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1934
1935 // If the comparison constant has bits in the upper part, the
1936 // zero-extended value could never match.
1937 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1938 C1.getBitWidth() - InSize))) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1939 switch (Cond) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1940 case ISD::SETUGT:
1941 case ISD::SETUGE:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1942 case ISD::SETEQ: return DAG.getConstant(0, VT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1943 case ISD::SETULT:
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1944 case ISD::SETULE:
1945 case ISD::SETNE: return DAG.getConstant(1, VT);
1946 case ISD::SETGT:
1947 case ISD::SETGE:
1948 // True if the sign bit of C1 is set.
1949 return DAG.getConstant(C1.isNegative(), VT);
1950 case ISD::SETLT:
1951 case ISD::SETLE:
1952 // True if the sign bit of C1 isn't set.
1953 return DAG.getConstant(C1.isNonNegative(), VT);
1954 default:
Jakob Stoklund Olesen78d12642009-07-24 18:22:59 +0000[diff] [blame]1955 break;
1956 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1957 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]1958
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1959 // Otherwise, we can perform the comparison with the low bits.
1960 switch (Cond) {
1961 case ISD::SETEQ:
1962 case ISD::SETNE:
1963 case ISD::SETUGT:
1964 case ISD::SETUGE:
1965 case ISD::SETULT:
1966 case ISD::SETULE: {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1967 EVT newVT = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1968 if (DCI.isBeforeLegalizeOps() ||
1969 (isOperationLegal(ISD::SETCC, newVT) &&
1970 getCondCodeAction(Cond, newVT)==Legal))
1971 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1972 DAG.getConstant(APInt(C1).trunc(InSize), newVT),
1973 Cond);
1974 break;
1975 }
1976 default:
1977 break; // todo, be more careful with signed comparisons
1978 }
1979 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]1980 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1981 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1982 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1983 EVT ExtDstTy = N0.getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1984 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1985
Eli Friedmanad78a882010-07-30 06:44:31 +0000[diff] [blame]1986 // If the constant doesn't fit into the number of bits for the source of
1987 // the sign extension, it is impossible for both sides to be equal.
1988 if (C1.getMinSignedBits() > ExtSrcTyBits)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1989 return DAG.getConstant(Cond == ISD::SETNE, VT);
1990
1991 SDValue ZextOp;
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]1992 EVT Op0Ty = N0.getOperand(0).getValueType();
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]1993 if (Op0Ty == ExtSrcTy) {
1994 ZextOp = N0.getOperand(0);
1995 } else {
1996 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1997 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1998 DAG.getConstant(Imm, Op0Ty));
1999 }
2000 if (!DCI.isCalledByLegalizer())
2001 DCI.AddToWorklist(ZextOp.getNode());
2002 // Otherwise, make this a use of a zext.
2003 return DAG.getSetCC(dl, VT, ZextOp,
2004 DAG.getConstant(C1 & APInt::getLowBitsSet(
2005 ExtDstTyBits,
2006 ExtSrcTyBits),
2007 ExtDstTy),
2008 Cond);
2009 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2010 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2011 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2012 if (N0.getOpcode() == ISD::SETCC &&
2013 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2014 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2015 if (TrueWhenTrue)
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2016 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2017 // Invert the condition.
2018 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2019 CC = ISD::getSetCCInverse(CC,
2020 N0.getOperand(0).getValueType().isInteger());
2021 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2022 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2023
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2024 if ((N0.getOpcode() == ISD::XOR ||
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2025 (N0.getOpcode() == ISD::AND &&
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2026 N0.getOperand(0).getOpcode() == ISD::XOR &&
2027 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2028 isa<ConstantSDNode>(N0.getOperand(1)) &&
2029 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2030 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2031 // can only do this if the top bits are known zero.
2032 unsigned BitWidth = N0.getValueSizeInBits();
2033 if (DAG.MaskedValueIsZero(N0,
2034 APInt::getHighBitsSet(BitWidth,
2035 BitWidth-1))) {
2036 // Okay, get the un-inverted input value.
2037 SDValue Val;
2038 if (N0.getOpcode() == ISD::XOR)
2039 Val = N0.getOperand(0);
2040 else {
2041 assert(N0.getOpcode() == ISD::AND &&
2042 N0.getOperand(0).getOpcode() == ISD::XOR);
2043 // ((X^1)&1)^1 -> X & 1
2044 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2045 N0.getOperand(0).getOperand(0),
2046 N0.getOperand(1));
2047 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2048
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2049 return DAG.getSetCC(dl, VT, Val, N1,
2050 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2051 }
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2052 } else if (N1C->getAPIntValue() == 1 &&
2053 (VT == MVT::i1 ||
2054 getBooleanContents() == ZeroOrOneBooleanContent)) {
2055 SDValue Op0 = N0;
2056 if (Op0.getOpcode() == ISD::TRUNCATE)
2057 Op0 = Op0.getOperand(0);
2058
2059 if ((Op0.getOpcode() == ISD::XOR) &&
2060 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2061 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2062 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2063 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2064 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2065 Cond);
2066 } else if (Op0.getOpcode() == ISD::AND &&
2067 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2068 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2069 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2070 if (Op0.getValueType().bitsGT(VT))
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2071 Op0 = DAG.getNode(ISD::AND, dl, VT,
2072 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2073 DAG.getConstant(1, VT));
Anton Korobeynikov17458a72010-05-01 12:52:34 +0000[diff] [blame]2074 else if (Op0.getValueType().bitsLT(VT))
2075 Op0 = DAG.getNode(ISD::AND, dl, VT,
2076 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2077 DAG.getConstant(1, VT));
2078
Evan Cheng2c755ba2010-02-27 07:36:59 +0000[diff] [blame]2079 return DAG.getSetCC(dl, VT, Op0,
2080 DAG.getConstant(0, Op0.getValueType()),
2081 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2082 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2083 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2084 }
2085
2086 APInt MinVal, MaxVal;
2087 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2088 if (ISD::isSignedIntSetCC(Cond)) {
2089 MinVal = APInt::getSignedMinValue(OperandBitSize);
2090 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2091 } else {
2092 MinVal = APInt::getMinValue(OperandBitSize);
2093 MaxVal = APInt::getMaxValue(OperandBitSize);
2094 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2095
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2096 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2097 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2098 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2099 // X >= C0 --> X > (C0-1)
2100 return DAG.getSetCC(dl, VT, N0,
2101 DAG.getConstant(C1-1, N1.getValueType()),
2102 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2103 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2104
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2105 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2106 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2107 // X <= C0 --> X < (C0+1)
2108 return DAG.getSetCC(dl, VT, N0,
2109 DAG.getConstant(C1+1, N1.getValueType()),
2110 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2111 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2112
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2113 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2114 return DAG.getConstant(0, VT); // X < MIN --> false
2115 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2116 return DAG.getConstant(1, VT); // X >= MIN --> true
2117 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2118 return DAG.getConstant(0, VT); // X > MAX --> false
2119 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2120 return DAG.getConstant(1, VT); // X <= MAX --> true
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2121
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2122 // Canonicalize setgt X, Min --> setne X, Min
2123 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2124 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2125 // Canonicalize setlt X, Max --> setne X, Max
2126 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2127 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2128
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2129 // If we have setult X, 1, turn it into seteq X, 0
2130 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2131 return DAG.getSetCC(dl, VT, N0,
2132 DAG.getConstant(MinVal, N0.getValueType()),
2133 ISD::SETEQ);
2134 // If we have setugt X, Max-1, turn it into seteq X, Max
2135 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2136 return DAG.getSetCC(dl, VT, N0,
2137 DAG.getConstant(MaxVal, N0.getValueType()),
2138 ISD::SETEQ);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2139
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2140 // If we have "setcc X, C0", check to see if we can shrink the immediate
2141 // by changing cc.
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2142
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2143 // SETUGT X, SINTMAX -> SETLT X, 0
2144 if (Cond == ISD::SETUGT &&
2145 C1 == APInt::getSignedMaxValue(OperandBitSize))
2146 return DAG.getSetCC(dl, VT, N0,
2147 DAG.getConstant(0, N1.getValueType()),
2148 ISD::SETLT);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2149
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2150 // SETULT X, SINTMIN -> SETGT X, -1
2151 if (Cond == ISD::SETULT &&
2152 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2153 SDValue ConstMinusOne =
2154 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2155 N1.getValueType());
2156 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2157 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2158
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2159 // Fold bit comparisons when we can.
2160 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2161 (VT == N0.getValueType() ||
2162 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2163 N0.getOpcode() == ISD::AND)
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2164 if (ConstantSDNode *AndRHS =
2165 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2166 EVT ShiftTy = DCI.isBeforeLegalize() ?
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2167 getPointerTy() : getShiftAmountTy();
2168 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2169 // Perform the xform if the AND RHS is a single bit.
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2170 if (AndRHS->getAPIntValue().isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2171 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2172 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2173 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2174 }
Evan Cheng347a9cb2010-01-07 20:58:44 +0000[diff] [blame]2175 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2176 // (X & 8) == 8 --> (X & 8) >> 3
2177 // Perform the xform if C1 is a single bit.
2178 if (C1.isPowerOf2()) {
Evan Chengd40d03e2010-01-06 19:38:29 +0000[diff] [blame]2179 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2180 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2181 DAG.getConstant(C1.logBase2(), ShiftTy)));
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2182 }
2183 }
Eli Friedmanb101b0b2009-07-26 23:47:17 +0000[diff] [blame]2184 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2185 }
2186
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2187 if (isa<ConstantFPSDNode>(N0.getNode())) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2188 // Constant fold or commute setcc.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2189 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2190 if (O.getNode()) return O;
2191 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2192 // If the RHS of an FP comparison is a constant, simplify it away in
2193 // some cases.
2194 if (CFP->getValueAPF().isNaN()) {
2195 // If an operand is known to be a nan, we can fold it.
2196 switch (ISD::getUnorderedFlavor(Cond)) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2197 default: llvm_unreachable("Unknown flavor!");
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2198 case 0: // Known false.
2199 return DAG.getConstant(0, VT);
2200 case 1: // Known true.
2201 return DAG.getConstant(1, VT);
Chris Lattner1c3e1e22007-12-30 21:21:10 +0000[diff] [blame]2202 case 2: // Undefined.
Dale Johannesene8d72302009-02-06 23:05:02 +0000[diff] [blame]2203 return DAG.getUNDEF(VT);
Chris Lattner63079f02007-12-29 08:37:08 +0000[diff] [blame]2204 }
2205 }
2206
2207 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2208 // constant if knowing that the operand is non-nan is enough. We prefer to
2209 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2210 // materialize 0.0.
2211 if (Cond == ISD::SETO || Cond == ISD::SETUO)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2212 return DAG.getSetCC(dl, VT, N0, N0, Cond);
Dan Gohman11eab022009-09-26 15:24:17 +0000[diff] [blame]2213
2214 // If the condition is not legal, see if we can find an equivalent one
2215 // which is legal.
2216 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2217 // If the comparison was an awkward floating-point == or != and one of
2218 // the comparison operands is infinity or negative infinity, convert the
2219 // condition to a less-awkward <= or >=.
2220 if (CFP->getValueAPF().isInfinity()) {
2221 if (CFP->getValueAPF().isNegative()) {
2222 if (Cond == ISD::SETOEQ &&
2223 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2224 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2225 if (Cond == ISD::SETUEQ &&
2226 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2227 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2228 if (Cond == ISD::SETUNE &&
2229 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2230 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2231 if (Cond == ISD::SETONE &&
2232 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2233 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2234 } else {
2235 if (Cond == ISD::SETOEQ &&
2236 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2237 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2238 if (Cond == ISD::SETUEQ &&
2239 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2240 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2241 if (Cond == ISD::SETUNE &&
2242 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2243 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2244 if (Cond == ISD::SETONE &&
2245 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2246 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2247 }
2248 }
2249 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2250 }
2251
2252 if (N0 == N1) {
2253 // We can always fold X == X for integer setcc's.
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2254 if (N0.getValueType().isInteger())
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2255 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2256 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2257 if (UOF == 2) // FP operators that are undefined on NaNs.
2258 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2259 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2260 return DAG.getConstant(UOF, VT);
2261 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2262 // if it is not already.
2263 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2264 if (NewCond != Cond)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2265 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2266 }
2267
2268 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2269 N0.getValueType().isInteger()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2270 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2271 N0.getOpcode() == ISD::XOR) {
2272 // Simplify (X+Y) == (X+Z) --> Y == Z
2273 if (N0.getOpcode() == N1.getOpcode()) {
2274 if (N0.getOperand(0) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2275 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2276 if (N0.getOperand(1) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2277 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2278 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2279 // If X op Y == Y op X, try other combinations.
2280 if (N0.getOperand(0) == N1.getOperand(1))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2281 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2282 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2283 if (N0.getOperand(1) == N1.getOperand(0))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2284 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2285 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2286 }
2287 }
2288
2289 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2290 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2291 // Turn (X+C1) == C2 --> X == C2-C1
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2292 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2293 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2294 DAG.getConstant(RHSC->getAPIntValue()-
2295 LHSR->getAPIntValue(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2296 N0.getValueType()), Cond);
2297 }
2298
2299 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2300 if (N0.getOpcode() == ISD::XOR)
2301 // If we know that all of the inverted bits are zero, don't bother
2302 // performing the inversion.
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2303 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2304 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2305 DAG.getSetCC(dl, VT, N0.getOperand(0),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2306 DAG.getConstant(LHSR->getAPIntValue() ^
2307 RHSC->getAPIntValue(),
2308 N0.getValueType()),
2309 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2310 }
2311
2312 // Turn (C1-X) == C2 --> X == C1-C2
2313 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2314 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2315 return
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2316 DAG.getSetCC(dl, VT, N0.getOperand(1),
Dan Gohman2e68b6f2008-02-25 21:11:39 +0000[diff] [blame]2317 DAG.getConstant(SUBC->getAPIntValue() -
2318 RHSC->getAPIntValue(),
2319 N0.getValueType()),
2320 Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2321 }
2322 }
2323 }
2324
2325 // Simplify (X+Z) == X --> Z == 0
2326 if (N0.getOperand(0) == N1)
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2327 return DAG.getSetCC(dl, VT, N0.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2328 DAG.getConstant(0, N0.getValueType()), Cond);
2329 if (N0.getOperand(1) == N1) {
2330 if (DAG.isCommutativeBinOp(N0.getOpcode()))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2331 return DAG.getSetCC(dl, VT, N0.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2332 DAG.getConstant(0, N0.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2333 else if (N0.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2334 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2335 // (Z-X) == X --> Z == X<<1
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2336 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2337 N1,
2338 DAG.getConstant(1, getShiftAmountTy()));
2339 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2340 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2341 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2342 }
2343 }
2344 }
2345
2346 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2347 N1.getOpcode() == ISD::XOR) {
2348 // Simplify X == (X+Z) --> Z == 0
2349 if (N1.getOperand(0) == N0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2350 return DAG.getSetCC(dl, VT, N1.getOperand(1),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2351 DAG.getConstant(0, N1.getValueType()), Cond);
2352 } else if (N1.getOperand(1) == N0) {
2353 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2354 return DAG.getSetCC(dl, VT, N1.getOperand(0),
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2355 DAG.getConstant(0, N1.getValueType()), Cond);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2356 } else if (N1.getNode()->hasOneUse()) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2357 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2358 // X == (Z-X) --> X<<1 == Z
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2359 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2360 DAG.getConstant(1, getShiftAmountTy()));
2361 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2362 DCI.AddToWorklist(SH.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2363 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2364 }
2365 }
2366 }
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2367
Dan Gohman2c65c3d2009-01-29 16:18:12 +0000[diff] [blame]2368 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2369 // Note that where y is variable and is known to have at most
2370 // one bit set (for example, if it is z&1) we cannot do this;
2371 // the expressions are not equivalent when y==0.
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2372 if (N0.getOpcode() == ISD::AND)
2373 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2374 if (ValueHasExactlyOneBitSet(N1, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2375 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2376 SDValue Zero = DAG.getConstant(0, N1.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2377 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2378 }
2379 }
2380 if (N1.getOpcode() == ISD::AND)
2381 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
Dale Johannesen85b0ede2009-02-11 19:19:41 +0000[diff] [blame]2382 if (ValueHasExactlyOneBitSet(N0, DAG)) {
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2383 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2384 SDValue Zero = DAG.getConstant(0, N0.getValueType());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2385 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
Dan Gohmane5af2d32009-01-29 01:59:02 +0000[diff] [blame]2386 }
2387 }
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2388 }
2389
2390 // Fold away ALL boolean setcc's.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2391 SDValue Temp;
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2392 if (N0.getValueType() == MVT::i1 && foldBooleans) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2393 switch (Cond) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2394 default: llvm_unreachable("Unknown integer setcc!");
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2395 case ISD::SETEQ: // X == Y -> ~(X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2396 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2397 N0 = DAG.getNOT(dl, Temp, MVT::i1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2398 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2399 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2400 break;
2401 case ISD::SETNE: // X != Y --> (X^Y)
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2402 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2403 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2404 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2405 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2406 Temp = DAG.getNOT(dl, N0, MVT::i1);
2407 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2408 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2409 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2410 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2411 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2412 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2413 Temp = DAG.getNOT(dl, N1, MVT::i1);
2414 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2415 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2416 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2417 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2418 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2419 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2420 Temp = DAG.getNOT(dl, N0, MVT::i1);
2421 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2422 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2423 DCI.AddToWorklist(Temp.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2424 break;
Bob Wilson4c245462009-01-22 17:39:32 +0000[diff] [blame]2425 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2426 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2427 Temp = DAG.getNOT(dl, N1, MVT::i1);
2428 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2429 break;
2430 }
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2431 if (VT != MVT::i1) {
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2432 if (!DCI.isCalledByLegalizer())
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2433 DCI.AddToWorklist(N0.getNode());
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2434 // FIXME: If running after legalize, we probably can't do this.
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2435 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2436 }
2437 return N0;
2438 }
2439
2440 // Could not fold it.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2441 return SDValue();
Evan Chengfa1eb272007-02-08 22:13:59 +0000[diff] [blame]2442}
2443
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2444/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2445/// node is a GlobalAddress + offset.
Dan Gohman46510a72010-04-15 01:51:59 +0000[diff] [blame]2446bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2447 int64_t &Offset) const {
2448 if (isa<GlobalAddressSDNode>(N)) {
Dan Gohman9ea3f562008-06-09 22:05:52 +0000[diff] [blame]2449 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2450 GA = GASD->getGlobal();
2451 Offset += GASD->getOffset();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2452 return true;
2453 }
2454
2455 if (N->getOpcode() == ISD::ADD) {
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2456 SDValue N1 = N->getOperand(0);
2457 SDValue N2 = N->getOperand(1);
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2458 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2459 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2460 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2461 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2462 return true;
2463 }
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2464 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2465 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2466 if (V) {
Dan Gohman7810bfe2008-09-26 21:54:37 +0000[diff] [blame]2467 Offset += V->getSExtValue();
Evan Chengad4196b2008-05-12 19:56:52 +0000[diff] [blame]2468 return true;
2469 }
2470 }
2471 }
2472 return false;
2473}
2474
2475
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2476SDValue TargetLowering::
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2477PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2478 // Default implementation: no optimization.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2479 return SDValue();
Chris Lattner00ffed02006-03-01 04:52:55 +0000[diff] [blame]2480}
2481
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2482//===----------------------------------------------------------------------===//
2483// Inline Assembler Implementation Methods
2484//===----------------------------------------------------------------------===//
2485
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2486
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2487TargetLowering::ConstraintType
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2488TargetLowering::getConstraintType(const std::string &Constraint) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2489 // FIXME: lots more standard ones to handle.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2490 if (Constraint.size() == 1) {
2491 switch (Constraint[0]) {
2492 default: break;
2493 case 'r': return C_RegisterClass;
2494 case 'm': // memory
2495 case 'o': // offsetable
2496 case 'V': // not offsetable
2497 return C_Memory;
2498 case 'i': // Simple Integer or Relocatable Constant
2499 case 'n': // Simple Integer
2500 case 's': // Relocatable Constant
Chris Lattnerc13dd1c2007-03-25 04:35:41 +0000[diff] [blame]2501 case 'X': // Allow ANY value.
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2502 case 'I': // Target registers.
2503 case 'J':
2504 case 'K':
2505 case 'L':
2506 case 'M':
2507 case 'N':
2508 case 'O':
2509 case 'P':
2510 return C_Other;
2511 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2512 }
Chris Lattner065421f2007-03-25 02:18:14 +0000[diff] [blame]2513
2514 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2515 Constraint[Constraint.size()-1] == '}')
2516 return C_Register;
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]2517 return C_Unknown;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2518}
2519
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2520/// LowerXConstraint - try to replace an X constraint, which matches anything,
2521/// with another that has more specific requirements based on the type of the
2522/// corresponding operand.
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2523const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2524 if (ConstraintVT.isInteger())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2525 return "r";
Duncan Sands83ec4b62008-06-06 12:08:01 +0000[diff] [blame]2526 if (ConstraintVT.isFloatingPoint())
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2527 return "f"; // works for many targets
2528 return 0;
Dale Johannesenba2a0b92008-01-29 02:21:21 +0000[diff] [blame]2529}
2530
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2531/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2532/// vector. If it is invalid, don't add anything to Ops.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2533void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2534 char ConstraintLetter,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2535 std::vector<SDValue> &Ops,
Chris Lattner5e764232008-04-26 23:02:14 +0000[diff] [blame]2536 SelectionDAG &DAG) const {
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2537 switch (ConstraintLetter) {
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2538 default: break;
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2539 case 'X': // Allows any operand; labels (basic block) use this.
2540 if (Op.getOpcode() == ISD::BasicBlock) {
2541 Ops.push_back(Op);
2542 return;
2543 }
2544 // fall through
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2545 case 'i': // Simple Integer or Relocatable Constant
2546 case 'n': // Simple Integer
Dale Johanneseneb57ea72007-11-05 21:20:28 +0000[diff] [blame]2547 case 's': { // Relocatable Constant
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2548 // These operands are interested in values of the form (GV+C), where C may
2549 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2550 // is possible and fine if either GV or C are missing.
2551 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2552 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2553
2554 // If we have "(add GV, C)", pull out GV/C
2555 if (Op.getOpcode() == ISD::ADD) {
2556 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2557 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2558 if (C == 0 || GA == 0) {
2559 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2560 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2561 }
2562 if (C == 0 || GA == 0)
2563 C = 0, GA = 0;
2564 }
2565
2566 // If we find a valid operand, map to the TargetXXX version so that the
2567 // value itself doesn't get selected.
2568 if (GA) { // Either &GV or &GV+C
2569 if (ConstraintLetter != 'n') {
2570 int64_t Offs = GA->getOffset();
Dan Gohmanf5aeb1a2008-09-12 16:56:44 +0000[diff] [blame]2571 if (C) Offs += C->getZExtValue();
Devang Patel0d881da2010-07-06 22:08:15 +0000[diff] [blame]2572 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
Devang Patel07538ad2010-07-15 18:45:27 +0000[diff] [blame]2573 C ? C->getDebugLoc() : DebugLoc(),
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2574 Op.getValueType(), Offs));
2575 return;
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2576 }
2577 }
2578 if (C) { // just C, no GV.
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2579 // Simple constants are not allowed for 's'.
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2580 if (ConstraintLetter != 's') {
Dale Johannesen78e3e522009-02-12 20:58:09 +0000[diff] [blame]2581 // gcc prints these as sign extended. Sign extend value to 64 bits
2582 // now; without this it would get ZExt'd later in
2583 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2584 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
Owen Anderson825b72b2009-08-11 20:47:22 +0000[diff] [blame]2585 MVT::i64));
Chris Lattner48884cd2007-08-25 00:47:38 +0000[diff] [blame]2586 return;
2587 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2588 }
Chris Lattner9ff6ee82007-02-17 06:00:35 +0000[diff] [blame]2589 break;
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2590 }
Chris Lattner75c7d2b2007-05-03 16:54:34 +0000[diff] [blame]2591 }
Chris Lattnereb8146b2006-02-04 02:13:02 +0000[diff] [blame]2592}
2593
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2594std::vector<unsigned> TargetLowering::
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2595getRegClassForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2596 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2597 return std::vector<unsigned>();
2598}
2599
2600
2601std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
Chris Lattner4217ca8dc2006-02-21 23:11:00 +0000[diff] [blame]2602getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2603 EVT VT) const {
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2604 if (Constraint[0] != '{')
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2605 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2606 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2607
2608 // Remove the braces from around the name.
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2609 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2610
2611 // Figure out which register class contains this reg.
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]2612 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2613 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2614 E = RI->regclass_end(); RCI != E; ++RCI) {
2615 const TargetRegisterClass *RC = *RCI;
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2616
Dan Gohmanf451cb82010-02-10 16:03:48 +0000[diff] [blame]2617 // If none of the value types for this register class are valid, we
Chris Lattnerb3befd42006-02-22 23:00:51 +0000[diff] [blame]2618 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2619 bool isLegal = false;
2620 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2621 I != E; ++I) {
2622 if (isTypeLegal(*I)) {
2623 isLegal = true;
2624 break;
2625 }
2626 }
2627
2628 if (!isLegal) continue;
2629
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2630 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2631 I != E; ++I) {
Benjamin Kramer05872ea2009-11-12 20:36:59 +0000[diff] [blame]2632 if (RegName.equals_lower(RI->getName(*I)))
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2633 return std::make_pair(*I, RC);
Chris Lattner1efa40f2006-02-22 00:56:39 +0000[diff] [blame]2634 }
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2635 }
Chris Lattnera55079a2006-02-01 01:29:47 +0000[diff] [blame]2636
Douglas Gregor7d9663c2010-05-11 06:17:44 +0000[diff] [blame]2637 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
Chris Lattner4ccb0702006-01-26 20:37:03 +0000[diff] [blame]2638}
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2639
2640//===----------------------------------------------------------------------===//
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2641// Constraint Selection.
2642
Chris Lattner6bdcda32008-10-17 16:47:46 +0000[diff] [blame]2643/// isMatchingInputConstraint - Return true of this is an input operand that is
2644/// a matching constraint like "4".
2645bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
Chris Lattner58f15c42008-10-17 16:21:11 +0000[diff] [blame]2646 assert(!ConstraintCode.empty() && "No known constraint!");
2647 return isdigit(ConstraintCode[0]);
2648}
2649
2650/// getMatchedOperand - If this is an input matching constraint, this method
2651/// returns the output operand it matches.
2652unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2653 assert(!ConstraintCode.empty() && "No known constraint!");
2654 return atoi(ConstraintCode.c_str());
2655}
2656
2657
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2658/// getConstraintGenerality - Return an integer indicating how general CT
2659/// is.
2660static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2661 switch (CT) {
Torok Edwinc23197a2009-07-14 16:55:14 +0000[diff] [blame]2662 default: llvm_unreachable("Unknown constraint type!");
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2663 case TargetLowering::C_Other:
2664 case TargetLowering::C_Unknown:
2665 return 0;
2666 case TargetLowering::C_Register:
2667 return 1;
2668 case TargetLowering::C_RegisterClass:
2669 return 2;
2670 case TargetLowering::C_Memory:
2671 return 3;
2672 }
2673}
2674
2675/// ChooseConstraint - If there are multiple different constraints that we
2676/// could pick for this operand (e.g. "imr") try to pick the 'best' one.
Chris Lattner24e1a9d2008-04-27 01:49:46 +0000[diff] [blame]2677/// This is somewhat tricky: constraints fall into four classes:
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2678/// Other -> immediates and magic values
2679/// Register -> one specific register
2680/// RegisterClass -> a group of regs
2681/// Memory -> memory
2682/// Ideally, we would pick the most specific constraint possible: if we have
2683/// something that fits into a register, we would pick it. The problem here
2684/// is that if we have something that could either be in a register or in
2685/// memory that use of the register could cause selection of *other*
2686/// operands to fail: they might only succeed if we pick memory. Because of
2687/// this the heuristic we use is:
2688///
2689/// 1) If there is an 'other' constraint, and if the operand is valid for
2690/// that constraint, use it. This makes us take advantage of 'i'
2691/// constraints when available.
2692/// 2) Otherwise, pick the most general constraint present. This prefers
2693/// 'm' over 'r', for example.
2694///
2695static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2696 const TargetLowering &TLI,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2697 SDValue Op, SelectionDAG *DAG) {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2698 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2699 unsigned BestIdx = 0;
2700 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2701 int BestGenerality = -1;
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2702
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2703 // Loop over the options, keeping track of the most general one.
2704 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2705 TargetLowering::ConstraintType CType =
2706 TLI.getConstraintType(OpInfo.Codes[i]);
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2707
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2708 // If this is an 'other' constraint, see if the operand is valid for it.
2709 // For example, on X86 we might have an 'rI' constraint. If the operand
2710 // is an integer in the range [0..31] we want to use I (saving a load
2711 // of a register), otherwise we must use 'r'.
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2712 if (CType == TargetLowering::C_Other && Op.getNode()) {
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2713 assert(OpInfo.Codes[i].size() == 1 &&
2714 "Unhandled multi-letter 'other' constraint");
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2715 std::vector<SDValue> ResultOps;
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2716 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0],
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2717 ResultOps, *DAG);
2718 if (!ResultOps.empty()) {
2719 BestType = CType;
2720 BestIdx = i;
2721 break;
2722 }
2723 }
2724
Dale Johannesena5989f82010-06-28 22:09:45 +0000[diff] [blame]2725 // Things with matching constraints can only be registers, per gcc
2726 // documentation. This mainly affects "g" constraints.
2727 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2728 continue;
2729
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2730 // This constraint letter is more general than the previous one, use it.
2731 int Generality = getConstraintGenerality(CType);
2732 if (Generality > BestGenerality) {
2733 BestType = CType;
2734 BestIdx = i;
2735 BestGenerality = Generality;
2736 }
2737 }
2738
2739 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2740 OpInfo.ConstraintType = BestType;
2741}
2742
2743/// ComputeConstraintToUse - Determines the constraint code and constraint
2744/// type to use for the specific AsmOperandInfo, setting
2745/// OpInfo.ConstraintCode and OpInfo.ConstraintType.
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2746void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2747 SDValue Op,
Chris Lattner5a096902008-04-27 00:37:18 +0000[diff] [blame]2748 SelectionDAG *DAG) const {
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2749 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2750
2751 // Single-letter constraints ('r') are very common.
2752 if (OpInfo.Codes.size() == 1) {
2753 OpInfo.ConstraintCode = OpInfo.Codes[0];
2754 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2755 } else {
Dale Johannesen1784d162010-06-25 21:55:36 +0000[diff] [blame]2756 ChooseConstraint(OpInfo, *this, Op, DAG);
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2757 }
2758
2759 // 'X' matches anything.
2760 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2761 // Labels and constants are handled elsewhere ('X' is the only thing
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2762 // that matches labels). For Functions, the type here is the type of
Dale Johannesen5339c552009-07-20 23:27:39 +0000[diff] [blame]2763 // the result, which is not what we want to look at; leave them alone.
2764 Value *v = OpInfo.CallOperandVal;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2765 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2766 OpInfo.CallOperandVal = v;
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2767 return;
Dale Johannesen8ea5ec62009-07-07 23:26:33 +0000[diff] [blame]2768 }
Chris Lattner4376fea2008-04-27 00:09:47 +0000[diff] [blame]2769
2770 // Otherwise, try to resolve it to something we know about by looking at
2771 // the actual operand type.
2772 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2773 OpInfo.ConstraintCode = Repl;
2774 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2775 }
2776 }
2777}
2778
2779//===----------------------------------------------------------------------===//
Evan Cheng30b37b52006-03-13 23:18:16 +0000[diff] [blame]2780// Loop Strength Reduction hooks
2781//===----------------------------------------------------------------------===//
2782
Chris Lattner1436bb62007-03-30 23:14:50 +0000[diff] [blame]2783/// isLegalAddressingMode - Return true if the addressing mode represented
2784/// by AM is legal for this target, for a load/store of the specified type.
2785bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
2786 const Type *Ty) const {
2787 // The default implementation of this implements a conservative RISCy, r+r and
2788 // r+i addr mode.
2789
2790 // Allows a sign-extended 16-bit immediate field.
2791 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
2792 return false;
2793
2794 // No global is ever allowed as a base.
2795 if (AM.BaseGV)
2796 return false;
2797
2798 // Only support r+r,
2799 switch (AM.Scale) {
2800 case 0: // "r+i" or just "i", depending on HasBaseReg.
2801 break;
2802 case 1:
2803 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
2804 return false;
2805 // Otherwise we have r+r or r+i.
2806 break;
2807 case 2:
2808 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
2809 return false;
2810 // Allow 2*r as r+r.
2811 break;
2812 }
2813
2814 return true;
2815}
2816
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2817/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2818/// return a DAG expression to select that will generate the same value by
2819/// multiplying by a magic number. See:
2820/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2821SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
2822 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2823 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2824 DebugLoc dl= N->getDebugLoc();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2825
2826 // Check to see if we can do this.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2827 // FIXME: We should be more aggressive here.
2828 if (!isTypeLegal(VT))
2829 return SDValue();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2830
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2831 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2832 APInt::ms magics = d.magic();
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2833
2834 // Multiply the numerator (operand 0) by the magic value
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2835 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2836 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2837 if (isOperationLegalOrCustom(ISD::MULHS, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2838 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2839 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2840 else if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2841 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2842 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2843 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2844 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2845 return SDValue(); // No mulhs or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2846 // If d > 0 and m < 0, add the numerator
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2847 if (d.isStrictlyPositive() && magics.m.isNegative()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2848 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2849 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2850 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2851 }
2852 // If d < 0 and m > 0, subtract the numerator.
Eli Friedmanfc69cb42008-11-30 06:35:39 +0000[diff] [blame]2853 if (d.isNegative() && magics.m.isStrictlyPositive()) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2854 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2855 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2856 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2857 }
2858 // Shift right algebraic if shift value is nonzero
2859 if (magics.s > 0) {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2860 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2861 DAG.getConstant(magics.s, getShiftAmountTy()));
2862 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2863 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2864 }
2865 // Extract the sign bit and add it to the quotient
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2866 SDValue T =
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2867 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2868 getShiftAmountTy()));
2869 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2870 Created->push_back(T.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2871 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2872}
2873
2874/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2875/// return a DAG expression to select that will generate the same value by
2876/// multiplying by a magic number. See:
2877/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2878SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
2879 std::vector<SDNode*>* Created) const {
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]2880 EVT VT = N->getValueType(0);
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2881 DebugLoc dl = N->getDebugLoc();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2882
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2883 // Check to see if we can do this.
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2884 // FIXME: We should be more aggressive here.
2885 if (!isTypeLegal(VT))
2886 return SDValue();
2887
2888 // FIXME: We should use a narrower constant when the upper
2889 // bits are known to be zero.
2890 ConstantSDNode *N1C = cast<ConstantSDNode>(N->getOperand(1));
Jay Foad4e5ea552009-04-30 10:15:35 +0000[diff] [blame]2891 APInt::mu magics = N1C->getAPIntValue().magicu();
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2892
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2893 // Multiply the numerator (operand 0) by the magic value
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2894 // FIXME: We should support doing a MUL in a wider type
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2895 SDValue Q;
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2896 if (isOperationLegalOrCustom(ISD::MULHU, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2897 Q = DAG.getNode(ISD::MULHU, dl, VT, N->getOperand(0),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2898 DAG.getConstant(magics.m, VT));
Dan Gohmanf560ffa2009-01-28 17:46:25 +0000[diff] [blame]2899 else if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2900 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT),
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2901 N->getOperand(0),
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2902 DAG.getConstant(magics.m, VT)).getNode(), 1);
Dan Gohman525178c2007-10-08 18:33:35 +0000[diff] [blame]2903 else
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]2904 return SDValue(); // No mulhu or equvialent
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2905 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2906 Created->push_back(Q.getNode());
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2907
2908 if (magics.a == 0) {
Eli Friedman201c9772008-11-30 06:02:26 +0000[diff] [blame]2909 assert(magics.s < N1C->getAPIntValue().getBitWidth() &&
2910 "We shouldn't generate an undefined shift!");
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2911 return DAG.getNode(ISD::SRL, dl, VT, Q,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2912 DAG.getConstant(magics.s, getShiftAmountTy()));
2913 } else {
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2914 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2915 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2916 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2917 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2918 DAG.getConstant(1, getShiftAmountTy()));
2919 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2920 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2921 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2922 if (Created)
Gabor Greifba36cb52008-08-28 21:40:38 +0000[diff] [blame]2923 Created->push_back(NPQ.getNode());
Dale Johannesenff97d4f2009-02-03 00:47:48 +0000[diff] [blame]2924 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
Andrew Lenharthdae9cbe2006-05-16 17:42:15 +0000[diff] [blame]2925 DAG.getConstant(magics.s-1, getShiftAmountTy()));
2926 }
2927}