Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 1 | ///===-- FastISel.cpp - Implementation of the FastISel class --------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the implementation of the FastISel class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 14 | #include "llvm/Instructions.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 15 | #include "llvm/CodeGen/FastISel.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 18 | #include "llvm/Target/TargetData.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 19 | #include "llvm/Target/TargetInstrInfo.h" |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 20 | #include "llvm/Target/TargetLowering.h" |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetMachine.h" |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 22 | using namespace llvm; |
| 23 | |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 24 | /// SelectBinaryOp - Select and emit code for a binary operator instruction, |
| 25 | /// which has an opcode which directly corresponds to the given ISD opcode. |
| 26 | /// |
| 27 | bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode, |
| 28 | DenseMap<const Value*, unsigned> &ValueMap) { |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 29 | MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); |
| 30 | if (VT == MVT::Other || !VT.isSimple()) |
| 31 | // Unhandled type. Halt "fast" selection and bail. |
| 32 | return false; |
| 33 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 34 | unsigned Op0 = ValueMap[I->getOperand(0)]; |
| 35 | if (Op0 == 0) |
| 36 | // Unhandled operand. Halt "fast" selection and bail. |
| 37 | return false; |
| 38 | |
| 39 | // Check if the second operand is a constant and handle it appropriately. |
| 40 | if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) { |
| 41 | unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, |
| 42 | CI->getZExtValue(), VT.getSimpleVT()); |
| 43 | if (ResultReg == 0) |
| 44 | // Target-specific code wasn't able to find a machine opcode for |
| 45 | // the given ISD opcode and type. Halt "fast" selection and bail. |
| 46 | return false; |
| 47 | |
| 48 | // We successfully emitted code for the given LLVM Instruction. |
| 49 | ValueMap[I] = ResultReg; |
| 50 | return true; |
| 51 | } |
| 52 | |
| 53 | unsigned Op1 = ValueMap[I->getOperand(1)]; |
| 54 | if (Op1 == 0) |
| 55 | // Unhandled operand. Halt "fast" selection and bail. |
| 56 | return false; |
| 57 | |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 58 | unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1); |
| 59 | if (ResultReg == 0) |
| 60 | // Target-specific code wasn't able to find a machine opcode for |
| 61 | // the given ISD opcode and type. Halt "fast" selection and bail. |
| 62 | return false; |
| 63 | |
Dan Gohman | 8014e86 | 2008-08-20 00:23:20 +0000 | [diff] [blame] | 64 | // We successfully emitted code for the given LLVM Instruction. |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 65 | ValueMap[I] = ResultReg; |
| 66 | return true; |
| 67 | } |
| 68 | |
| 69 | bool FastISel::SelectGetElementPtr(Instruction *I, |
| 70 | DenseMap<const Value*, unsigned> &ValueMap) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 71 | unsigned N = ValueMap[I->getOperand(0)]; |
| 72 | if (N == 0) |
| 73 | // Unhandled operand. Halt "fast" selection and bail. |
| 74 | return false; |
| 75 | |
| 76 | const Type *Ty = I->getOperand(0)->getType(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 77 | MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT(); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 78 | for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); |
| 79 | OI != E; ++OI) { |
| 80 | Value *Idx = *OI; |
| 81 | if (const StructType *StTy = dyn_cast<StructType>(Ty)) { |
| 82 | unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); |
| 83 | if (Field) { |
| 84 | // N = N + Offset |
| 85 | uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field); |
| 86 | // FIXME: This can be optimized by combining the add with a |
| 87 | // subsequent one. |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 88 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 89 | if (N == 0) |
| 90 | // Unhandled operand. Halt "fast" selection and bail. |
| 91 | return false; |
| 92 | } |
| 93 | Ty = StTy->getElementType(Field); |
| 94 | } else { |
| 95 | Ty = cast<SequentialType>(Ty)->getElementType(); |
| 96 | |
| 97 | // If this is a constant subscript, handle it quickly. |
| 98 | if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { |
| 99 | if (CI->getZExtValue() == 0) continue; |
| 100 | uint64_t Offs = |
| 101 | TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 102 | N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 103 | if (N == 0) |
| 104 | // Unhandled operand. Halt "fast" selection and bail. |
| 105 | return false; |
| 106 | continue; |
| 107 | } |
| 108 | |
| 109 | // N = N + Idx * ElementSize; |
| 110 | uint64_t ElementSize = TD.getABITypeSize(Ty); |
| 111 | unsigned IdxN = ValueMap[Idx]; |
| 112 | if (IdxN == 0) |
| 113 | // Unhandled operand. Halt "fast" selection and bail. |
| 114 | return false; |
| 115 | |
| 116 | // If the index is smaller or larger than intptr_t, truncate or extend |
| 117 | // it. |
Evan Cheng | 2076aa8 | 2008-08-21 01:19:11 +0000 | [diff] [blame] | 118 | MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 119 | if (IdxVT.bitsLT(VT)) |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 120 | IdxN = FastEmit_r(VT, ISD::SIGN_EXTEND, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 121 | else if (IdxVT.bitsGT(VT)) |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 122 | IdxN = FastEmit_r(VT, ISD::TRUNCATE, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 123 | if (IdxN == 0) |
| 124 | // Unhandled operand. Halt "fast" selection and bail. |
| 125 | return false; |
| 126 | |
Dan Gohman | f93cf79 | 2008-08-21 17:37:05 +0000 | [diff] [blame] | 127 | if (ElementSize != 1) |
| 128 | IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 129 | if (IdxN == 0) |
| 130 | // Unhandled operand. Halt "fast" selection and bail. |
| 131 | return false; |
Dan Gohman | 7a0e659 | 2008-08-21 17:25:26 +0000 | [diff] [blame] | 132 | N = FastEmit_rr(VT, ISD::ADD, N, IdxN); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 133 | if (N == 0) |
| 134 | // Unhandled operand. Halt "fast" selection and bail. |
| 135 | return false; |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | // We successfully emitted code for the given LLVM Instruction. |
| 140 | ValueMap[I] = N; |
| 141 | return true; |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 142 | } |
| 143 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 144 | BasicBlock::iterator |
Dan Gohman | b7864a9 | 2008-08-20 18:09:02 +0000 | [diff] [blame] | 145 | FastISel::SelectInstructions(BasicBlock::iterator Begin, |
| 146 | BasicBlock::iterator End, |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 147 | DenseMap<const Value*, unsigned> &ValueMap, |
Dan Gohman | 6ecf509 | 2008-08-23 02:44:46 +0000 | [diff] [blame] | 148 | DenseMap<const BasicBlock*, |
Dan Gohman | 3c8f36f | 2008-08-22 21:28:19 +0000 | [diff] [blame] | 149 | MachineBasicBlock *> &MBBMap, |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 150 | MachineBasicBlock *mbb) { |
| 151 | MBB = mbb; |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 152 | BasicBlock::iterator I = Begin; |
| 153 | |
| 154 | for (; I != End; ++I) { |
| 155 | switch (I->getOpcode()) { |
Dan Gohman | 8014e86 | 2008-08-20 00:23:20 +0000 | [diff] [blame] | 156 | case Instruction::Add: { |
| 157 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD; |
| 158 | if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; |
| 159 | } |
| 160 | case Instruction::Sub: { |
| 161 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB; |
| 162 | if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; |
| 163 | } |
| 164 | case Instruction::Mul: { |
| 165 | ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL; |
| 166 | if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break; |
| 167 | } |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 168 | case Instruction::SDiv: |
| 169 | if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break; |
| 170 | case Instruction::UDiv: |
| 171 | if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break; |
| 172 | case Instruction::FDiv: |
| 173 | if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break; |
| 174 | case Instruction::SRem: |
| 175 | if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break; |
| 176 | case Instruction::URem: |
| 177 | if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break; |
| 178 | case Instruction::FRem: |
| 179 | if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break; |
| 180 | case Instruction::Shl: |
| 181 | if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break; |
| 182 | case Instruction::LShr: |
| 183 | if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break; |
| 184 | case Instruction::AShr: |
| 185 | if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break; |
| 186 | case Instruction::And: |
| 187 | if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break; |
| 188 | case Instruction::Or: |
| 189 | if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break; |
| 190 | case Instruction::Xor: |
| 191 | if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break; |
| 192 | |
| 193 | case Instruction::GetElementPtr: |
| 194 | if (!SelectGetElementPtr(I, ValueMap)) return I; |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 195 | break; |
Dan Gohman | bdedd44 | 2008-08-20 00:11:48 +0000 | [diff] [blame] | 196 | |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 197 | case Instruction::Br: { |
| 198 | BranchInst *BI = cast<BranchInst>(I); |
| 199 | |
Dan Gohman | e6798b7 | 2008-08-20 01:17:01 +0000 | [diff] [blame] | 200 | if (BI->isUnconditional()) { |
Dan Gohman | 3c8f36f | 2008-08-22 21:28:19 +0000 | [diff] [blame] | 201 | MachineFunction::iterator NextMBB = |
Dan Gohman | e6798b7 | 2008-08-20 01:17:01 +0000 | [diff] [blame] | 202 | next(MachineFunction::iterator(MBB)); |
Dan Gohman | 3c8f36f | 2008-08-22 21:28:19 +0000 | [diff] [blame] | 203 | BasicBlock *LLVMSucc = BI->getSuccessor(0); |
| 204 | MachineBasicBlock *MSucc = MBBMap[LLVMSucc]; |
| 205 | |
| 206 | if (NextMBB != MF.end() && MSucc == NextMBB) { |
| 207 | // The unconditional fall-through case, which needs no instructions. |
| 208 | } else { |
| 209 | // The unconditional branch case. |
| 210 | TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>()); |
Dan Gohman | e6798b7 | 2008-08-20 01:17:01 +0000 | [diff] [blame] | 211 | } |
Dan Gohman | 3c8f36f | 2008-08-22 21:28:19 +0000 | [diff] [blame] | 212 | MBB->addSuccessor(MSucc); |
| 213 | break; |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 214 | } |
| 215 | |
Dan Gohman | 3c8f36f | 2008-08-22 21:28:19 +0000 | [diff] [blame] | 216 | // Conditional branches are not handed yet. |
| 217 | // Halt "fast" selection and bail. |
Dan Gohman | 6f2766d | 2008-08-19 22:31:46 +0000 | [diff] [blame] | 218 | return I; |
| 219 | } |
Dan Gohman | 3b7753b | 2008-08-22 17:37:48 +0000 | [diff] [blame] | 220 | |
| 221 | case Instruction::PHI: |
| 222 | // PHI nodes are already emitted. |
| 223 | break; |
| 224 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 225 | default: |
| 226 | // Unhandled instruction. Halt "fast" selection and bail. |
| 227 | return I; |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | return I; |
| 232 | } |
| 233 | |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 234 | FastISel::FastISel(MachineFunction &mf) |
Dan Gohman | 22bb311 | 2008-08-22 00:20:26 +0000 | [diff] [blame] | 235 | : MF(mf), |
| 236 | MRI(mf.getRegInfo()), |
| 237 | TM(mf.getTarget()), |
| 238 | TD(*TM.getTargetData()), |
| 239 | TII(*TM.getInstrInfo()), |
| 240 | TLI(*TM.getTargetLowering()) { |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 241 | } |
| 242 | |
Dan Gohman | e285a74 | 2008-08-14 21:51:29 +0000 | [diff] [blame] | 243 | FastISel::~FastISel() {} |
| 244 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 245 | unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) { |
| 246 | return 0; |
| 247 | } |
| 248 | |
| 249 | unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType, |
| 250 | unsigned /*Op0*/) { |
| 251 | return 0; |
| 252 | } |
| 253 | |
| 254 | unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType, |
| 255 | unsigned /*Op0*/, unsigned /*Op0*/) { |
| 256 | return 0; |
| 257 | } |
| 258 | |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 259 | unsigned FastISel::FastEmit_i(MVT::SimpleValueType, uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 260 | return 0; |
| 261 | } |
| 262 | |
| 263 | unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, ISD::NodeType, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 264 | unsigned /*Op0*/, uint64_t /*Imm*/) { |
| 265 | return 0; |
| 266 | } |
| 267 | |
| 268 | unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, ISD::NodeType, |
| 269 | unsigned /*Op0*/, unsigned /*Op1*/, |
| 270 | uint64_t /*Imm*/) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 271 | return 0; |
| 272 | } |
| 273 | |
| 274 | /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries |
| 275 | /// to emit an instruction with an immediate operand using FastEmit_ri. |
| 276 | /// If that fails, it materializes the immediate into a register and try |
| 277 | /// FastEmit_rr instead. |
| 278 | unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 279 | unsigned Op0, uint64_t Imm, |
| 280 | MVT::SimpleValueType ImmType) { |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 281 | unsigned ResultReg = 0; |
| 282 | // First check if immediate type is legal. If not, we can't use the ri form. |
| 283 | if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal) |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 284 | ResultReg = FastEmit_ri(VT, Opcode, Op0, Imm); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 285 | if (ResultReg != 0) |
| 286 | return ResultReg; |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 287 | unsigned MaterialReg = FastEmit_i(ImmType, Imm); |
| 288 | if (MaterialReg == 0) |
| 289 | return 0; |
| 290 | return FastEmit_rr(VT, Opcode, Op0, MaterialReg); |
| 291 | } |
| 292 | |
| 293 | unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { |
| 294 | return MRI.createVirtualRegister(RC); |
Evan Cheng | 83785c8 | 2008-08-20 22:45:34 +0000 | [diff] [blame] | 295 | } |
| 296 | |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 297 | unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, |
Dan Gohman | 77ad796 | 2008-08-20 18:09:38 +0000 | [diff] [blame] | 298 | const TargetRegisterClass* RC) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 299 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 300 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 301 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 302 | BuildMI(MBB, II, ResultReg); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 303 | return ResultReg; |
| 304 | } |
| 305 | |
| 306 | unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, |
| 307 | const TargetRegisterClass *RC, |
| 308 | unsigned Op0) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 309 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 310 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 311 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 312 | BuildMI(MBB, II, ResultReg).addReg(Op0); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 313 | return ResultReg; |
| 314 | } |
| 315 | |
| 316 | unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, |
| 317 | const TargetRegisterClass *RC, |
| 318 | unsigned Op0, unsigned Op1) { |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 319 | unsigned ResultReg = createResultReg(RC); |
Dan Gohman | bb46633 | 2008-08-20 21:05:57 +0000 | [diff] [blame] | 320 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 321 | |
Dan Gohman | fd90394 | 2008-08-20 23:53:10 +0000 | [diff] [blame] | 322 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1); |
Dan Gohman | b0cf29c | 2008-08-13 20:19:35 +0000 | [diff] [blame] | 323 | return ResultReg; |
| 324 | } |
Dan Gohman | d5fe57d | 2008-08-21 01:41:07 +0000 | [diff] [blame] | 325 | |
| 326 | unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode, |
| 327 | const TargetRegisterClass *RC, |
| 328 | unsigned Op0, uint64_t Imm) { |
| 329 | unsigned ResultReg = createResultReg(RC); |
| 330 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 331 | |
| 332 | BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm); |
| 333 | return ResultReg; |
| 334 | } |
| 335 | |
| 336 | unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode, |
| 337 | const TargetRegisterClass *RC, |
| 338 | unsigned Op0, unsigned Op1, uint64_t Imm) { |
| 339 | unsigned ResultReg = createResultReg(RC); |
| 340 | const TargetInstrDesc &II = TII.get(MachineInstOpcode); |
| 341 | |
| 342 | BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm); |
| 343 | return ResultReg; |
| 344 | } |