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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
65 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000066 grow();
67}
68
Chris Lattner8c4d88d2004-09-30 01:54:45 +000069void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000070 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
71 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000072}
73
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
75 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000076 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000077 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000078 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
79 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
80 RC->getAlignment());
81 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000082 ++NumSpills;
83 return frameIndex;
84}
85
86void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
87 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000088 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000089 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000090 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000091}
92
Evan Cheng2638e1a2007-03-20 08:13:50 +000093int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
94 assert(MRegisterInfo::isVirtualRegister(virtReg));
95 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
96 "attempt to assign re-mat id to already spilled register");
97 Virt2StackSlotMap[virtReg] = ReMatId;
98 ++NumReMats;
99 return ReMatId++;
100}
101
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000102void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000103 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000104 // Move previous memory references folded to new instruction.
105 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000106 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
108 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000109 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000110 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000111
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000112 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000113 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
114 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000115 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000116 // Folded a two-address operand.
117 MRInfo = isModRef;
118 } else if (OldMI->getOperand(OpNo).isDef()) {
119 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000120 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000121 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000122 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000123
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000125 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000126}
127
Chris Lattner7f690e62004-09-30 02:15:18 +0000128void VirtRegMap::print(std::ostream &OS) const {
129 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000130
Chris Lattner7f690e62004-09-30 02:15:18 +0000131 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000132 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000133 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
134 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
135 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000136
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000137 }
138
139 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000140 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
141 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
142 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
143 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000144}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000145
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000146void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000147 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000148}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000149
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000150
151//===----------------------------------------------------------------------===//
152// Simple Spiller Implementation
153//===----------------------------------------------------------------------===//
154
155Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000156
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000157namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000158 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000159 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000160 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000161}
162
Chris Lattner35f27052006-05-01 21:16:03 +0000163bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000164 DOUT << "********** REWRITE MACHINE CODE **********\n";
165 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000166 const TargetMachine &TM = MF.getTarget();
167 const MRegisterInfo &MRI = *TM.getRegisterInfo();
168 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000169
Chris Lattner4ea1b822004-09-30 02:33:48 +0000170 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
171 // each vreg once (in the case where a spilled vreg is used by multiple
172 // operands). This is always smaller than the number of operands to the
173 // current machine instr, so it should be small.
174 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000175
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000176 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
177 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000178 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000179 MachineBasicBlock &MBB = *MBBI;
180 for (MachineBasicBlock::iterator MII = MBB.begin(),
181 E = MBB.end(); MII != E; ++MII) {
182 MachineInstr &MI = *MII;
183 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000184 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000185 if (MO.isRegister() && MO.getReg())
186 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
187 unsigned VirtReg = MO.getReg();
188 unsigned PhysReg = VRM.getPhys(VirtReg);
189 if (VRM.hasStackSlot(VirtReg)) {
190 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000191 const TargetRegisterClass* RC =
192 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000193
Chris Lattner886dd912005-04-04 21:35:34 +0000194 if (MO.isUse() &&
195 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
196 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000197 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000198 LoadedRegs.push_back(VirtReg);
199 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000200 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000201 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000202
Chris Lattner886dd912005-04-04 21:35:34 +0000203 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000204 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000205 ++NumStores;
206 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000207 }
Chris Lattner886dd912005-04-04 21:35:34 +0000208 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000209 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000210 } else {
211 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000212 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000213 }
Chris Lattner886dd912005-04-04 21:35:34 +0000214
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000215 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000216 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000217 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000218 }
219 return true;
220}
221
222//===----------------------------------------------------------------------===//
223// Local Spiller Implementation
224//===----------------------------------------------------------------------===//
225
226namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000227 /// LocalSpiller - This spiller does a simple pass over the machine basic
228 /// block to attempt to keep spills in registers as much as possible for
229 /// blocks that have low register pressure (the vreg may be spilled due to
230 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000231 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000232 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000233 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000234 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000235 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000236 MRI = MF.getTarget().getRegisterInfo();
237 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000238 DOUT << "\n**** Local spiller rewriting function '"
239 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000240
Evan Cheng2638e1a2007-03-20 08:13:50 +0000241 std::vector<MachineInstr *> ReMatedMIs;
Chris Lattner7fb64342004-10-01 19:04:51 +0000242 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
243 MBB != E; ++MBB)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000244 RewriteMBB(*MBB, VRM, ReMatedMIs);
245 for (unsigned i = 0, e = ReMatedMIs.size(); i != e; ++i)
246 delete ReMatedMIs[i];
Chris Lattner7fb64342004-10-01 19:04:51 +0000247 return true;
248 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000249 private:
Evan Cheng2638e1a2007-03-20 08:13:50 +0000250 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
251 std::vector<MachineInstr*> &ReMatedMIs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000252 };
253}
254
Chris Lattner66cf80f2006-02-03 23:13:58 +0000255/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
256/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000257///
258/// Note that not all physregs are created equal here. In particular, some
259/// physregs are reloads that we are allowed to clobber or ignore at any time.
260/// Other physregs are values that the register allocated program is using that
261/// we cannot CHANGE, but we can read if we like. We keep track of this on a
262/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
263/// entries. The predicate 'canClobberPhysReg()' checks this bit and
264/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000265namespace {
266class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000267 const MRegisterInfo *MRI;
268 const TargetInstrInfo *TII;
269
270 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
271 // register values that are still available, due to being loaded or stored to,
Evan Cheng6b448092007-03-02 08:52:00 +0000272 // but not invalidated yet. It also tracks the instructions that defined
Evan Chengde4e9422007-02-25 09:51:27 +0000273 // or used the register.
Evan Cheng6b448092007-03-02 08:52:00 +0000274 typedef std::pair<unsigned, std::vector<MachineInstr*> > SSInfo;
Evan Cheng91e23902007-02-23 01:13:26 +0000275 std::map<int, SSInfo> SpillSlotsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000276
277 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
278 // which stack slot values are currently held by a physreg. This is used to
279 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
280 std::multimap<unsigned, int> PhysRegsAvailable;
281
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000282 void disallowClobberPhysRegOnly(unsigned PhysReg);
283
Chris Lattner66cf80f2006-02-03 23:13:58 +0000284 void ClobberPhysRegOnly(unsigned PhysReg);
285public:
286 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
287 : MRI(mri), TII(tii) {
288 }
289
Evan Cheng91e23902007-02-23 01:13:26 +0000290 const MRegisterInfo *getRegInfo() const { return MRI; }
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 /// getSpillSlotPhysReg - If the specified stack slot is available in a
Evan Cheng91e23902007-02-23 01:13:26 +0000293 /// physical register, return that PhysReg, otherwise return 0. It also
294 /// returns by reference the instruction that either defines or last uses
295 /// the register.
296 unsigned getSpillSlotPhysReg(int Slot, MachineInstr *&SSMI) const {
297 std::map<int, SSInfo>::const_iterator I = SpillSlotsAvailable.find(Slot);
298 if (I != SpillSlotsAvailable.end()) {
Evan Cheng6b448092007-03-02 08:52:00 +0000299 if (!I->second.second.empty())
300 SSMI = I->second.second.back();
Evan Cheng91e23902007-02-23 01:13:26 +0000301 return I->second.first >> 1; // Remove the CanClobber bit.
302 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000303 return 0;
304 }
Evan Chengde4e9422007-02-25 09:51:27 +0000305
Evan Cheng6b448092007-03-02 08:52:00 +0000306 /// addLastUse - Add the last use information of all stack slots whose
Evan Chengde4e9422007-02-25 09:51:27 +0000307 /// values are available in the specific register.
Evan Cheng6b448092007-03-02 08:52:00 +0000308 void addLastUse(unsigned PhysReg, MachineInstr *Use) {
Evan Chengde4e9422007-02-25 09:51:27 +0000309 std::multimap<unsigned, int>::iterator I =
310 PhysRegsAvailable.lower_bound(PhysReg);
311 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
312 int Slot = I->second;
313 I++;
314
315 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
316 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
317 unsigned Val = II->second.first;
318 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
Evan Cheng6b448092007-03-02 08:52:00 +0000319 II->second.second.push_back(Use);
320 }
321 }
322
323 /// removeLastUse - Remove the last use information of all stack slots whose
324 /// values are available in the specific register.
325 void removeLastUse(unsigned PhysReg, MachineInstr *Use) {
326 std::multimap<unsigned, int>::iterator I =
327 PhysRegsAvailable.lower_bound(PhysReg);
328 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
329 int Slot = I->second;
330 I++;
331
332 std::map<int, SSInfo>::iterator II = SpillSlotsAvailable.find(Slot);
333 assert(II != SpillSlotsAvailable.end() && "Slot not available!");
334 unsigned Val = II->second.first;
335 assert((Val >> 1) == PhysReg && "Bidirectional map mismatch!");
336 if (II->second.second.back() == Use)
337 II->second.second.pop_back();
Evan Chengde4e9422007-02-25 09:51:27 +0000338 }
339 }
Chris Lattner540fec62006-02-25 01:51:33 +0000340
Chris Lattner66cf80f2006-02-03 23:13:58 +0000341 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000342 /// specified physreg. If CanClobber is true, the physreg can be modified at
343 /// any time without changing the semantics of the program.
Evan Cheng91e23902007-02-23 01:13:26 +0000344 void addAvailable(int Slot, MachineInstr *MI, unsigned Reg,
345 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000346 // If this stack slot is thought to be available in some other physreg,
347 // remove its record.
348 ModifyStackSlot(Slot);
349
Chris Lattner66cf80f2006-02-03 23:13:58 +0000350 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Evan Cheng6b448092007-03-02 08:52:00 +0000351 std::vector<MachineInstr*> DefUses;
352 DefUses.push_back(MI);
Evan Cheng91e23902007-02-23 01:13:26 +0000353 SpillSlotsAvailable[Slot] =
Evan Cheng6b448092007-03-02 08:52:00 +0000354 std::make_pair((Reg << 1) | (unsigned)CanClobber, DefUses);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000355
Evan Cheng2638e1a2007-03-20 08:13:50 +0000356 if (Slot > VirtRegMap::MAX_STACK_SLOT)
357 DOUT << "Remembering RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1;
358 else
359 DOUT << "Remembering SS#" << Slot;
360 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000361 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000362
Chris Lattner593c9582006-02-03 23:28:46 +0000363 /// canClobberPhysReg - Return true if the spiller is allowed to change the
364 /// value of the specified stackslot register if it desires. The specified
365 /// stack slot must be available in a physreg for this query to make sense.
366 bool canClobberPhysReg(int Slot) const {
367 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
Evan Cheng91e23902007-02-23 01:13:26 +0000368 return SpillSlotsAvailable.find(Slot)->second.first & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000369 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000370
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000371 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
372 /// stackslot register. The register is still available but is no longer
373 /// allowed to be modifed.
374 void disallowClobberPhysReg(unsigned PhysReg);
375
Chris Lattner66cf80f2006-02-03 23:13:58 +0000376 /// ClobberPhysReg - This is called when the specified physreg changes
377 /// value. We use this to invalidate any info about stuff we thing lives in
378 /// it and any of its aliases.
379 void ClobberPhysReg(unsigned PhysReg);
380
381 /// ModifyStackSlot - This method is called when the value in a stack slot
382 /// changes. This removes information about which register the previous value
383 /// for this slot lives in (as the previous value is dead now).
384 void ModifyStackSlot(int Slot);
385};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000386}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000387
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000388/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
389/// stackslot register. The register is still available but is no longer
390/// allowed to be modifed.
391void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
392 std::multimap<unsigned, int>::iterator I =
393 PhysRegsAvailable.lower_bound(PhysReg);
394 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
395 int Slot = I->second;
396 I++;
Evan Cheng91e23902007-02-23 01:13:26 +0000397 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000398 "Bidirectional map mismatch!");
Evan Cheng91e23902007-02-23 01:13:26 +0000399 SpillSlotsAvailable[Slot].first &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000400 DOUT << "PhysReg " << MRI->getName(PhysReg)
401 << " copied, it is available for use but can no longer be modified\n";
402 }
403}
404
405/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
406/// stackslot register and its aliases. The register and its aliases may
407/// still available but is no longer allowed to be modifed.
408void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
409 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
410 disallowClobberPhysRegOnly(*AS);
411 disallowClobberPhysRegOnly(PhysReg);
412}
413
Chris Lattner66cf80f2006-02-03 23:13:58 +0000414/// ClobberPhysRegOnly - This is called when the specified physreg changes
415/// value. We use this to invalidate any info about stuff we thing lives in it.
416void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
417 std::multimap<unsigned, int>::iterator I =
418 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000419 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000420 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000421 PhysRegsAvailable.erase(I++);
Evan Cheng91e23902007-02-23 01:13:26 +0000422 assert((SpillSlotsAvailable[Slot].first >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000423 "Bidirectional map mismatch!");
424 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000425 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000426 << " clobbered, invalidating ";
427 if (Slot > VirtRegMap::MAX_STACK_SLOT)
428 DOUT << "RM#" << Slot-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
429 else
430 DOUT << "SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000431 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000432}
433
Chris Lattner66cf80f2006-02-03 23:13:58 +0000434/// ClobberPhysReg - This is called when the specified physreg changes
435/// value. We use this to invalidate any info about stuff we thing lives in
436/// it and any of its aliases.
437void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000438 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000439 ClobberPhysRegOnly(*AS);
440 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000441}
442
Chris Lattner07cf1412006-02-03 00:36:31 +0000443/// ModifyStackSlot - This method is called when the value in a stack slot
444/// changes. This removes information about which register the previous value
445/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000446void AvailableSpills::ModifyStackSlot(int Slot) {
Evan Cheng91e23902007-02-23 01:13:26 +0000447 std::map<int, SSInfo>::iterator It = SpillSlotsAvailable.find(Slot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000448 if (It == SpillSlotsAvailable.end()) return;
Evan Cheng91e23902007-02-23 01:13:26 +0000449 unsigned Reg = It->second.first >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000450 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000451
452 // This register may hold the value of multiple stack slots, only remove this
453 // stack slot from the set of values the register contains.
454 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
455 for (; ; ++I) {
456 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
457 "Map inverse broken!");
458 if (I->second == Slot) break;
459 }
460 PhysRegsAvailable.erase(I);
461}
462
463
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000464
Chris Lattner7fb64342004-10-01 19:04:51 +0000465// ReusedOp - For each reused operand, we keep track of a bit of information, in
466// case we need to rollback upon processing a new operand. See comments below.
467namespace {
468 struct ReusedOp {
469 // The MachineInstr operand that reused an available value.
470 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000471
Chris Lattner7fb64342004-10-01 19:04:51 +0000472 // StackSlot - The spill slot of the value being reused.
473 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000474
Chris Lattner7fb64342004-10-01 19:04:51 +0000475 // PhysRegReused - The physical register the value was available in.
476 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000477
Chris Lattner7fb64342004-10-01 19:04:51 +0000478 // AssignedPhysReg - The physreg that was assigned for use by the reload.
479 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000480
481 // VirtReg - The virtual register itself.
482 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000483
Chris Lattner8a61a752005-10-06 17:19:06 +0000484 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
485 unsigned vreg)
486 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
487 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000488 };
Chris Lattner540fec62006-02-25 01:51:33 +0000489
490 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
491 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000492 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000493 MachineInstr &MI;
494 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000495 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000496 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000497 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000498 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000499 }
Chris Lattner540fec62006-02-25 01:51:33 +0000500
501 bool hasReuses() const {
502 return !Reuses.empty();
503 }
504
505 /// addReuse - If we choose to reuse a virtual register that is already
506 /// available instead of reloading it, remember that we did so.
507 void addReuse(unsigned OpNo, unsigned StackSlot,
508 unsigned PhysRegReused, unsigned AssignedPhysReg,
509 unsigned VirtReg) {
510 // If the reload is to the assigned register anyway, no undo will be
511 // required.
512 if (PhysRegReused == AssignedPhysReg) return;
513
514 // Otherwise, remember this.
515 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
516 AssignedPhysReg, VirtReg));
517 }
Evan Chenge077ef62006-11-04 00:21:55 +0000518
519 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000520 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000521 }
522
523 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000524 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000525 }
Chris Lattner540fec62006-02-25 01:51:33 +0000526
527 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
528 /// is some other operand that is using the specified register, either pick
529 /// a new register to use, or evict the previous reload and use this reg.
530 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
531 AvailableSpills &Spills,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000532 std::map<int, MachineInstr*> &MaybeDeadStores,
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000533 SmallSet<unsigned, 8> &Rejected) {
Chris Lattner540fec62006-02-25 01:51:33 +0000534 if (Reuses.empty()) return PhysReg; // This is most often empty.
535
536 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
537 ReusedOp &Op = Reuses[ro];
538 // If we find some other reuse that was supposed to use this register
539 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000540 // register. That is, unless its reload register has already been
541 // considered and subsequently rejected because it has also been reused
542 // by another operand.
543 if (Op.PhysRegReused == PhysReg &&
544 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000545 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000546 unsigned NewReg = Op.AssignedPhysReg;
547 Rejected.insert(PhysReg);
548 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner540fec62006-02-25 01:51:33 +0000549 } else {
550 // Otherwise, we might also have a problem if a previously reused
551 // value aliases the new register. If so, codegen the previous reload
552 // and use this one.
553 unsigned PRRU = Op.PhysRegReused;
554 const MRegisterInfo *MRI = Spills.getRegInfo();
555 if (MRI->areAliases(PRRU, PhysReg)) {
556 // Okay, we found out that an alias of a reused register
557 // was used. This isn't good because it means we have
558 // to undo a previous reuse.
559 MachineBasicBlock *MBB = MI->getParent();
560 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000561 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
562
563 // Copy Op out of the vector and remove it, we're going to insert an
564 // explicit load for it.
565 ReusedOp NewOp = Op;
566 Reuses.erase(Reuses.begin()+ro);
567
568 // Ok, we're going to try to reload the assigned physreg into the
569 // slot that we were supposed to in the first place. However, that
570 // register could hold a reuse. Check to see if it conflicts or
571 // would prefer us to use a different register.
572 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng3c82cab2007-01-19 22:40:14 +0000573 MI, Spills, MaybeDeadStores, Rejected);
Chris Lattner28bad082006-02-25 02:17:31 +0000574
575 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
576 NewOp.StackSlot, AliasRC);
577 Spills.ClobberPhysReg(NewPhysReg);
578 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000579
580 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000581 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000582
Chris Lattnere53f4a02006-05-04 17:52:23 +0000583 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000584
Evan Cheng91e23902007-02-23 01:13:26 +0000585 Spills.addAvailable(NewOp.StackSlot, MI, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000586 ++NumLoads;
587 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000588 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000589
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000590 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000591 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000592
593 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000594 return PhysReg;
595 }
596 }
597 }
598 return PhysReg;
599 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000600
601 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
602 /// 'Rejected' set to remember which registers have been considered and
603 /// rejected for the reload. This avoids infinite looping in case like
604 /// this:
605 /// t1 := op t2, t3
606 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
607 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
608 /// t1 <- desires r1
609 /// sees r1 is taken by t2, tries t2's reload register r0
610 /// sees r0 is taken by t3, tries t3's reload register r1
611 /// sees r1 is taken by t2, tries t2's reload register r0 ...
612 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
613 AvailableSpills &Spills,
614 std::map<int, MachineInstr*> &MaybeDeadStores) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000615 SmallSet<unsigned, 8> Rejected;
Evan Cheng3c82cab2007-01-19 22:40:14 +0000616 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected);
617 }
Chris Lattner540fec62006-02-25 01:51:33 +0000618 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000619}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000620
Chris Lattner7fb64342004-10-01 19:04:51 +0000621
622/// rewriteMBB - Keep track of which spills are available even after the
623/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000624void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
625 std::vector<MachineInstr*> &ReMatedMIs) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000626
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000627 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000628
Chris Lattner66cf80f2006-02-03 23:13:58 +0000629 // Spills - Keep track of which spilled values are available in physregs so
630 // that we can choose to reuse the physregs instead of emitting reloads.
631 AvailableSpills Spills(MRI, TII);
632
Chris Lattner52b25db2004-10-01 19:47:12 +0000633 // MaybeDeadStores - When we need to write a value back into a stack slot,
634 // keep track of the inserted store. If the stack slot value is never read
635 // (because the value was used from some available register, for example), and
636 // subsequently stored to, the original store is dead. This map keeps track
637 // of inserted stores that are not used. If we see a subsequent store to the
638 // same stack slot, the original store is deleted.
639 std::map<int, MachineInstr*> MaybeDeadStores;
640
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000641 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
642
Chris Lattner7fb64342004-10-01 19:04:51 +0000643 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
644 MII != E; ) {
645 MachineInstr &MI = *MII;
646 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
647
Chris Lattner540fec62006-02-25 01:51:33 +0000648 /// ReusedOperands - Keep track of operand reuse in case we need to undo
649 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000650 ReuseInfo ReusedOperands(MI, MRI);
651
652 // Loop over all of the implicit defs, clearing them from our available
653 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000654 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng2638e1a2007-03-20 08:13:50 +0000655
656 // If this instruction is being rematerialized, just remove it!
657 if (TID->Flags & M_REMATERIALIZIBLE) {
658 bool Remove = true;
659 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
660 MachineOperand &MO = MI.getOperand(i);
661 if (!MO.isRegister() || MO.getReg() == 0)
662 continue; // Ignore non-register operands.
663 if (MO.isDef() && !VRM.isReMaterialized(MO.getReg())) {
664 Remove = false;
665 break;
666 }
667 }
668 if (Remove) {
669 VRM.RemoveFromFoldedVirtMap(&MI);
670 ReMatedMIs.push_back(MI.removeFromParent());
671 MII = NextMII;
672 continue;
673 }
674 }
675
Evan Cheng86facc22006-12-15 06:41:01 +0000676 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000677 if (ImpDef) {
678 for ( ; *ImpDef; ++ImpDef) {
679 PhysRegsUsed[*ImpDef] = true;
680 ReusedOperands.markClobbered(*ImpDef);
681 Spills.ClobberPhysReg(*ImpDef);
682 }
683 }
684
Chris Lattner7fb64342004-10-01 19:04:51 +0000685 // Process all of the spilled uses and all non spilled reg references.
686 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
687 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000688 if (!MO.isRegister() || MO.getReg() == 0)
689 continue; // Ignore non-register operands.
690
691 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
692 // Ignore physregs for spilling, but remember that it is used by this
693 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000694 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000695 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000696 continue;
697 }
698
699 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
700 "Not a virtual or a physical register?");
701
702 unsigned VirtReg = MO.getReg();
703 if (!VRM.hasStackSlot(VirtReg)) {
704 // This virtual register was assigned a physreg!
705 unsigned Phys = VRM.getPhys(VirtReg);
706 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000707 if (MO.isDef())
708 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000709 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000710 continue;
711 }
712
713 // This virtual register is now known to be a spilled value.
714 if (!MO.isUse())
715 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000716
Evan Cheng2638e1a2007-03-20 08:13:50 +0000717 bool doReMat = VRM.isReMaterialized(VirtReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000718 int StackSlot = VRM.getStackSlot(VirtReg);
719 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000720
Chris Lattner50ea01e2005-09-09 20:29:51 +0000721 // Check to see if this stack slot is available.
Evan Cheng91e23902007-02-23 01:13:26 +0000722 MachineInstr *SSMI = NULL;
723 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot, SSMI))) {
Chris Lattner29268692006-09-05 02:12:02 +0000724 // This spilled operand might be part of a two-address operand. If this
725 // is the case, then changing it will necessarily require changing the
726 // def part of the instruction as well. However, in some cases, we
727 // aren't allowed to modify the reused register. If none of these cases
728 // apply, reuse it.
729 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000730 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000731 if (ti != -1 &&
732 MI.getOperand(ti).isReg() &&
733 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000734 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000735 // long as we are allowed to clobber the value and there isn't an
736 // earlier def that has already clobbered the physreg.
Evan Chenge077ef62006-11-04 00:21:55 +0000737 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
738 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000739 }
740
741 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000742 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000743 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
744 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
745 else
746 DOUT << "Reusing SS#" << StackSlot;
747 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000748 << MRI->getName(PhysReg) << " for vreg"
749 << VirtReg <<" instead of reloading into physreg "
750 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000751 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000752
Evan Cheng91e23902007-02-23 01:13:26 +0000753 // Extend the live range of the MI that last kill the register if
754 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000755 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000756 if (SSMI) {
757 MachineOperand *MOK = SSMI->findRegisterUseOperand(PhysReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000758 if (MOK) {
759 WasKill = MOK->isKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000760 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000761 }
Evan Cheng6b448092007-03-02 08:52:00 +0000762 }
763 if (ti == -1) {
764 // Unless it's the use of a two-address code, transfer the kill
765 // of the reused register to this use.
Evan Chenga7288df2007-03-03 06:32:37 +0000766 if (WasKill)
767 MI.getOperand(i).setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000768 Spills.addLastUse(PhysReg, &MI);
Evan Cheng50d25d72007-02-23 21:47:50 +0000769 }
Evan Cheng91e23902007-02-23 01:13:26 +0000770
Chris Lattneraddc55a2006-04-28 01:46:50 +0000771 // The only technical detail we have is that we don't know that
772 // PhysReg won't be clobbered by a reloaded stack slot that occurs
773 // later in the instruction. In particular, consider 'op V1, V2'.
774 // If V1 is available in physreg R0, we would choose to reuse it
775 // here, instead of reloading it into the register the allocator
776 // indicated (say R1). However, V2 might have to be reloaded
777 // later, and it might indicate that it needs to live in R0. When
778 // this occurs, we need to have information available that
779 // indicates it is safe to use R1 for the reload instead of R0.
780 //
781 // To further complicate matters, we might conflict with an alias,
782 // or R0 and R1 might not be compatible with each other. In this
783 // case, we actually insert a reload for V1 in R1, ensuring that
784 // we can get at R0 or its alias.
785 ReusedOperands.addReuse(i, StackSlot, PhysReg,
786 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000787 if (ti != -1)
788 // Only mark it clobbered if this is a use&def operand.
789 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000790 ++NumReused;
791 continue;
792 }
793
794 // Otherwise we have a situation where we have a two-address instruction
795 // whose mod/ref operand needs to be reloaded. This reload is already
796 // available in some register "PhysReg", but if we used PhysReg as the
797 // operand to our 2-addr instruction, the instruction would modify
798 // PhysReg. This isn't cool if something later uses PhysReg and expects
799 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000800 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000801 // To avoid this problem, and to avoid doing a load right after a store,
802 // we emit a copy from PhysReg into the designated register for this
803 // operand.
804 unsigned DesignatedReg = VRM.getPhys(VirtReg);
805 assert(DesignatedReg && "Must map virtreg to physreg!");
806
807 // Note that, if we reused a register for a previous operand, the
808 // register we want to reload into might not actually be
809 // available. If this occurs, use the register indicated by the
810 // reuser.
811 if (ReusedOperands.hasReuses())
812 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
813 Spills, MaybeDeadStores);
814
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000815 // If the mapped designated register is actually the physreg we have
816 // incoming, we don't need to inserted a dead copy.
817 if (DesignatedReg == PhysReg) {
818 // If this stack slot value is already available, reuse it!
Evan Cheng2638e1a2007-03-20 08:13:50 +0000819 if (StackSlot > VirtRegMap::MAX_STACK_SLOT)
820 DOUT << "Reusing RM#" << StackSlot-VirtRegMap::MAX_STACK_SLOT-1;
821 else
822 DOUT << "Reusing SS#" << StackSlot;
823 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000824 << VirtReg
825 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000826 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000827 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000828 ++NumReused;
829 continue;
830 }
831
Chris Lattneraddc55a2006-04-28 01:46:50 +0000832 const TargetRegisterClass* RC =
833 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
834
835 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000836 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000837 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000838
839 // Extend the live range of the MI that last kill the register if
840 // necessary.
Evan Chenga7288df2007-03-03 06:32:37 +0000841 bool WasKill = false;
Evan Chengde4e9422007-02-25 09:51:27 +0000842 if (SSMI) {
843 MachineOperand *MOK = SSMI->findRegisterUseOperand(PhysReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000844 if (MOK) {
845 WasKill = MOK->isKill();
Evan Chengde4e9422007-02-25 09:51:27 +0000846 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000847 }
Evan Chengde4e9422007-02-25 09:51:27 +0000848 }
Evan Cheng6b448092007-03-02 08:52:00 +0000849 MachineInstr *CopyMI = prior(MII);
Evan Chenga7288df2007-03-03 06:32:37 +0000850 if (WasKill) {
851 // Transfer kill to the next use.
852 MachineOperand *MOU = CopyMI->findRegisterUseOperand(PhysReg);
853 MOU->setIsKill();
854 }
855 Spills.addLastUse(PhysReg, CopyMI);
Evan Chengde4e9422007-02-25 09:51:27 +0000856
Chris Lattneraddc55a2006-04-28 01:46:50 +0000857 // This invalidates DesignatedReg.
858 Spills.ClobberPhysReg(DesignatedReg);
859
Evan Cheng91e23902007-02-23 01:13:26 +0000860 Spills.addAvailable(StackSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000861 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000862 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000863 ++NumReused;
864 continue;
865 }
866
867 // Otherwise, reload it and remember that we have it.
868 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000869 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000870 const TargetRegisterClass* RC =
871 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000872
Chris Lattner50ea01e2005-09-09 20:29:51 +0000873 // Note that, if we reused a register for a previous operand, the
874 // register we want to reload into might not actually be
875 // available. If this occurs, use the register indicated by the
876 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000877 if (ReusedOperands.hasReuses())
878 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
879 Spills, MaybeDeadStores);
880
Chris Lattner50ea01e2005-09-09 20:29:51 +0000881 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000882 ReusedOperands.markClobbered(PhysReg);
Evan Cheng2638e1a2007-03-20 08:13:50 +0000883 if (doReMat)
884 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
885 else
886 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000887 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000888 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000889
890 // Any stores to this stack slot are not dead anymore.
Evan Cheng2638e1a2007-03-20 08:13:50 +0000891 if (!doReMat)
892 MaybeDeadStores.erase(StackSlot);
Evan Cheng91e23902007-02-23 01:13:26 +0000893 Spills.addAvailable(StackSlot, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000894 // Assumes this is the last use. IsKill will be unset if reg is reused
895 // unless it's a two-address operand.
896 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
897 MI.getOperand(i).setIsKill();
Chris Lattner50ea01e2005-09-09 20:29:51 +0000898 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000899 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000900 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000901 }
902
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000903 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000904
Chris Lattner7fb64342004-10-01 19:04:51 +0000905 // If we have folded references to memory operands, make sure we clear all
906 // physical registers that may contain the value of the spilled virtual
907 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000908 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
909 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000910 DOUT << "Folded vreg: " << I->second.first << " MR: "
911 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000912 unsigned VirtReg = I->second.first;
913 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000914 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000915 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000916 continue;
917 }
918 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000919 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000920
921 // If this folded instruction is just a use, check to see if it's a
922 // straight load from the virt reg slot.
923 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
924 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000925 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000926 if (FrameIdx == SS) {
927 // If this spill slot is available, turn it into a copy (or nothing)
928 // instead of leaving it as a load!
Evan Chengde4e9422007-02-25 09:51:27 +0000929 MachineInstr *SSMI = NULL;
930 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS, SSMI)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000931 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000932 MachineFunction &MF = *MBB.getParent();
933 if (DestReg != InReg) {
934 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
935 MF.getSSARegMap()->getRegClass(VirtReg));
936 // Revisit the copy so we make sure to notice the effects of the
937 // operation on the destreg (either needing to RA it if it's
938 // virtual or needing to clobber any values if it's physical).
939 NextMII = &MI;
940 --NextMII; // backtrack to the copy.
Evan Chengde4e9422007-02-25 09:51:27 +0000941 } else
942 DOUT << "Removing now-noop copy: " << MI;
943
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000944 // Either way, the live range of the last kill of InReg has been
945 // extended. Remove its kill.
Evan Chenga7288df2007-03-03 06:32:37 +0000946 bool WasKill = false;
Evan Cheng6b448092007-03-02 08:52:00 +0000947 if (SSMI) {
948 MachineOperand *MOK = SSMI->findRegisterUseOperand(InReg, true);
Evan Chenga7288df2007-03-03 06:32:37 +0000949 if (MOK) {
950 WasKill = MOK->isKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000951 MOK->unsetIsKill();
Evan Chenga7288df2007-03-03 06:32:37 +0000952 }
Evan Cheng6b448092007-03-02 08:52:00 +0000953 }
954 if (NextMII != MBB.end()) {
Evan Chengc0ba1bc2007-03-01 02:27:30 +0000955 // If NextMII uses InReg (must be the copy?), mark it killed.
Evan Chengde4e9422007-02-25 09:51:27 +0000956 MachineOperand *MOU = NextMII->findRegisterUseOperand(InReg);
957 if (MOU) {
Evan Chenga7288df2007-03-03 06:32:37 +0000958 if (WasKill)
959 MOU->setIsKill();
Evan Cheng6b448092007-03-02 08:52:00 +0000960 Spills.addLastUse(InReg, &(*NextMII));
Evan Chengde4e9422007-02-25 09:51:27 +0000961 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000962 }
Evan Chengde4e9422007-02-25 09:51:27 +0000963
Chris Lattner6ec36262006-10-12 17:45:38 +0000964 VRM.RemoveFromFoldedVirtMap(&MI);
965 MBB.erase(&MI);
966 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000967 }
Chris Lattnercea86882005-09-19 06:56:21 +0000968 }
969 }
970 }
971
972 // If this reference is not a use, any previous store is now dead.
973 // Otherwise, the store to this stack slot is not dead anymore.
974 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
975 if (MDSI != MaybeDeadStores.end()) {
976 if (MR & VirtRegMap::isRef) // Previous store is not dead.
977 MaybeDeadStores.erase(MDSI);
978 else {
979 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000980 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000981 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000982 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000983 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000984 MaybeDeadStores.erase(MDSI);
985 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000986 }
987 }
988
989 // If the spill slot value is available, and this is a new definition of
990 // the value, the value is not available anymore.
991 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000992 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000993 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000994
995 // If this is *just* a mod of the value, check to see if this is just a
996 // store to the spill slot (i.e. the spill got merged into the copy). If
997 // so, realize that the vreg is available now, and add the store to the
998 // MaybeDeadStore info.
999 int StackSlot;
1000 if (!(MR & VirtRegMap::isRef)) {
1001 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1002 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1003 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001004 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001005 // this as a potentially dead store in case there is a subsequent
1006 // store into the stack slot without a read from it.
1007 MaybeDeadStores[StackSlot] = &MI;
1008
Chris Lattnercd816392006-02-02 23:29:36 +00001009 // If the stack slot value was previously available in some other
1010 // register, change it now. Otherwise, make the register available,
1011 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001012 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001013 }
1014 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001015 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001016 }
1017
Chris Lattner7fb64342004-10-01 19:04:51 +00001018 // Process all of the spilled defs.
1019 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1020 MachineOperand &MO = MI.getOperand(i);
1021 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1022 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001023
Chris Lattner7fb64342004-10-01 19:04:51 +00001024 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001025 // Check to see if this is a noop copy. If so, eliminate the
1026 // instruction before considering the dest reg to be changed.
1027 unsigned Src, Dst;
1028 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1029 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001030 DOUT << "Removing now-noop copy: " << MI;
Evan Cheng6b448092007-03-02 08:52:00 +00001031 Spills.removeLastUse(Src, &MI);
Chris Lattner29268692006-09-05 02:12:02 +00001032 MBB.erase(&MI);
1033 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001034 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001035 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001036 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001037
1038 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001039 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001040 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001041
1042 // Check to see if this instruction is a load from a stack slot into
1043 // a register. If so, this provides the stack slot value in the reg.
1044 int FrameIdx;
1045 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1046 assert(DestReg == VirtReg && "Unknown load situation!");
1047
1048 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001049 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001050 goto ProcessNextInst;
1051 }
1052
Chris Lattner29268692006-09-05 02:12:02 +00001053 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001054 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001055
Chris Lattner84e752a2006-02-03 03:06:49 +00001056 // The only vregs left are stack slot definitions.
1057 int StackSlot = VRM.getStackSlot(VirtReg);
1058 const TargetRegisterClass *RC =
1059 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001060
Chris Lattner29268692006-09-05 02:12:02 +00001061 // If this def is part of a two-address operand, make sure to execute
1062 // the store from the correct physical register.
1063 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001064 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001065 if (TiedOp != -1)
1066 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001067 else {
Chris Lattner29268692006-09-05 02:12:02 +00001068 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001069 if (ReusedOperands.isClobbered(PhysReg)) {
1070 // Another def has taken the assigned physreg. It must have been a
1071 // use&def which got it due to reuse. Undo the reuse!
1072 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1073 Spills, MaybeDeadStores);
1074 }
1075 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001076
Chris Lattner84e752a2006-02-03 03:06:49 +00001077 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +00001078 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001079 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001080 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001081 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001082
Chris Lattner84e752a2006-02-03 03:06:49 +00001083 // If there is a dead store to this stack slot, nuke it now.
1084 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1085 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001086 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001087 ++NumDSE;
1088 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001089 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001090 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001091 LastStore = next(MII);
1092
1093 // If the stack slot value was previously available in some other
1094 // register, change it now. Otherwise, make the register available,
1095 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +00001096 Spills.ModifyStackSlot(StackSlot);
1097 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001098 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001099 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001100
1101 // Check to see if this is a noop copy. If so, eliminate the
1102 // instruction before considering the dest reg to be changed.
1103 {
1104 unsigned Src, Dst;
1105 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1106 ++NumDCE;
1107 DOUT << "Removing now-noop copy: " << MI;
1108 MBB.erase(&MI);
1109 VRM.RemoveFromFoldedVirtMap(&MI);
1110 goto ProcessNextInst;
1111 }
1112 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001113 }
1114 }
Chris Lattnercea86882005-09-19 06:56:21 +00001115 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +00001116 MII = NextMII;
1117 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001118}
1119
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001120
1121
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001122llvm::Spiller* llvm::createSpiller() {
1123 switch (SpillerOpt) {
1124 default: assert(0 && "Unreachable!");
1125 case local:
1126 return new LocalSpiller();
1127 case simple:
1128 return new SimpleSpiller();
1129 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001130}