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Duraid Madinaf2db9b82005-10-28 17:46:35 +00001//===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Duraid Madina and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a pattern matching instruction selector for IA64,
11// converting a legalized dag to an IA64 dag.
12//
13//===----------------------------------------------------------------------===//
14
15#include "IA64.h"
16#include "IA64TargetMachine.h"
17#include "IA64ISelLowering.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/SSARegMap.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/Target/TargetOptions.h"
24#include "llvm/ADT/Statistic.h"
25#include "llvm/Constants.h"
26#include "llvm/GlobalValue.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/MathExtras.h"
29using namespace llvm;
30
31namespace {
32 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
34
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
38 ///
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
42 public:
43 IA64DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
45
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
48 GlobalBaseReg = 0;
49 return SelectionDAGISel::runOnFunction(Fn);
50 }
51
52 /// getI64Imm - Return a target constant with the specified value, of type
53 /// i64.
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
56 }
57
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
61
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
65
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
69 bool Negate = false);
70 SDNode *SelectBitfieldInsert(SDNode *N);
71
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
75
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
78 /// operation.
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
80
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
83
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
87
88 virtual const char *getPassName() const {
89 return "IA64 (Itanium) DAG->DAG Instruction Selector";
90 }
91
92// Include the pieces autogenerated from the target description.
93#include "IA64GenDAGISel.inc"
94
95private:
Duraid Madinab6f023a2005-11-21 14:14:54 +000096 SDOperand SelectDIV(SDOperand Op);
Duraid Madinaf2db9b82005-10-28 17:46:35 +000097 };
98}
99
100/// InstructionSelectBasicBlock - This callback is invoked by
101/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
103 DEBUG(BB->dump());
104
105 // The selection process is inherently a bottom-up recursive process (users
106 // select their uses before themselves). Given infinite stack space, we
107 // could just start selecting on the root and traverse the whole graph. In
108 // practice however, this causes us to run out of stack space on large basic
109 // blocks. To avoid this problem, select the entry node, then all its uses,
110 // iteratively instead of recursively.
111 std::vector<SDOperand> Worklist;
112 Worklist.push_back(DAG.getEntryNode());
113
114 // Note that we can do this in the IA64 target (scanning forward across token
115 // chain edges) because no nodes ever get folded across these edges. On a
116 // target like X86 which supports load/modify/store operations, this would
117 // have to be more careful.
118 while (!Worklist.empty()) {
119 SDOperand Node = Worklist.back();
120 Worklist.pop_back();
121
122 // Chose from the least deep of the top two nodes.
123 if (!Worklist.empty() &&
124 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
125 std::swap(Worklist.back(), Node);
126
127 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
128 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
129 CodeGenMap.count(Node)) continue;
130
131 for (SDNode::use_iterator UI = Node.Val->use_begin(),
132 E = Node.Val->use_end(); UI != E; ++UI) {
133 // Scan the values. If this use has a value that is a token chain, add it
134 // to the worklist.
135 SDNode *User = *UI;
136 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
137 if (User->getValueType(i) == MVT::Other) {
138 Worklist.push_back(SDOperand(User, i));
139 break;
140 }
141 }
142
143 // Finally, legalize this node.
144 Select(Node);
145 }
146
147 // Select target instructions for the DAG.
148 DAG.setRoot(Select(DAG.getRoot()));
149 CodeGenMap.clear();
150 DAG.RemoveDeadNodes();
151
152 // Emit machine code to BB.
153 ScheduleAndEmitDAG(DAG);
154}
155
Duraid Madinab6f023a2005-11-21 14:14:54 +0000156SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
157 SDNode *N = Op.Val;
158 SDOperand Chain = Select(N->getOperand(0));
159
160 SDOperand Tmp1 = Select(N->getOperand(0));
161 SDOperand Tmp2 = Select(N->getOperand(1));
162
163 bool isFP=false;
164
165 if(MVT::isFloatingPoint(Tmp1.getValueType()))
166 isFP=true;
167
168 bool isModulus=false; // is it a division or a modulus?
169 bool isSigned=false;
170
171 switch(N->getOpcode()) {
172 case ISD::FDIV:
173 case ISD::SDIV: isModulus=false; isSigned=true; break;
174 case ISD::UDIV: isModulus=false; isSigned=false; break;
175 case ISD::FREM:
176 case ISD::SREM: isModulus=true; isSigned=true; break;
177 case ISD::UREM: isModulus=true; isSigned=false; break;
178 }
179
180 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
181
182 SDOperand TmpPR, TmpPR2;
183 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
184 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
185 SDOperand Result;
Duraid Madina76bb6ae2006-01-16 14:33:04 +0000186
187 // we'll need copies of F0 and F1
188 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
189 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
Duraid Madinab6f023a2005-11-21 14:14:54 +0000190
191 // OK, emit some code:
192
193 if(!isFP) {
194 // first, load the inputs into FP regs.
195 TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
196 Chain = TmpF1.getValue(1);
197 TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
198 Chain = TmpF2.getValue(1);
199
200 // next, convert the inputs to FP
201 if(isSigned) {
202 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
203 Chain = TmpF3.getValue(1);
204 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
205 Chain = TmpF4.getValue(1);
Duraid Madina0c81dc82006-01-16 06:33:38 +0000206 } else { // is unsigned
Duraid Madina76bb6ae2006-01-16 14:33:04 +0000207 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
208 Chain = TmpF3.getValue(1);
209 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
210 Chain = TmpF4.getValue(1);
Duraid Madinab6f023a2005-11-21 14:14:54 +0000211 }
212
213 } else { // this is an FP divide/remainder, so we 'leak' some temp
214 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
215 TmpF3=Tmp1;
216 TmpF4=Tmp2;
217 }
218
219 // we start by computing an approximate reciprocal (good to 9 bits?)
220 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
Duraid Madina0c81dc82006-01-16 06:33:38 +0000221 if(isFP)
222 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
Duraid Madinab6f023a2005-11-21 14:14:54 +0000223 TmpF3, TmpF4);
Duraid Madina0c81dc82006-01-16 06:33:38 +0000224 else
225 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
226 TmpF3, TmpF4);
227
Duraid Madinab6f023a2005-11-21 14:14:54 +0000228 TmpPR = TmpF5.getValue(1);
229 Chain = TmpF5.getValue(2);
230
Duraid Madinaae6dcdd2006-01-17 01:19:49 +0000231 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, TmpF5);
232
Duraid Madina0c81dc82006-01-16 06:33:38 +0000233 SDOperand minusB;
234 if(isModulus) { // for remainders, it'll be handy to have
235 // copies of -input_b
236 minusB = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
237 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
238 Chain = minusB.getValue(1);
239 }
240
241 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
242
243 TmpE0 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
Duraid Madinab6f023a2005-11-21 14:14:54 +0000244 TmpF4, TmpF5, F1, TmpPR);
Duraid Madina0c81dc82006-01-16 06:33:38 +0000245 Chain = TmpE0.getValue(1);
246 TmpY1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
247 TmpF5, TmpE0, TmpF5, TmpPR);
248 Chain = TmpY1.getValue(1);
249 TmpE1 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
250 TmpE0, TmpE0, F0, TmpPR);
251 Chain = TmpE1.getValue(1);
252 TmpY2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
253 TmpY1, TmpE1, TmpY1, TmpPR);
254 Chain = TmpY2.getValue(1);
Duraid Madinab6f023a2005-11-21 14:14:54 +0000255
Duraid Madina0c81dc82006-01-16 06:33:38 +0000256 if(isFP) { // if this is an FP divide, we finish up here and exit early
257 if(isModulus)
258 assert(0 && "Sorry, try another FORTRAN compiler.");
259
260 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
261
262 TmpE2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
263 TmpE1, TmpE1, F0, TmpPR);
264 Chain = TmpE2.getValue(1);
265 TmpY3 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
266 TmpY2, TmpE2, TmpY2, TmpPR);
267 Chain = TmpY3.getValue(1);
268 TmpQ0 = CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
269 Tmp1, TmpY3, F0, TmpPR);
270 Chain = TmpQ0.getValue(1);
271 TmpR0 = CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
272 Tmp2, TmpQ0, Tmp1, TmpPR);
273 Chain = TmpR0.getValue(1);
Duraid Madinab6f023a2005-11-21 14:14:54 +0000274
Duraid Madina0c81dc82006-01-16 06:33:38 +0000275// we want Result to have the same target register as the frcpa, so
276// we two-address hack it. See the comment "for this to work..." on
277// page 48 of Intel application note #245415
278 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
Duraid Madina76bb6ae2006-01-16 14:33:04 +0000279 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
Duraid Madinab6f023a2005-11-21 14:14:54 +0000280 Chain = Result.getValue(1);
Duraid Madina0c81dc82006-01-16 06:33:38 +0000281 return Result; // XXX: early exit!
282 } else { // this is *not* an FP divide, so there's a bit left to do:
283
284 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
285
286 TmpQ2 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
287 TmpF3, TmpY2, F0, TmpPR);
288 Chain = TmpQ2.getValue(1);
289 TmpR2 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
290 TmpF4, TmpQ2, TmpF3, TmpPR);
291 Chain = TmpR2.getValue(1);
Duraid Madinaae6dcdd2006-01-17 01:19:49 +0000292
Duraid Madina76bb6ae2006-01-16 14:33:04 +0000293// we want TmpQ3 to have the same target register as the frcpa? maybe we
294// should two-address hack it. See the comment "for this to work..." on page
295// 48 of Intel application note #245415
Duraid Madinaae6dcdd2006-01-17 01:19:49 +0000296 TmpQ3 = CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
297 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR);
Duraid Madina0c81dc82006-01-16 06:33:38 +0000298 Chain = TmpQ3.getValue(1);
Duraid Madina76bb6ae2006-01-16 14:33:04 +0000299
Duraid Madinaae6dcdd2006-01-17 01:19:49 +0000300 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
301 // the FPSWA won't be able to help out in the case of large/tiny
302 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
303
Duraid Madina0c81dc82006-01-16 06:33:38 +0000304 if(isSigned)
305 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::f64, TmpQ3);
306 else
307 TmpQ = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::f64, TmpQ3);
308
309 Chain = TmpQ.getValue(1);
310
311 if(isModulus) {
312 SDOperand FPminusB = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64,
313 minusB);
314 Chain = FPminusB.getValue(1);
315 SDOperand Remainder = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
316 TmpQ, FPminusB, TmpF1);
317 Chain = Remainder.getValue(1);
318 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
319 Chain = Result.getValue(1);
320 } else { // just an integer divide
321 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
322 Chain = Result.getValue(1);
323 }
324
325 return Result;
326 } // wasn't an FP divide
Duraid Madinab6f023a2005-11-21 14:14:54 +0000327}
328
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000329// Select - Convert the specified operand from a target-independent to a
330// target-specific node if it hasn't already been changed.
331SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
332 SDNode *N = Op.Val;
333 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
334 N->getOpcode() < IA64ISD::FIRST_NUMBER)
335 return Op; // Already selected.
336
337 // If this has already been converted, use it.
338 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
339 if (CGMI != CodeGenMap.end()) return CGMI->second;
340
341 switch (N->getOpcode()) {
342 default: break;
343
Duraid Madina64aa0ea2005-12-22 13:29:14 +0000344 case IA64ISD::BRCALL: { // XXX: this is also a hack!
345 SDOperand Chain = Select(N->getOperand(0));
346 SDOperand InFlag; // Null incoming flag value.
347
348 if(N->getNumOperands()==3) // we have an incoming chain, callee and flag
349 InFlag = Select(N->getOperand(2));
350
351 unsigned CallOpcode;
352 SDOperand CallOperand;
Duraid Madina64aa0ea2005-12-22 13:29:14 +0000353
354 // if we can call directly, do so
355 if (GlobalAddressSDNode *GASD =
356 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
357 CallOpcode = IA64::BRCALL_IPREL_GA;
358 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
359 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
360 // case for correctness, to avoid
361 // "non-pic code with imm reloc.n
362 // against dynamic symbol" errors
363 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
364 CallOpcode = IA64::BRCALL_IPREL_ES;
365 CallOperand = N->getOperand(1);
366 } else {
367 // otherwise we need to load the function descriptor,
368 // load the branch target (function)'s entry point and GP,
369 // branch (call) then restore the GP
370 SDOperand FnDescriptor = Select(N->getOperand(1));
371
372 // load the branch target's entry point [mem] and
373 // GP value [mem+8]
374 SDOperand targetEntryPoint=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
375 FnDescriptor);
376 Chain = targetEntryPoint.getValue(1);
377 SDOperand targetGPAddr=CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
378 FnDescriptor, CurDAG->getConstant(8, MVT::i64));
379 Chain = targetGPAddr.getValue(1);
380 SDOperand targetGP=CurDAG->getTargetNode(IA64::LD8, MVT::i64,
381 targetGPAddr);
382 Chain = targetGP.getValue(1);
383
384 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
385 InFlag = Chain.getValue(1);
386 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
387 InFlag = Chain.getValue(1);
388
389 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
390 CallOpcode = IA64::BRCALL_INDIRECT;
391 }
392
393 // Finally, once everything is setup, emit the call itself
394 if(InFlag.Val)
Duraid Madinab13d74a2005-12-25 14:09:08 +0000395 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, InFlag);
Duraid Madina64aa0ea2005-12-22 13:29:14 +0000396 else // there might be no arguments
397 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, CallOperand, Chain);
398 InFlag = Chain.getValue(1);
399
400 std::vector<SDOperand> CallResults;
401
402 CallResults.push_back(Chain);
403 CallResults.push_back(InFlag);
404
405 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
406 CodeGenMap[Op.getValue(i)] = CallResults[i];
407 return CallResults[Op.ResNo];
408 }
Duraid Madinaa36153a2005-12-22 03:58:17 +0000409
Duraid Madina8617f3c2005-12-22 07:14:45 +0000410 case IA64ISD::GETFD: {
411 SDOperand Input = Select(N->getOperand(0));
Duraid Madinabf094582006-01-11 03:50:40 +0000412 SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
413 CodeGenMap[Op] = Result;
414 return Result;
Duraid Madina8617f3c2005-12-22 07:14:45 +0000415 }
416
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000417 case ISD::CALL:
Duraid Madinaa36153a2005-12-22 03:58:17 +0000418 case ISD::TAILCALL: { {
419 // FIXME: This is a workaround for a bug in tblgen.
420 // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
421 // Emits: (CALL:void (tglobaladdr:i32):$dst)
422 // Pattern complexity = 2 cost = 1
423 SDOperand N1 = N->getOperand(1);
424 if (N1.getOpcode() != ISD::TargetGlobalAddress &&
425 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
426 SDOperand InFlag = SDOperand(0, 0);
427 SDOperand Chain = N->getOperand(0);
428 SDOperand Tmp0 = N1;
429 Chain = Select(Chain);
430 SDOperand Result;
431 if (N->getNumOperands() == 3) {
432 InFlag = Select(N->getOperand(2));
433 Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag, Tmp0,
434 Chain, InFlag);
435 } else {
436 Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag, Tmp0,
437 Chain);
438 }
439 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
440 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
441 return Result.getValue(Op.ResNo);
442 }
443 P47Fail:;
444
445 }
Duraid Madinab6f023a2005-11-21 14:14:54 +0000446
447 case ISD::FDIV:
448 case ISD::SDIV:
449 case ISD::UDIV:
450 case ISD::SREM:
451 case ISD::UREM: return SelectDIV(Op);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000452
Duraid Madina93856802005-11-02 02:35:04 +0000453 case ISD::ConstantFP: {
Duraid Madina056728f2005-11-02 07:32:59 +0000454 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
455
Duraid Madina93856802005-11-02 02:35:04 +0000456 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
Duraid Madina056728f2005-11-02 07:32:59 +0000457 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
Duraid Madina93856802005-11-02 02:35:04 +0000458 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
Duraid Madina056728f2005-11-02 07:32:59 +0000459 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
Duraid Madina93856802005-11-02 02:35:04 +0000460 else
461 assert(0 && "Unexpected FP constant!");
462 }
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000463
464 case ISD::FrameIndex: { // TODO: reduce creepyness
465 int FI = cast<FrameIndexSDNode>(N)->getIndex();
Chris Lattnerb19b8992005-11-30 23:02:08 +0000466 if (N->hasOneUse())
467 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
468 CurDAG->getTargetFrameIndex(FI, MVT::i64));
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000469 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
470 CurDAG->getTargetFrameIndex(FI, MVT::i64));
471 }
472
Duraid Madina2e0348e2006-01-15 09:45:23 +0000473 case ISD::ConstantPool: { // TODO: nuke the constant pool
474 // (ia64 doesn't need one)
Duraid Madina25d0a882005-10-29 16:08:30 +0000475 Constant *C = cast<ConstantPoolSDNode>(N)->get();
476 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
477 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
478 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
479 }
480
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000481 case ISD::GlobalAddress: {
482 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
483 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
484 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
485 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
486 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
487 }
Duraid Madinaa36153a2005-12-22 03:58:17 +0000488
489/* XXX case ISD::ExternalSymbol: {
490 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
491 MVT::i64);
492 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
493 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
494 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
495 }
496*/
497
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000498 case ISD::LOAD:
499 case ISD::EXTLOAD:
500 case ISD::ZEXTLOAD: {
501 SDOperand Chain = Select(N->getOperand(0));
502 SDOperand Address = Select(N->getOperand(1));
503
504 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
505 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
506 unsigned Opc;
507 switch (TypeBeingLoaded) {
508 default: N->dump(); assert(0 && "Cannot load this type!");
Duraid Madina9f729062005-11-04 09:59:06 +0000509 case MVT::i1: { // this is a bool
510 Opc = IA64::LD1; // first we load a byte, then compare for != 0
Duraid Madinaa36153a2005-12-22 03:58:17 +0000511 if(N->getValueType(0) == MVT::i1) // XXX: early exit!
512 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
Chris Lattnerb19b8992005-11-30 23:02:08 +0000513 CurDAG->getTargetNode(Opc, MVT::i64, Address),
514 CurDAG->getRegister(IA64::r0, MVT::i64),
515 Chain).getValue(Op.ResNo);
Duraid Madinaa36153a2005-12-22 03:58:17 +0000516 /* otherwise, we want to load a bool into something bigger: LD1
517 will do that for us, so we just fall through */
Chris Lattnerb19b8992005-11-30 23:02:08 +0000518 }
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000519 case MVT::i8: Opc = IA64::LD1; break;
520 case MVT::i16: Opc = IA64::LD2; break;
521 case MVT::i32: Opc = IA64::LD4; break;
522 case MVT::i64: Opc = IA64::LD8; break;
523
524 case MVT::f32: Opc = IA64::LDF4; break;
525 case MVT::f64: Opc = IA64::LDF8; break;
526 }
527
Chris Lattnerb19b8992005-11-30 23:02:08 +0000528 // TODO: comment this
529 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
530 Address, Chain).getValue(Op.ResNo);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000531 }
532
533 case ISD::TRUNCSTORE:
534 case ISD::STORE: {
535 SDOperand Address = Select(N->getOperand(2));
Duraid Madinad525df32005-11-07 03:11:02 +0000536 SDOperand Chain = Select(N->getOperand(0));
537
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000538 unsigned Opc;
539 if (N->getOpcode() == ISD::STORE) {
540 switch (N->getOperand(1).getValueType()) {
Duraid Madinad525df32005-11-07 03:11:02 +0000541 default: assert(0 && "unknown type in store");
542 case MVT::i1: { // this is a bool
543 Opc = IA64::ST1; // we store either 0 or 1 as a byte
Duraid Madina544cbbd2006-01-13 10:28:25 +0000544 // first load zero!
545 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
546 Chain = Initial.getValue(1);
547 // then load 1 iff the predicate to store is 1
Chris Lattnerb19b8992005-11-30 23:02:08 +0000548 SDOperand Tmp =
Duraid Madina544cbbd2006-01-13 10:28:25 +0000549 CurDAG->getTargetNode(IA64::PADDS, MVT::i64, Initial,
Chris Lattnerb19b8992005-11-30 23:02:08 +0000550 CurDAG->getConstant(1, MVT::i64),
551 Select(N->getOperand(1)));
552 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
553 }
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000554 case MVT::i64: Opc = IA64::ST8; break;
555 case MVT::f64: Opc = IA64::STF8; break;
Duraid Madinad525df32005-11-07 03:11:02 +0000556 }
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000557 } else { //ISD::TRUNCSTORE
558 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
Duraid Madinad525df32005-11-07 03:11:02 +0000559 default: assert(0 && "unknown type in truncstore");
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000560 case MVT::i8: Opc = IA64::ST1; break;
561 case MVT::i16: Opc = IA64::ST2; break;
562 case MVT::i32: Opc = IA64::ST4; break;
563 case MVT::f32: Opc = IA64::STF4; break;
564 }
565 }
566
Chris Lattnerb19b8992005-11-30 23:02:08 +0000567 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
568 Select(N->getOperand(1)), Chain);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000569 }
570
571 case ISD::BRCOND: {
572 SDOperand Chain = Select(N->getOperand(0));
573 SDOperand CC = Select(N->getOperand(1));
574 MachineBasicBlock *Dest =
575 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
576 //FIXME - we do NOT need long branches all the time
Chris Lattnerb19b8992005-11-30 23:02:08 +0000577 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
578 CurDAG->getBasicBlock(Dest), Chain);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000579 }
580
581 case ISD::CALLSEQ_START:
582 case ISD::CALLSEQ_END: {
583 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
584 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
585 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
Chris Lattnerb19b8992005-11-30 23:02:08 +0000586 return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
587 getI64Imm(Amt), Select(N->getOperand(0)));
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000588 }
589
590 case ISD::RET: {
591 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
Duraid Madinaa36153a2005-12-22 03:58:17 +0000592 SDOperand InFlag;
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000593
594 switch (N->getNumOperands()) {
595 default:
596 assert(0 && "Unknown return instruction!");
597 case 2: {
598 SDOperand RetVal = Select(N->getOperand(1));
599 switch (RetVal.getValueType()) {
600 default: assert(0 && "I don't know how to return this type! (promote?)");
601 // FIXME: do I need to add support for bools here?
602 // (return '0' or '1' in r8, basically...)
603 //
604 // FIXME: need to round floats - 80 bits is bad, the tester
605 // told me so
606 case MVT::i64:
607 // we mark r8 as live on exit up above in LowerArguments()
608 // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
609 Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
Duraid Madinaa36153a2005-12-22 03:58:17 +0000610 InFlag = Chain.getValue(1);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000611 break;
612 case MVT::f64:
613 // we mark F8 as live on exit up above in LowerArguments()
614 // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
615 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
Duraid Madinaa36153a2005-12-22 03:58:17 +0000616 InFlag = Chain.getValue(1);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000617 break;
618 }
619 break;
620 }
621 case 1:
622 break;
623 }
624
625 // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
626 // the output of this function's alloc instruction back into ar.pfs
627 // before we return. this copy must not float up above the last
628 // outgoing call in this function!!!
629 SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
630 MVT::i64);
631 Chain = AR_PFSVal.getValue(1);
632 Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
633
Chris Lattnerb19b8992005-11-30 23:02:08 +0000634 // and then just emit a 'ret' instruction
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000635 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
636 // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
637 //
Chris Lattnerb19b8992005-11-30 23:02:08 +0000638 return CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000639 }
640
641 case ISD::BR:
642 // FIXME: we don't need long branches all the time!
Chris Lattnerb19b8992005-11-30 23:02:08 +0000643 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
644 N->getOperand(1), Select(N->getOperand(0)));
Duraid Madinaf2db9b82005-10-28 17:46:35 +0000645 }
646
647 return SelectCode(Op);
648}
649
650
651/// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
652/// into an IA64-specific DAG, ready for instruction scheduling.
653///
654FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
655 return new IA64DAGToDAGISel(TM);
656}
657