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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 3f71cf14b224d8c4f5634296ab785e227ba3c03c / . / lib / Target / NVPTX / NVPTXISelDAGToDAG.cpp
blob: e26f9e4bf56f4cd564e3e547d2b6b72a490ab1cd [file] [log] [blame]
Justin Holewinski49683f32012-05-04 20:18:50 +0000[diff] [blame]1//===-- NVPTXISelDAGToDAG.cpp - A dag to dag inst selector for NVPTX ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the NVPTX target.
11//
12//===----------------------------------------------------------------------===//
13
14
15#include "llvm/Instructions.h"
16#include "llvm/Support/raw_ostream.h"
17#include "NVPTXISelDAGToDAG.h"
18#include "llvm/Support/Debug.h"
19#include "llvm/Support/ErrorHandling.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Target/TargetIntrinsicInfo.h"
22#include "llvm/GlobalValue.h"
23
24#undef DEBUG_TYPE
25#define DEBUG_TYPE "nvptx-isel"
26
27using namespace llvm;
28
29
30static cl::opt<bool>
31UseFMADInstruction("nvptx-mad-enable",
32 cl::ZeroOrMore,
33 cl::desc("NVPTX Specific: Enable generating FMAD instructions"),
34 cl::init(false));
35
36static cl::opt<int>
37FMAContractLevel("nvptx-fma-level",
38 cl::ZeroOrMore,
39 cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
40 " 1: do it 2: do it aggressively"),
41 cl::init(2));
42
43
44static cl::opt<int>
45UsePrecDivF32("nvptx-prec-divf32",
46 cl::ZeroOrMore,
47 cl::desc("NVPTX Specifies: 0 use div.approx, 1 use div.full, 2 use"
48 " IEEE Compliant F32 div.rnd if avaiable."),
49 cl::init(2));
50
51/// createNVPTXISelDag - This pass converts a legalized DAG into a
52/// NVPTX-specific DAG, ready for instruction scheduling.
53FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM,
54 llvm::CodeGenOpt::Level OptLevel) {
55 return new NVPTXDAGToDAGISel(TM, OptLevel);
56}
57
58
59NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm,
60 CodeGenOpt::Level OptLevel)
61: SelectionDAGISel(tm, OptLevel),
62 Subtarget(tm.getSubtarget<NVPTXSubtarget>())
63{
64 // Always do fma.f32 fpcontract if the target supports the instruction.
65 // Always do fma.f64 fpcontract if the target supports the instruction.
66 // Do mad.f32 is nvptx-mad-enable is specified and the target does not
67 // support fma.f32.
68
69 doFMADF32 = (OptLevel > 0) && UseFMADInstruction && !Subtarget.hasFMAF32();
70 doFMAF32 = (OptLevel > 0) && Subtarget.hasFMAF32() &&
71 (FMAContractLevel>=1);
72 doFMAF64 = (OptLevel > 0) && Subtarget.hasFMAF64() &&
73 (FMAContractLevel>=1);
74 doFMAF32AGG = (OptLevel > 0) && Subtarget.hasFMAF32() &&
75 (FMAContractLevel==2);
76 doFMAF64AGG = (OptLevel > 0) && Subtarget.hasFMAF64() &&
77 (FMAContractLevel==2);
78
79 allowFMA = (FMAContractLevel >= 1) || UseFMADInstruction;
80
81 doMulWide = (OptLevel > 0);
82
83 // Decide how to translate f32 div
84 do_DIVF32_PREC = UsePrecDivF32;
85 // sm less than sm_20 does not support div.rnd. Use div.full.
86 if (do_DIVF32_PREC == 2 && !Subtarget.reqPTX20())
87 do_DIVF32_PREC = 1;
88
89}
90
91/// Select - Select instructions not customized! Used for
92/// expanded, promoted and normal instructions.
93SDNode* NVPTXDAGToDAGISel::Select(SDNode *N) {
94
95 if (N->isMachineOpcode())
96 return NULL; // Already selected.
97
98 SDNode *ResNode = NULL;
99 switch (N->getOpcode()) {
100 case ISD::LOAD:
101 ResNode = SelectLoad(N);
102 break;
103 case ISD::STORE:
104 ResNode = SelectStore(N);
105 break;
106 }
107 if (ResNode)
108 return ResNode;
109 return SelectCode(N);
110}
111
112
113static unsigned int
114getCodeAddrSpace(MemSDNode *N, const NVPTXSubtarget &Subtarget)
115{
116 const Value *Src = N->getSrcValue();
117 if (!Src)
118 return NVPTX::PTXLdStInstCode::LOCAL;
119
120 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType())) {
121 switch (PT->getAddressSpace()) {
122 case llvm::ADDRESS_SPACE_LOCAL: return NVPTX::PTXLdStInstCode::LOCAL;
123 case llvm::ADDRESS_SPACE_GLOBAL: return NVPTX::PTXLdStInstCode::GLOBAL;
124 case llvm::ADDRESS_SPACE_SHARED: return NVPTX::PTXLdStInstCode::SHARED;
125 case llvm::ADDRESS_SPACE_CONST_NOT_GEN:
126 return NVPTX::PTXLdStInstCode::CONSTANT;
127 case llvm::ADDRESS_SPACE_GENERIC: return NVPTX::PTXLdStInstCode::GENERIC;
128 case llvm::ADDRESS_SPACE_PARAM: return NVPTX::PTXLdStInstCode::PARAM;
129 case llvm::ADDRESS_SPACE_CONST:
130 // If the arch supports generic address space, translate it to GLOBAL
131 // for correctness.
132 // If the arch does not support generic address space, then the arch
133 // does not really support ADDRESS_SPACE_CONST, translate it to
134 // to CONSTANT for better performance.
135 if (Subtarget.hasGenericLdSt())
136 return NVPTX::PTXLdStInstCode::GLOBAL;
137 else
138 return NVPTX::PTXLdStInstCode::CONSTANT;
139 default: break;
140 }
141 }
142 return NVPTX::PTXLdStInstCode::LOCAL;
143}
144
145
146SDNode* NVPTXDAGToDAGISel::SelectLoad(SDNode *N) {
147 DebugLoc dl = N->getDebugLoc();
148 LoadSDNode *LD = cast<LoadSDNode>(N);
149 EVT LoadedVT = LD->getMemoryVT();
150 SDNode *NVPTXLD= NULL;
151
152 // do not support pre/post inc/dec
153 if (LD->isIndexed())
154 return NULL;
155
156 if (!LoadedVT.isSimple())
157 return NULL;
158
159 // Address Space Setting
160 unsigned int codeAddrSpace = getCodeAddrSpace(LD, Subtarget);
161
162 // Volatile Setting
163 // - .volatile is only availalble for .global and .shared
164 bool isVolatile = LD->isVolatile();
165 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
166 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
167 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
168 isVolatile = false;
169
170 // Vector Setting
171 MVT SimpleVT = LoadedVT.getSimpleVT();
172 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
173 if (SimpleVT.isVector()) {
174 unsigned num = SimpleVT.getVectorNumElements();
175 if (num == 2)
176 vecType = NVPTX::PTXLdStInstCode::V2;
177 else if (num == 4)
178 vecType = NVPTX::PTXLdStInstCode::V4;
179 else
180 return NULL;
181 }
182
183 // Type Setting: fromType + fromTypeWidth
184 //
185 // Sign : ISD::SEXTLOAD
186 // Unsign : ISD::ZEXTLOAD, ISD::NON_EXTLOAD or ISD::EXTLOAD and the
187 // type is integer
188 // Float : ISD::NON_EXTLOAD or ISD::EXTLOAD and the type is float
189 MVT ScalarVT = SimpleVT.getScalarType();
190 unsigned fromTypeWidth = ScalarVT.getSizeInBits();
191 unsigned int fromType;
192 if ((LD->getExtensionType() == ISD::SEXTLOAD))
193 fromType = NVPTX::PTXLdStInstCode::Signed;
194 else if (ScalarVT.isFloatingPoint())
195 fromType = NVPTX::PTXLdStInstCode::Float;
196 else
197 fromType = NVPTX::PTXLdStInstCode::Unsigned;
198
199 // Create the machine instruction DAG
200 SDValue Chain = N->getOperand(0);
201 SDValue N1 = N->getOperand(1);
202 SDValue Addr;
203 SDValue Offset, Base;
204 unsigned Opcode;
205 MVT::SimpleValueType TargetVT = LD->getValueType(0).getSimpleVT().SimpleTy;
206
207 if (SelectDirectAddr(N1, Addr)) {
208 switch (TargetVT) {
209 case MVT::i8: Opcode = NVPTX::LD_i8_avar; break;
210 case MVT::i16: Opcode = NVPTX::LD_i16_avar; break;
211 case MVT::i32: Opcode = NVPTX::LD_i32_avar; break;
212 case MVT::i64: Opcode = NVPTX::LD_i64_avar; break;
213 case MVT::f32: Opcode = NVPTX::LD_f32_avar; break;
214 case MVT::f64: Opcode = NVPTX::LD_f64_avar; break;
215 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_avar; break;
216 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_avar; break;
217 case MVT::v2i32: Opcode = NVPTX::LD_v2i32_avar; break;
218 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_avar; break;
219 case MVT::v2f32: Opcode = NVPTX::LD_v2f32_avar; break;
220 case MVT::v2f64: Opcode = NVPTX::LD_v2f64_avar; break;
221 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_avar; break;
222 case MVT::v4i16: Opcode = NVPTX::LD_v4i16_avar; break;
223 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_avar; break;
224 case MVT::v4f32: Opcode = NVPTX::LD_v4f32_avar; break;
225 default: return NULL;
226 }
227 SDValue Ops[] = { getI32Imm(isVolatile),
228 getI32Imm(codeAddrSpace),
229 getI32Imm(vecType),
230 getI32Imm(fromType),
231 getI32Imm(fromTypeWidth),
232 Addr, Chain };
233 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
234 MVT::Other, Ops, 7);
235 } else if (Subtarget.is64Bit()?
236 SelectADDRsi64(N1.getNode(), N1, Base, Offset):
237 SelectADDRsi(N1.getNode(), N1, Base, Offset)) {
238 switch (TargetVT) {
239 case MVT::i8: Opcode = NVPTX::LD_i8_asi; break;
240 case MVT::i16: Opcode = NVPTX::LD_i16_asi; break;
241 case MVT::i32: Opcode = NVPTX::LD_i32_asi; break;
242 case MVT::i64: Opcode = NVPTX::LD_i64_asi; break;
243 case MVT::f32: Opcode = NVPTX::LD_f32_asi; break;
244 case MVT::f64: Opcode = NVPTX::LD_f64_asi; break;
245 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_asi; break;
246 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_asi; break;
247 case MVT::v2i32: Opcode = NVPTX::LD_v2i32_asi; break;
248 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_asi; break;
249 case MVT::v2f32: Opcode = NVPTX::LD_v2f32_asi; break;
250 case MVT::v2f64: Opcode = NVPTX::LD_v2f64_asi; break;
251 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_asi; break;
252 case MVT::v4i16: Opcode = NVPTX::LD_v4i16_asi; break;
253 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_asi; break;
254 case MVT::v4f32: Opcode = NVPTX::LD_v4f32_asi; break;
255 default: return NULL;
256 }
257 SDValue Ops[] = { getI32Imm(isVolatile),
258 getI32Imm(codeAddrSpace),
259 getI32Imm(vecType),
260 getI32Imm(fromType),
261 getI32Imm(fromTypeWidth),
262 Base, Offset, Chain };
263 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
264 MVT::Other, Ops, 8);
265 } else if (Subtarget.is64Bit()?
266 SelectADDRri64(N1.getNode(), N1, Base, Offset):
267 SelectADDRri(N1.getNode(), N1, Base, Offset)) {
268 switch (TargetVT) {
269 case MVT::i8: Opcode = NVPTX::LD_i8_ari; break;
270 case MVT::i16: Opcode = NVPTX::LD_i16_ari; break;
271 case MVT::i32: Opcode = NVPTX::LD_i32_ari; break;
272 case MVT::i64: Opcode = NVPTX::LD_i64_ari; break;
273 case MVT::f32: Opcode = NVPTX::LD_f32_ari; break;
274 case MVT::f64: Opcode = NVPTX::LD_f64_ari; break;
275 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_ari; break;
276 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_ari; break;
277 case MVT::v2i32: Opcode = NVPTX::LD_v2i32_ari; break;
278 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_ari; break;
279 case MVT::v2f32: Opcode = NVPTX::LD_v2f32_ari; break;
280 case MVT::v2f64: Opcode = NVPTX::LD_v2f64_ari; break;
281 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_ari; break;
282 case MVT::v4i16: Opcode = NVPTX::LD_v4i16_ari; break;
283 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_ari; break;
284 case MVT::v4f32: Opcode = NVPTX::LD_v4f32_ari; break;
285 default: return NULL;
286 }
287 SDValue Ops[] = { getI32Imm(isVolatile),
288 getI32Imm(codeAddrSpace),
289 getI32Imm(vecType),
290 getI32Imm(fromType),
291 getI32Imm(fromTypeWidth),
292 Base, Offset, Chain };
293 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
294 MVT::Other, Ops, 8);
295 }
296 else {
297 switch (TargetVT) {
298 case MVT::i8: Opcode = NVPTX::LD_i8_areg; break;
299 case MVT::i16: Opcode = NVPTX::LD_i16_areg; break;
300 case MVT::i32: Opcode = NVPTX::LD_i32_areg; break;
301 case MVT::i64: Opcode = NVPTX::LD_i64_areg; break;
302 case MVT::f32: Opcode = NVPTX::LD_f32_areg; break;
303 case MVT::f64: Opcode = NVPTX::LD_f64_areg; break;
304 case MVT::v2i8: Opcode = NVPTX::LD_v2i8_areg; break;
305 case MVT::v2i16: Opcode = NVPTX::LD_v2i16_areg; break;
306 case MVT::v2i32: Opcode = NVPTX::LD_v2i32_areg; break;
307 case MVT::v2i64: Opcode = NVPTX::LD_v2i64_areg; break;
308 case MVT::v2f32: Opcode = NVPTX::LD_v2f32_areg; break;
309 case MVT::v2f64: Opcode = NVPTX::LD_v2f64_areg; break;
310 case MVT::v4i8: Opcode = NVPTX::LD_v4i8_areg; break;
311 case MVT::v4i16: Opcode = NVPTX::LD_v4i16_areg; break;
312 case MVT::v4i32: Opcode = NVPTX::LD_v4i32_areg; break;
313 case MVT::v4f32: Opcode = NVPTX::LD_v4f32_areg; break;
314 default: return NULL;
315 }
316 SDValue Ops[] = { getI32Imm(isVolatile),
317 getI32Imm(codeAddrSpace),
318 getI32Imm(vecType),
319 getI32Imm(fromType),
320 getI32Imm(fromTypeWidth),
321 N1, Chain };
322 NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT,
323 MVT::Other, Ops, 7);
324 }
325
326 if (NVPTXLD != NULL) {
327 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
328 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
329 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1);
330 }
331
332 return NVPTXLD;
333}
334
335SDNode* NVPTXDAGToDAGISel::SelectStore(SDNode *N) {
336 DebugLoc dl = N->getDebugLoc();
337 StoreSDNode *ST = cast<StoreSDNode>(N);
338 EVT StoreVT = ST->getMemoryVT();
339 SDNode *NVPTXST = NULL;
340
341 // do not support pre/post inc/dec
342 if (ST->isIndexed())
343 return NULL;
344
345 if (!StoreVT.isSimple())
346 return NULL;
347
348 // Address Space Setting
349 unsigned int codeAddrSpace = getCodeAddrSpace(ST, Subtarget);
350
351 // Volatile Setting
352 // - .volatile is only availalble for .global and .shared
353 bool isVolatile = ST->isVolatile();
354 if (codeAddrSpace != NVPTX::PTXLdStInstCode::GLOBAL &&
355 codeAddrSpace != NVPTX::PTXLdStInstCode::SHARED &&
356 codeAddrSpace != NVPTX::PTXLdStInstCode::GENERIC)
357 isVolatile = false;
358
359 // Vector Setting
360 MVT SimpleVT = StoreVT.getSimpleVT();
361 unsigned vecType = NVPTX::PTXLdStInstCode::Scalar;
362 if (SimpleVT.isVector()) {
363 unsigned num = SimpleVT.getVectorNumElements();
364 if (num == 2)
365 vecType = NVPTX::PTXLdStInstCode::V2;
366 else if (num == 4)
367 vecType = NVPTX::PTXLdStInstCode::V4;
368 else
369 return NULL;
370 }
371
372 // Type Setting: toType + toTypeWidth
373 // - for integer type, always use 'u'
374 //
375 MVT ScalarVT = SimpleVT.getScalarType();
376 unsigned toTypeWidth = ScalarVT.getSizeInBits();
377 unsigned int toType;
378 if (ScalarVT.isFloatingPoint())
379 toType = NVPTX::PTXLdStInstCode::Float;
380 else
381 toType = NVPTX::PTXLdStInstCode::Unsigned;
382
383 // Create the machine instruction DAG
384 SDValue Chain = N->getOperand(0);
385 SDValue N1 = N->getOperand(1);
386 SDValue N2 = N->getOperand(2);
387 SDValue Addr;
388 SDValue Offset, Base;
389 unsigned Opcode;
390 MVT::SimpleValueType SourceVT =
391 N1.getNode()->getValueType(0).getSimpleVT().SimpleTy;
392
393 if (SelectDirectAddr(N2, Addr)) {
394 switch (SourceVT) {
395 case MVT::i8: Opcode = NVPTX::ST_i8_avar; break;
396 case MVT::i16: Opcode = NVPTX::ST_i16_avar; break;
397 case MVT::i32: Opcode = NVPTX::ST_i32_avar; break;
398 case MVT::i64: Opcode = NVPTX::ST_i64_avar; break;
399 case MVT::f32: Opcode = NVPTX::ST_f32_avar; break;
400 case MVT::f64: Opcode = NVPTX::ST_f64_avar; break;
401 case MVT::v2i8: Opcode = NVPTX::ST_v2i8_avar; break;
402 case MVT::v2i16: Opcode = NVPTX::ST_v2i16_avar; break;
403 case MVT::v2i32: Opcode = NVPTX::ST_v2i32_avar; break;
404 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_avar; break;
405 case MVT::v2f32: Opcode = NVPTX::ST_v2f32_avar; break;
406 case MVT::v2f64: Opcode = NVPTX::ST_v2f64_avar; break;
407 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_avar; break;
408 case MVT::v4i16: Opcode = NVPTX::ST_v4i16_avar; break;
409 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_avar; break;
410 case MVT::v4f32: Opcode = NVPTX::ST_v4f32_avar; break;
411 default: return NULL;
412 }
413 SDValue Ops[] = { N1,
414 getI32Imm(isVolatile),
415 getI32Imm(codeAddrSpace),
416 getI32Imm(vecType),
417 getI32Imm(toType),
418 getI32Imm(toTypeWidth),
419 Addr, Chain };
420 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
421 MVT::Other, Ops, 8);
422 } else if (Subtarget.is64Bit()?
423 SelectADDRsi64(N2.getNode(), N2, Base, Offset):
424 SelectADDRsi(N2.getNode(), N2, Base, Offset)) {
425 switch (SourceVT) {
426 case MVT::i8: Opcode = NVPTX::ST_i8_asi; break;
427 case MVT::i16: Opcode = NVPTX::ST_i16_asi; break;
428 case MVT::i32: Opcode = NVPTX::ST_i32_asi; break;
429 case MVT::i64: Opcode = NVPTX::ST_i64_asi; break;
430 case MVT::f32: Opcode = NVPTX::ST_f32_asi; break;
431 case MVT::f64: Opcode = NVPTX::ST_f64_asi; break;
432 case MVT::v2i8: Opcode = NVPTX::ST_v2i8_asi; break;
433 case MVT::v2i16: Opcode = NVPTX::ST_v2i16_asi; break;
434 case MVT::v2i32: Opcode = NVPTX::ST_v2i32_asi; break;
435 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_asi; break;
436 case MVT::v2f32: Opcode = NVPTX::ST_v2f32_asi; break;
437 case MVT::v2f64: Opcode = NVPTX::ST_v2f64_asi; break;
438 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_asi; break;
439 case MVT::v4i16: Opcode = NVPTX::ST_v4i16_asi; break;
440 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_asi; break;
441 case MVT::v4f32: Opcode = NVPTX::ST_v4f32_asi; break;
442 default: return NULL;
443 }
444 SDValue Ops[] = { N1,
445 getI32Imm(isVolatile),
446 getI32Imm(codeAddrSpace),
447 getI32Imm(vecType),
448 getI32Imm(toType),
449 getI32Imm(toTypeWidth),
450 Base, Offset, Chain };
451 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
452 MVT::Other, Ops, 9);
453 } else if (Subtarget.is64Bit()?
454 SelectADDRri64(N2.getNode(), N2, Base, Offset):
455 SelectADDRri(N2.getNode(), N2, Base, Offset)) {
456 switch (SourceVT) {
457 case MVT::i8: Opcode = NVPTX::ST_i8_ari; break;
458 case MVT::i16: Opcode = NVPTX::ST_i16_ari; break;
459 case MVT::i32: Opcode = NVPTX::ST_i32_ari; break;
460 case MVT::i64: Opcode = NVPTX::ST_i64_ari; break;
461 case MVT::f32: Opcode = NVPTX::ST_f32_ari; break;
462 case MVT::f64: Opcode = NVPTX::ST_f64_ari; break;
463 case MVT::v2i8: Opcode = NVPTX::ST_v2i8_ari; break;
464 case MVT::v2i16: Opcode = NVPTX::ST_v2i16_ari; break;
465 case MVT::v2i32: Opcode = NVPTX::ST_v2i32_ari; break;
466 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_ari; break;
467 case MVT::v2f32: Opcode = NVPTX::ST_v2f32_ari; break;
468 case MVT::v2f64: Opcode = NVPTX::ST_v2f64_ari; break;
469 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_ari; break;
470 case MVT::v4i16: Opcode = NVPTX::ST_v4i16_ari; break;
471 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_ari; break;
472 case MVT::v4f32: Opcode = NVPTX::ST_v4f32_ari; break;
473 default: return NULL;
474 }
475 SDValue Ops[] = { N1,
476 getI32Imm(isVolatile),
477 getI32Imm(codeAddrSpace),
478 getI32Imm(vecType),
479 getI32Imm(toType),
480 getI32Imm(toTypeWidth),
481 Base, Offset, Chain };
482 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
483 MVT::Other, Ops, 9);
484 } else {
485 switch (SourceVT) {
486 case MVT::i8: Opcode = NVPTX::ST_i8_areg; break;
487 case MVT::i16: Opcode = NVPTX::ST_i16_areg; break;
488 case MVT::i32: Opcode = NVPTX::ST_i32_areg; break;
489 case MVT::i64: Opcode = NVPTX::ST_i64_areg; break;
490 case MVT::f32: Opcode = NVPTX::ST_f32_areg; break;
491 case MVT::f64: Opcode = NVPTX::ST_f64_areg; break;
492 case MVT::v2i8: Opcode = NVPTX::ST_v2i8_areg; break;
493 case MVT::v2i16: Opcode = NVPTX::ST_v2i16_areg; break;
494 case MVT::v2i32: Opcode = NVPTX::ST_v2i32_areg; break;
495 case MVT::v2i64: Opcode = NVPTX::ST_v2i64_areg; break;
496 case MVT::v2f32: Opcode = NVPTX::ST_v2f32_areg; break;
497 case MVT::v2f64: Opcode = NVPTX::ST_v2f64_areg; break;
498 case MVT::v4i8: Opcode = NVPTX::ST_v4i8_areg; break;
499 case MVT::v4i16: Opcode = NVPTX::ST_v4i16_areg; break;
500 case MVT::v4i32: Opcode = NVPTX::ST_v4i32_areg; break;
501 case MVT::v4f32: Opcode = NVPTX::ST_v4f32_areg; break;
502 default: return NULL;
503 }
504 SDValue Ops[] = { N1,
505 getI32Imm(isVolatile),
506 getI32Imm(codeAddrSpace),
507 getI32Imm(vecType),
508 getI32Imm(toType),
509 getI32Imm(toTypeWidth),
510 N2, Chain };
511 NVPTXST = CurDAG->getMachineNode(Opcode, dl,
512 MVT::Other, Ops, 8);
513 }
514
515 if (NVPTXST != NULL) {
516 MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
517 MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
518 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1);
519 }
520
521 return NVPTXST;
522}
523
524// SelectDirectAddr - Match a direct address for DAG.
525// A direct address could be a globaladdress or externalsymbol.
526bool NVPTXDAGToDAGISel::SelectDirectAddr(SDValue N, SDValue &Address) {
527 // Return true if TGA or ES.
528 if (N.getOpcode() == ISD::TargetGlobalAddress
529 || N.getOpcode() == ISD::TargetExternalSymbol) {
530 Address = N;
531 return true;
532 }
533 if (N.getOpcode() == NVPTXISD::Wrapper) {
534 Address = N.getOperand(0);
535 return true;
536 }
537 if (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
538 unsigned IID = cast<ConstantSDNode>(N.getOperand(0))->getZExtValue();
539 if (IID == Intrinsic::nvvm_ptr_gen_to_param)
540 if (N.getOperand(1).getOpcode() == NVPTXISD::MoveParam)
541 return (SelectDirectAddr(N.getOperand(1).getOperand(0), Address));
542 }
543 return false;
544}
545
546// symbol+offset
547bool NVPTXDAGToDAGISel::SelectADDRsi_imp(SDNode *OpNode, SDValue Addr,
548 SDValue &Base, SDValue &Offset,
549 MVT mvt) {
550 if (Addr.getOpcode() == ISD::ADD) {
551 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
552 SDValue base=Addr.getOperand(0);
553 if (SelectDirectAddr(base, Base)) {
554 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
555 return true;
556 }
557 }
558 }
559 return false;
560}
561
562// symbol+offset
563bool NVPTXDAGToDAGISel::SelectADDRsi(SDNode *OpNode, SDValue Addr,
564 SDValue &Base, SDValue &Offset) {
565 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i32);
566}
567
568// symbol+offset
569bool NVPTXDAGToDAGISel::SelectADDRsi64(SDNode *OpNode, SDValue Addr,
570 SDValue &Base, SDValue &Offset) {
571 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64);
572}
573
574// register+offset
575bool NVPTXDAGToDAGISel::SelectADDRri_imp(SDNode *OpNode, SDValue Addr,
576 SDValue &Base, SDValue &Offset,
577 MVT mvt) {
578 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
579 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
580 Offset = CurDAG->getTargetConstant(0, mvt);
581 return true;
582 }
583 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
584 Addr.getOpcode() == ISD::TargetGlobalAddress)
585 return false; // direct calls.
586
587 if (Addr.getOpcode() == ISD::ADD) {
588 if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
589 return false;
590 }
591 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
592 if (FrameIndexSDNode *FIN =
593 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
594 // Constant offset from frame ref.
595 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), mvt);
596 else
597 Base = Addr.getOperand(0);
598 Offset = CurDAG->getTargetConstant(CN->getZExtValue(), mvt);
599 return true;
600 }
601 }
602 return false;
603}
604
605// register+offset
606bool NVPTXDAGToDAGISel::SelectADDRri(SDNode *OpNode, SDValue Addr,
607 SDValue &Base, SDValue &Offset) {
608 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i32);
609}
610
611// register+offset
612bool NVPTXDAGToDAGISel::SelectADDRri64(SDNode *OpNode, SDValue Addr,
613 SDValue &Base, SDValue &Offset) {
614 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64);
615}
616
617bool NVPTXDAGToDAGISel::ChkMemSDNodeAddressSpace(SDNode *N,
618 unsigned int spN) const {
619 const Value *Src = NULL;
620 // Even though MemIntrinsicSDNode is a subclas of MemSDNode,
621 // the classof() for MemSDNode does not include MemIntrinsicSDNode
622 // (See SelectionDAGNodes.h). So we need to check for both.
623 if (MemSDNode *mN = dyn_cast<MemSDNode>(N)) {
624 Src = mN->getSrcValue();
625 }
626 else if (MemSDNode *mN = dyn_cast<MemIntrinsicSDNode>(N)) {
627 Src = mN->getSrcValue();
628 }
629 if (!Src)
630 return false;
631 if (const PointerType *PT = dyn_cast<PointerType>(Src->getType()))
632 return (PT->getAddressSpace() == spN);
633 return false;
634}
635
636/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
637/// inline asm expressions.
638bool NVPTXDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
639 char ConstraintCode,
640 std::vector<SDValue> &OutOps) {
641 SDValue Op0, Op1;
642 switch (ConstraintCode) {
643 default: return true;
644 case 'm': // memory
645 if (SelectDirectAddr(Op, Op0)) {
646 OutOps.push_back(Op0);
647 OutOps.push_back(CurDAG->getTargetConstant(0, MVT::i32));
648 return false;
649 }
650 if (SelectADDRri(Op.getNode(), Op, Op0, Op1)) {
651 OutOps.push_back(Op0);
652 OutOps.push_back(Op1);
653 return false;
654 }
655 break;
656 }
657 return true;
658}
659
660// Return true if N is a undef or a constant.
661// If N was undef, return a (i8imm 0) in Retval
662// If N was imm, convert it to i8imm and return in Retval
663// Note: The convert to i8imm is required, otherwise the
664// pattern matcher inserts a bunch of IMOVi8rr to convert
665// the imm to i8imm, and this causes instruction selection
666// to fail.
667bool NVPTXDAGToDAGISel::UndefOrImm(SDValue Op, SDValue N,
668 SDValue &Retval) {
669 if (!(N.getOpcode() == ISD::UNDEF) &&
670 !(N.getOpcode() == ISD::Constant))
671 return false;
672
673 if (N.getOpcode() == ISD::UNDEF)
674 Retval = CurDAG->getTargetConstant(0, MVT::i8);
675 else {
676 ConstantSDNode *cn = cast<ConstantSDNode>(N.getNode());
677 unsigned retval = cn->getZExtValue();
678 Retval = CurDAG->getTargetConstant(retval, MVT::i8);
679 }
680 return true;
681}