Dan Gohman | 0a06310 | 2009-09-08 23:54:48 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s |
Mon P Wang | bc3c526 | 2009-09-03 19:57:35 +0000 | [diff] [blame] | 2 | |
| 3 | ; When loading the shift amount from memory, avoid generating the splat. |
| 4 | |
| 5 | define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind { |
| 6 | entry: |
| 7 | ; CHECK: shift5a: |
| 8 | ; CHECK: movd |
| 9 | ; CHECK-NEXT: pslld |
| 10 | %amt = load i32* %pamt |
| 11 | %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0 |
| 12 | %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer |
| 13 | %shl = shl <4 x i32> %val, %shamt |
| 14 | store <4 x i32> %shl, <4 x i32>* %dst |
| 15 | ret void |
| 16 | } |
| 17 | |
| 18 | |
| 19 | define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind { |
| 20 | entry: |
| 21 | ; CHECK: shift5b: |
| 22 | ; CHECK: movd |
| 23 | ; CHECK-NEXT: psrad |
| 24 | %amt = load i32* %pamt |
| 25 | %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0 |
| 26 | %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer |
| 27 | %shr = ashr <4 x i32> %val, %shamt |
| 28 | store <4 x i32> %shr, <4 x i32>* %dst |
| 29 | ret void |
| 30 | } |
| 31 | |
| 32 | |
| 33 | define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind { |
| 34 | entry: |
| 35 | ; CHECK: shift5c: |
| 36 | ; CHECK: movd |
| 37 | ; CHECK-NEXT: pslld |
| 38 | %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0 |
| 39 | %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer |
| 40 | %shl = shl <4 x i32> %val, %shamt |
| 41 | store <4 x i32> %shl, <4 x i32>* %dst |
| 42 | ret void |
| 43 | } |
| 44 | |
| 45 | |
| 46 | define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind { |
| 47 | entry: |
| 48 | ; CHECK: shift5d: |
| 49 | ; CHECK: movd |
| 50 | ; CHECK-NEXT: psrad |
| 51 | %tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0 |
| 52 | %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer |
| 53 | %shr = ashr <4 x i32> %val, %shamt |
| 54 | store <4 x i32> %shr, <4 x i32>* %dst |
| 55 | ret void |
| 56 | } |