Jia Liu | 31d157a | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file contains the base ARM implementation of TargetRegisterInfo class. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Craig Topper | c1f6f42 | 2012-03-17 07:33:42 +0000 | [diff] [blame] | 14 | #include "ARMBaseRegisterInfo.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 15 | #include "ARM.h" |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 16 | #include "ARMBaseInstrInfo.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 17 | #include "ARMFrameLowering.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 18 | #include "ARMMachineFunctionInfo.h" |
| 19 | #include "ARMSubtarget.h" |
Evan Cheng | ee04a6d | 2011-07-20 23:34:39 +0000 | [diff] [blame] | 20 | #include "MCTargetDesc/ARMAddressingModes.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 21 | #include "llvm/Constants.h" |
| 22 | #include "llvm/DerivedTypes.h" |
Owen Anderson | 9adc0ab | 2009-07-14 23:09:55 +0000 | [diff] [blame] | 23 | #include "llvm/Function.h" |
| 24 | #include "llvm/LLVMContext.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 25 | #include "llvm/CodeGen/MachineConstantPool.h" |
| 26 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 27 | #include "llvm/CodeGen/MachineFunction.h" |
| 28 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 29 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 30 | #include "llvm/CodeGen/RegisterScavenging.h" |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 31 | #include "llvm/Support/Debug.h" |
Torok Edwin | ab7c09b | 2009-07-08 18:01:40 +0000 | [diff] [blame] | 32 | #include "llvm/Support/ErrorHandling.h" |
Torok Edwin | dac237e | 2009-07-08 20:53:28 +0000 | [diff] [blame] | 33 | #include "llvm/Support/raw_ostream.h" |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 34 | #include "llvm/Target/TargetFrameLowering.h" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 35 | #include "llvm/Target/TargetMachine.h" |
| 36 | #include "llvm/Target/TargetOptions.h" |
| 37 | #include "llvm/ADT/BitVector.h" |
| 38 | #include "llvm/ADT/SmallVector.h" |
Jim Grosbach | 18ed9c9 | 2009-10-20 20:19:50 +0000 | [diff] [blame] | 39 | #include "llvm/Support/CommandLine.h" |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 40 | |
Evan Cheng | 73f50d9 | 2011-06-27 18:32:37 +0000 | [diff] [blame] | 41 | #define GET_REGINFO_TARGET_DESC |
Evan Cheng | a347f85 | 2011-06-24 01:44:41 +0000 | [diff] [blame] | 42 | #include "ARMGenRegisterInfo.inc" |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 43 | |
Evan Cheng | 1b4886d | 2010-11-18 01:28:51 +0000 | [diff] [blame] | 44 | using namespace llvm; |
| 45 | |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 46 | static cl::opt<bool> |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 47 | ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 48 | cl::desc("Force use of virtual base registers for stack load/store")); |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 49 | static cl::opt<bool> |
Jim Grosbach | ae47c6d | 2010-08-26 00:58:06 +0000 | [diff] [blame] | 50 | EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 51 | cl::desc("Enable pre-regalloc stack frame index allocation")); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 52 | static cl::opt<bool> |
Jim Grosbach | d0bd76b | 2010-09-08 20:12:02 +0000 | [diff] [blame] | 53 | EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 54 | cl::desc("Enable use of a base pointer for complex stack frames")); |
| 55 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 56 | ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 57 | const ARMSubtarget &sti) |
Evan Cheng | 0e6a052 | 2011-07-18 20:57:22 +0000 | [diff] [blame] | 58 | : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 59 | FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), |
| 60 | BasePtr(ARM::R6) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 61 | } |
| 62 | |
Craig Topper | 015f228 | 2012-03-04 03:33:22 +0000 | [diff] [blame] | 63 | const uint16_t* |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 64 | ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { |
Evan Cheng | afb3b5e | 2012-04-27 02:11:10 +0000 | [diff] [blame^] | 65 | return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) |
| 66 | ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; |
Jakob Stoklund Olesen | 3ee7d15 | 2012-01-17 23:09:00 +0000 | [diff] [blame] | 67 | } |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 68 | |
Jakob Stoklund Olesen | 3ee7d15 | 2012-01-17 23:09:00 +0000 | [diff] [blame] | 69 | const uint32_t* |
| 70 | ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { |
Evan Cheng | afb3b5e | 2012-04-27 02:11:10 +0000 | [diff] [blame^] | 71 | return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) |
| 72 | ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 73 | } |
| 74 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 75 | BitVector ARMBaseRegisterInfo:: |
| 76 | getReservedRegs(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 77 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 78 | |
Chris Lattner | 7a2bdde | 2011-04-15 05:18:47 +0000 | [diff] [blame] | 79 | // FIXME: avoid re-calculating this every time. |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 80 | BitVector Reserved(getNumRegs()); |
| 81 | Reserved.set(ARM::SP); |
| 82 | Reserved.set(ARM::PC); |
Lang Hames | 4f92b5e | 2012-03-06 00:19:55 +0000 | [diff] [blame] | 83 | Reserved.set(ARM::FPSCR); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 84 | if (TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 85 | Reserved.set(FramePtr); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 86 | if (hasBasePointer(MF)) |
| 87 | Reserved.set(BasePtr); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 88 | // Some targets reserve R9. |
| 89 | if (STI.isR9Reserved()) |
| 90 | Reserved.set(ARM::R9); |
Jakob Stoklund Olesen | 3b6434e | 2011-06-18 00:53:27 +0000 | [diff] [blame] | 91 | // Reserve D16-D31 if the subtarget doesn't support them. |
| 92 | if (!STI.hasVFP3() || STI.hasD16()) { |
| 93 | assert(ARM::D31 == ARM::D16 + 15); |
| 94 | for (unsigned i = 0; i != 16; ++i) |
| 95 | Reserved.set(ARM::D16 + i); |
| 96 | } |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 97 | return Reserved; |
| 98 | } |
| 99 | |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 100 | bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, |
| 101 | unsigned Reg) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 102 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 103 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 104 | switch (Reg) { |
| 105 | default: break; |
| 106 | case ARM::SP: |
| 107 | case ARM::PC: |
| 108 | return true; |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 109 | case ARM::R6: |
| 110 | if (hasBasePointer(MF)) |
| 111 | return true; |
| 112 | break; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 113 | case ARM::R7: |
| 114 | case ARM::R11: |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 115 | if (FramePtr == Reg && TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 116 | return true; |
| 117 | break; |
| 118 | case ARM::R9: |
| 119 | return STI.isR9Reserved(); |
| 120 | } |
| 121 | |
| 122 | return false; |
| 123 | } |
| 124 | |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 125 | bool |
Bob Wilson | 91a74da | 2010-06-02 18:54:47 +0000 | [diff] [blame] | 126 | ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 127 | SmallVectorImpl<unsigned> &SubIndices, |
| 128 | unsigned &NewSubIdx) const { |
| 129 | |
| 130 | unsigned Size = RC->getSize() * 8; |
| 131 | if (Size < 6) |
| 132 | return 0; |
| 133 | |
| 134 | NewSubIdx = 0; // Whole register. |
| 135 | unsigned NumRegs = SubIndices.size(); |
| 136 | if (NumRegs == 8) { |
| 137 | // 8 D registers -> 1 QQQQ register. |
| 138 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 139 | SubIndices[0] == ARM::dsub_0 && |
| 140 | SubIndices[1] == ARM::dsub_1 && |
| 141 | SubIndices[2] == ARM::dsub_2 && |
| 142 | SubIndices[3] == ARM::dsub_3 && |
| 143 | SubIndices[4] == ARM::dsub_4 && |
| 144 | SubIndices[5] == ARM::dsub_5 && |
| 145 | SubIndices[6] == ARM::dsub_6 && |
| 146 | SubIndices[7] == ARM::dsub_7); |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 147 | } else if (NumRegs == 4) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 148 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 149 | // 4 Q registers -> 1 QQQQ register. |
| 150 | return (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 151 | SubIndices[1] == ARM::qsub_1 && |
| 152 | SubIndices[2] == ARM::qsub_2 && |
| 153 | SubIndices[3] == ARM::qsub_3); |
| 154 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 155 | // 4 D registers -> 1 QQ register. |
| 156 | if (Size >= 256 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 157 | SubIndices[1] == ARM::dsub_1 && |
| 158 | SubIndices[2] == ARM::dsub_2 && |
| 159 | SubIndices[3] == ARM::dsub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 160 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 161 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 162 | return true; |
| 163 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 164 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 165 | // 4 D registers -> 1 QQ register (2nd). |
| 166 | if (Size == 512 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 167 | SubIndices[1] == ARM::dsub_5 && |
| 168 | SubIndices[2] == ARM::dsub_6 && |
| 169 | SubIndices[3] == ARM::dsub_7) { |
| 170 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 171 | return true; |
| 172 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 173 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 174 | // 4 S registers -> 1 Q register. |
| 175 | if (Size >= 128 && |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 176 | SubIndices[1] == ARM::ssub_1 && |
| 177 | SubIndices[2] == ARM::ssub_2 && |
| 178 | SubIndices[3] == ARM::ssub_3) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 179 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 180 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 181 | return true; |
| 182 | } |
| 183 | } |
| 184 | } else if (NumRegs == 2) { |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 185 | if (SubIndices[0] == ARM::qsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 186 | // 2 Q registers -> 1 QQ register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 187 | if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 188 | if (Size == 512) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 189 | NewSubIdx = ARM::qqsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 190 | return true; |
| 191 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 192 | } else if (SubIndices[0] == ARM::qsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 193 | // 2 Q registers -> 1 QQ register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 194 | if (Size == 512 && SubIndices[1] == ARM::qsub_3) { |
| 195 | NewSubIdx = ARM::qqsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 196 | return true; |
| 197 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 198 | } else if (SubIndices[0] == ARM::dsub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 199 | // 2 D registers -> 1 Q register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 200 | if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 201 | if (Size >= 256) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 202 | NewSubIdx = ARM::qsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 203 | return true; |
| 204 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 205 | } else if (SubIndices[0] == ARM::dsub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 206 | // 2 D registers -> 1 Q register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 207 | if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { |
| 208 | NewSubIdx = ARM::qsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 209 | return true; |
| 210 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 211 | } else if (SubIndices[0] == ARM::dsub_4) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 212 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 213 | if (Size == 512 && SubIndices[1] == ARM::dsub_5) { |
| 214 | NewSubIdx = ARM::qsub_2; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 215 | return true; |
| 216 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 217 | } else if (SubIndices[0] == ARM::dsub_6) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 218 | // 2 D registers -> 1 Q register (3rd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 219 | if (Size == 512 && SubIndices[1] == ARM::dsub_7) { |
| 220 | NewSubIdx = ARM::qsub_3; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 221 | return true; |
| 222 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 223 | } else if (SubIndices[0] == ARM::ssub_0) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 224 | // 2 S registers -> 1 D register. |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 225 | if (SubIndices[1] == ARM::ssub_1) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 226 | if (Size >= 128) |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 227 | NewSubIdx = ARM::dsub_0; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 228 | return true; |
| 229 | } |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 230 | } else if (SubIndices[0] == ARM::ssub_2) { |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 231 | // 2 S registers -> 1 D register (2nd). |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 232 | if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { |
| 233 | NewSubIdx = ARM::dsub_1; |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 234 | return true; |
| 235 | } |
| 236 | } |
| 237 | } |
| 238 | return false; |
| 239 | } |
| 240 | |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 241 | const TargetRegisterClass* |
| 242 | ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) |
| 243 | const { |
| 244 | const TargetRegisterClass *Super = RC; |
Jakob Stoklund Olesen | c8e2bb6 | 2011-09-30 22:19:07 +0000 | [diff] [blame] | 245 | TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); |
Jakob Stoklund Olesen | c9e5015 | 2011-04-26 18:52:33 +0000 | [diff] [blame] | 246 | do { |
| 247 | switch (Super->getID()) { |
| 248 | case ARM::GPRRegClassID: |
| 249 | case ARM::SPRRegClassID: |
| 250 | case ARM::DPRRegClassID: |
| 251 | case ARM::QPRRegClassID: |
| 252 | case ARM::QQPRRegClassID: |
| 253 | case ARM::QQQQPRRegClassID: |
| 254 | return Super; |
| 255 | } |
| 256 | Super = *I++; |
| 257 | } while (Super); |
| 258 | return RC; |
| 259 | } |
Evan Cheng | b990a2f | 2010-05-14 23:21:14 +0000 | [diff] [blame] | 260 | |
Evan Cheng | 4f54c12 | 2009-10-25 07:53:28 +0000 | [diff] [blame] | 261 | const TargetRegisterClass * |
Chris Lattner | 2cfd52c | 2009-07-29 20:31:52 +0000 | [diff] [blame] | 262 | ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const { |
Craig Topper | 420761a | 2012-04-20 07:30:17 +0000 | [diff] [blame] | 263 | return &ARM::GPRRegClass; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 264 | } |
| 265 | |
Evan Cheng | 342e316 | 2011-08-30 01:34:54 +0000 | [diff] [blame] | 266 | const TargetRegisterClass * |
| 267 | ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { |
| 268 | if (RC == &ARM::CCRRegClass) |
| 269 | return 0; // Can't copy CCR registers. |
| 270 | return RC; |
| 271 | } |
| 272 | |
Cameron Zwarich | be2119e | 2011-03-07 21:56:36 +0000 | [diff] [blame] | 273 | unsigned |
| 274 | ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, |
| 275 | MachineFunction &MF) const { |
| 276 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
| 277 | |
| 278 | switch (RC->getID()) { |
| 279 | default: |
| 280 | return 0; |
| 281 | case ARM::tGPRRegClassID: |
| 282 | return TFI->hasFP(MF) ? 4 : 5; |
| 283 | case ARM::GPRRegClassID: { |
| 284 | unsigned FP = TFI->hasFP(MF) ? 1 : 0; |
| 285 | return 10 - FP - (STI.isR9Reserved() ? 1 : 0); |
| 286 | } |
| 287 | case ARM::SPRRegClassID: // Currently not used as 'rep' register class. |
| 288 | case ARM::DPRRegClassID: |
| 289 | return 32 - 10; |
| 290 | } |
| 291 | } |
| 292 | |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 293 | /// getRawAllocationOrder - Returns the register allocation order for a |
| 294 | /// specified register class with a target-dependent hint. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 295 | ArrayRef<uint16_t> |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 296 | ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, |
| 297 | unsigned HintType, unsigned HintReg, |
| 298 | const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 299 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 300 | // Alternative register allocation orders when favoring even / odd registers |
| 301 | // of register pairs. |
| 302 | |
| 303 | // No FP, R9 is available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 304 | static const uint16_t GPREven1[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 305 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, |
| 306 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 307 | ARM::R9, ARM::R11 |
| 308 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 309 | static const uint16_t GPROdd1[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 310 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, |
| 311 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 312 | ARM::R8, ARM::R10 |
| 313 | }; |
| 314 | |
| 315 | // FP is R7, R9 is available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 316 | static const uint16_t GPREven2[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 317 | ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, |
| 318 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, |
| 319 | ARM::R9, ARM::R11 |
| 320 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 321 | static const uint16_t GPROdd2[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 322 | ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, |
| 323 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, |
| 324 | ARM::R8, ARM::R10 |
| 325 | }; |
| 326 | |
| 327 | // FP is R11, R9 is available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 328 | static const uint16_t GPREven3[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 329 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, |
| 330 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, |
| 331 | ARM::R9 |
| 332 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 333 | static const uint16_t GPROdd3[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 334 | ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, |
| 335 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, |
| 336 | ARM::R8 |
| 337 | }; |
| 338 | |
| 339 | // No FP, R9 is not available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 340 | static const uint16_t GPREven4[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 341 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, |
| 342 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, |
| 343 | ARM::R11 |
| 344 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 345 | static const uint16_t GPROdd4[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 346 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, |
| 347 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 348 | ARM::R10 |
| 349 | }; |
| 350 | |
| 351 | // FP is R7, R9 is not available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 352 | static const uint16_t GPREven5[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 353 | ARM::R0, ARM::R2, ARM::R4, ARM::R10, |
| 354 | ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, |
| 355 | ARM::R11 |
| 356 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 357 | static const uint16_t GPROdd5[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 358 | ARM::R1, ARM::R3, ARM::R5, ARM::R11, |
| 359 | ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, |
| 360 | ARM::R10 |
| 361 | }; |
| 362 | |
| 363 | // FP is R11, R9 is not available. |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 364 | static const uint16_t GPREven6[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 365 | ARM::R0, ARM::R2, ARM::R4, ARM::R6, |
| 366 | ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 |
| 367 | }; |
Craig Topper | b6632ba | 2012-03-04 10:16:38 +0000 | [diff] [blame] | 368 | static const uint16_t GPROdd6[] = { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 369 | ARM::R1, ARM::R3, ARM::R5, ARM::R7, |
| 370 | ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 |
| 371 | }; |
| 372 | |
Jakob Stoklund Olesen | eb5067e | 2011-03-25 01:48:18 +0000 | [diff] [blame] | 373 | // We only support even/odd hints for GPR and rGPR. |
Craig Topper | 420761a | 2012-04-20 07:30:17 +0000 | [diff] [blame] | 374 | if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass) |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 375 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 376 | |
| 377 | if (HintType == ARMRI::RegPairEven) { |
| 378 | if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) |
| 379 | // It's no longer possible to fulfill this hint. Return the default |
| 380 | // allocation order. |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 381 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 382 | |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 383 | if (!TFI->hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 384 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 385 | return makeArrayRef(GPREven1); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 386 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 387 | return makeArrayRef(GPREven4); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 388 | } else if (FramePtr == ARM::R7) { |
| 389 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 390 | return makeArrayRef(GPREven2); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 391 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 392 | return makeArrayRef(GPREven5); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 393 | } else { // FramePtr == ARM::R11 |
| 394 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 395 | return makeArrayRef(GPREven3); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 396 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 397 | return makeArrayRef(GPREven6); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 398 | } |
| 399 | } else if (HintType == ARMRI::RegPairOdd) { |
| 400 | if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) |
| 401 | // It's no longer possible to fulfill this hint. Return the default |
| 402 | // allocation order. |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 403 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 404 | |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 405 | if (!TFI->hasFP(MF)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 406 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 407 | return makeArrayRef(GPROdd1); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 408 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 409 | return makeArrayRef(GPROdd4); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 410 | } else if (FramePtr == ARM::R7) { |
| 411 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 412 | return makeArrayRef(GPROdd2); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 413 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 414 | return makeArrayRef(GPROdd5); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 415 | } else { // FramePtr == ARM::R11 |
| 416 | if (!STI.isR9Reserved()) |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 417 | return makeArrayRef(GPROdd3); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 418 | else |
Frits van Bommel | 39b5abf | 2011-07-18 12:00:32 +0000 | [diff] [blame] | 419 | return makeArrayRef(GPROdd6); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 420 | } |
| 421 | } |
Jakob Stoklund Olesen | dd5a847 | 2011-06-16 23:31:16 +0000 | [diff] [blame] | 422 | return RC->getRawAllocationOrder(MF); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | /// ResolveRegAllocHint - Resolves the specified register allocation hint |
| 426 | /// to a physical register. Returns the physical register if it is successful. |
| 427 | unsigned |
| 428 | ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, |
| 429 | const MachineFunction &MF) const { |
| 430 | if (Reg == 0 || !isPhysicalRegister(Reg)) |
| 431 | return 0; |
| 432 | if (Type == 0) |
| 433 | return Reg; |
| 434 | else if (Type == (unsigned)ARMRI::RegPairOdd) |
| 435 | // Odd register. |
| 436 | return getRegisterPairOdd(Reg, MF); |
| 437 | else if (Type == (unsigned)ARMRI::RegPairEven) |
| 438 | // Even register. |
| 439 | return getRegisterPairEven(Reg, MF); |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | void |
| 444 | ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, |
| 445 | MachineFunction &MF) const { |
| 446 | MachineRegisterInfo *MRI = &MF.getRegInfo(); |
| 447 | std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); |
| 448 | if ((Hint.first == (unsigned)ARMRI::RegPairOdd || |
| 449 | Hint.first == (unsigned)ARMRI::RegPairEven) && |
Jakob Stoklund Olesen | c9df025 | 2011-01-10 02:58:51 +0000 | [diff] [blame] | 450 | TargetRegisterInfo::isVirtualRegister(Hint.second)) { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 451 | // If 'Reg' is one of the even / odd register pair and it's now changed |
| 452 | // (e.g. coalesced) into a different register. The other register of the |
| 453 | // pair allocation hint must be updated to reflect the relationship |
| 454 | // change. |
| 455 | unsigned OtherReg = Hint.second; |
| 456 | Hint = MRI->getRegAllocationHint(OtherReg); |
| 457 | if (Hint.second == Reg) |
| 458 | // Make sure the pair has not already divorced. |
| 459 | MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); |
| 460 | } |
| 461 | } |
| 462 | |
Bob Wilson | f6a4d3c | 2011-04-19 18:11:45 +0000 | [diff] [blame] | 463 | bool |
| 464 | ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { |
| 465 | // CortexA9 has a Write-after-write hazard for NEON registers. |
| 466 | if (!STI.isCortexA9()) |
| 467 | return false; |
| 468 | |
| 469 | switch (RC->getID()) { |
| 470 | case ARM::DPRRegClassID: |
| 471 | case ARM::DPR_8RegClassID: |
| 472 | case ARM::DPR_VFP2RegClassID: |
| 473 | case ARM::QPRRegClassID: |
| 474 | case ARM::QPR_8RegClassID: |
| 475 | case ARM::QPR_VFP2RegClassID: |
| 476 | case ARM::SPRRegClassID: |
| 477 | case ARM::SPR_8RegClassID: |
| 478 | // Avoid reusing S, D, and Q registers. |
| 479 | // Don't increase register pressure for QQ and QQQQ. |
| 480 | return true; |
| 481 | default: |
| 482 | return false; |
| 483 | } |
| 484 | } |
| 485 | |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 486 | bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 487 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 488 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jakob Stoklund Olesen | 0f9d07f | 2012-02-28 01:15:01 +0000 | [diff] [blame] | 489 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 490 | |
| 491 | if (!EnableBasePointer) |
| 492 | return false; |
| 493 | |
Jakob Stoklund Olesen | 0f9d07f | 2012-02-28 01:15:01 +0000 | [diff] [blame] | 494 | // When outgoing call frames are so large that we adjust the stack pointer |
| 495 | // around the call, we can no longer use the stack pointer to reach the |
| 496 | // emergency spill slot. |
Bob Wilson | 055a812 | 2012-03-20 19:28:22 +0000 | [diff] [blame] | 497 | if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 498 | return true; |
| 499 | |
| 500 | // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited |
| 501 | // negative range for ldr/str (255), and thumb1 is positive offsets only. |
| 502 | // It's going to be better to use the SP or Base Pointer instead. When there |
| 503 | // are variable sized objects, we can't reference off of the SP, so we |
| 504 | // reserve a Base Pointer. |
| 505 | if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { |
| 506 | // Conservatively estimate whether the negative offset from the frame |
| 507 | // pointer will be sufficient to reach. If a function has a smallish |
| 508 | // frame, it's less likely to have lots of spills and callee saved |
| 509 | // space, so it's all more likely to be within range of the frame pointer. |
| 510 | // If it's wrong, the scavenger will still enable access to work, it just |
| 511 | // won't be optimal. |
| 512 | if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) |
| 513 | return false; |
| 514 | return true; |
| 515 | } |
| 516 | |
| 517 | return false; |
| 518 | } |
| 519 | |
| 520 | bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { |
Jakob Stoklund Olesen | 54f3b7a | 2012-01-05 00:26:52 +0000 | [diff] [blame] | 521 | const MachineRegisterInfo *MRI = &MF.getRegInfo(); |
Chad Rosier | 6690bca | 2011-10-20 00:07:12 +0000 | [diff] [blame] | 522 | const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 30c93e1 | 2010-09-08 17:22:12 +0000 | [diff] [blame] | 523 | // We can't realign the stack if: |
| 524 | // 1. Dynamic stack realignment is explicitly disabled, |
Chad Rosier | 6690bca | 2011-10-20 00:07:12 +0000 | [diff] [blame] | 525 | // 2. This is a Thumb1 function (it's not useful, so we don't bother), or |
| 526 | // 3. There are VLAs in the function and the base pointer is disabled. |
Jakob Stoklund Olesen | 54f3b7a | 2012-01-05 00:26:52 +0000 | [diff] [blame] | 527 | if (!MF.getTarget().Options.RealignStack) |
| 528 | return false; |
| 529 | if (AFI->isThumb1OnlyFunction()) |
| 530 | return false; |
| 531 | // Stack realignment requires a frame pointer. If we already started |
| 532 | // register allocation with frame pointer elimination, it is too late now. |
| 533 | if (!MRI->canReserveReg(FramePtr)) |
| 534 | return false; |
Bob Wilson | aaa1e2f | 2012-03-20 19:28:25 +0000 | [diff] [blame] | 535 | // We may also need a base pointer if there are dynamic allocas or stack |
| 536 | // pointer adjustments around calls. |
| 537 | if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) |
Jakob Stoklund Olesen | 54f3b7a | 2012-01-05 00:26:52 +0000 | [diff] [blame] | 538 | return true; |
| 539 | if (!EnableBasePointer) |
| 540 | return false; |
| 541 | // A base pointer is required and allowed. Check that it isn't too late to |
| 542 | // reserve it. |
| 543 | return MRI->canReserveReg(BasePtr); |
Jim Grosbach | e45ab8a | 2010-01-19 18:31:11 +0000 | [diff] [blame] | 544 | } |
| 545 | |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 546 | bool ARMBaseRegisterInfo:: |
| 547 | needsStackRealignment(const MachineFunction &MF) const { |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 548 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 549 | const Function *F = MF.getFunction(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 550 | unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); |
Jakob Stoklund Olesen | 7255a4e | 2012-01-05 00:26:57 +0000 | [diff] [blame] | 551 | bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || |
Eric Christopher | 697cba8 | 2010-07-17 00:33:04 +0000 | [diff] [blame] | 552 | F->hasFnAttr(Attribute::StackAlignment)); |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 553 | |
Eric Christopher | d4c36ce | 2010-07-17 00:27:24 +0000 | [diff] [blame] | 554 | return requiresRealignment && canRealignStack(MF); |
Jim Grosbach | 3dab277 | 2009-10-27 22:45:39 +0000 | [diff] [blame] | 555 | } |
| 556 | |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 557 | bool ARMBaseRegisterInfo:: |
| 558 | cannotEliminateFrame(const MachineFunction &MF) const { |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 559 | const MachineFrameInfo *MFI = MF.getFrameInfo(); |
Nick Lewycky | 8a8d479 | 2011-12-02 22:16:29 +0000 | [diff] [blame] | 560 | if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 561 | return true; |
Jim Grosbach | 31bc849 | 2009-11-08 00:27:19 +0000 | [diff] [blame] | 562 | return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() |
| 563 | || needsStackRealignment(MF); |
Evan Cheng | 98a0104 | 2009-08-14 20:48:13 +0000 | [diff] [blame] | 564 | } |
| 565 | |
Jim Grosbach | 5c33f5b | 2010-09-02 19:52:39 +0000 | [diff] [blame] | 566 | unsigned |
David Greene | 3f2bf85 | 2009-11-12 20:49:22 +0000 | [diff] [blame] | 567 | ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 568 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 569 | |
| 570 | if (TFI->hasFP(MF)) |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 571 | return FramePtr; |
| 572 | return ARM::SP; |
| 573 | } |
| 574 | |
| 575 | unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 576 | llvm_unreachable("What is the exception register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 577 | } |
| 578 | |
| 579 | unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { |
Torok Edwin | c23197a | 2009-07-14 16:55:14 +0000 | [diff] [blame] | 580 | llvm_unreachable("What is the exception handler register"); |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 581 | } |
| 582 | |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 583 | unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, |
Jim Grosbach | 9631864 | 2010-01-06 23:54:42 +0000 | [diff] [blame] | 584 | const MachineFunction &MF) const { |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 585 | switch (Reg) { |
| 586 | default: break; |
| 587 | // Return 0 if either register of the pair is a special register. |
| 588 | // So no R12, etc. |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 589 | case ARM::R1: return ARM::R0; |
| 590 | case ARM::R3: return ARM::R2; |
| 591 | case ARM::R5: return ARM::R4; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 592 | case ARM::R7: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 593 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 594 | ? 0 : ARM::R6; |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 595 | case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; |
| 596 | case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 597 | |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 598 | case ARM::S1: return ARM::S0; |
| 599 | case ARM::S3: return ARM::S2; |
| 600 | case ARM::S5: return ARM::S4; |
| 601 | case ARM::S7: return ARM::S6; |
| 602 | case ARM::S9: return ARM::S8; |
| 603 | case ARM::S11: return ARM::S10; |
| 604 | case ARM::S13: return ARM::S12; |
| 605 | case ARM::S15: return ARM::S14; |
| 606 | case ARM::S17: return ARM::S16; |
| 607 | case ARM::S19: return ARM::S18; |
| 608 | case ARM::S21: return ARM::S20; |
| 609 | case ARM::S23: return ARM::S22; |
| 610 | case ARM::S25: return ARM::S24; |
| 611 | case ARM::S27: return ARM::S26; |
| 612 | case ARM::S29: return ARM::S28; |
| 613 | case ARM::S31: return ARM::S30; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 614 | |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 615 | case ARM::D1: return ARM::D0; |
| 616 | case ARM::D3: return ARM::D2; |
| 617 | case ARM::D5: return ARM::D4; |
| 618 | case ARM::D7: return ARM::D6; |
| 619 | case ARM::D9: return ARM::D8; |
| 620 | case ARM::D11: return ARM::D10; |
| 621 | case ARM::D13: return ARM::D12; |
| 622 | case ARM::D15: return ARM::D14; |
| 623 | case ARM::D17: return ARM::D16; |
| 624 | case ARM::D19: return ARM::D18; |
| 625 | case ARM::D21: return ARM::D20; |
| 626 | case ARM::D23: return ARM::D22; |
| 627 | case ARM::D25: return ARM::D24; |
| 628 | case ARM::D27: return ARM::D26; |
| 629 | case ARM::D29: return ARM::D28; |
| 630 | case ARM::D31: return ARM::D30; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 631 | } |
| 632 | |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, |
| 637 | const MachineFunction &MF) const { |
| 638 | switch (Reg) { |
| 639 | default: break; |
| 640 | // Return 0 if either register of the pair is a special register. |
| 641 | // So no R12, etc. |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 642 | case ARM::R0: return ARM::R1; |
| 643 | case ARM::R2: return ARM::R3; |
| 644 | case ARM::R4: return ARM::R5; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 645 | case ARM::R6: |
Jim Grosbach | 65482b1 | 2010-09-03 18:37:12 +0000 | [diff] [blame] | 646 | return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) |
| 647 | ? 0 : ARM::R7; |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 648 | case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; |
| 649 | case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 650 | |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 651 | case ARM::S0: return ARM::S1; |
| 652 | case ARM::S2: return ARM::S3; |
| 653 | case ARM::S4: return ARM::S5; |
| 654 | case ARM::S6: return ARM::S7; |
| 655 | case ARM::S8: return ARM::S9; |
| 656 | case ARM::S10: return ARM::S11; |
| 657 | case ARM::S12: return ARM::S13; |
| 658 | case ARM::S14: return ARM::S15; |
| 659 | case ARM::S16: return ARM::S17; |
| 660 | case ARM::S18: return ARM::S19; |
| 661 | case ARM::S20: return ARM::S21; |
| 662 | case ARM::S22: return ARM::S23; |
| 663 | case ARM::S24: return ARM::S25; |
| 664 | case ARM::S26: return ARM::S27; |
| 665 | case ARM::S28: return ARM::S29; |
| 666 | case ARM::S30: return ARM::S31; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 667 | |
Jim Grosbach | 8f310d9 | 2011-09-13 20:27:44 +0000 | [diff] [blame] | 668 | case ARM::D0: return ARM::D1; |
| 669 | case ARM::D2: return ARM::D3; |
| 670 | case ARM::D4: return ARM::D5; |
| 671 | case ARM::D6: return ARM::D7; |
| 672 | case ARM::D8: return ARM::D9; |
| 673 | case ARM::D10: return ARM::D11; |
| 674 | case ARM::D12: return ARM::D13; |
| 675 | case ARM::D14: return ARM::D15; |
| 676 | case ARM::D16: return ARM::D17; |
| 677 | case ARM::D18: return ARM::D19; |
| 678 | case ARM::D20: return ARM::D21; |
| 679 | case ARM::D22: return ARM::D23; |
| 680 | case ARM::D24: return ARM::D25; |
| 681 | case ARM::D26: return ARM::D27; |
| 682 | case ARM::D28: return ARM::D29; |
| 683 | case ARM::D30: return ARM::D31; |
David Goodwin | c140c48 | 2009-07-08 17:28:55 +0000 | [diff] [blame] | 684 | } |
| 685 | |
| 686 | return 0; |
| 687 | } |
| 688 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 689 | /// emitLoadConstPool - Emits a load from constpool to materialize the |
| 690 | /// specified immediate. |
| 691 | void ARMBaseRegisterInfo:: |
| 692 | emitLoadConstPool(MachineBasicBlock &MBB, |
| 693 | MachineBasicBlock::iterator &MBBI, |
David Goodwin | 77521f5 | 2009-07-08 20:28:28 +0000 | [diff] [blame] | 694 | DebugLoc dl, |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 695 | unsigned DestReg, unsigned SubIdx, int Val, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 696 | ARMCC::CondCodes Pred, |
Anton Korobeynikov | 3daccd8 | 2011-03-05 18:43:50 +0000 | [diff] [blame] | 697 | unsigned PredReg, unsigned MIFlags) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 698 | MachineFunction &MF = *MBB.getParent(); |
| 699 | MachineConstantPool *ConstantPool = MF.getConstantPool(); |
Dan Gohman | 46510a7 | 2010-04-15 01:51:59 +0000 | [diff] [blame] | 700 | const Constant *C = |
Owen Anderson | 1d0be15 | 2009-08-13 21:58:54 +0000 | [diff] [blame] | 701 | ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 702 | unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); |
| 703 | |
Evan Cheng | 3784453 | 2009-07-16 09:20:10 +0000 | [diff] [blame] | 704 | BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) |
| 705 | .addReg(DestReg, getDefRegState(true), SubIdx) |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 706 | .addConstantPoolIndex(Idx) |
Anton Korobeynikov | 3daccd8 | 2011-03-05 18:43:50 +0000 | [diff] [blame] | 707 | .addImm(0).addImm(Pred).addReg(PredReg) |
| 708 | .setMIFlags(MIFlags); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 709 | } |
| 710 | |
| 711 | bool ARMBaseRegisterInfo:: |
| 712 | requiresRegisterScavenging(const MachineFunction &MF) const { |
| 713 | return true; |
| 714 | } |
Jim Grosbach | 41fff8c | 2009-10-21 23:40:56 +0000 | [diff] [blame] | 715 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 716 | bool ARMBaseRegisterInfo:: |
Preston Gurd | 6a8c7bf | 2012-04-23 21:39:35 +0000 | [diff] [blame] | 717 | trackLivenessAfterRegAlloc(const MachineFunction &MF) const { |
| 718 | return true; |
| 719 | } |
| 720 | |
| 721 | bool ARMBaseRegisterInfo:: |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 722 | requiresFrameIndexScavenging(const MachineFunction &MF) const { |
Jim Grosbach | ca5dfb7 | 2009-10-28 17:33:28 +0000 | [diff] [blame] | 723 | return true; |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 724 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 725 | |
Jim Grosbach | a273442 | 2010-08-24 19:05:43 +0000 | [diff] [blame] | 726 | bool ARMBaseRegisterInfo:: |
| 727 | requiresVirtualBaseRegisters(const MachineFunction &MF) const { |
| 728 | return EnableLocalStackAlloc; |
| 729 | } |
| 730 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 731 | static void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 732 | emitSPUpdate(bool isARM, |
| 733 | MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, |
| 734 | DebugLoc dl, const ARMBaseInstrInfo &TII, |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 735 | int NumBytes, |
| 736 | ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 737 | if (isARM) |
| 738 | emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 739 | Pred, PredReg, TII); |
| 740 | else |
| 741 | emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, |
| 742 | Pred, PredReg, TII); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 743 | } |
| 744 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 745 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 746 | void ARMBaseRegisterInfo:: |
| 747 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, |
| 748 | MachineBasicBlock::iterator I) const { |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 749 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 750 | if (!TFI->hasReservedCallFrame(MF)) { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 751 | // If we have alloca, convert as follows: |
| 752 | // ADJCALLSTACKDOWN -> sub, sp, sp, amount |
| 753 | // ADJCALLSTACKUP -> add, sp, sp, amount |
| 754 | MachineInstr *Old = I; |
| 755 | DebugLoc dl = Old->getDebugLoc(); |
| 756 | unsigned Amount = Old->getOperand(0).getImm(); |
| 757 | if (Amount != 0) { |
| 758 | // We need to keep the stack aligned properly. To do this, we round the |
| 759 | // amount of space needed for the outgoing arguments up to the next |
| 760 | // alignment boundary. |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 761 | unsigned Align = TFI->getStackAlignment(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 762 | Amount = (Amount+Align-1)/Align*Align; |
| 763 | |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 764 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 765 | assert(!AFI->isThumb1OnlyFunction() && |
Jim Grosbach | cf453ee | 2010-02-23 17:16:27 +0000 | [diff] [blame] | 766 | "This eliminateCallFramePseudoInstr does not support Thumb1!"); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 767 | bool isARM = !AFI->isThumbFunction(); |
| 768 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 769 | // Replace the pseudo instruction with a new instruction... |
| 770 | unsigned Opc = Old->getOpcode(); |
Jim Grosbach | 4c7628e | 2010-02-22 22:47:46 +0000 | [diff] [blame] | 771 | int PIdx = Old->findFirstPredOperandIdx(); |
| 772 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 773 | ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 774 | if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { |
| 775 | // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. |
| 776 | unsigned PredReg = Old->getOperand(2).getReg(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 777 | emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 778 | } else { |
| 779 | // Note: PredReg is operand 3 for ADJCALLSTACKUP. |
| 780 | unsigned PredReg = Old->getOperand(3).getReg(); |
| 781 | assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 782 | emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 783 | } |
| 784 | } |
| 785 | } |
| 786 | MBB.erase(I); |
| 787 | } |
| 788 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 789 | int64_t ARMBaseRegisterInfo:: |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 790 | getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 791 | const MCInstrDesc &Desc = MI->getDesc(); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 792 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
Chad Rosier | 90f2004 | 2012-02-22 17:25:00 +0000 | [diff] [blame] | 793 | int64_t InstrOffs = 0; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 794 | int Scale = 1; |
| 795 | unsigned ImmIdx = 0; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 796 | switch (AddrMode) { |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 797 | case ARMII::AddrModeT2_i8: |
| 798 | case ARMII::AddrModeT2_i12: |
Jim Grosbach | 3e55612 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 799 | case ARMII::AddrMode_i12: |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 800 | InstrOffs = MI->getOperand(Idx+1).getImm(); |
| 801 | Scale = 1; |
| 802 | break; |
| 803 | case ARMII::AddrMode5: { |
| 804 | // VFP address mode. |
| 805 | const MachineOperand &OffOp = MI->getOperand(Idx+1); |
Jim Grosbach | f78ee63 | 2010-08-25 19:11:34 +0000 | [diff] [blame] | 806 | InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 807 | if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) |
| 808 | InstrOffs = -InstrOffs; |
| 809 | Scale = 4; |
| 810 | break; |
| 811 | } |
| 812 | case ARMII::AddrMode2: { |
| 813 | ImmIdx = Idx+2; |
| 814 | InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); |
| 815 | if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 816 | InstrOffs = -InstrOffs; |
| 817 | break; |
| 818 | } |
| 819 | case ARMII::AddrMode3: { |
| 820 | ImmIdx = Idx+2; |
| 821 | InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); |
| 822 | if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) |
| 823 | InstrOffs = -InstrOffs; |
| 824 | break; |
| 825 | } |
| 826 | case ARMII::AddrModeT1_s: { |
| 827 | ImmIdx = Idx+1; |
| 828 | InstrOffs = MI->getOperand(ImmIdx).getImm(); |
| 829 | Scale = 4; |
| 830 | break; |
| 831 | } |
| 832 | default: |
| 833 | llvm_unreachable("Unsupported addressing mode!"); |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | return InstrOffs * Scale; |
| 837 | } |
| 838 | |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 839 | /// needsFrameBaseReg - Returns true if the instruction's frame index |
| 840 | /// reference would be better served by a base register other than FP |
| 841 | /// or SP. Used by LocalStackFrameAllocation to determine which frame index |
| 842 | /// references it should create new base registers for. |
| 843 | bool ARMBaseRegisterInfo:: |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 844 | needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { |
| 845 | for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { |
| 846 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 847 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 848 | |
| 849 | // It's the load/store FI references that cause issues, as it can be difficult |
| 850 | // to materialize the offset if it won't fit in the literal field. Estimate |
| 851 | // based on the size of the local frame and some conservative assumptions |
| 852 | // about the rest of the stack frame (note, this is pre-regalloc, so |
| 853 | // we don't know everything for certain yet) whether this offset is likely |
| 854 | // to be out of range of the immediate. Return true if so. |
| 855 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 856 | // We only generate virtual base registers for loads and stores, so |
| 857 | // return false for everything else. |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 858 | unsigned Opc = MI->getOpcode(); |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 859 | switch (Opc) { |
Jim Grosbach | c1d3021 | 2010-10-27 00:19:44 +0000 | [diff] [blame] | 860 | case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: |
Jim Grosbach | 7e3383c | 2010-10-27 23:12:14 +0000 | [diff] [blame] | 861 | case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 862 | case ARM::t2LDRi12: case ARM::t2LDRi8: |
| 863 | case ARM::t2STRi12: case ARM::t2STRi8: |
| 864 | case ARM::VLDRS: case ARM::VLDRD: |
| 865 | case ARM::VSTRS: case ARM::VSTRD: |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 866 | case ARM::tSTRspi: case ARM::tLDRspi: |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 867 | if (ForceAllBaseRegAlloc) |
| 868 | return true; |
| 869 | break; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 870 | default: |
| 871 | return false; |
| 872 | } |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 873 | |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 874 | // Without a virtual base register, if the function has variable sized |
| 875 | // objects, all fixed-size local references will be via the frame pointer, |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 876 | // Approximate the offset and see if it's legal for the instruction. |
| 877 | // Note that the incoming offset is based on the SP value at function entry, |
| 878 | // so it'll be negative. |
| 879 | MachineFunction &MF = *MI->getParent()->getParent(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 880 | const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 881 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 882 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 883 | |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 884 | // Estimate an offset from the frame pointer. |
| 885 | // Conservatively assume all callee-saved registers get pushed. R4-R6 |
| 886 | // will be earlier than the FP, so we ignore those. |
| 887 | // R7, LR |
| 888 | int64_t FPOffset = Offset - 8; |
| 889 | // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 |
| 890 | if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) |
| 891 | FPOffset -= 80; |
| 892 | // Estimate an offset from the stack pointer. |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 893 | // The incoming offset is relating to the SP at the start of the function, |
| 894 | // but when we access the local it'll be relative to the SP after local |
| 895 | // allocation, so adjust our SP-relative offset by that allocation size. |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 896 | Offset = -Offset; |
Jim Grosbach | c1dc78d | 2010-08-31 18:52:31 +0000 | [diff] [blame] | 897 | Offset += MFI->getLocalFrameSize(); |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 898 | // Assume that we'll have at least some spill slots allocated. |
| 899 | // FIXME: This is a total SWAG number. We should run some statistics |
| 900 | // and pick a real one. |
| 901 | Offset += 128; // 128 bytes of spill slots |
| 902 | |
| 903 | // If there is a frame pointer, try using it. |
| 904 | // The FP is only available if there is no dynamic realignment. We |
| 905 | // don't know for sure yet whether we'll need that, so we guess based |
| 906 | // on whether there are any local variables that would trigger it. |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 907 | unsigned StackAlign = TFI->getStackAlignment(); |
Anton Korobeynikov | d0c3817 | 2010-11-18 21:19:35 +0000 | [diff] [blame] | 908 | if (TFI->hasFP(MF) && |
Jim Grosbach | 3197380 | 2010-08-24 21:19:33 +0000 | [diff] [blame] | 909 | !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { |
| 910 | if (isFrameOffsetLegal(MI, FPOffset)) |
| 911 | return false; |
| 912 | } |
| 913 | // If we can reference via the stack pointer, try that. |
| 914 | // FIXME: This (and the code that resolves the references) can be improved |
| 915 | // to only disallow SP relative references in the live range of |
| 916 | // the VLA(s). In practice, it's unclear how much difference that |
| 917 | // would make, but it may be worth doing. |
| 918 | if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) |
| 919 | return false; |
| 920 | |
| 921 | // The offset likely isn't legal, we want to allocate a virtual base register. |
Jim Grosbach | cd59dc5 | 2010-08-24 18:04:52 +0000 | [diff] [blame] | 922 | return true; |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 923 | } |
| 924 | |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 925 | /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to |
| 926 | /// be a pointer to FrameIdx at the beginning of the basic block. |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 927 | void ARMBaseRegisterInfo:: |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 928 | materializeFrameBaseRegister(MachineBasicBlock *MBB, |
| 929 | unsigned BaseReg, int FrameIdx, |
| 930 | int64_t Offset) const { |
| 931 | ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 932 | unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : |
| 933 | (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 934 | |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 935 | MachineBasicBlock::iterator Ins = MBB->begin(); |
| 936 | DebugLoc DL; // Defaults to "unknown" |
| 937 | if (Ins != MBB->end()) |
| 938 | DL = Ins->getDebugLoc(); |
| 939 | |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 940 | const MCInstrDesc &MCID = TII.get(ADDriOpc); |
Cameron Zwarich | 2180372 | 2011-05-19 02:18:27 +0000 | [diff] [blame] | 941 | MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 942 | MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this)); |
Cameron Zwarich | 2180372 | 2011-05-19 02:18:27 +0000 | [diff] [blame] | 943 | |
Jim Grosbach | 5b81584 | 2011-08-24 17:46:13 +0000 | [diff] [blame] | 944 | MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) |
| 945 | .addFrameIndex(FrameIdx).addImm(Offset)); |
Bill Wendling | 976ef86 | 2010-12-17 23:09:14 +0000 | [diff] [blame] | 946 | |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 947 | if (!AFI->isThumb1OnlyFunction()) |
Jim Grosbach | 5b81584 | 2011-08-24 17:46:13 +0000 | [diff] [blame] | 948 | AddDefaultCC(MIB); |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 949 | } |
| 950 | |
| 951 | void |
| 952 | ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, |
| 953 | unsigned BaseReg, int64_t Offset) const { |
| 954 | MachineInstr &MI = *I; |
| 955 | MachineBasicBlock &MBB = *MI.getParent(); |
| 956 | MachineFunction &MF = *MBB.getParent(); |
| 957 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 958 | int Off = Offset; // ARM doesn't need the general 64-bit offsets |
| 959 | unsigned i = 0; |
| 960 | |
| 961 | assert(!AFI->isThumb1OnlyFunction() && |
| 962 | "This resolveFrameIndex does not support Thumb1!"); |
| 963 | |
| 964 | while (!MI.getOperand(i).isFI()) { |
| 965 | ++i; |
| 966 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 967 | } |
| 968 | bool Done = false; |
| 969 | if (!AFI->isThumbFunction()) |
| 970 | Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); |
| 971 | else { |
| 972 | assert(AFI->isThumb2Function()); |
| 973 | Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); |
| 974 | } |
| 975 | assert (Done && "Unable to resolve frame index!"); |
Duncan Sands | 1f6a329 | 2011-08-12 14:54:45 +0000 | [diff] [blame] | 976 | (void)Done; |
Jim Grosbach | dc140c6 | 2010-08-17 22:41:55 +0000 | [diff] [blame] | 977 | } |
Jim Grosbach | 8708ead | 2010-08-17 18:13:53 +0000 | [diff] [blame] | 978 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 979 | bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, |
| 980 | int64_t Offset) const { |
Evan Cheng | e837dea | 2011-06-28 19:10:37 +0000 | [diff] [blame] | 981 | const MCInstrDesc &Desc = MI->getDesc(); |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 982 | unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); |
| 983 | unsigned i = 0; |
| 984 | |
| 985 | while (!MI->getOperand(i).isFI()) { |
| 986 | ++i; |
| 987 | assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); |
| 988 | } |
| 989 | |
| 990 | // AddrMode4 and AddrMode6 cannot handle any offset. |
| 991 | if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) |
| 992 | return Offset == 0; |
| 993 | |
| 994 | unsigned NumBits = 0; |
| 995 | unsigned Scale = 1; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 996 | bool isSigned = true; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 997 | switch (AddrMode) { |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 998 | case ARMII::AddrModeT2_i8: |
| 999 | case ARMII::AddrModeT2_i12: |
| 1000 | // i8 supports only negative, and i12 supports only positive, so |
| 1001 | // based on Offset sign, consider the appropriate instruction |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1002 | Scale = 1; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1003 | if (Offset < 0) { |
| 1004 | NumBits = 8; |
| 1005 | Offset = -Offset; |
| 1006 | } else { |
| 1007 | NumBits = 12; |
| 1008 | } |
| 1009 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1010 | case ARMII::AddrMode5: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1011 | // VFP address mode. |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1012 | NumBits = 8; |
| 1013 | Scale = 4; |
| 1014 | break; |
Jim Grosbach | 3e55612 | 2010-10-26 22:37:02 +0000 | [diff] [blame] | 1015 | case ARMII::AddrMode_i12: |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1016 | case ARMII::AddrMode2: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1017 | NumBits = 12; |
| 1018 | break; |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1019 | case ARMII::AddrMode3: |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1020 | NumBits = 8; |
| 1021 | break; |
Bill Wendling | e575499 | 2011-10-11 21:40:47 +0000 | [diff] [blame] | 1022 | case ARMII::AddrModeT1_s: |
| 1023 | NumBits = 5; |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1024 | Scale = 4; |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1025 | isSigned = false; |
Jim Grosbach | 74d7b0a | 2010-08-19 17:52:13 +0000 | [diff] [blame] | 1026 | break; |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1027 | default: |
| 1028 | llvm_unreachable("Unsupported addressing mode!"); |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1029 | } |
| 1030 | |
Jim Grosbach | 1ab3f16 | 2010-08-26 21:56:30 +0000 | [diff] [blame] | 1031 | Offset += getFrameIndexInstrOffset(MI, i); |
Jim Grosbach | d4511e9 | 2010-08-31 18:49:31 +0000 | [diff] [blame] | 1032 | // Make sure the offset is encodable for instructions that scale the |
| 1033 | // immediate. |
| 1034 | if ((Offset & (Scale-1)) != 0) |
| 1035 | return false; |
| 1036 | |
Jim Grosbach | e2f5569 | 2010-08-19 23:52:25 +0000 | [diff] [blame] | 1037 | if (isSigned && Offset < 0) |
Jim Grosbach | 2b1e202 | 2010-08-18 22:44:49 +0000 | [diff] [blame] | 1038 | Offset = -Offset; |
| 1039 | |
| 1040 | unsigned Mask = (1 << NumBits) - 1; |
| 1041 | if ((unsigned)Offset <= Mask * Scale) |
| 1042 | return true; |
Jim Grosbach | 74d803a | 2010-08-18 17:57:37 +0000 | [diff] [blame] | 1043 | |
| 1044 | return false; |
| 1045 | } |
| 1046 | |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1047 | void |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1048 | ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1049 | int SPAdj, RegScavenger *RS) const { |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1050 | unsigned i = 0; |
| 1051 | MachineInstr &MI = *II; |
| 1052 | MachineBasicBlock &MBB = *MI.getParent(); |
| 1053 | MachineFunction &MF = *MBB.getParent(); |
Anton Korobeynikov | 16c29b5 | 2011-01-10 12:39:04 +0000 | [diff] [blame] | 1054 | const ARMFrameLowering *TFI = |
| 1055 | static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1056 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1057 | assert(!AFI->isThumb1OnlyFunction() && |
Bob Wilson | a15de00 | 2009-09-18 21:42:44 +0000 | [diff] [blame] | 1058 | "This eliminateFrameIndex does not support Thumb1!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1059 | |
| 1060 | while (!MI.getOperand(i).isFI()) { |
| 1061 | ++i; |
| 1062 | assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); |
| 1063 | } |
| 1064 | |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1065 | int FrameIndex = MI.getOperand(i).getIndex(); |
Jim Grosbach | a37aa54 | 2009-11-22 20:05:32 +0000 | [diff] [blame] | 1066 | unsigned FrameReg; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1067 | |
Anton Korobeynikov | 82f5874 | 2010-11-20 15:59:32 +0000 | [diff] [blame] | 1068 | int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1069 | |
Jakob Stoklund Olesen | 0f9d07f | 2012-02-28 01:15:01 +0000 | [diff] [blame] | 1070 | // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the |
| 1071 | // call frame setup/destroy instructions have already been eliminated. That |
| 1072 | // means the stack pointer cannot be used to access the emergency spill slot |
| 1073 | // when !hasReservedCallFrame(). |
| 1074 | #ifndef NDEBUG |
| 1075 | if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ |
| 1076 | assert(TFI->hasReservedCallFrame(MF) && |
| 1077 | "Cannot use SP to access the emergency spill slot in " |
| 1078 | "functions without a reserved call frame"); |
| 1079 | assert(!MF.getFrameInfo()->hasVarSizedObjects() && |
| 1080 | "Cannot use SP to access the emergency spill slot in " |
| 1081 | "functions with variable sized frame objects"); |
| 1082 | } |
| 1083 | #endif // NDEBUG |
| 1084 | |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1085 | // Special handling of dbg_value instructions. |
| 1086 | if (MI.isDebugValue()) { |
| 1087 | MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); |
| 1088 | MI.getOperand(i+1).ChangeToImmediate(Offset); |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1089 | return; |
Evan Cheng | 62b5065 | 2010-04-26 07:39:25 +0000 | [diff] [blame] | 1090 | } |
| 1091 | |
Evan Cheng | 48d8afa | 2009-11-01 21:12:51 +0000 | [diff] [blame] | 1092 | // Modify MI as necessary to handle as much of 'Offset' as possible |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1093 | bool Done = false; |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1094 | if (!AFI->isThumbFunction()) |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1095 | Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1096 | else { |
| 1097 | assert(AFI->isThumb2Function()); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1098 | Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1099 | } |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1100 | if (Done) |
Jim Grosbach | fcb4a8e | 2010-08-26 23:32:16 +0000 | [diff] [blame] | 1101 | return; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1102 | |
| 1103 | // If we get here, the immediate doesn't fit into the instruction. We folded |
| 1104 | // as much as possible above, handle the rest, providing a register that is |
| 1105 | // SP+LargeImm. |
Daniel Dunbar | 19bb87d | 2009-08-28 08:08:22 +0000 | [diff] [blame] | 1106 | assert((Offset || |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1107 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || |
| 1108 | (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1109 | "This code isn't needed if offset already handled!"); |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1110 | |
Jim Grosbach | 7e831db | 2009-10-20 01:26:58 +0000 | [diff] [blame] | 1111 | unsigned ScratchReg = 0; |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1112 | int PIdx = MI.findFirstPredOperandIdx(); |
| 1113 | ARMCC::CondCodes Pred = (PIdx == -1) |
| 1114 | ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); |
| 1115 | unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1116 | if (Offset == 0) |
Jim Grosbach | a443217 | 2009-11-15 21:45:34 +0000 | [diff] [blame] | 1117 | // Must be addrmode4/6. |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1118 | MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1119 | else { |
Craig Topper | 420761a | 2012-04-20 07:30:17 +0000 | [diff] [blame] | 1120 | ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1121 | if (!AFI->isThumbFunction()) |
| 1122 | emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1123 | Offset, Pred, PredReg, TII); |
| 1124 | else { |
| 1125 | assert(AFI->isThumb2Function()); |
| 1126 | emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, |
| 1127 | Offset, Pred, PredReg, TII); |
| 1128 | } |
Jim Grosbach | cde3129 | 2010-12-09 01:22:13 +0000 | [diff] [blame] | 1129 | // Update the original instruction to use the scratch register. |
Evan Cheng | cdbb3f5 | 2009-08-27 01:23:50 +0000 | [diff] [blame] | 1130 | MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); |
Evan Cheng | 6495f63 | 2009-07-28 05:48:47 +0000 | [diff] [blame] | 1131 | } |
David Goodwin | db5a71a | 2009-07-08 18:31:39 +0000 | [diff] [blame] | 1132 | } |