Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1 | //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file was developed by Evan Cheng and is distributed under |
| 6 | // the University of Illinois Open Source License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines the interfaces that ARM uses to lower LLVM code into a |
| 11 | // selection DAG. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #include "ARM.h" |
| 16 | #include "ARMAddressingModes.h" |
| 17 | #include "ARMConstantPoolValue.h" |
| 18 | #include "ARMISelLowering.h" |
| 19 | #include "ARMMachineFunctionInfo.h" |
| 20 | #include "ARMRegisterInfo.h" |
| 21 | #include "ARMSubtarget.h" |
| 22 | #include "ARMTargetMachine.h" |
| 23 | #include "llvm/CallingConv.h" |
| 24 | #include "llvm/Constants.h" |
| 25 | #include "llvm/CodeGen/MachineBasicBlock.h" |
| 26 | #include "llvm/CodeGen/MachineFrameInfo.h" |
| 27 | #include "llvm/CodeGen/MachineFunction.h" |
| 28 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
| 29 | #include "llvm/CodeGen/SelectionDAG.h" |
| 30 | #include "llvm/CodeGen/SSARegMap.h" |
Evan Cheng | b6ab254 | 2007-01-31 08:40:13 +0000 | [diff] [blame] | 31 | #include "llvm/Target/TargetOptions.h" |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 32 | #include "llvm/ADT/VectorExtras.h" |
| 33 | using namespace llvm; |
| 34 | |
| 35 | ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) |
| 36 | : TargetLowering(TM), ARMPCLabelIndex(0) { |
| 37 | Subtarget = &TM.getSubtarget<ARMSubtarget>(); |
| 38 | |
| 39 | // Uses VFP for Thumb libfuncs if available. |
Evan Cheng | b6ab254 | 2007-01-31 08:40:13 +0000 | [diff] [blame] | 40 | if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) { |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 41 | // Single-precision floating-point arithmetic. |
| 42 | setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); |
| 43 | setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); |
| 44 | setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); |
| 45 | setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); |
| 46 | |
| 47 | // Double-precision floating-point arithmetic. |
| 48 | setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); |
| 49 | setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); |
| 50 | setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); |
| 51 | setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); |
| 52 | |
| 53 | // Single-precision comparisons. |
| 54 | setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); |
| 55 | setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); |
| 56 | setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); |
| 57 | setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); |
| 58 | setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); |
| 59 | setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); |
| 60 | setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); |
Evan Cheng | 193f850 | 2007-01-31 09:30:58 +0000 | [diff] [blame] | 61 | setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); |
| 62 | |
| 63 | setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); |
| 64 | setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); |
| 65 | setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); |
| 66 | setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); |
| 67 | setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); |
| 68 | setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); |
| 69 | setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); |
| 70 | setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 71 | |
| 72 | // Double-precision comparisons. |
| 73 | setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); |
| 74 | setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); |
| 75 | setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); |
| 76 | setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); |
| 77 | setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); |
| 78 | setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); |
| 79 | setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); |
Evan Cheng | 193f850 | 2007-01-31 09:30:58 +0000 | [diff] [blame] | 80 | setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); |
| 81 | |
| 82 | setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); |
| 83 | setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); |
| 84 | setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); |
| 85 | setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); |
| 86 | setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); |
| 87 | setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); |
| 88 | setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); |
| 89 | setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 90 | |
| 91 | // Floating-point to integer conversions. |
| 92 | // i64 conversions are done via library routines even when generating VFP |
| 93 | // instructions, so use the same ones. |
| 94 | setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); |
| 95 | setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); |
| 96 | setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); |
| 97 | setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); |
| 98 | |
| 99 | // Conversions between floating types. |
| 100 | setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); |
| 101 | setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); |
| 102 | |
| 103 | // Integer to floating-point conversions. |
| 104 | // i64 conversions are done via library routines even when generating VFP |
| 105 | // instructions, so use the same ones. |
| 106 | // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. |
| 107 | // __floatunsidf vs. __floatunssidfvfp. |
| 108 | setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); |
| 109 | setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); |
| 110 | setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); |
| 111 | setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); |
| 112 | } |
| 113 | |
| 114 | addRegisterClass(MVT::i32, ARM::GPRRegisterClass); |
Evan Cheng | b6ab254 | 2007-01-31 08:40:13 +0000 | [diff] [blame] | 115 | if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 116 | addRegisterClass(MVT::f32, ARM::SPRRegisterClass); |
| 117 | addRegisterClass(MVT::f64, ARM::DPRRegisterClass); |
| 118 | } |
| 119 | |
| 120 | // ARM does not have f32 extending load. |
| 121 | setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); |
| 122 | |
| 123 | // ARM supports all 4 flavors of integer indexed load / store. |
| 124 | for (unsigned im = (unsigned)ISD::PRE_INC; |
| 125 | im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { |
| 126 | setIndexedLoadAction(im, MVT::i1, Legal); |
| 127 | setIndexedLoadAction(im, MVT::i8, Legal); |
| 128 | setIndexedLoadAction(im, MVT::i16, Legal); |
| 129 | setIndexedLoadAction(im, MVT::i32, Legal); |
| 130 | setIndexedStoreAction(im, MVT::i1, Legal); |
| 131 | setIndexedStoreAction(im, MVT::i8, Legal); |
| 132 | setIndexedStoreAction(im, MVT::i16, Legal); |
| 133 | setIndexedStoreAction(im, MVT::i32, Legal); |
| 134 | } |
| 135 | |
| 136 | // i64 operation support. |
| 137 | if (Subtarget->isThumb()) { |
| 138 | setOperationAction(ISD::MUL, MVT::i64, Expand); |
| 139 | setOperationAction(ISD::MULHU, MVT::i32, Expand); |
| 140 | setOperationAction(ISD::MULHS, MVT::i32, Expand); |
| 141 | } else { |
| 142 | setOperationAction(ISD::MUL, MVT::i64, Custom); |
| 143 | setOperationAction(ISD::MULHU, MVT::i32, Custom); |
| 144 | if (!Subtarget->hasV6Ops()) |
| 145 | setOperationAction(ISD::MULHS, MVT::i32, Custom); |
| 146 | } |
| 147 | setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); |
| 148 | setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); |
| 149 | setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); |
| 150 | setOperationAction(ISD::SRL, MVT::i64, Custom); |
| 151 | setOperationAction(ISD::SRA, MVT::i64, Custom); |
| 152 | |
| 153 | // ARM does not have ROTL. |
| 154 | setOperationAction(ISD::ROTL, MVT::i32, Expand); |
| 155 | setOperationAction(ISD::CTTZ , MVT::i32, Expand); |
| 156 | setOperationAction(ISD::CTPOP, MVT::i32, Expand); |
| 157 | if (!Subtarget->hasV5TOps()) |
| 158 | setOperationAction(ISD::CTLZ, MVT::i32, Expand); |
| 159 | |
| 160 | // These are expanded into libcalls. |
| 161 | setOperationAction(ISD::SDIV, MVT::i32, Expand); |
| 162 | setOperationAction(ISD::UDIV, MVT::i32, Expand); |
| 163 | setOperationAction(ISD::SREM, MVT::i32, Expand); |
| 164 | setOperationAction(ISD::UREM, MVT::i32, Expand); |
| 165 | |
| 166 | // Support label based line numbers. |
| 167 | setOperationAction(ISD::LOCATION, MVT::Other, Expand); |
| 168 | setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); |
| 169 | // FIXME - use subtarget debug flags |
Evan Cheng | 970a419 | 2007-01-19 19:28:01 +0000 | [diff] [blame] | 170 | if (Subtarget->isTargetDarwin()) |
Jim Laskey | 1ee2925 | 2007-01-26 14:34:52 +0000 | [diff] [blame] | 171 | setOperationAction(ISD::LABEL, MVT::Other, Expand); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 172 | |
| 173 | setOperationAction(ISD::RET, MVT::Other, Custom); |
| 174 | setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); |
| 175 | setOperationAction(ISD::ConstantPool, MVT::i32, Custom); |
| 176 | |
| 177 | // Expand mem operations genericly. |
| 178 | setOperationAction(ISD::MEMSET , MVT::Other, Expand); |
| 179 | setOperationAction(ISD::MEMCPY , MVT::Other, Expand); |
| 180 | setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); |
| 181 | |
| 182 | // Use the default implementation. |
| 183 | setOperationAction(ISD::VASTART , MVT::Other, Expand); |
| 184 | setOperationAction(ISD::VAARG , MVT::Other, Expand); |
| 185 | setOperationAction(ISD::VACOPY , MVT::Other, Expand); |
| 186 | setOperationAction(ISD::VAEND , MVT::Other, Expand); |
| 187 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| 188 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| 189 | setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); |
| 190 | |
| 191 | if (!Subtarget->hasV6Ops()) { |
| 192 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); |
| 193 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); |
| 194 | } |
| 195 | setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); |
| 196 | |
Evan Cheng | b6ab254 | 2007-01-31 08:40:13 +0000 | [diff] [blame] | 197 | if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 198 | // Turn f64->i64 into FMRRD iff target supports vfp2. |
| 199 | setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); |
| 200 | |
| 201 | setOperationAction(ISD::SETCC , MVT::i32, Expand); |
| 202 | setOperationAction(ISD::SETCC , MVT::f32, Expand); |
| 203 | setOperationAction(ISD::SETCC , MVT::f64, Expand); |
| 204 | setOperationAction(ISD::SELECT , MVT::i32, Expand); |
| 205 | setOperationAction(ISD::SELECT , MVT::f32, Expand); |
| 206 | setOperationAction(ISD::SELECT , MVT::f64, Expand); |
| 207 | setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); |
| 208 | setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); |
| 209 | setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); |
| 210 | |
| 211 | setOperationAction(ISD::BRCOND , MVT::Other, Expand); |
| 212 | setOperationAction(ISD::BR_CC , MVT::i32, Custom); |
| 213 | setOperationAction(ISD::BR_CC , MVT::f32, Custom); |
| 214 | setOperationAction(ISD::BR_CC , MVT::f64, Custom); |
| 215 | setOperationAction(ISD::BR_JT , MVT::Other, Custom); |
| 216 | |
| 217 | setOperationAction(ISD::VASTART, MVT::Other, Custom); |
| 218 | setOperationAction(ISD::VACOPY, MVT::Other, Expand); |
| 219 | setOperationAction(ISD::VAEND, MVT::Other, Expand); |
| 220 | setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| 221 | setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| 222 | |
| 223 | // FP Constants can't be immediates. |
| 224 | setOperationAction(ISD::ConstantFP, MVT::f64, Expand); |
| 225 | setOperationAction(ISD::ConstantFP, MVT::f32, Expand); |
| 226 | |
| 227 | // We don't support sin/cos/fmod/copysign |
| 228 | setOperationAction(ISD::FSIN , MVT::f64, Expand); |
| 229 | setOperationAction(ISD::FSIN , MVT::f32, Expand); |
| 230 | setOperationAction(ISD::FCOS , MVT::f32, Expand); |
| 231 | setOperationAction(ISD::FCOS , MVT::f64, Expand); |
| 232 | setOperationAction(ISD::FREM , MVT::f64, Expand); |
| 233 | setOperationAction(ISD::FREM , MVT::f32, Expand); |
| 234 | setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); |
| 235 | setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); |
| 236 | |
| 237 | // int <-> fp are custom expanded into bit_convert + ARMISD ops. |
| 238 | setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); |
| 239 | setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); |
| 240 | setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); |
| 241 | setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); |
| 242 | |
| 243 | setStackPointerRegisterToSaveRestore(ARM::SP); |
| 244 | |
| 245 | setSchedulingPreference(SchedulingForRegPressure); |
| 246 | computeRegisterProperties(); |
| 247 | } |
| 248 | |
| 249 | |
| 250 | const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { |
| 251 | switch (Opcode) { |
| 252 | default: return 0; |
| 253 | case ARMISD::Wrapper: return "ARMISD::Wrapper"; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 254 | case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; |
| 255 | case ARMISD::CALL: return "ARMISD::CALL"; |
| 256 | case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; |
| 257 | case ARMISD::tCALL: return "ARMISD::tCALL"; |
| 258 | case ARMISD::BRCOND: return "ARMISD::BRCOND"; |
| 259 | case ARMISD::BR_JT: return "ARMISD::BR_JT"; |
| 260 | case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; |
| 261 | case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; |
| 262 | case ARMISD::CMP: return "ARMISD::CMP"; |
| 263 | case ARMISD::CMPFP: return "ARMISD::CMPFP"; |
| 264 | case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; |
| 265 | case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; |
| 266 | case ARMISD::CMOV: return "ARMISD::CMOV"; |
| 267 | case ARMISD::CNEG: return "ARMISD::CNEG"; |
| 268 | |
| 269 | case ARMISD::FTOSI: return "ARMISD::FTOSI"; |
| 270 | case ARMISD::FTOUI: return "ARMISD::FTOUI"; |
| 271 | case ARMISD::SITOF: return "ARMISD::SITOF"; |
| 272 | case ARMISD::UITOF: return "ARMISD::UITOF"; |
| 273 | case ARMISD::MULHILOU: return "ARMISD::MULHILOU"; |
| 274 | case ARMISD::MULHILOS: return "ARMISD::MULHILOS"; |
| 275 | |
| 276 | case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; |
| 277 | case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; |
| 278 | case ARMISD::RRX: return "ARMISD::RRX"; |
| 279 | |
| 280 | case ARMISD::FMRRD: return "ARMISD::FMRRD"; |
| 281 | case ARMISD::FMDRR: return "ARMISD::FMDRR"; |
| 282 | } |
| 283 | } |
| 284 | |
| 285 | //===----------------------------------------------------------------------===// |
| 286 | // Lowering Code |
| 287 | //===----------------------------------------------------------------------===// |
| 288 | |
| 289 | |
| 290 | /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC |
| 291 | static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { |
| 292 | switch (CC) { |
| 293 | default: assert(0 && "Unknown condition code!"); |
| 294 | case ISD::SETNE: return ARMCC::NE; |
| 295 | case ISD::SETEQ: return ARMCC::EQ; |
| 296 | case ISD::SETGT: return ARMCC::GT; |
| 297 | case ISD::SETGE: return ARMCC::GE; |
| 298 | case ISD::SETLT: return ARMCC::LT; |
| 299 | case ISD::SETLE: return ARMCC::LE; |
| 300 | case ISD::SETUGT: return ARMCC::HI; |
| 301 | case ISD::SETUGE: return ARMCC::HS; |
| 302 | case ISD::SETULT: return ARMCC::LO; |
| 303 | case ISD::SETULE: return ARMCC::LS; |
| 304 | } |
| 305 | } |
| 306 | |
| 307 | /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It |
| 308 | /// returns true if the operands should be inverted to form the proper |
| 309 | /// comparison. |
| 310 | static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, |
| 311 | ARMCC::CondCodes &CondCode2) { |
| 312 | bool Invert = false; |
| 313 | CondCode2 = ARMCC::AL; |
| 314 | switch (CC) { |
| 315 | default: assert(0 && "Unknown FP condition!"); |
| 316 | case ISD::SETEQ: |
| 317 | case ISD::SETOEQ: CondCode = ARMCC::EQ; break; |
| 318 | case ISD::SETGT: |
| 319 | case ISD::SETOGT: CondCode = ARMCC::GT; break; |
| 320 | case ISD::SETGE: |
| 321 | case ISD::SETOGE: CondCode = ARMCC::GE; break; |
| 322 | case ISD::SETOLT: CondCode = ARMCC::MI; break; |
| 323 | case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; |
| 324 | case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; |
| 325 | case ISD::SETO: CondCode = ARMCC::VC; break; |
| 326 | case ISD::SETUO: CondCode = ARMCC::VS; break; |
| 327 | case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; |
| 328 | case ISD::SETUGT: CondCode = ARMCC::HI; break; |
| 329 | case ISD::SETUGE: CondCode = ARMCC::PL; break; |
| 330 | case ISD::SETLT: |
| 331 | case ISD::SETULT: CondCode = ARMCC::LT; break; |
| 332 | case ISD::SETLE: |
| 333 | case ISD::SETULE: CondCode = ARMCC::LE; break; |
| 334 | case ISD::SETNE: |
| 335 | case ISD::SETUNE: CondCode = ARMCC::NE; break; |
| 336 | } |
| 337 | return Invert; |
| 338 | } |
| 339 | |
| 340 | static void |
| 341 | HowToPassArgument(MVT::ValueType ObjectVT, |
| 342 | unsigned NumGPRs, unsigned &ObjSize, unsigned &ObjGPRs) { |
| 343 | ObjSize = 0; |
| 344 | ObjGPRs = 0; |
| 345 | |
| 346 | switch (ObjectVT) { |
| 347 | default: assert(0 && "Unhandled argument type!"); |
| 348 | case MVT::i32: |
| 349 | case MVT::f32: |
| 350 | if (NumGPRs < 4) |
| 351 | ObjGPRs = 1; |
| 352 | else |
| 353 | ObjSize = 4; |
| 354 | break; |
| 355 | case MVT::i64: |
| 356 | case MVT::f64: |
| 357 | if (NumGPRs < 3) |
| 358 | ObjGPRs = 2; |
| 359 | else if (NumGPRs == 3) { |
| 360 | ObjGPRs = 1; |
| 361 | ObjSize = 4; |
| 362 | } else |
| 363 | ObjSize = 8; |
| 364 | } |
| 365 | } |
| 366 | |
| 367 | // This transforms a ISD::CALL node into a |
| 368 | // callseq_star <- ARMISD:CALL <- callseq_end |
| 369 | // chain |
| 370 | SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { |
| 371 | MVT::ValueType RetVT= Op.Val->getValueType(0); |
| 372 | SDOperand Chain = Op.getOperand(0); |
| 373 | unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); |
| 374 | assert((CallConv == CallingConv::C || |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 375 | CallConv == CallingConv::Fast) && "unknown calling convention"); |
| 376 | SDOperand Callee = Op.getOperand(4); |
| 377 | unsigned NumOps = (Op.getNumOperands() - 5) / 2; |
| 378 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 379 | unsigned NumGPRs = 0; // GPRs used for parameter passing. |
| 380 | |
| 381 | // Count how many bytes are to be pushed on the stack. |
| 382 | unsigned NumBytes = 0; |
| 383 | |
| 384 | // Add up all the space actually used. |
| 385 | for (unsigned i = 0; i < NumOps; ++i) { |
| 386 | unsigned ObjSize = 0; |
| 387 | unsigned ObjGPRs = 0; |
| 388 | MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); |
| 389 | HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs); |
| 390 | NumBytes += ObjSize; |
| 391 | NumGPRs += ObjGPRs; |
| 392 | } |
| 393 | |
| 394 | // Adjust the stack pointer for the new arguments... |
| 395 | // These operations are automatically eliminated by the prolog/epilog pass |
| 396 | Chain = DAG.getCALLSEQ_START(Chain, |
| 397 | DAG.getConstant(NumBytes, MVT::i32)); |
| 398 | |
| 399 | SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); |
| 400 | |
| 401 | static const unsigned GPRArgRegs[] = { |
| 402 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
| 403 | }; |
| 404 | |
| 405 | NumGPRs = 0; |
| 406 | std::vector<std::pair<unsigned, SDOperand> > RegsToPass; |
| 407 | std::vector<SDOperand> MemOpChains; |
| 408 | for (unsigned i = 0; i != NumOps; ++i) { |
| 409 | SDOperand Arg = Op.getOperand(5+2*i); |
| 410 | MVT::ValueType ArgVT = Arg.getValueType(); |
| 411 | |
| 412 | unsigned ObjSize = 0; |
| 413 | unsigned ObjGPRs = 0; |
| 414 | HowToPassArgument(ArgVT, NumGPRs, ObjSize, ObjGPRs); |
| 415 | if (ObjGPRs > 0) { |
| 416 | switch (ArgVT) { |
| 417 | default: assert(0 && "Unexpected ValueType for argument!"); |
| 418 | case MVT::i32: |
| 419 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); |
| 420 | break; |
| 421 | case MVT::f32: |
| 422 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], |
| 423 | DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); |
| 424 | break; |
| 425 | case MVT::i64: { |
| 426 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, |
| 427 | DAG.getConstant(0, getPointerTy())); |
| 428 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, |
| 429 | DAG.getConstant(1, getPointerTy())); |
| 430 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); |
| 431 | if (ObjGPRs == 2) |
| 432 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); |
| 433 | else { |
| 434 | SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); |
| 435 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 436 | MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); |
| 437 | } |
| 438 | break; |
| 439 | } |
| 440 | case MVT::f64: { |
| 441 | SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, |
| 442 | DAG.getVTList(MVT::i32, MVT::i32), |
| 443 | &Arg, 1); |
| 444 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); |
| 445 | if (ObjGPRs == 2) |
| 446 | RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], |
| 447 | Cvt.getValue(1))); |
| 448 | else { |
| 449 | SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); |
| 450 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 451 | MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, |
| 452 | NULL, 0)); |
| 453 | } |
| 454 | break; |
| 455 | } |
| 456 | } |
| 457 | } else { |
| 458 | assert(ObjSize != 0); |
| 459 | SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); |
| 460 | PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); |
| 461 | MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); |
| 462 | } |
| 463 | |
| 464 | NumGPRs += ObjGPRs; |
| 465 | ArgOffset += ObjSize; |
| 466 | } |
| 467 | |
| 468 | if (!MemOpChains.empty()) |
| 469 | Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 470 | &MemOpChains[0], MemOpChains.size()); |
| 471 | |
| 472 | // Build a sequence of copy-to-reg nodes chained together with token chain |
| 473 | // and flag operands which copy the outgoing args into the appropriate regs. |
| 474 | SDOperand InFlag; |
| 475 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { |
| 476 | Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, |
| 477 | InFlag); |
| 478 | InFlag = Chain.getValue(1); |
| 479 | } |
| 480 | |
| 481 | // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every |
| 482 | // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol |
| 483 | // node so that legalize doesn't hack it. |
| 484 | bool isDirect = false; |
| 485 | bool isARMFunc = false; |
| 486 | if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { |
| 487 | GlobalValue *GV = G->getGlobal(); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 488 | isDirect = true; |
Reid Spencer | 5cbf985 | 2007-01-30 20:08:39 +0000 | [diff] [blame] | 489 | bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 490 | GV->hasLinkOnceLinkage()); |
Evan Cheng | 970a419 | 2007-01-19 19:28:01 +0000 | [diff] [blame] | 491 | bool isStub = (isExt && Subtarget->isTargetDarwin()) && |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 492 | getTargetMachine().getRelocationModel() != Reloc::Static; |
| 493 | isARMFunc = !Subtarget->isThumb() || isStub; |
Evan Cheng | c60e76d | 2007-01-30 20:37:08 +0000 | [diff] [blame] | 494 | // tBX takes a register source operand. |
| 495 | if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { |
| 496 | ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, |
| 497 | ARMCP::CPStub, 4); |
| 498 | SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); |
| 499 | CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); |
| 500 | Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); |
| 501 | SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); |
| 502 | Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); |
| 503 | } else |
| 504 | Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 505 | } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 506 | isDirect = true; |
Evan Cheng | 970a419 | 2007-01-19 19:28:01 +0000 | [diff] [blame] | 507 | bool isStub = Subtarget->isTargetDarwin() && |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 508 | getTargetMachine().getRelocationModel() != Reloc::Static; |
| 509 | isARMFunc = !Subtarget->isThumb() || isStub; |
Evan Cheng | c60e76d | 2007-01-30 20:37:08 +0000 | [diff] [blame] | 510 | // tBX takes a register source operand. |
| 511 | const char *Sym = S->getSymbol(); |
| 512 | if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { |
| 513 | ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, |
| 514 | ARMCP::CPStub, 4); |
| 515 | SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); |
| 516 | CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); |
| 517 | Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); |
| 518 | SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); |
| 519 | Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); |
| 520 | } else |
| 521 | Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 522 | } |
| 523 | |
| 524 | std::vector<MVT::ValueType> NodeTys; |
| 525 | NodeTys.push_back(MVT::Other); // Returns a chain |
| 526 | NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. |
| 527 | |
| 528 | std::vector<SDOperand> Ops; |
| 529 | Ops.push_back(Chain); |
| 530 | Ops.push_back(Callee); |
| 531 | |
| 532 | // Add argument registers to the end of the list so that they are known live |
| 533 | // into the call. |
| 534 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) |
| 535 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, |
| 536 | RegsToPass[i].second.getValueType())); |
| 537 | |
| 538 | // FIXME: handle tail calls differently. |
| 539 | unsigned CallOpc; |
| 540 | if (Subtarget->isThumb()) { |
| 541 | if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) |
| 542 | CallOpc = ARMISD::CALL_NOLINK; |
| 543 | else |
| 544 | CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; |
| 545 | } else { |
| 546 | CallOpc = (isDirect || Subtarget->hasV5TOps()) |
| 547 | ? ARMISD::CALL : ARMISD::CALL_NOLINK; |
| 548 | } |
| 549 | if (InFlag.Val) |
| 550 | Ops.push_back(InFlag); |
| 551 | Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); |
| 552 | InFlag = Chain.getValue(1); |
| 553 | |
| 554 | SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; |
| 555 | Chain = DAG.getNode(ISD::CALLSEQ_END, |
| 556 | DAG.getNodeValueTypes(MVT::Other, MVT::Flag), |
| 557 | ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); |
| 558 | if (RetVT != MVT::Other) |
| 559 | InFlag = Chain.getValue(1); |
| 560 | |
| 561 | std::vector<SDOperand> ResultVals; |
| 562 | NodeTys.clear(); |
| 563 | |
| 564 | // If the call has results, copy the values out of the ret val registers. |
| 565 | switch (RetVT) { |
| 566 | default: assert(0 && "Unexpected ret value!"); |
| 567 | case MVT::Other: |
| 568 | break; |
| 569 | case MVT::i32: |
| 570 | Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); |
| 571 | ResultVals.push_back(Chain.getValue(0)); |
| 572 | if (Op.Val->getValueType(1) == MVT::i32) { |
| 573 | // Returns a i64 value. |
| 574 | Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, |
| 575 | Chain.getValue(2)).getValue(1); |
| 576 | ResultVals.push_back(Chain.getValue(0)); |
| 577 | NodeTys.push_back(MVT::i32); |
| 578 | } |
| 579 | NodeTys.push_back(MVT::i32); |
| 580 | break; |
| 581 | case MVT::f32: |
| 582 | Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); |
| 583 | ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, |
| 584 | Chain.getValue(0))); |
| 585 | NodeTys.push_back(MVT::f32); |
| 586 | break; |
| 587 | case MVT::f64: { |
| 588 | SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); |
| 589 | SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); |
| 590 | ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); |
| 591 | NodeTys.push_back(MVT::f64); |
| 592 | break; |
| 593 | } |
| 594 | } |
| 595 | |
| 596 | NodeTys.push_back(MVT::Other); |
| 597 | |
| 598 | if (ResultVals.empty()) |
| 599 | return Chain; |
| 600 | |
| 601 | ResultVals.push_back(Chain); |
| 602 | SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], |
| 603 | ResultVals.size()); |
| 604 | return Res.getValue(Op.ResNo); |
| 605 | } |
| 606 | |
| 607 | static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { |
| 608 | SDOperand Copy; |
| 609 | SDOperand Chain = Op.getOperand(0); |
| 610 | switch(Op.getNumOperands()) { |
| 611 | default: |
| 612 | assert(0 && "Do not know how to return this many arguments!"); |
| 613 | abort(); |
| 614 | case 1: { |
| 615 | SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); |
| 616 | return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); |
| 617 | } |
| 618 | case 3: |
| 619 | Op = Op.getOperand(1); |
| 620 | if (Op.getValueType() == MVT::f32) { |
| 621 | Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); |
| 622 | } else if (Op.getValueType() == MVT::f64) { |
| 623 | // Recursively legalize f64 -> i64. |
| 624 | Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op); |
| 625 | return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, |
| 626 | DAG.getConstant(0, MVT::i32)); |
| 627 | } |
| 628 | Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); |
| 629 | if (DAG.getMachineFunction().liveout_empty()) |
| 630 | DAG.getMachineFunction().addLiveOut(ARM::R0); |
| 631 | break; |
| 632 | case 5: |
| 633 | Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); |
| 634 | Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); |
| 635 | // If we haven't noted the R0+R1 are live out, do so now. |
| 636 | if (DAG.getMachineFunction().liveout_empty()) { |
| 637 | DAG.getMachineFunction().addLiveOut(ARM::R0); |
| 638 | DAG.getMachineFunction().addLiveOut(ARM::R1); |
| 639 | } |
| 640 | break; |
| 641 | } |
| 642 | |
| 643 | //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag |
| 644 | return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); |
| 645 | } |
| 646 | |
| 647 | // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as |
| 648 | // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is |
| 649 | // one of the above mentioned nodes. It has to be wrapped because otherwise |
| 650 | // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only |
| 651 | // be used to form addressing mode. These wrapped nodes will be selected |
| 652 | // into MOVri. |
| 653 | static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { |
| 654 | MVT::ValueType PtrVT = Op.getValueType(); |
| 655 | ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); |
| 656 | SDOperand Res; |
| 657 | if (CP->isMachineConstantPoolEntry()) |
| 658 | Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, |
| 659 | CP->getAlignment()); |
| 660 | else |
| 661 | Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, |
| 662 | CP->getAlignment()); |
| 663 | return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); |
| 664 | } |
| 665 | |
| 666 | /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol |
| 667 | /// even in dynamic-no-pic mode. |
| 668 | static bool GVIsIndirectSymbol(GlobalValue *GV) { |
| 669 | return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || |
Reid Spencer | 5cbf985 | 2007-01-30 20:08:39 +0000 | [diff] [blame] | 670 | (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode())); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | SDOperand ARMTargetLowering::LowerGlobalAddress(SDOperand Op, |
| 674 | SelectionDAG &DAG) { |
| 675 | MVT::ValueType PtrVT = getPointerTy(); |
| 676 | GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); |
| 677 | Reloc::Model RelocM = getTargetMachine().getRelocationModel(); |
Evan Cheng | 970a419 | 2007-01-19 19:28:01 +0000 | [diff] [blame] | 678 | bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 679 | SDOperand CPAddr; |
| 680 | if (RelocM == Reloc::Static) |
| 681 | CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); |
| 682 | else { |
| 683 | unsigned PCAdj = (RelocM != Reloc::PIC_) |
| 684 | ? 0 : (Subtarget->isThumb() ? 4 : 8); |
Evan Cheng | c60e76d | 2007-01-30 20:37:08 +0000 | [diff] [blame] | 685 | ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr |
| 686 | : ARMCP::CPValue; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 687 | ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, |
Evan Cheng | c60e76d | 2007-01-30 20:37:08 +0000 | [diff] [blame] | 688 | Kind, PCAdj); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 689 | CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); |
| 690 | } |
| 691 | CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); |
| 692 | |
| 693 | SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); |
| 694 | SDOperand Chain = Result.getValue(1); |
| 695 | |
| 696 | if (RelocM == Reloc::PIC_) { |
| 697 | SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); |
| 698 | Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); |
| 699 | } |
| 700 | if (IsIndirect) |
| 701 | Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); |
| 702 | |
| 703 | return Result; |
| 704 | } |
| 705 | |
| 706 | static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, |
| 707 | unsigned VarArgsFrameIndex) { |
| 708 | // vastart just stores the address of the VarArgsFrameIndex slot into the |
| 709 | // memory location argument. |
| 710 | MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); |
| 711 | SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); |
| 712 | SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); |
| 713 | return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), |
| 714 | SV->getOffset()); |
| 715 | } |
| 716 | |
| 717 | static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, |
| 718 | unsigned *vRegs, unsigned ArgNo, |
| 719 | unsigned &NumGPRs, unsigned &ArgOffset) { |
| 720 | MachineFunction &MF = DAG.getMachineFunction(); |
| 721 | MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); |
| 722 | SDOperand Root = Op.getOperand(0); |
| 723 | std::vector<SDOperand> ArgValues; |
| 724 | SSARegMap *RegMap = MF.getSSARegMap(); |
| 725 | |
| 726 | static const unsigned GPRArgRegs[] = { |
| 727 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
| 728 | }; |
| 729 | |
| 730 | unsigned ObjSize = 0; |
| 731 | unsigned ObjGPRs = 0; |
| 732 | HowToPassArgument(ObjectVT, NumGPRs, ObjSize, ObjGPRs); |
| 733 | |
| 734 | SDOperand ArgValue; |
| 735 | if (ObjGPRs == 1) { |
| 736 | unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); |
| 737 | MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); |
| 738 | vRegs[NumGPRs] = VReg; |
| 739 | ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
| 740 | if (ObjectVT == MVT::f32) |
| 741 | ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); |
| 742 | } else if (ObjGPRs == 2) { |
| 743 | unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); |
| 744 | MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); |
| 745 | vRegs[NumGPRs] = VReg; |
| 746 | ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
| 747 | |
| 748 | VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); |
| 749 | MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); |
| 750 | vRegs[NumGPRs+1] = VReg; |
| 751 | SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
| 752 | |
| 753 | if (ObjectVT == MVT::i64) |
| 754 | ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); |
| 755 | else |
| 756 | ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); |
| 757 | } |
| 758 | NumGPRs += ObjGPRs; |
| 759 | |
| 760 | if (ObjSize) { |
| 761 | // If the argument is actually used, emit a load from the right stack |
| 762 | // slot. |
| 763 | if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { |
| 764 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 765 | int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); |
| 766 | SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); |
| 767 | if (ObjGPRs == 0) |
| 768 | ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); |
| 769 | else { |
| 770 | SDOperand ArgValue2 = |
| 771 | DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); |
| 772 | if (ObjectVT == MVT::i64) |
| 773 | ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); |
| 774 | else |
| 775 | ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); |
| 776 | } |
| 777 | } else { |
| 778 | // Don't emit a dead load. |
| 779 | ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); |
| 780 | } |
| 781 | |
| 782 | ArgOffset += ObjSize; // Move on to the next argument. |
| 783 | } |
| 784 | |
| 785 | return ArgValue; |
| 786 | } |
| 787 | |
| 788 | SDOperand |
| 789 | ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { |
| 790 | std::vector<SDOperand> ArgValues; |
| 791 | SDOperand Root = Op.getOperand(0); |
| 792 | unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot |
| 793 | unsigned NumGPRs = 0; // GPRs used for parameter passing. |
| 794 | unsigned VRegs[4]; |
| 795 | |
| 796 | unsigned NumArgs = Op.Val->getNumValues()-1; |
| 797 | for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) |
| 798 | ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, |
| 799 | NumGPRs, ArgOffset)); |
| 800 | |
| 801 | bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; |
| 802 | if (isVarArg) { |
| 803 | static const unsigned GPRArgRegs[] = { |
| 804 | ARM::R0, ARM::R1, ARM::R2, ARM::R3 |
| 805 | }; |
| 806 | |
| 807 | MachineFunction &MF = DAG.getMachineFunction(); |
| 808 | SSARegMap *RegMap = MF.getSSARegMap(); |
| 809 | MachineFrameInfo *MFI = MF.getFrameInfo(); |
| 810 | ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); |
| 811 | unsigned VARegSaveSize = (4 - NumGPRs) * 4; |
| 812 | if (VARegSaveSize) { |
| 813 | // If this function is vararg, store any remaining integer argument regs |
| 814 | // to their spots on the stack so that they may be loaded by deferencing |
| 815 | // the result of va_next. |
| 816 | AFI->setVarArgsRegSaveSize(VARegSaveSize); |
| 817 | VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset); |
| 818 | SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); |
| 819 | |
| 820 | SmallVector<SDOperand, 4> MemOps; |
| 821 | for (; NumGPRs < 4; ++NumGPRs) { |
| 822 | unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); |
| 823 | MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); |
| 824 | SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); |
| 825 | SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); |
| 826 | MemOps.push_back(Store); |
| 827 | FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, |
| 828 | DAG.getConstant(4, getPointerTy())); |
| 829 | } |
| 830 | if (!MemOps.empty()) |
| 831 | Root = DAG.getNode(ISD::TokenFactor, MVT::Other, |
| 832 | &MemOps[0], MemOps.size()); |
| 833 | } else |
| 834 | // This will point to the next argument passed via stack. |
| 835 | VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); |
| 836 | } |
| 837 | |
| 838 | ArgValues.push_back(Root); |
| 839 | |
| 840 | // Return the new list of results. |
| 841 | std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), |
| 842 | Op.Val->value_end()); |
| 843 | return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); |
| 844 | } |
| 845 | |
| 846 | /// isFloatingPointZero - Return true if this is +0.0. |
| 847 | static bool isFloatingPointZero(SDOperand Op) { |
| 848 | if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) |
| 849 | return CFP->isExactlyValue(0.0); |
| 850 | else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { |
| 851 | // Maybe this has already been legalized into the constant pool? |
| 852 | if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { |
| 853 | SDOperand WrapperOp = Op.getOperand(1).getOperand(0); |
| 854 | if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) |
| 855 | if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) |
| 856 | return CFP->isExactlyValue(0.0); |
| 857 | } |
| 858 | } |
| 859 | return false; |
| 860 | } |
| 861 | |
| 862 | static bool isLegalCmpImmediate(int C, bool isThumb) { |
| 863 | return ( isThumb && (C & ~255U) == 0) || |
| 864 | (!isThumb && ARM_AM::getSOImmVal(C) != -1); |
| 865 | } |
| 866 | |
| 867 | /// Returns appropriate ARM CMP (cmp) and corresponding condition code for |
| 868 | /// the given operands. |
| 869 | static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, |
| 870 | SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { |
| 871 | if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { |
| 872 | int C = (int)RHSC->getValue(); |
| 873 | if (!isLegalCmpImmediate(C, isThumb)) { |
| 874 | // Constant does not fit, try adjusting it by one? |
| 875 | switch (CC) { |
| 876 | default: break; |
| 877 | case ISD::SETLT: |
| 878 | case ISD::SETULT: |
| 879 | case ISD::SETGE: |
| 880 | case ISD::SETUGE: |
| 881 | if (isLegalCmpImmediate(C-1, isThumb)) { |
| 882 | switch (CC) { |
| 883 | default: break; |
| 884 | case ISD::SETLT: CC = ISD::SETLE; break; |
| 885 | case ISD::SETULT: CC = ISD::SETULE; break; |
| 886 | case ISD::SETGE: CC = ISD::SETGT; break; |
| 887 | case ISD::SETUGE: CC = ISD::SETUGT; break; |
| 888 | } |
| 889 | RHS = DAG.getConstant(C-1, MVT::i32); |
| 890 | } |
| 891 | break; |
| 892 | case ISD::SETLE: |
| 893 | case ISD::SETULE: |
| 894 | case ISD::SETGT: |
| 895 | case ISD::SETUGT: |
| 896 | if (isLegalCmpImmediate(C+1, isThumb)) { |
| 897 | switch (CC) { |
| 898 | default: break; |
| 899 | case ISD::SETLE: CC = ISD::SETLT; break; |
| 900 | case ISD::SETULE: CC = ISD::SETULT; break; |
| 901 | case ISD::SETGT: CC = ISD::SETGE; break; |
| 902 | case ISD::SETUGT: CC = ISD::SETUGE; break; |
| 903 | } |
| 904 | RHS = DAG.getConstant(C+1, MVT::i32); |
| 905 | } |
| 906 | break; |
| 907 | } |
| 908 | } |
| 909 | } |
| 910 | |
| 911 | ARMCC::CondCodes CondCode = IntCCToARMCC(CC); |
| 912 | ARMCC = DAG.getConstant(CondCode, MVT::i32); |
| 913 | return DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS); |
| 914 | } |
| 915 | |
| 916 | /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. |
| 917 | static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { |
| 918 | SDOperand Cmp; |
| 919 | if (!isFloatingPointZero(RHS)) |
| 920 | Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); |
| 921 | else |
| 922 | Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); |
| 923 | return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); |
| 924 | } |
| 925 | |
| 926 | static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, |
| 927 | const ARMSubtarget *ST) { |
| 928 | MVT::ValueType VT = Op.getValueType(); |
| 929 | SDOperand LHS = Op.getOperand(0); |
| 930 | SDOperand RHS = Op.getOperand(1); |
| 931 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); |
| 932 | SDOperand TrueVal = Op.getOperand(2); |
| 933 | SDOperand FalseVal = Op.getOperand(3); |
| 934 | |
| 935 | if (LHS.getValueType() == MVT::i32) { |
| 936 | SDOperand ARMCC; |
| 937 | SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); |
| 938 | return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp); |
| 939 | } |
| 940 | |
| 941 | ARMCC::CondCodes CondCode, CondCode2; |
| 942 | if (FPCCToARMCC(CC, CondCode, CondCode2)) |
| 943 | std::swap(TrueVal, FalseVal); |
| 944 | |
| 945 | SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); |
| 946 | SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); |
| 947 | SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, |
| 948 | ARMCC, Cmp); |
| 949 | if (CondCode2 != ARMCC::AL) { |
| 950 | SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); |
| 951 | // FIXME: Needs another CMP because flag can have but one use. |
| 952 | SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); |
| 953 | Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2); |
| 954 | } |
| 955 | return Result; |
| 956 | } |
| 957 | |
| 958 | static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, |
| 959 | const ARMSubtarget *ST) { |
| 960 | SDOperand Chain = Op.getOperand(0); |
| 961 | ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); |
| 962 | SDOperand LHS = Op.getOperand(2); |
| 963 | SDOperand RHS = Op.getOperand(3); |
| 964 | SDOperand Dest = Op.getOperand(4); |
| 965 | |
| 966 | if (LHS.getValueType() == MVT::i32) { |
| 967 | SDOperand ARMCC; |
| 968 | SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); |
| 969 | return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp); |
| 970 | } |
| 971 | |
| 972 | assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); |
| 973 | ARMCC::CondCodes CondCode, CondCode2; |
| 974 | if (FPCCToARMCC(CC, CondCode, CondCode2)) |
| 975 | // Swap the LHS/RHS of the comparison if needed. |
| 976 | std::swap(LHS, RHS); |
| 977 | |
| 978 | SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); |
| 979 | SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); |
| 980 | SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); |
| 981 | SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp }; |
| 982 | SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4); |
| 983 | if (CondCode2 != ARMCC::AL) { |
| 984 | ARMCC = DAG.getConstant(CondCode2, MVT::i32); |
| 985 | SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) }; |
| 986 | Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4); |
| 987 | } |
| 988 | return Res; |
| 989 | } |
| 990 | |
| 991 | SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { |
| 992 | SDOperand Chain = Op.getOperand(0); |
| 993 | SDOperand Table = Op.getOperand(1); |
| 994 | SDOperand Index = Op.getOperand(2); |
| 995 | |
| 996 | MVT::ValueType PTy = getPointerTy(); |
| 997 | JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); |
| 998 | ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); |
| 999 | SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); |
| 1000 | SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); |
| 1001 | Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); |
| 1002 | Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); |
| 1003 | SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); |
| 1004 | bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; |
| 1005 | Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0); |
| 1006 | Chain = Addr.getValue(1); |
| 1007 | if (isPIC) |
| 1008 | Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); |
| 1009 | return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); |
| 1010 | } |
| 1011 | |
| 1012 | static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { |
| 1013 | unsigned Opc = |
| 1014 | Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; |
| 1015 | Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); |
| 1016 | return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); |
| 1017 | } |
| 1018 | |
| 1019 | static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { |
| 1020 | MVT::ValueType VT = Op.getValueType(); |
| 1021 | unsigned Opc = |
| 1022 | Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; |
| 1023 | |
| 1024 | Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); |
| 1025 | return DAG.getNode(Opc, VT, Op); |
| 1026 | } |
| 1027 | |
| 1028 | static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { |
| 1029 | // Implement fcopysign with a fabs and a conditional fneg. |
| 1030 | SDOperand Tmp0 = Op.getOperand(0); |
| 1031 | SDOperand Tmp1 = Op.getOperand(1); |
| 1032 | MVT::ValueType VT = Op.getValueType(); |
| 1033 | MVT::ValueType SrcVT = Tmp1.getValueType(); |
| 1034 | SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); |
| 1035 | SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); |
| 1036 | SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); |
| 1037 | return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp); |
| 1038 | } |
| 1039 | |
| 1040 | static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) { |
| 1041 | // Turn f64->i64 into FMRRD. |
| 1042 | assert(Op.getValueType() == MVT::i64 && |
| 1043 | Op.getOperand(0).getValueType() == MVT::f64); |
| 1044 | |
| 1045 | Op = Op.getOperand(0); |
| 1046 | SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), |
| 1047 | &Op, 1); |
| 1048 | |
| 1049 | // Merge the pieces into a single i64 value. |
| 1050 | return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); |
| 1051 | } |
| 1052 | |
| 1053 | static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { |
| 1054 | // FIXME: All this code is target-independent. Create a new target-indep |
| 1055 | // MULHILO node and move this code to the legalizer. |
| 1056 | // |
| 1057 | assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!"); |
| 1058 | |
| 1059 | SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), |
| 1060 | DAG.getConstant(0, MVT::i32)); |
| 1061 | SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), |
| 1062 | DAG.getConstant(0, MVT::i32)); |
| 1063 | |
| 1064 | const TargetLowering &TL = DAG.getTargetLoweringInfo(); |
| 1065 | unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0)); |
| 1066 | unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1)); |
| 1067 | |
| 1068 | SDOperand Lo, Hi; |
| 1069 | // Figure out how to lower this multiply. |
| 1070 | if (LHSSB >= 33 && RHSSB >= 33) { |
| 1071 | // If the input values are both sign extended, we can emit a mulhs+mul. |
| 1072 | Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); |
| 1073 | Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL); |
| 1074 | } else if (LHSSB == 32 && RHSSB == 32 && |
| 1075 | TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && |
| 1076 | TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { |
| 1077 | // If the inputs are zero extended, use mulhu. |
| 1078 | Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); |
| 1079 | Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL); |
| 1080 | } else { |
| 1081 | SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), |
| 1082 | DAG.getConstant(1, MVT::i32)); |
| 1083 | SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), |
| 1084 | DAG.getConstant(1, MVT::i32)); |
| 1085 | |
| 1086 | // Lo,Hi = umul LHS, RHS. |
| 1087 | SDOperand Ops[] = { LL, RL }; |
| 1088 | SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU, |
| 1089 | DAG.getVTList(MVT::i32, MVT::i32), Ops, 2); |
| 1090 | Lo = UMul64; |
| 1091 | Hi = UMul64.getValue(1); |
| 1092 | RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH); |
| 1093 | LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL); |
| 1094 | Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH); |
| 1095 | Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH); |
| 1096 | } |
| 1097 | |
| 1098 | // Merge the pieces into a single i64 value. |
| 1099 | return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 1100 | } |
| 1101 | |
| 1102 | static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) { |
| 1103 | SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; |
| 1104 | return DAG.getNode(ARMISD::MULHILOU, |
| 1105 | DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); |
| 1106 | } |
| 1107 | |
| 1108 | static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) { |
| 1109 | SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; |
| 1110 | return DAG.getNode(ARMISD::MULHILOS, |
| 1111 | DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); |
| 1112 | } |
| 1113 | |
| 1114 | static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG, |
| 1115 | const ARMSubtarget *ST) { |
| 1116 | assert(Op.getValueType() == MVT::i64 && |
| 1117 | (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && |
| 1118 | "Unknown shift to lower!"); |
| 1119 | |
| 1120 | // We only lower SRA, SRL of 1 here, all others use generic lowering. |
| 1121 | if (!isa<ConstantSDNode>(Op.getOperand(1)) || |
| 1122 | cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1) |
| 1123 | return SDOperand(); |
| 1124 | |
| 1125 | // If we are in thumb mode, we don't have RRX. |
| 1126 | if (ST->isThumb()) return SDOperand(); |
| 1127 | |
| 1128 | // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. |
| 1129 | SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), |
| 1130 | DAG.getConstant(0, MVT::i32)); |
| 1131 | SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), |
| 1132 | DAG.getConstant(1, MVT::i32)); |
| 1133 | |
| 1134 | // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and |
| 1135 | // captures the result into a carry flag. |
| 1136 | unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; |
| 1137 | Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); |
| 1138 | |
| 1139 | // The low part is an ARMISD::RRX operand, which shifts the carry in. |
| 1140 | Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); |
| 1141 | |
| 1142 | // Merge the pieces into a single i64 value. |
| 1143 | return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); |
| 1144 | } |
| 1145 | |
| 1146 | SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { |
| 1147 | switch (Op.getOpcode()) { |
| 1148 | default: assert(0 && "Don't know how to custom lower this!"); abort(); |
| 1149 | case ISD::ConstantPool: return LowerConstantPool(Op, DAG); |
| 1150 | case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); |
| 1151 | case ISD::CALL: return LowerCALL(Op, DAG); |
| 1152 | case ISD::RET: return LowerRET(Op, DAG); |
| 1153 | case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); |
| 1154 | case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); |
| 1155 | case ISD::BR_JT: return LowerBR_JT(Op, DAG); |
| 1156 | case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); |
| 1157 | case ISD::SINT_TO_FP: |
| 1158 | case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); |
| 1159 | case ISD::FP_TO_SINT: |
| 1160 | case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); |
| 1161 | case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); |
| 1162 | case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); |
| 1163 | case ISD::MUL: return LowerMUL(Op, DAG); |
| 1164 | case ISD::MULHU: return LowerMULHU(Op, DAG); |
| 1165 | case ISD::MULHS: return LowerMULHS(Op, DAG); |
| 1166 | case ISD::SRL: |
| 1167 | case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); |
| 1168 | case ISD::FORMAL_ARGUMENTS: |
| 1169 | return LowerFORMAL_ARGUMENTS(Op, DAG); |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 1170 | case ISD::RETURNADDR: break; |
| 1171 | case ISD::FRAMEADDR: break; |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1172 | } |
Nate Begeman | bcc5f36 | 2007-01-29 22:58:52 +0000 | [diff] [blame] | 1173 | return SDOperand(); |
Evan Cheng | a8e2989 | 2007-01-19 07:51:42 +0000 | [diff] [blame] | 1174 | } |
| 1175 | |
| 1176 | //===----------------------------------------------------------------------===// |
| 1177 | // ARM Scheduler Hooks |
| 1178 | //===----------------------------------------------------------------------===// |
| 1179 | |
| 1180 | MachineBasicBlock * |
| 1181 | ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, |
| 1182 | MachineBasicBlock *BB) { |
| 1183 | const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); |
| 1184 | switch (MI->getOpcode()) { |
| 1185 | default: assert(false && "Unexpected instr type to insert"); |
| 1186 | case ARM::tMOVCCr: { |
| 1187 | // To "insert" a SELECT_CC instruction, we actually have to insert the |
| 1188 | // diamond control-flow pattern. The incoming instruction knows the |
| 1189 | // destination vreg to set, the condition code register to branch on, the |
| 1190 | // true/false values to select between, and a branch opcode to use. |
| 1191 | const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| 1192 | ilist<MachineBasicBlock>::iterator It = BB; |
| 1193 | ++It; |
| 1194 | |
| 1195 | // thisMBB: |
| 1196 | // ... |
| 1197 | // TrueVal = ... |
| 1198 | // cmpTY ccX, r1, r2 |
| 1199 | // bCC copy1MBB |
| 1200 | // fallthrough --> copy0MBB |
| 1201 | MachineBasicBlock *thisMBB = BB; |
| 1202 | MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); |
| 1203 | MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); |
| 1204 | BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) |
| 1205 | .addImm(MI->getOperand(3).getImm()); |
| 1206 | MachineFunction *F = BB->getParent(); |
| 1207 | F->getBasicBlockList().insert(It, copy0MBB); |
| 1208 | F->getBasicBlockList().insert(It, sinkMBB); |
| 1209 | // Update machine-CFG edges by first adding all successors of the current |
| 1210 | // block to the new block which will contain the Phi node for the select. |
| 1211 | for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), |
| 1212 | e = BB->succ_end(); i != e; ++i) |
| 1213 | sinkMBB->addSuccessor(*i); |
| 1214 | // Next, remove all successors of the current block, and add the true |
| 1215 | // and fallthrough blocks as its successors. |
| 1216 | while(!BB->succ_empty()) |
| 1217 | BB->removeSuccessor(BB->succ_begin()); |
| 1218 | BB->addSuccessor(copy0MBB); |
| 1219 | BB->addSuccessor(sinkMBB); |
| 1220 | |
| 1221 | // copy0MBB: |
| 1222 | // %FalseValue = ... |
| 1223 | // # fallthrough to sinkMBB |
| 1224 | BB = copy0MBB; |
| 1225 | |
| 1226 | // Update machine-CFG edges |
| 1227 | BB->addSuccessor(sinkMBB); |
| 1228 | |
| 1229 | // sinkMBB: |
| 1230 | // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] |
| 1231 | // ... |
| 1232 | BB = sinkMBB; |
| 1233 | BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) |
| 1234 | .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) |
| 1235 | .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); |
| 1236 | |
| 1237 | delete MI; // The pseudo instruction is gone now. |
| 1238 | return BB; |
| 1239 | } |
| 1240 | } |
| 1241 | } |
| 1242 | |
| 1243 | //===----------------------------------------------------------------------===// |
| 1244 | // ARM Optimization Hooks |
| 1245 | //===----------------------------------------------------------------------===// |
| 1246 | |
| 1247 | /// isLegalAddressImmediate - Return true if the integer value or |
| 1248 | /// GlobalValue can be used as the offset of the target addressing mode. |
| 1249 | bool ARMTargetLowering::isLegalAddressImmediate(int64_t V) const { |
| 1250 | // ARM allows a 12-bit immediate field. |
| 1251 | return V == V & ((1LL << 12) - 1); |
| 1252 | } |
| 1253 | |
| 1254 | bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const { |
| 1255 | return false; |
| 1256 | } |
| 1257 | |
| 1258 | static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, |
| 1259 | bool isSEXTLoad, SDOperand &Base, |
| 1260 | SDOperand &Offset, bool &isInc, |
| 1261 | SelectionDAG &DAG) { |
| 1262 | if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) |
| 1263 | return false; |
| 1264 | |
| 1265 | if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { |
| 1266 | // AddressingMode 3 |
| 1267 | Base = Ptr->getOperand(0); |
| 1268 | if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { |
| 1269 | int RHSC = (int)RHS->getValue(); |
| 1270 | if (RHSC < 0 && RHSC > -256) { |
| 1271 | isInc = false; |
| 1272 | Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); |
| 1273 | return true; |
| 1274 | } |
| 1275 | } |
| 1276 | isInc = (Ptr->getOpcode() == ISD::ADD); |
| 1277 | Offset = Ptr->getOperand(1); |
| 1278 | return true; |
| 1279 | } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { |
| 1280 | // AddressingMode 2 |
| 1281 | if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { |
| 1282 | int RHSC = (int)RHS->getValue(); |
| 1283 | if (RHSC < 0 && RHSC > -0x1000) { |
| 1284 | isInc = false; |
| 1285 | Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); |
| 1286 | Base = Ptr->getOperand(0); |
| 1287 | return true; |
| 1288 | } |
| 1289 | } |
| 1290 | |
| 1291 | if (Ptr->getOpcode() == ISD::ADD) { |
| 1292 | isInc = true; |
| 1293 | ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); |
| 1294 | if (ShOpcVal != ARM_AM::no_shift) { |
| 1295 | Base = Ptr->getOperand(1); |
| 1296 | Offset = Ptr->getOperand(0); |
| 1297 | } else { |
| 1298 | Base = Ptr->getOperand(0); |
| 1299 | Offset = Ptr->getOperand(1); |
| 1300 | } |
| 1301 | return true; |
| 1302 | } |
| 1303 | |
| 1304 | isInc = (Ptr->getOpcode() == ISD::ADD); |
| 1305 | Base = Ptr->getOperand(0); |
| 1306 | Offset = Ptr->getOperand(1); |
| 1307 | return true; |
| 1308 | } |
| 1309 | |
| 1310 | // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. |
| 1311 | return false; |
| 1312 | } |
| 1313 | |
| 1314 | /// getPreIndexedAddressParts - returns true by value, base pointer and |
| 1315 | /// offset pointer and addressing mode by reference if the node's address |
| 1316 | /// can be legally represented as pre-indexed load / store address. |
| 1317 | bool |
| 1318 | ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, |
| 1319 | SDOperand &Offset, |
| 1320 | ISD::MemIndexedMode &AM, |
| 1321 | SelectionDAG &DAG) { |
| 1322 | if (Subtarget->isThumb()) |
| 1323 | return false; |
| 1324 | |
| 1325 | MVT::ValueType VT; |
| 1326 | SDOperand Ptr; |
| 1327 | bool isSEXTLoad = false; |
| 1328 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
| 1329 | Ptr = LD->getBasePtr(); |
| 1330 | VT = LD->getLoadedVT(); |
| 1331 | isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; |
| 1332 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
| 1333 | Ptr = ST->getBasePtr(); |
| 1334 | VT = ST->getStoredVT(); |
| 1335 | } else |
| 1336 | return false; |
| 1337 | |
| 1338 | bool isInc; |
| 1339 | bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, |
| 1340 | isInc, DAG); |
| 1341 | if (isLegal) { |
| 1342 | AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; |
| 1343 | return true; |
| 1344 | } |
| 1345 | return false; |
| 1346 | } |
| 1347 | |
| 1348 | /// getPostIndexedAddressParts - returns true by value, base pointer and |
| 1349 | /// offset pointer and addressing mode by reference if this node can be |
| 1350 | /// combined with a load / store to form a post-indexed load / store. |
| 1351 | bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, |
| 1352 | SDOperand &Base, |
| 1353 | SDOperand &Offset, |
| 1354 | ISD::MemIndexedMode &AM, |
| 1355 | SelectionDAG &DAG) { |
| 1356 | if (Subtarget->isThumb()) |
| 1357 | return false; |
| 1358 | |
| 1359 | MVT::ValueType VT; |
| 1360 | SDOperand Ptr; |
| 1361 | bool isSEXTLoad = false; |
| 1362 | if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { |
| 1363 | VT = LD->getLoadedVT(); |
| 1364 | isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; |
| 1365 | } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { |
| 1366 | VT = ST->getStoredVT(); |
| 1367 | } else |
| 1368 | return false; |
| 1369 | |
| 1370 | bool isInc; |
| 1371 | bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, |
| 1372 | isInc, DAG); |
| 1373 | if (isLegal) { |
| 1374 | AM = isInc ? ISD::POST_INC : ISD::POST_DEC; |
| 1375 | return true; |
| 1376 | } |
| 1377 | return false; |
| 1378 | } |
| 1379 | |
| 1380 | void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, |
| 1381 | uint64_t Mask, |
| 1382 | uint64_t &KnownZero, |
| 1383 | uint64_t &KnownOne, |
| 1384 | unsigned Depth) const { |
| 1385 | KnownZero = 0; |
| 1386 | KnownOne = 0; |
| 1387 | switch (Op.getOpcode()) { |
| 1388 | default: break; |
| 1389 | case ARMISD::CMOV: { |
| 1390 | // Bits are known zero/one if known on the LHS and RHS. |
| 1391 | ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); |
| 1392 | if (KnownZero == 0 && KnownOne == 0) return; |
| 1393 | |
| 1394 | uint64_t KnownZeroRHS, KnownOneRHS; |
| 1395 | ComputeMaskedBits(Op.getOperand(1), Mask, |
| 1396 | KnownZeroRHS, KnownOneRHS, Depth+1); |
| 1397 | KnownZero &= KnownZeroRHS; |
| 1398 | KnownOne &= KnownOneRHS; |
| 1399 | return; |
| 1400 | } |
| 1401 | } |
| 1402 | } |
| 1403 | |
| 1404 | //===----------------------------------------------------------------------===// |
| 1405 | // ARM Inline Assembly Support |
| 1406 | //===----------------------------------------------------------------------===// |
| 1407 | |
| 1408 | /// getConstraintType - Given a constraint letter, return the type of |
| 1409 | /// constraint it is for this target. |
| 1410 | ARMTargetLowering::ConstraintType |
| 1411 | ARMTargetLowering::getConstraintType(char ConstraintLetter) const { |
| 1412 | switch (ConstraintLetter) { |
| 1413 | case 'l': |
| 1414 | return C_RegisterClass; |
| 1415 | default: return TargetLowering::getConstraintType(ConstraintLetter); |
| 1416 | } |
| 1417 | } |
| 1418 | |
| 1419 | std::pair<unsigned, const TargetRegisterClass*> |
| 1420 | ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, |
| 1421 | MVT::ValueType VT) const { |
| 1422 | if (Constraint.size() == 1) { |
| 1423 | // GCC RS6000 Constraint Letters |
| 1424 | switch (Constraint[0]) { |
| 1425 | case 'l': |
| 1426 | // FIXME: in thumb mode, 'l' is only low-regs. |
| 1427 | // FALL THROUGH. |
| 1428 | case 'r': |
| 1429 | return std::make_pair(0U, ARM::GPRRegisterClass); |
| 1430 | break; |
| 1431 | } |
| 1432 | } |
| 1433 | return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); |
| 1434 | } |
| 1435 | |
| 1436 | std::vector<unsigned> ARMTargetLowering:: |
| 1437 | getRegClassForInlineAsmConstraint(const std::string &Constraint, |
| 1438 | MVT::ValueType VT) const { |
| 1439 | if (Constraint.size() != 1) |
| 1440 | return std::vector<unsigned>(); |
| 1441 | |
| 1442 | switch (Constraint[0]) { // GCC ARM Constraint Letters |
| 1443 | default: break; |
| 1444 | case 'l': |
| 1445 | case 'r': |
| 1446 | return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, |
| 1447 | ARM::R4, ARM::R5, ARM::R6, ARM::R7, |
| 1448 | ARM::R8, ARM::R9, ARM::R10, ARM::R11, |
| 1449 | ARM::R12, ARM::LR, 0); |
| 1450 | } |
| 1451 | |
| 1452 | return std::vector<unsigned>(); |
| 1453 | } |