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Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +00001/* Title: PhyRegAlloc.h
2 Author: Ruchira Sasanka
3 Date: Aug 20, 01
4 Purpose: This is the main entry point for register allocation.
5
6 Notes:
7
8 * RegisterClasses: Each RegClass accepts a
9 MachineRegClass which contains machine specific info about that register
10 class. The code in the RegClass is machine independent and they use
11 access functions in the MachineRegClass object passed into it to get
12 machine specific info.
13
14 * Machine dependent work: All parts of the register coloring algorithm
15 except coloring of an individual node are machine independent.
16
17 Register allocation must be done as:
18
19 static const MachineRegInfo MRI = MachineRegInfo(); // machine reg info
20
21 MethodLiveVarInfo LVI(*MethodI ); // compute LV info
22 LVI.analyze();
23
24 PhyRegAlloc PRA(*MethodI, &MRI, &LVI); // allocate regs
25 PRA.allocateRegisters();
26
27 Assumptions:
28 All values in a live range will be of the same physical reg class.
29
30*/
31
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000032#ifndef PHY_REG_ALLOC_H
33#define PHY_REG_ALLOC_H
34
35#include "llvm/CodeGen/MachineInstr.h"
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000036#include "llvm/CodeGen/RegClass.h"
37#include "llvm/CodeGen/LiveRangeInfo.h"
38#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
39
Ruchira Sasanka21721b62001-10-15 16:22:44 +000040#include <deque>
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000041
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000042
43//----------------------------------------------------------------------------
44// Class AddedInstrns:
45// When register allocator inserts new instructions in to the existing
46// instruction stream, it does NOT directly modify the instruction stream.
47// Rather, it creates an object of AddedInstrns and stick it in the
48// AddedInstrMap for an existing instruction. This class contains two vectors
49// to store such instructions added before and after an existing instruction.
50//----------------------------------------------------------------------------
51
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000052class AddedInstrns
53{
54 public:
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000055 deque<MachineInstr *> InstrnsBefore; // Added insts BEFORE an existing inst
56 deque<MachineInstr *> InstrnsAfter; // Added insts AFTER an existing inst
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000057
58 AddedInstrns() : InstrnsBefore(), InstrnsAfter() { }
59};
60
61typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
62
63
64
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000065//----------------------------------------------------------------------------
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000066// class PhyRegAlloc:
67// Main class the register allocator. Call allocateRegisters() to allocate
68// registers for a Method.
69//----------------------------------------------------------------------------
70
71
Vikram S. Adve12af1642001-11-08 04:48:50 +000072class PhyRegAlloc: public NonCopyable
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000073{
74
75 vector<RegClass *> RegClassList ; // vector of register classes
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000076 const TargetMachine &TM; // target machine
Vikram S. Adve12af1642001-11-08 04:48:50 +000077 const Method* Meth; // name of the method we work on
78 MachineCodeForMethod& mcInfo; // descriptor for method's native code
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000079 MethodLiveVarInfo *const LVI; // LV information for this method
80 // (already computed for BBs)
81 LiveRangeInfo LRI; // LR info (will be computed)
82 const MachineRegInfo &MRI; // Machine Register information
83 const unsigned NumOfRegClasses; // recorded here for efficiency
84
Ruchira Sasankaab304c42001-09-30 23:19:57 +000085 //vector<const Instruction *> CallInstrList; // a list of all call instrs
86 //vector<const Instruction *> RetInstrList; // a list of all return instrs
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000087
Ruchira Sasanka51bc0e72001-11-03 17:14:44 +000088
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000089 AddedInstrMapType AddedInstrMap; // to store instrns added in this phase
90
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +000091 //vector<const MachineInstr *> PhiInstList; // a list of all phi instrs
Ruchira Sasanka51bc0e72001-11-03 17:14:44 +000092
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000093 //------- private methods ---------------------------------------------------
94
95 void addInterference(const Value *const Def, const LiveVarSet *const LVSet,
96 const bool isCallInst);
97
98 void addInterferencesForArgs();
99 void createIGNodeListsAndIGs();
100 void buildInterferenceGraphs();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000101 //void insertCallerSavingCode(const MachineInstr *MInst,
102 // const BasicBlock *BB );
Ruchira Sasankac4d4b762001-10-16 01:23:19 +0000103
Ruchira Sasanka36f77072001-10-19 17:21:59 +0000104 void setCallInterferences(const MachineInstr *MInst,
105 const LiveVarSet *const LVSetAft );
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000106
Ruchira Sasankaf7434f02001-10-23 21:38:42 +0000107 void move2DelayedInstr(const MachineInstr *OrigMI,
108 const MachineInstr *DelayedMI );
109
Ruchira Sasanka44d2b942001-10-19 21:42:06 +0000110 void markUnusableSugColors();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000111 void allocateStackSpace4SpilledLRs();
112
Ruchira Sasanka44d2b942001-10-19 21:42:06 +0000113
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000114 inline void constructLiveRanges()
115 { LRI.constructLiveRanges(); }
116
117 void colorIncomingArgs();
Ruchira Sasankaab304c42001-09-30 23:19:57 +0000118 void colorCallRetArgs();
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000119 void updateMachineCode();
Ruchira Sasankaab304c42001-09-30 23:19:57 +0000120
Ruchira Sasanka6053b932001-09-15 19:08:41 +0000121 void printLabel(const Value *const Val);
122 void printMachineCode();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000123
124 friend class UltraSparcRegInfo;
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000125
126
127 int getUsableRegAtMI(RegClass *RC, const int RegType, const MachineInstr *MInst,
128 const LiveVarSet *LVSetBef, MachineInstr *MIBef,
129 MachineInstr *MIAft );
130
131 int getUnusedRegAtMI(RegClass *RC, const MachineInstr *MInst,
132 const LiveVarSet *LVSetBef);
133
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000134 void setRegsUsedByThisInst(RegClass *RC, const MachineInstr *MInst );
135 int getRegNotUsedByThisInst(RegClass *RC, const MachineInstr *MInst);
136
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000137
138
Ruchira Sasanka51bc0e72001-11-03 17:14:44 +0000139 void PhyRegAlloc::insertPhiEleminateInstrns();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000140
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000141 public:
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000142
Vikram S. Adve12af1642001-11-08 04:48:50 +0000143 PhyRegAlloc(Method *const M, const TargetMachine& TM,
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000144 MethodLiveVarInfo *const Lvi);
145
146 void allocateRegisters(); // main method called for allocatin
147
148};
149
150
151
Ruchira Sasanka51bc0e72001-11-03 17:14:44 +0000152/*
153
154
155What to do:
156
157 * Insert IntCCReg checking code to insertCallerSaving
158 * add methods like cpCCReg2Mem & cpMem2CCReg (these will accept an array
159 and push back or push_front the instr according to PUSH_BACK, PUSH_FRONT
160 flags
161
162*/
163
164
165
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000166
167
168
169
170
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000171
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173
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000174#endif
175