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Juergen Ributzka5a364c52013-11-15 22:34:48 +00001//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=//
Tony Linthicumb4b54152011-12-12 21:14:40 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef HexagonMACHINEFUNCTIONINFO_H
11#define HexagonMACHINEFUNCTIONINFO_H
12
Juergen Ributzka5a364c52013-11-15 22:34:48 +000013#include <map>
Tony Linthicumb4b54152011-12-12 21:14:40 +000014#include "llvm/CodeGen/MachineFunction.h"
15
16namespace llvm {
17
18 namespace Hexagon {
19 const unsigned int StartPacket = 0x1;
20 const unsigned int EndPacket = 0x2;
21 }
22
23
24/// Hexagon target-specific information for each MachineFunction.
25class HexagonMachineFunctionInfo : public MachineFunctionInfo {
26 // SRetReturnReg - Some subtargets require that sret lowering includes
27 // returning the value of the returned struct in a register. This field
28 // holds the virtual register into which the sret argument is passed.
29 unsigned SRetReturnReg;
30 std::vector<MachineInstr*> AllocaAdjustInsts;
31 int VarArgsFrameIndex;
32 bool HasClobberLR;
Jyotsna Verma6ea706e2013-05-01 21:37:34 +000033 bool HasEHReturn;
Tony Linthicumb4b54152011-12-12 21:14:40 +000034
35 std::map<const MachineInstr*, unsigned> PacketInfo;
36
Juergen Ributzka5a364c52013-11-15 22:34:48 +000037 virtual void anchor();
Tony Linthicumb4b54152011-12-12 21:14:40 +000038
39public:
Jyotsna Verma6ea706e2013-05-01 21:37:34 +000040 HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0),
41 HasEHReturn(false) {}
Tony Linthicumb4b54152011-12-12 21:14:40 +000042
43 HexagonMachineFunctionInfo(MachineFunction &MF) : SRetReturnReg(0),
Jyotsna Verma6ea706e2013-05-01 21:37:34 +000044 HasClobberLR(0),
45 HasEHReturn(false) {}
Tony Linthicumb4b54152011-12-12 21:14:40 +000046
47 unsigned getSRetReturnReg() const { return SRetReturnReg; }
48 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
49
50 void addAllocaAdjustInst(MachineInstr* MI) {
51 AllocaAdjustInsts.push_back(MI);
52 }
53 const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
54 return AllocaAdjustInsts;
55 }
56
57 void setVarArgsFrameIndex(int v) { VarArgsFrameIndex = v; }
58 int getVarArgsFrameIndex() { return VarArgsFrameIndex; }
59
60 void setStartPacket(MachineInstr* MI) {
61 PacketInfo[MI] |= Hexagon::StartPacket;
62 }
63 void setEndPacket(MachineInstr* MI) {
64 PacketInfo[MI] |= Hexagon::EndPacket;
65 }
66 bool isStartPacket(const MachineInstr* MI) const {
67 return (PacketInfo.count(MI) &&
68 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
69 }
70 bool isEndPacket(const MachineInstr* MI) const {
71 return (PacketInfo.count(MI) &&
72 (PacketInfo.find(MI)->second & Hexagon::EndPacket));
73 }
74 void setHasClobberLR(bool v) { HasClobberLR = v; }
75 bool hasClobberLR() const { return HasClobberLR; }
76
Jyotsna Verma6ea706e2013-05-01 21:37:34 +000077 bool hasEHReturn() const { return HasEHReturn; };
78 void setHasEHReturn(bool H = true) { HasEHReturn = H; };
Tony Linthicumb4b54152011-12-12 21:14:40 +000079};
80} // End llvm namespace
81
82#endif