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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / b31b099a3722ad5b5d94ffe862ee92df51565b51 / . / lib / Target / PowerPC / PPC.td
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Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]1//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
2//
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liu31d157a2012-02-18 12:03:15 +0000[diff] [blame]7//
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
Evan Cheng027fdbe2008-11-24 07:34:46 +0000[diff] [blame]16include "llvm/Target/Target.td"
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]17
18//===----------------------------------------------------------------------===//
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]19// PowerPC Subtarget features.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]20//
21
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]22//===----------------------------------------------------------------------===//
23// CPU Directives //
24//===----------------------------------------------------------------------===//
25
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame]26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
Hal Finkel4d989ac2012-04-01 19:22:40 +0000[diff] [blame]37def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
Hal Finkel621b77a2012-08-28 16:12:39 +0000[diff] [blame]38def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
39 "PPC::DIR_E500mc", "">;
40def DirectiveE5500 : SubtargetFeature<"", "DarwinDirective",
41 "PPC::DIR_E5500", "">;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]42def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
43def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
44def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
45def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
Hal Finkel622382f2012-06-11 15:43:08 +0000[diff] [blame]46def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]47def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
Hal Finkel622382f2012-06-11 15:43:08 +0000[diff] [blame]48def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]49
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]50def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]51 "Enable 64-bit instructions">;
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]52def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
53 "Enable 64-bit registers usage for ppc32 [beta]">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]54def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]55 "Enable Altivec instructions">;
Hal Finkelbd5cafd2012-06-11 19:57:01 +0000[diff] [blame]56def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
57 "Enable the MFOCRF instruction">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]58def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]59 "Enable the fsqrt instruction">;
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]60def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
61 "Enable the fre instruction">;
62def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
63 "Enable the fres instruction">;
64def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
65 "Enable the frsqrte instruction">;
66def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
67 "Enable the frsqrtes instruction">;
68def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
69 "Assume higher precision reciprocal estimates">;
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]70def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]71 "Enable the stfiwx instruction">;
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]72def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
73 "Enable the lfiwax instruction">;
Hal Finkelf5d5c432013-03-29 08:57:48 +0000[diff] [blame]74def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
75 "Enable the fri[mnpz] instructions">;
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]76def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
77 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
Hal Finkel009f7af2012-06-22 23:10:08 +0000[diff] [blame]78def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
79 "Enable the isel instruction">;
Hal Finkelc53ab4d2013-03-28 13:29:47 +0000[diff] [blame]80def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
81 "Enable the popcnt[dw] instructions">;
Hal Finkelefdd4672013-03-28 19:25:55 +0000[diff] [blame]82def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
83 "Enable the ldbrx instruction">;
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame]84def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
85 "Enable Book E instructions">;
Hal Finkel5bb16fd2013-01-30 21:17:42 +0000[diff] [blame]86def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
87 "Enable QPX instructions">;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]88
Bill Schmidtdbc86b92013-02-01 23:10:09 +0000[diff] [blame]89// Note: Future features to add when support is extended to more
90// recent ISA levels:
91//
92// CMPB p6, p6x, p7 cmpb
93// DFP p6, p6x, p7 decimal floating-point instructions
Bill Schmidtdbc86b92013-02-01 23:10:09 +0000[diff] [blame]94// POPCNTB p5 through p7 popcntb and related instructions
Bill Schmidtdbc86b92013-02-01 23:10:09 +0000[diff] [blame]95// VSX p7 vector-scalar instruction set
96
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]97//===----------------------------------------------------------------------===//
Chris Lattnerc8d28892005-10-23 22:08:13 +0000[diff] [blame]98// Register File Description
99//===----------------------------------------------------------------------===//
100
101include "PPCRegisterInfo.td"
102include "PPCSchedule.td"
103include "PPCInstrInfo.td"
104
105//===----------------------------------------------------------------------===//
106// PowerPC processors supported.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]107//
108
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]109def : Processor<"generic", G3Itineraries, [Directive32]>;
Hal Finkel009f7af2012-06-22 23:10:08 +0000[diff] [blame]110def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]111 FeatureFRES, FeatureFRSQRTE,
Hal Finkel009f7af2012-06-22 23:10:08 +0000[diff] [blame]112 FeatureBookE]>;
113def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]114 FeatureFRES, FeatureFRSQRTE,
Hal Finkel009f7af2012-06-22 23:10:08 +0000[diff] [blame]115 FeatureBookE]>;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]116def : Processor<"601", G3Itineraries, [Directive601]>;
117def : Processor<"602", G3Itineraries, [Directive602]>;
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]118def : Processor<"603", G3Itineraries, [Directive603,
119 FeatureFRES, FeatureFRSQRTE]>;
120def : Processor<"603e", G3Itineraries, [Directive603,
121 FeatureFRES, FeatureFRSQRTE]>;
122def : Processor<"603ev", G3Itineraries, [Directive603,
123 FeatureFRES, FeatureFRSQRTE]>;
124def : Processor<"604", G3Itineraries, [Directive604,
125 FeatureFRES, FeatureFRSQRTE]>;
126def : Processor<"604e", G3Itineraries, [Directive604,
127 FeatureFRES, FeatureFRSQRTE]>;
128def : Processor<"620", G3Itineraries, [Directive620,
129 FeatureFRES, FeatureFRSQRTE]>;
130def : Processor<"750", G4Itineraries, [Directive750,
131 FeatureFRES, FeatureFRSQRTE]>;
132def : Processor<"g3", G3Itineraries, [Directive750,
133 FeatureFRES, FeatureFRSQRTE]>;
134def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
135 FeatureFRES, FeatureFRSQRTE]>;
136def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
137 FeatureFRES, FeatureFRSQRTE]>;
138def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
139 FeatureFRES, FeatureFRSQRTE]>;
140def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
141 FeatureFRES, FeatureFRSQRTE]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]142def : Processor<"970", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]143 [Directive970, FeatureAltivec,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]144 FeatureMFOCRF, FeatureFSqrt,
145 FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]146 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]147def : Processor<"g5", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]148 [Directive970, FeatureAltivec,
Hal Finkelbd5cafd2012-06-11 19:57:01 +0000[diff] [blame]149 FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]150 FeatureFRES, FeatureFRSQRTE,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]151 Feature64Bit /*, Feature64BitRegs */]>;
Hal Finkel621b77a2012-08-28 16:12:39 +0000[diff] [blame]152def : ProcessorModel<"e500mc", PPCE500mcModel,
153 [DirectiveE500mc, FeatureMFOCRF,
154 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
155def : ProcessorModel<"e5500", PPCE5500Model,
156 [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
157 FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
Hal Finkelefdd4672013-03-28 19:25:55 +0000[diff] [blame]158def : Processor<"a2", PPCA2Itineraries,
159 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]160 FeatureFSqrt, FeatureFRE, FeatureFRES,
161 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
162 FeatureSTFIWX, FeatureLFIWAX,
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]163 FeatureFPRND, FeatureFPCVT, FeatureISEL,
164 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
165 /*, Feature64BitRegs */]>;
Hal Finkelefdd4672013-03-28 19:25:55 +0000[diff] [blame]166def : Processor<"a2q", PPCA2Itineraries,
167 [DirectiveA2, FeatureBookE, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]168 FeatureFSqrt, FeatureFRE, FeatureFRES,
169 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
170 FeatureSTFIWX, FeatureLFIWAX,
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]171 FeatureFPRND, FeatureFPCVT, FeatureISEL,
172 FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
173 /*, Feature64BitRegs */, FeatureQPX]>;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]174def : Processor<"pwr3", G5Itineraries,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]175 [DirectivePwr3, FeatureAltivec,
176 FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]177 FeatureSTFIWX, Feature64Bit]>;
178def : Processor<"pwr4", G5Itineraries,
179 [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]180 FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
181 FeatureSTFIWX, Feature64Bit]>;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]182def : Processor<"pwr5", G5Itineraries,
183 [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]184 FeatureFSqrt, FeatureFRE, FeatureFRES,
185 FeatureFRSQRTE, FeatureFRSQRTES,
186 FeatureSTFIWX, Feature64Bit]>;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]187def : Processor<"pwr5x", G5Itineraries,
188 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]189 FeatureFSqrt, FeatureFRE, FeatureFRES,
190 FeatureFRSQRTE, FeatureFRSQRTES,
191 FeatureSTFIWX, FeatureFPRND, Feature64Bit]>;
Hal Finkel622382f2012-06-11 15:43:08 +0000[diff] [blame]192def : Processor<"pwr6", G5Itineraries,
193 [DirectivePwr6, FeatureAltivec,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]194 FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
195 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
196 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
197 FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
Bill Schmidtcdc3b742013-02-01 22:59:51 +0000[diff] [blame]198def : Processor<"pwr6x", G5Itineraries,
199 [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]200 FeatureFSqrt, FeatureFRE, FeatureFRES,
201 FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
202 FeatureSTFIWX, FeatureLFIWAX,
Hal Finkel8049ab12013-03-31 10:12:51 +0000[diff] [blame]203 FeatureFPRND, Feature64Bit]>;
Hal Finkel622382f2012-06-11 15:43:08 +0000[diff] [blame]204def : Processor<"pwr7", G5Itineraries,
205 [DirectivePwr7, FeatureAltivec,
Hal Finkel827307b2013-04-03 04:01:11 +0000[diff] [blame]206 FeatureMFOCRF, FeatureFSqrt, FeatureFRE,
207 FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
208 FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
209 FeatureFPRND, FeatureFPCVT, FeatureISEL,
210 FeaturePOPCNTD, FeatureLDBRX,
Hal Finkel46479192013-04-01 17:52:07 +0000[diff] [blame]211 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]212def : Processor<"ppc", G3Itineraries, [Directive32]>;
213def : Processor<"ppc64", G5Itineraries,
214 [Directive64, FeatureAltivec,
Hal Finkel110e3232013-04-03 14:40:18 +0000[diff] [blame]215 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
216 FeatureFRSQRTE, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]217 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]218
219
Chris Lattnerb9a7bea2007-03-06 00:59:59 +0000[diff] [blame]220//===----------------------------------------------------------------------===//
221// Calling Conventions
222//===----------------------------------------------------------------------===//
223
224include "PPCCallingConv.td"
225
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]226def PPCInstrInfo : InstrInfo {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]227 let isLittleEndianEncoding = 1;
228}
229
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]230def PPCAsmWriter : AsmWriter {
231 string AsmWriterClassName = "InstPrinter";
232 bit isMCAsmWriter = 1;
233}
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]234
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]235def PPC : Target {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]236 // Information about the instructions.
237 let InstructionSet = PPCInstrInfo;
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]238
239 let AssemblyWriters = [PPCAsmWriter];
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]240}