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Tony Linthicumb4b54152011-12-12 21:14:40 +00001//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonMCAsmInfo.h"
14#include "HexagonTargetMachine.h"
15#include "Hexagon.h"
16#include "HexagonISelLowering.h"
17#include "llvm/Module.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/PassManager.h"
20#include "llvm/Support/CommandLine.h"
21#include "llvm/Transforms/IPO/PassManagerBuilder.h"
22#include "llvm/Transforms/Scalar.h"
23#include "llvm/Support/TargetRegistry.h"
24#include <iostream>
25
26#define GET_REGINFO_MC_DESC
27#define GET_REGINFO_TARGET_DESC
28#include "HexagonGenRegisterInfo.inc"
29
30extern "C" void LLVMInitializeHexagonTargetMC() {}
31
32using namespace llvm;
33
34static cl::
35opt<bool> DisableHardwareLoops(
36 "disable-hexagon-hwloops", cl::Hidden,
37 cl::desc("Disable Hardware Loops for Hexagon target"));
38
39/// HexagonTargetMachineModule - Note that this is used on hosts that
40/// cannot link in a library unless there are references into the
41/// library. In particular, it seems that it is not possible to get
42/// things to work on Win32 without this. Though it is unused, do not
43/// remove it.
44extern "C" int HexagonTargetMachineModule;
45int HexagonTargetMachineModule = 0;
46
47extern "C" void LLVMInitializeHexagonTarget() {
48 // Register the target.
49 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
50
51 // Register the target asm info.
52 RegisterMCAsmInfo<HexagonMCAsmInfo> A(TheHexagonTarget);
53}
54
55
56/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
57///
58
59/// Hexagon_TODO: Do I need an aggregate alignment?
60///
61HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
62 StringRef CPU, StringRef FS,
63 TargetOptions Options,
64 Reloc::Model RM,
65 CodeModel::Model CM,
66 CodeGenOpt::Level OL)
67 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
68 DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
69 Subtarget(TT, CPU, FS), TLInfo(*this), InstrInfo(Subtarget),
70 TSInfo(*this),
71 FrameLowering(Subtarget),
72 InstrItins(&Subtarget.getInstrItineraryData()) {
73 setMCUseCFI(false);
74}
75
76// addPassesForOptimizations - Allow the backend (target) to add Target
77// Independent Optimization passes to the Pass Manager.
78bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
79
80 PM.add(createConstantPropagationPass());
81 PM.add(createLoopSimplifyPass());
82 PM.add(createDeadCodeEliminationPass());
83 PM.add(createConstantPropagationPass());
84 PM.add(createLoopUnrollPass());
85 PM.add(createLoopStrengthReducePass(getTargetLowering()));
86 return true;
87}
88
89bool HexagonTargetMachine::addInstSelector(PassManagerBase &PM) {
90 PM.add(createHexagonRemoveExtendOps(*this));
91 PM.add(createHexagonISelDag(*this));
92 return false;
93}
94
95
96bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
97 if (!DisableHardwareLoops) {
98 PM.add(createHexagonHardwareLoops());
99 }
100
101 return false;
102}
103
104bool HexagonTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
105 PM.add(createHexagonCFGOptimizer(*this));
106 return true;
107}
108
109
110bool HexagonTargetMachine::addPreSched2(PassManagerBase &PM) {
111 PM.add(createIfConverterPass());
112 return true;
113}
114
115bool HexagonTargetMachine::addPreEmitPass(PassManagerBase &PM) {
116
117 if (!DisableHardwareLoops) {
118 PM.add(createHexagonFixupHwLoops());
119 }
120
121 // Expand Spill code for predicate registers.
122 PM.add(createHexagonExpandPredSpillCode(*this));
123
124 // Split up TFRcondsets into conditional transfers.
125 PM.add(createHexagonSplitTFRCondSets(*this));
126
127 return false;
128}