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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / b4f4cbd199318901d12737ded05ebebd8cb21336 / . / test / CodeGen / ARM / inlineasm3.ll
blob: 853585d9499a4f072ad28c981e25b87dba7ee5cb [file] [log] [blame]
Eric Christopher5e653c92011-07-01 01:00:07 +0000[diff] [blame]1; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
Evan Chengd831cda2009-12-08 23:06:22 +0000[diff] [blame]2
Bob Wilson5afffae2009-12-18 01:03:29 +0000[diff] [blame]3; Radar 7449043
Evan Chengd831cda2009-12-08 23:06:22 +0000[diff] [blame]4%struct.int32x4_t = type { <4 x i32> }
5
Rafael Espindola1e819662010-06-17 15:18:27 +0000[diff] [blame]6define void @t() nounwind {
Evan Chengd831cda2009-12-08 23:06:22 +0000[diff] [blame]7entry:
8; CHECK: vmov.I64 q15, #0
Jakob Stoklund Olesen775c3e52011-04-19 00:14:43 +0000[diff] [blame]9; CHECK: vmov.32 d30[0],
Bob Wilson7d247052010-10-08 06:15:13 +0000[diff] [blame]10; CHECK: vmov q8, q15
Evan Chengd831cda2009-12-08 23:06:22 +0000[diff] [blame]11 %tmp = alloca %struct.int32x4_t, align 16
12 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
13 ret void
14}
Bob Wilson5afffae2009-12-18 01:03:29 +0000[diff] [blame]15
16; Radar 7457110
17%struct.int32x2_t = type { <4 x i32> }
18
Rafael Espindola1e819662010-06-17 15:18:27 +0000[diff] [blame]19define void @t2() nounwind {
Bob Wilson5afffae2009-12-18 01:03:29 +0000[diff] [blame]20entry:
Bob Wilson7d247052010-10-08 06:15:13 +0000[diff] [blame]21; CHECK: vmov d30, d16
Bob Wilson5afffae2009-12-18 01:03:29 +0000[diff] [blame]22; CHECK: vmov.32 r0, d30[0]
23 %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
24 ret void
25}
Eric Christopher9aaa02a2011-06-01 19:55:10 +0000[diff] [blame]26
27; Radar 9306086
28
29%0 = type { <8 x i8>, <16 x i8>* }
30
31define hidden void @conv4_8_E() nounwind {
32entry:
33%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
34unreachable
35}
Eric Christophercf714d42011-06-03 17:24:37 +0000[diff] [blame]36
37; Radar 9037836 & 9119939
38
39define i32 @t3() nounwind {
40entry:
41tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind
42ret i32 0
43}
Eric Christopherce1ecf52011-06-03 20:44:52 +0000[diff] [blame]44
45; Radar 9037836 & 9119939
46
47@k.2126 = internal unnamed_addr global float 1.000000e+00
48define i32 @t4() nounwind {
49entry:
50call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind
51ret i32 0
52}
Eric Christopherec281c82011-06-03 22:09:12 +0000[diff] [blame]53
54; Radar 9037836 & 9119939
55
56define i32 @t5() nounwind {
57entry:
58call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
59ret i32 0
60}
Eric Christopher89bd71f2011-07-01 00:14:47 +0000[diff] [blame]61
62; Radar 9307836 & 9119939
63
64define float @t6(float %y) nounwind {
65entry:
66; CHECK: t6
67; CHECK: flds s15, s0
68 %0 = tail call float asm "flds s15, $0", "=x"() nounwind
69 ret float %0
70}
Eric Christopherd5dc9ec2011-07-01 00:30:46 +0000[diff] [blame]71
72; Radar 9307836 & 9119939
73
Eric Christopher5e653c92011-07-01 01:00:07 +0000[diff] [blame]74define double @t7(double %y) nounwind {
Eric Christopherd5dc9ec2011-07-01 00:30:46 +0000[diff] [blame]75entry:
76; CHECK: t7
77; CHECK: flds s15, d0
78 %0 = tail call double asm "flds s15, $0", "=x"() nounwind
79 ret double %0
80}
81
82; Radar 9307836 & 9119939
83
Eric Christopher5e653c92011-07-01 01:00:07 +0000[diff] [blame]84define float @t8(float %y) nounwind {
Eric Christopherd5dc9ec2011-07-01 00:30:46 +0000[diff] [blame]85entry:
86; CHECK: t8
87; CHECK: flds s15, s0
88 %0 = tail call float asm "flds s15, $0", "=t"() nounwind
89 ret float %0
90}
Eric Christopher5e653c92011-07-01 01:00:07 +0000[diff] [blame]91
92; Radar 9307836 & 9119939
93
94define i32 @t9(i32 %r0) nounwind {
95entry:
96; CHECK: t9
97; CHECK: movw r0, #27182
98 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
99 ret i32 %0
100}