Blame - lib/Target/PowerPC/PPC.td - fp2-dev/platform/external/llvm

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Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- PPC.td - Describe the PowerPC Target Machine -------- tablegen --===//
				2	//
Chris Lattner	4c7b43b	2005-10-14 23:37:35 +0000	[diff] [blame]	3	// The LLVM Compiler Infrastructure
				4	//
Chris Lattner	4ee451d	2007-12-29 20:36:04 +0000	[diff] [blame]	5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
Jia Liu	31d157a	2012-02-18 12:03:15 +0000	[diff] [blame]	7	//
Chris Lattner	4c7b43b	2005-10-14 23:37:35 +0000	[diff] [blame]	8	//===----------------------------------------------------------------------===//
				9	//
				10	// This is the top level entry point for the PowerPC target.
				11	//
				12	//===----------------------------------------------------------------------===//
				13
				14	// Get the target-independent interfaces which we are implementing.
				15	//
Evan Cheng	027fdbe	2008-11-24 07:34:46 +0000	[diff] [blame]	16	include "llvm/Target/Target.td"
Chris Lattner	4c7b43b	2005-10-14 23:37:35 +0000	[diff] [blame]	17
				18	//===----------------------------------------------------------------------===//
Jim Laskey	5476b9b	2005-10-22 08:04:24 +0000	[diff] [blame]	19	// PowerPC Subtarget features.
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	20	//
				21
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	22	//===----------------------------------------------------------------------===//
				23	// CPU Directives //
				24	//===----------------------------------------------------------------------===//
				25
Hal Finkel	c6d08f1	2011-10-17 04:03:49 +0000	[diff] [blame]	26	def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	27	def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
				28	def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
				29	def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
				30	def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
				31	def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
				32	def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
				33	def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
				34	def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
				35	def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
				36	def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
Hal Finkel	4d989ac	2012-04-01 19:22:40 +0000	[diff] [blame]	37	def DirectiveA2 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	38
Chris Lattner	a7a5854	2006-06-16 17:34:12 +0000	[diff] [blame]	39	def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
Chris Lattner	2e1f823	2005-10-23 05:28:51 +0000	[diff] [blame]	40	"Enable 64-bit instructions">;
Chris Lattner	a7a5854	2006-06-16 17:34:12 +0000	[diff] [blame]	41	def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
				42	"Enable 64-bit registers usage for ppc32 [beta]">;
Evan Cheng	19c9550	2006-01-27 08:09:42 +0000	[diff] [blame]	43	def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner	2e1f823	2005-10-23 05:28:51 +0000	[diff] [blame]	44	"Enable Altivec instructions">;
Evan Cheng	19c9550	2006-01-27 08:09:42 +0000	[diff] [blame]	45	def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Chris Lattner	2e1f823	2005-10-23 05:28:51 +0000	[diff] [blame]	46	"Enable GPUL instructions">;
Evan Cheng	19c9550	2006-01-27 08:09:42 +0000	[diff] [blame]	47	def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Hal Finkel	8ee53e2	2011-10-14 18:54:13 +0000	[diff] [blame]	48	"Enable the fsqrt instruction">;
Chris Lattner	bf751e2	2006-02-28 07:08:22 +0000	[diff] [blame]	49	def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
Hal Finkel	8ee53e2	2011-10-14 18:54:13 +0000	[diff] [blame]	50	"Enable the stfiwx instruction">;
Hal Finkel	c6d08f1	2011-10-17 04:03:49 +0000	[diff] [blame]	51	def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
				52	"Enable Book E instructions">;
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	53
				54	//===----------------------------------------------------------------------===//
Chris Lattner	c8d2889	2005-10-23 22:08:13 +0000	[diff] [blame]	55	// Register File Description
				56	//===----------------------------------------------------------------------===//
				57
				58	include "PPCRegisterInfo.td"
				59	include "PPCSchedule.td"
				60	include "PPCInstrInfo.td"
				61
				62	//===----------------------------------------------------------------------===//
				63	// PowerPC processors supported.
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	64	//
				65
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	66	def : Processor<"generic", G3Itineraries, [Directive32]>;
Hal Finkel	c6d08f1	2011-10-17 04:03:49 +0000	[diff] [blame]	67	def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
				68	def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	69	def : Processor<"601", G3Itineraries, [Directive601]>;
				70	def : Processor<"602", G3Itineraries, [Directive602]>;
				71	def : Processor<"603", G3Itineraries, [Directive603]>;
				72	def : Processor<"603e", G3Itineraries, [Directive603]>;
				73	def : Processor<"603ev", G3Itineraries, [Directive603]>;
				74	def : Processor<"604", G3Itineraries, [Directive604]>;
				75	def : Processor<"604e", G3Itineraries, [Directive604]>;
				76	def : Processor<"620", G3Itineraries, [Directive620]>;
				77	def : Processor<"g3", G3Itineraries, [Directive7400]>;
				78	def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
				79	def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
				80	def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
				81	def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
				82	def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	83	def : Processor<"970", G5Itineraries,
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	84	[Directive970, FeatureAltivec,
				85	FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey	5476b9b	2005-10-22 08:04:24 +0000	[diff] [blame]	86	Feature64Bit /, Feature64BitRegs /]>;
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	87	def : Processor<"g5", G5Itineraries,
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	88	[Directive970, FeatureAltivec,
				89	FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
				90	Feature64Bit /, Feature64BitRegs /]>;
Hal Finkel	4d989ac	2012-04-01 19:22:40 +0000	[diff] [blame]	91	def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
				92	FeatureFSqrt, FeatureSTFIWX,
Hal Finkel	b66e943	2012-04-01 21:20:14 +0000	[diff] [blame^]	93	Feature64Bit
				94	/, Feature64BitRegs /]>;
Jim Laskey	c35010d	2006-12-12 20:57:08 +0000	[diff] [blame]	95	def : Processor<"ppc", G3Itineraries, [Directive32]>;
				96	def : Processor<"ppc64", G5Itineraries,
				97	[Directive64, FeatureAltivec,
				98	FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey	5476b9b	2005-10-22 08:04:24 +0000	[diff] [blame]	99	Feature64Bit /, Feature64BitRegs /]>;
Jim Laskey	5384214	2005-10-19 19:51:16 +0000	[diff] [blame]	100
				101
Chris Lattner	b9a7bea	2007-03-06 00:59:59 +0000	[diff] [blame]	102	//===----------------------------------------------------------------------===//
				103	// Calling Conventions
				104	//===----------------------------------------------------------------------===//
				105
				106	include "PPCCallingConv.td"
				107
Chris Lattner	88d211f	2006-03-12 09:13:49 +0000	[diff] [blame]	108	def PPCInstrInfo : InstrInfo {
Chris Lattner	88d211f	2006-03-12 09:13:49 +0000	[diff] [blame]	109	let isLittleEndianEncoding = 1;
				110	}
				111
Chris Lattner	84a04ad	2010-11-15 03:53:53 +0000	[diff] [blame]	112	def PPCAsmWriter : AsmWriter {
				113	string AsmWriterClassName = "InstPrinter";
				114	bit isMCAsmWriter = 1;
				115	}
Chris Lattner	88d211f	2006-03-12 09:13:49 +0000	[diff] [blame]	116
Chris Lattner	4c7b43b	2005-10-14 23:37:35 +0000	[diff] [blame]	117	def PPC : Target {
Chris Lattner	88d211f	2006-03-12 09:13:49 +0000	[diff] [blame]	118	// Information about the instructions.
				119	let InstructionSet = PPCInstrInfo;
Chris Lattner	84a04ad	2010-11-15 03:53:53 +0000	[diff] [blame]	120
				121	let AssemblyWriters = [PPCAsmWriter];
Chris Lattner	4c7b43b	2005-10-14 23:37:35 +0000	[diff] [blame]	122	}