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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 8154094f225ccb52a058501b84c6fa0a51862ca7 / . / lib / Target / X86 / X86InstrMMX.td
blob: c77446017db49d34eb198fe92dc02d8ae5326844 [file] [log] [blame]
Dan Gohmanf17a25c2007-07-18 16:29:46 +0000[diff] [blame]1//====- X86InstrMMX.td - Describe the X86 Instruction Set --*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MMX instruction set, defining the instructions,
11// and properties of the instructions which are needed for code generation,
12// machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17// Instruction templates
18//===----------------------------------------------------------------------===//
19
20// MMXI - MMX instructions with TB prefix.
21// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
22// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
23// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
24// MMXID - MMX instructions with XD prefix.
25// MMXIS - MMX instructions with XS prefix.
26class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
27 : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
28class MMXRI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
29 : I<o, F, ops, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
30class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
31 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
32class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
33 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
34class MMXID<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
35 : Ii8<o, F, ops, asm, pattern>, XD, Requires<[HasMMX]>;
36class MMXIS<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
37 : Ii8<o, F, ops, asm, pattern>, XS, Requires<[HasMMX]>;
38
39// Some 'special' instructions
40def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
41 "#IMPLICIT_DEF $dst",
42 [(set VR64:$dst, (v8i8 (undef)))]>,
43 Requires<[HasMMX]>;
44
45// 64-bit vector undef's.
46def : Pat<(v8i8 (undef)), (IMPLICIT_DEF_VR64)>;
47def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>;
48def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>;
49def : Pat<(v1i64 (undef)), (IMPLICIT_DEF_VR64)>;
50
51//===----------------------------------------------------------------------===//
52// MMX Pattern Fragments
53//===----------------------------------------------------------------------===//
54
55def load_mmx : PatFrag<(ops node:$ptr), (v1i64 (load node:$ptr))>;
56
57def bc_v8i8 : PatFrag<(ops node:$in), (v8i8 (bitconvert node:$in))>;
58def bc_v4i16 : PatFrag<(ops node:$in), (v4i16 (bitconvert node:$in))>;
59def bc_v2i32 : PatFrag<(ops node:$in), (v2i32 (bitconvert node:$in))>;
60def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
61
62//===----------------------------------------------------------------------===//
63// MMX Masks
64//===----------------------------------------------------------------------===//
65
66// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
67// PSHUFW imm.
68def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
69 return getI8Imm(X86::getShuffleSHUFImmediate(N));
70}]>;
71
72// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
73def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
74 return X86::isUNPCKHMask(N);
75}]>;
76
77// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
78def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
79 return X86::isUNPCKLMask(N);
80}]>;
81
82// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
83def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
84 return X86::isUNPCKH_v_undef_Mask(N);
85}]>;
86
87// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
88def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
89 return X86::isUNPCKL_v_undef_Mask(N);
90}]>;
91
92// Patterns for shuffling.
93def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
94 return X86::isPSHUFDMask(N);
95}], MMX_SHUFFLE_get_shuf_imm>;
96
97// Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
98def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
99 return X86::isMOVLMask(N);
100}]>;
101
102//===----------------------------------------------------------------------===//
103// MMX Multiclasses
104//===----------------------------------------------------------------------===//
105
106let isTwoAddress = 1 in {
107 // MMXI_binop_rm - Simple MMX binary operator.
108 multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
109 ValueType OpVT, bit Commutable = 0> {
110 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
111 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
112 [(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
113 let isCommutable = Commutable;
114 }
115 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
116 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
117 [(set VR64:$dst, (OpVT (OpNode VR64:$src1,
118 (bitconvert
119 (load_mmx addr:$src2)))))]>;
120 }
121
122 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
123 bit Commutable = 0> {
124 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
125 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
126 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
127 let isCommutable = Commutable;
128 }
129 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
130 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
131 [(set VR64:$dst, (IntId VR64:$src1,
132 (bitconvert (load_mmx addr:$src2))))]>;
133 }
134
135 // MMXI_binop_rm_v1i64 - Simple MMX binary operator whose type is v1i64.
136 //
137 // FIXME: we could eliminate this and use MMXI_binop_rm instead if tblgen knew
138 // to collapse (bitconvert VT to VT) into its operand.
139 //
140 multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
141 bit Commutable = 0> {
142 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
143 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
144 [(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
145 let isCommutable = Commutable;
146 }
147 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
148 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
149 [(set VR64:$dst,
150 (OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
151 }
152
153 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
154 string OpcodeStr, Intrinsic IntId> {
155 def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
156 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
157 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
158 def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
159 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
160 [(set VR64:$dst, (IntId VR64:$src1,
161 (bitconvert (load_mmx addr:$src2))))]>;
162 def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
163 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
164 [(set VR64:$dst, (IntId VR64:$src1,
165 (scalar_to_vector (i32 imm:$src2))))]>;
166 }
167}
168
169//===----------------------------------------------------------------------===//
170// MMX EMMS & FEMMS Instructions
171//===----------------------------------------------------------------------===//
172
173def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
174def MMX_FEMMS : MMXI<0x0E, RawFrm, (ops), "femms", [(int_x86_mmx_femms)]>;
175
176//===----------------------------------------------------------------------===//
177// MMX Scalar Instructions
178//===----------------------------------------------------------------------===//
179
180// Data Transfer Instructions
181def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
182 "movd {$src, $dst|$dst, $src}", []>;
183def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
184 "movd {$src, $dst|$dst, $src}", []>;
185def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
186 "movd {$src, $dst|$dst, $src}", []>;
187
188def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src),
189 "movd {$src, $dst|$dst, $src}", []>;
190
191def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
192 "movq {$src, $dst|$dst, $src}", []>;
193def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
194 "movq {$src, $dst|$dst, $src}",
195 [(set VR64:$dst, (load_mmx addr:$src))]>;
196def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
197 "movq {$src, $dst|$dst, $src}",
198 [(store (v1i64 VR64:$src), addr:$dst)]>;
199
200def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
201 "movdq2q {$src, $dst|$dst, $src}",
202 [(set VR64:$dst,
203 (v1i64 (vector_extract (v2i64 VR128:$src),
204 (iPTR 0))))]>;
205
206def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
207 "movq2dq {$src, $dst|$dst, $src}",
208 [(set VR128:$dst,
209 (bitconvert (v1i64 VR64:$src)))]>;
210
211def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
212 "movntq {$src, $dst|$dst, $src}",
213 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
214
215let AddedComplexity = 15 in
216// movd to MMX register zero-extends
217def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
218 "movd {$src, $dst|$dst, $src}",
219 [(set VR64:$dst,
220 (v2i32 (vector_shuffle immAllZerosV,
221 (v2i32 (scalar_to_vector GR32:$src)),
222 MMX_MOVL_shuffle_mask)))]>;
223let AddedComplexity = 20 in
224def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
225 "movd {$src, $dst|$dst, $src}",
226 [(set VR64:$dst,
227 (v2i32 (vector_shuffle immAllZerosV,
228 (v2i32 (scalar_to_vector
229 (loadi32 addr:$src))),
230 MMX_MOVL_shuffle_mask)))]>;
231
232// Arithmetic Instructions
233
234// -- Addition
235defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>;
236defm MMX_PADDW : MMXI_binop_rm<0xFD, "paddw", add, v4i16, 1>;
237defm MMX_PADDD : MMXI_binop_rm<0xFE, "paddd", add, v2i32, 1>;
238defm MMX_PADDQ : MMXI_binop_rm<0xD4, "paddq", add, v1i64, 1>;
239
240defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 1>;
241defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
242
243defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
244defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
245
246// -- Subtraction
247defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
248defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
249defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
250defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
251
252defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
253defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
254
255defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
256defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
257
258// -- Multiplication
259defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>;
260
261defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
262defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
263defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
264
265// -- Miscellanea
266defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
267
268defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
269defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
270
271defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 1>;
272defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 1>;
273
274defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 1>;
275defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
276
277defm MMX_PSADBW : MMXI_binop_rm_int<0xE0, "psadbw", int_x86_mmx_psad_bw, 1>;
278
279// Logical Instructions
280defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>;
281defm MMX_POR : MMXI_binop_rm_v1i64<0xEB, "por" , or, 1>;
282defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
283
284let isTwoAddress = 1 in {
285 def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
286 (ops VR64:$dst, VR64:$src1, VR64:$src2),
287 "pandn {$src2, $dst|$dst, $src2}",
288 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
289 VR64:$src2)))]>;
290 def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
291 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
292 "pandn {$src2, $dst|$dst, $src2}",
293 [(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
294 (load addr:$src2))))]>;
295}
296
297// Shift Instructions
298defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
299 int_x86_mmx_psrl_w>;
300defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
301 int_x86_mmx_psrl_d>;
302defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
303 int_x86_mmx_psrl_q>;
304
305defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
306 int_x86_mmx_psll_w>;
307defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
308 int_x86_mmx_psll_d>;
309defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
310 int_x86_mmx_psll_q>;
311
312defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
313 int_x86_mmx_psra_w>;
314defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
315 int_x86_mmx_psra_d>;
316
317// Comparison Instructions
318defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b>;
319defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w>;
320defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d>;
321
322defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b>;
323defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w>;
324defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
325
326// Conversion Instructions
327
328// -- Unpack Instructions
329let isTwoAddress = 1 in {
330 // Unpack High Packed Data Instructions
331 def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
332 (ops VR64:$dst, VR64:$src1, VR64:$src2),
333 "punpckhbw {$src2, $dst|$dst, $src2}",
334 [(set VR64:$dst,
335 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
336 MMX_UNPCKH_shuffle_mask)))]>;
337 def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
338 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
339 "punpckhbw {$src2, $dst|$dst, $src2}",
340 [(set VR64:$dst,
341 (v8i8 (vector_shuffle VR64:$src1,
342 (bc_v8i8 (load_mmx addr:$src2)),
343 MMX_UNPCKH_shuffle_mask)))]>;
344
345 def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
346 (ops VR64:$dst, VR64:$src1, VR64:$src2),
347 "punpckhwd {$src2, $dst|$dst, $src2}",
348 [(set VR64:$dst,
349 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
350 MMX_UNPCKH_shuffle_mask)))]>;
351 def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
352 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
353 "punpckhwd {$src2, $dst|$dst, $src2}",
354 [(set VR64:$dst,
355 (v4i16 (vector_shuffle VR64:$src1,
356 (bc_v4i16 (load_mmx addr:$src2)),
357 MMX_UNPCKH_shuffle_mask)))]>;
358
359 def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
360 (ops VR64:$dst, VR64:$src1, VR64:$src2),
361 "punpckhdq {$src2, $dst|$dst, $src2}",
362 [(set VR64:$dst,
363 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
364 MMX_UNPCKH_shuffle_mask)))]>;
365 def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
366 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
367 "punpckhdq {$src2, $dst|$dst, $src2}",
368 [(set VR64:$dst,
369 (v2i32 (vector_shuffle VR64:$src1,
370 (bc_v2i32 (load_mmx addr:$src2)),
371 MMX_UNPCKH_shuffle_mask)))]>;
372
373 // Unpack Low Packed Data Instructions
374 def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
375 (ops VR64:$dst, VR64:$src1, VR64:$src2),
376 "punpcklbw {$src2, $dst|$dst, $src2}",
377 [(set VR64:$dst,
378 (v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
379 MMX_UNPCKL_shuffle_mask)))]>;
380 def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
381 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
382 "punpcklbw {$src2, $dst|$dst, $src2}",
383 [(set VR64:$dst,
384 (v8i8 (vector_shuffle VR64:$src1,
385 (bc_v8i8 (load_mmx addr:$src2)),
386 MMX_UNPCKL_shuffle_mask)))]>;
387
388 def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
389 (ops VR64:$dst, VR64:$src1, VR64:$src2),
390 "punpcklwd {$src2, $dst|$dst, $src2}",
391 [(set VR64:$dst,
392 (v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
393 MMX_UNPCKL_shuffle_mask)))]>;
394 def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
395 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
396 "punpcklwd {$src2, $dst|$dst, $src2}",
397 [(set VR64:$dst,
398 (v4i16 (vector_shuffle VR64:$src1,
399 (bc_v4i16 (load_mmx addr:$src2)),
400 MMX_UNPCKL_shuffle_mask)))]>;
401
402 def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
403 (ops VR64:$dst, VR64:$src1, VR64:$src2),
404 "punpckldq {$src2, $dst|$dst, $src2}",
405 [(set VR64:$dst,
406 (v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
407 MMX_UNPCKL_shuffle_mask)))]>;
408 def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
409 (ops VR64:$dst, VR64:$src1, i64mem:$src2),
410 "punpckldq {$src2, $dst|$dst, $src2}",
411 [(set VR64:$dst,
412 (v2i32 (vector_shuffle VR64:$src1,
413 (bc_v2i32 (load_mmx addr:$src2)),
414 MMX_UNPCKL_shuffle_mask)))]>;
415}
416
417// -- Pack Instructions
418defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
419defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
420defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
421
422// -- Shuffle Instructions
423def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
424 (ops VR64:$dst, VR64:$src1, i8imm:$src2),
425 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
426 [(set VR64:$dst,
427 (v4i16 (vector_shuffle
428 VR64:$src1, (undef),
429 MMX_PSHUFW_shuffle_mask:$src2)))]>;
430def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
431 (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
432 "pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
433 [(set VR64:$dst,
434 (v4i16 (vector_shuffle
435 (bc_v4i16 (load_mmx addr:$src1)),
436 (undef),
437 MMX_PSHUFW_shuffle_mask:$src2)))]>;
438
439// -- Conversion Instructions
440def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
441 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
442def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
443 "cvtpd2pi {$src, $dst|$dst, $src}", []>;
444
445def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
446 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
447def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
448 "cvtpi2pd {$src, $dst|$dst, $src}", []>;
449
450def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
451 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
452def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
453 "cvtpi2ps {$src, $dst|$dst, $src}", []>;
454
455def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
456 "cvtps2pi {$src, $dst|$dst, $src}", []>;
457def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
458 "cvtps2pi {$src, $dst|$dst, $src}", []>;
459
460def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
461 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
462def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
463 "cvttpd2pi {$src, $dst|$dst, $src}", []>;
464
465def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
466 "cvttps2pi {$src, $dst|$dst, $src}", []>;
467def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
468 "cvttps2pi {$src, $dst|$dst, $src}", []>;
469
470// Extract / Insert
471def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
472def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
473
474def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
475 (ops GR32:$dst, VR64:$src1, i16i8imm:$src2),
476 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
477 [(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
478 (iPTR imm:$src2)))]>;
479let isTwoAddress = 1 in {
480 def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
481 (ops VR64:$dst, VR64:$src1, GR32:$src2, i16i8imm:$src3),
482 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
483 [(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
484 GR32:$src2, (iPTR imm:$src3))))]>;
485 def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
486 (ops VR64:$dst, VR64:$src1, i16mem:$src2, i16i8imm:$src3),
487 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
488 [(set VR64:$dst,
489 (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
490 (i32 (anyext (loadi16 addr:$src2))),
491 (iPTR imm:$src3))))]>;
492}
493
494// Mask creation
495def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (ops GR32:$dst, VR64:$src),
496 "pmovmskb {$src, $dst|$dst, $src}",
497 [(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
498
499// Misc.
500def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
501 "maskmovq {$mask, $src|$src, $mask}",
502 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
503 Imp<[EDI],[]>;
504
505//===----------------------------------------------------------------------===//
506// Alias Instructions
507//===----------------------------------------------------------------------===//
508
509// Alias instructions that map zero vector to pxor.
510// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
511let isReMaterializable = 1 in {
512 def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
513 "pxor $dst, $dst",
514 [(set VR64:$dst, (v1i64 immAllZerosV))]>;
515 def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
516 "pcmpeqd $dst, $dst",
517 [(set VR64:$dst, (v1i64 immAllOnesV))]>;
518}
519
520//===----------------------------------------------------------------------===//
521// Non-Instruction Patterns
522//===----------------------------------------------------------------------===//
523
524// Store 64-bit integer vector values.
525def : Pat<(store (v8i8 VR64:$src), addr:$dst),
526 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
527def : Pat<(store (v4i16 VR64:$src), addr:$dst),
528 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
529def : Pat<(store (v2i32 VR64:$src), addr:$dst),
530 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
531def : Pat<(store (v1i64 VR64:$src), addr:$dst),
532 (MMX_MOVQ64mr addr:$dst, VR64:$src)>;
533
534// 64-bit vector all zero's.
535def : Pat<(v8i8 immAllZerosV), (MMX_V_SET0)>;
536def : Pat<(v4i16 immAllZerosV), (MMX_V_SET0)>;
537def : Pat<(v2i32 immAllZerosV), (MMX_V_SET0)>;
538def : Pat<(v1i64 immAllZerosV), (MMX_V_SET0)>;
539
540// 64-bit vector all one's.
541def : Pat<(v8i8 immAllOnesV), (MMX_V_SETALLONES)>;
542def : Pat<(v4i16 immAllOnesV), (MMX_V_SETALLONES)>;
543def : Pat<(v2i32 immAllOnesV), (MMX_V_SETALLONES)>;
544def : Pat<(v1i64 immAllOnesV), (MMX_V_SETALLONES)>;
545
546// Bit convert.
547def : Pat<(v8i8 (bitconvert (v1i64 VR64:$src))), (v8i8 VR64:$src)>;
548def : Pat<(v8i8 (bitconvert (v2i32 VR64:$src))), (v8i8 VR64:$src)>;
549def : Pat<(v8i8 (bitconvert (v4i16 VR64:$src))), (v8i8 VR64:$src)>;
550def : Pat<(v4i16 (bitconvert (v1i64 VR64:$src))), (v4i16 VR64:$src)>;
551def : Pat<(v4i16 (bitconvert (v2i32 VR64:$src))), (v4i16 VR64:$src)>;
552def : Pat<(v4i16 (bitconvert (v8i8 VR64:$src))), (v4i16 VR64:$src)>;
553def : Pat<(v2i32 (bitconvert (v1i64 VR64:$src))), (v2i32 VR64:$src)>;
554def : Pat<(v2i32 (bitconvert (v4i16 VR64:$src))), (v2i32 VR64:$src)>;
555def : Pat<(v2i32 (bitconvert (v8i8 VR64:$src))), (v2i32 VR64:$src)>;
556def : Pat<(v1i64 (bitconvert (v2i32 VR64:$src))), (v1i64 VR64:$src)>;
557def : Pat<(v1i64 (bitconvert (v4i16 VR64:$src))), (v1i64 VR64:$src)>;
558def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
559
560// 64-bit bit convert.
561def : Pat<(v1i64 (bitconvert (i64 GR64:$src))),
562 (MMX_MOVD64to64rr GR64:$src)>;
563def : Pat<(v2i32 (bitconvert (i64 GR64:$src))),
564 (MMX_MOVD64to64rr GR64:$src)>;
565def : Pat<(v4i16 (bitconvert (i64 GR64:$src))),
566 (MMX_MOVD64to64rr GR64:$src)>;
567def : Pat<(v8i8 (bitconvert (i64 GR64:$src))),
568 (MMX_MOVD64to64rr GR64:$src)>;
569
570def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
571
572// Move scalar to XMM zero-extended
573// movd to XMM register zero-extends
574let AddedComplexity = 15 in {
575 def : Pat<(v8i8 (vector_shuffle immAllZerosV,
576 (v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
577 (MMX_MOVZDI2PDIrr GR32:$src)>;
578 def : Pat<(v4i16 (vector_shuffle immAllZerosV,
579 (v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
580 (MMX_MOVZDI2PDIrr GR32:$src)>;
581 def : Pat<(v2i32 (vector_shuffle immAllZerosV,
582 (v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
583 (MMX_MOVZDI2PDIrr GR32:$src)>;
584}
585
586// Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
587// 8 or 16-bits matter.
588def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
589def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
590def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
591
592// Patterns to perform canonical versions of vector shuffling.
593let AddedComplexity = 10 in {
594 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
595 MMX_UNPCKL_v_undef_shuffle_mask)),
596 (MMX_PUNPCKLBWrr VR64:$src, VR64:$src)>;
597 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
598 MMX_UNPCKL_v_undef_shuffle_mask)),
599 (MMX_PUNPCKLWDrr VR64:$src, VR64:$src)>;
600 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
601 MMX_UNPCKL_v_undef_shuffle_mask)),
602 (MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
603}
604
605let AddedComplexity = 10 in {
606 def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
607 MMX_UNPCKH_v_undef_shuffle_mask)),
608 (MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
609 def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
610 MMX_UNPCKH_v_undef_shuffle_mask)),
611 (MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
612 def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
613 MMX_UNPCKH_v_undef_shuffle_mask)),
614 (MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
615}
616
617// Patterns to perform vector shuffling with a zeroed out vector.
618let AddedComplexity = 20 in {
619 def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
620 (v2i32 (scalar_to_vector (load_mmx addr:$src))),
621 MMX_UNPCKL_shuffle_mask)),
622 (MMX_PUNPCKLDQrm VR64:$src, VR64:$src)>;
623}
624
625// Some special case PANDN patterns.
626// FIXME: Get rid of these.
627def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
628 VR64:$src2)),
629 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
630def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
631 VR64:$src2)),
632 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
633def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
634 VR64:$src2)),
635 (MMX_PANDNrr VR64:$src1, VR64:$src2)>;
636
637def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v2i32 immAllOnesV))),
638 (load addr:$src2))),
639 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
640def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v4i16 immAllOnesV))),
641 (load addr:$src2))),
642 (MMX_PANDNrm VR64:$src1, addr:$src2)>;
643def : Pat<(v1i64 (and (xor VR64:$src1, (bc_v1i64 (v8i8 immAllOnesV))),
644 (load addr:$src2))),
645 (MMX_PANDNrm VR64:$src1, addr:$src2)>;