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Rafael Espindola4d4c0212006-09-19 16:41:40 +00001//===-- ARMMul.cpp - Define TargetMachine for A5CRM -----------------------===//
Rafael Espindola71f3b942006-09-19 15:49:25 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the "Instituto Nokia de Tecnologia" and
6// is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===----------------------------------------------------------------------===//
10//
Rafael Espindolabec2e382006-10-16 16:33:29 +000011// Modify the ARM multiplication instructions so that Rd{Hi,Lo} and Rm are distinct
Rafael Espindola71f3b942006-09-19 15:49:25 +000012//
13//===----------------------------------------------------------------------===//
14
15
16#include "ARM.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineFunctionPass.h"
19#include "llvm/Support/Compiler.h"
20
21using namespace llvm;
22
23namespace {
24 class VISIBILITY_HIDDEN FixMul : public MachineFunctionPass {
25 virtual bool runOnMachineFunction(MachineFunction &MF);
26 };
27}
28
29FunctionPass *llvm::createARMFixMulPass() { return new FixMul(); }
30
31bool FixMul::runOnMachineFunction(MachineFunction &MF) {
32 bool Changed = false;
33
34 for (MachineFunction::iterator BB = MF.begin(), E = MF.end();
35 BB != E; ++BB) {
36 MachineBasicBlock &MBB = *BB;
37
38 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
39 I != E; ++I) {
40 MachineInstr *MI = I;
41
Rafael Espindolabec2e382006-10-16 16:33:29 +000042 int Op = MI->getOpcode();
43 if (Op == ARM::MUL ||
44 Op == ARM::SMULL ||
45 Op == ARM::UMULL) {
Rafael Espindola4d4c0212006-09-19 16:41:40 +000046 MachineOperand &RdOp = MI->getOperand(0);
47 MachineOperand &RmOp = MI->getOperand(1);
48 MachineOperand &RsOp = MI->getOperand(2);
Rafael Espindola71f3b942006-09-19 15:49:25 +000049
Rafael Espindola4d4c0212006-09-19 16:41:40 +000050 unsigned Rd = RdOp.getReg();
51 unsigned Rm = RmOp.getReg();
52 unsigned Rs = RsOp.getReg();
Rafael Espindola71f3b942006-09-19 15:49:25 +000053
Rafael Espindolabec2e382006-10-16 16:33:29 +000054 if (Rd == Rm) {
Rafael Espindola4d4c0212006-09-19 16:41:40 +000055 Changed = true;
56 if (Rd != Rs) {
57 //Rd and Rm must be distinct, but Rd can be equal to Rs.
58 //Swap Rs and Rm
59 RmOp.setReg(Rs);
60 RsOp.setReg(Rm);
61 } else {
Rafael Espindolabec2e382006-10-16 16:33:29 +000062 unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
63 BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
Rafael Espindola4d4c0212006-09-19 16:41:40 +000064 .addImm(ARMShift::LSL);
Rafael Espindolabec2e382006-10-16 16:33:29 +000065 RmOp.setReg(scratch);
Rafael Espindola4d4c0212006-09-19 16:41:40 +000066 }
67 }
Rafael Espindola71f3b942006-09-19 15:49:25 +000068 }
69 }
70 }
71
72 return Changed;
73}