blob: a13c7eea7ea0d2f064a9c56ff6b02a3c9156fc12 [file] [log] [blame]
Jim Grosbach0f448b52010-10-08 00:47:59 +00001;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
2
3
4;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
5; should run on .s source files rather than using llc to generate the
6; assembly.
7
8define i32 @foo(i32 %a, i32 %b) nounwind ssp {
9entry:
10; CHECK: foo
Jim Grosbach42fac8e2010-10-11 23:16:21 +000011; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
12; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
Jim Grosbach0f448b52010-10-08 00:47:59 +000013
14 tail call void @llvm.trap()
15 ret i32 undef
16}
17
Jim Grosbach56ac9072010-10-08 21:45:55 +000018define i32 @f2(i32 %a, i32 %b) nounwind readnone ssp {
19entry:
20; CHECK: f2
Jim Grosbach42fac8e2010-10-11 23:16:21 +000021; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
22; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
Jim Grosbach56ac9072010-10-08 21:45:55 +000023 %add = add nsw i32 %b, %a
24 ret i32 %add
25}
Jim Grosbach42fac8e2010-10-11 23:16:21 +000026
27
28define i32 @f3(i32 %a, i32 %b) nounwind readnone ssp {
29entry:
30; CHECK: f3
31; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
32; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
33 %mul = shl i32 %b, 3
34 %add = add nsw i32 %mul, %a
35 ret i32 %add
36}
37
Jim Grosbach0de6ab32010-10-12 17:11:26 +000038define i32 @f4(i32 %a, i32 %b) nounwind readnone ssp {
39entry:
40; CHECK: f4
Jim Grosbachc14b80f2010-10-12 23:14:03 +000041; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
42; CHECK: @ 4064
Jim Grosbach0de6ab32010-10-12 17:11:26 +000043; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
44 %add = add nsw i32 %a, 4064
45 ret i32 %add
46}
47
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Jim Grosbach0f448b52010-10-08 00:47:59 +000049declare void @llvm.trap() nounwind