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Sean Callanan8ed9f512009-12-19 02:59:52 +00001//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13// X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
Sean Callanan8ed9f512009-12-19 02:59:52 +000017#include "X86RecognizableInstr.h"
Chandler Carruth4ffd89f2012-12-04 10:37:14 +000018#include "X86DisassemblerShared.h"
Sean Callanan8ed9f512009-12-19 02:59:52 +000019#include "X86ModRMFilters.h"
Sean Callanan8ed9f512009-12-19 02:59:52 +000020#include "llvm/Support/ErrorHandling.h"
Sean Callanan8ed9f512009-12-19 02:59:52 +000021#include <string>
22
23using namespace llvm;
24
Sean Callanan9492be82010-02-12 23:39:46 +000025#define MRM_MAPPING \
26 MAP(C1, 33) \
Chris Lattnera599de22010-02-13 00:41:14 +000027 MAP(C2, 34) \
28 MAP(C3, 35) \
29 MAP(C4, 36) \
30 MAP(C8, 37) \
31 MAP(C9, 38) \
Michael Liao02d2e612013-04-11 04:52:28 +000032 MAP(CA, 39) \
33 MAP(CB, 40) \
34 MAP(E8, 41) \
35 MAP(F0, 42) \
36 MAP(F8, 45) \
37 MAP(F9, 46) \
38 MAP(D0, 47) \
39 MAP(D1, 48) \
40 MAP(D4, 49) \
41 MAP(D5, 50) \
42 MAP(D6, 51) \
43 MAP(D8, 52) \
44 MAP(D9, 53) \
45 MAP(DA, 54) \
46 MAP(DB, 55) \
47 MAP(DC, 56) \
48 MAP(DD, 57) \
49 MAP(DE, 58) \
50 MAP(DF, 59)
Sean Callanan9492be82010-02-12 23:39:46 +000051
Sean Callanan8ed9f512009-12-19 02:59:52 +000052// A clone of X86 since we can't depend on something that is generated.
53namespace X86Local {
54 enum {
55 Pseudo = 0,
56 RawFrm = 1,
57 AddRegFrm = 2,
58 MRMDestReg = 3,
59 MRMDestMem = 4,
60 MRMSrcReg = 5,
61 MRMSrcMem = 6,
Craig Toppere6c97ff2012-07-30 04:48:12 +000062 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
Sean Callanan8ed9f512009-12-19 02:59:52 +000063 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
Sean Callanan9492be82010-02-12 23:39:46 +000066 MRMInitReg = 32,
Richard Trieu76f63ae2012-07-18 23:04:22 +000067 RawFrmImm8 = 43,
68 RawFrmImm16 = 44,
Sean Callanan9492be82010-02-12 23:39:46 +000069#define MAP(from, to) MRM_##from = to,
70 MRM_MAPPING
71#undef MAP
72 lastMRM
Sean Callanan8ed9f512009-12-19 02:59:52 +000073 };
Craig Toppere6c97ff2012-07-30 04:48:12 +000074
Sean Callanan8ed9f512009-12-19 02:59:52 +000075 enum {
76 TB = 1,
77 REP = 2,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
80 XD = 11, XS = 12,
Chris Lattner0d8db8e2010-02-12 02:06:33 +000081 T8 = 13, P_TA = 14,
Craig Topper75485d62011-10-23 07:34:00 +000082 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
Sean Callanan8ed9f512009-12-19 02:59:52 +000083 };
84}
Sean Callanan9492be82010-02-12 23:39:46 +000085
86// If rows are added to the opcode extension tables, then corresponding entries
Craig Toppere6c97ff2012-07-30 04:48:12 +000087// must be added here.
Sean Callanan9492be82010-02-12 23:39:46 +000088//
89// If the row corresponds to a single byte (i.e., 8f), then add an entry for
90// that byte to ONE_BYTE_EXTENSION_TABLES.
91//
Craig Toppere6c97ff2012-07-30 04:48:12 +000092// If the row corresponds to two bytes where the first is 0f, add an entry for
Sean Callanan9492be82010-02-12 23:39:46 +000093// the second byte to TWO_BYTE_EXTENSION_TABLES.
94//
95// If the row corresponds to some other set of bytes, you will need to modify
96// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
Craig Toppere6c97ff2012-07-30 04:48:12 +000097// to the X86 TD files, except in two cases: if the first two bytes of such a
Sean Callanan9492be82010-02-12 23:39:46 +000098// new combination are 0f 38 or 0f 3a, you just have to add maps called
99// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101// in RecognizableInstr::emitDecodePath().
102
Sean Callanan8ed9f512009-12-19 02:59:52 +0000103#define ONE_BYTE_EXTENSION_TABLES \
104 EXTENSION_TABLE(80) \
105 EXTENSION_TABLE(81) \
106 EXTENSION_TABLE(82) \
107 EXTENSION_TABLE(83) \
108 EXTENSION_TABLE(8f) \
109 EXTENSION_TABLE(c0) \
110 EXTENSION_TABLE(c1) \
111 EXTENSION_TABLE(c6) \
112 EXTENSION_TABLE(c7) \
113 EXTENSION_TABLE(d0) \
114 EXTENSION_TABLE(d1) \
115 EXTENSION_TABLE(d2) \
116 EXTENSION_TABLE(d3) \
117 EXTENSION_TABLE(f6) \
118 EXTENSION_TABLE(f7) \
119 EXTENSION_TABLE(fe) \
120 EXTENSION_TABLE(ff)
Craig Toppere6c97ff2012-07-30 04:48:12 +0000121
Sean Callanan8ed9f512009-12-19 02:59:52 +0000122#define TWO_BYTE_EXTENSION_TABLES \
123 EXTENSION_TABLE(00) \
124 EXTENSION_TABLE(01) \
Kay Tiong Khoo6c3daab2013-02-12 00:19:12 +0000125 EXTENSION_TABLE(0d) \
Sean Callanan8ed9f512009-12-19 02:59:52 +0000126 EXTENSION_TABLE(18) \
127 EXTENSION_TABLE(71) \
128 EXTENSION_TABLE(72) \
129 EXTENSION_TABLE(73) \
130 EXTENSION_TABLE(ae) \
Sean Callanan8ed9f512009-12-19 02:59:52 +0000131 EXTENSION_TABLE(ba) \
132 EXTENSION_TABLE(c7)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000133
Craig Topper566f2332011-10-15 20:46:47 +0000134#define THREE_BYTE_38_EXTENSION_TABLES \
135 EXTENSION_TABLE(F3)
136
Sean Callanan8ed9f512009-12-19 02:59:52 +0000137using namespace X86Disassembler;
138
139/// needsModRMForDecode - Indicates whether a particular instruction requires a
Craig Toppere6c97ff2012-07-30 04:48:12 +0000140/// ModR/M byte for the instruction to be properly decoded. For example, a
Sean Callanan8ed9f512009-12-19 02:59:52 +0000141/// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
142/// 0b11.
143///
144/// @param form - The form of the instruction.
145/// @return - true if the form implies that a ModR/M byte is required, false
146/// otherwise.
147static bool needsModRMForDecode(uint8_t form) {
148 if (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMDestMem ||
150 form == X86Local::MRMSrcReg ||
151 form == X86Local::MRMSrcMem ||
152 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
154 return true;
155 else
156 return false;
157}
158
159/// isRegFormat - Indicates whether a particular form requires the Mod field of
160/// the ModR/M byte to be 0b11.
161///
162/// @param form - The form of the instruction.
163/// @return - true if the form implies that Mod must be 0b11, false
164/// otherwise.
165static bool isRegFormat(uint8_t form) {
166 if (form == X86Local::MRMDestReg ||
167 form == X86Local::MRMSrcReg ||
168 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
169 return true;
170 else
171 return false;
172}
173
174/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175/// Useful for switch statements and the like.
176///
177/// @param init - A reference to the BitsInit to be decoded.
178/// @return - The field, with the first bit in the BitsInit as the lowest
179/// order bit.
David Greene05bce0b2011-07-29 22:43:06 +0000180static uint8_t byteFromBitsInit(BitsInit &init) {
Sean Callanan8ed9f512009-12-19 02:59:52 +0000181 int width = init.getNumBits();
182
183 assert(width <= 8 && "Field is too large for uint8_t!");
184
185 int index;
186 uint8_t mask = 0x01;
187
188 uint8_t ret = 0;
189
190 for (index = 0; index < width; index++) {
David Greene05bce0b2011-07-29 22:43:06 +0000191 if (static_cast<BitInit*>(init.getBit(index))->getValue())
Sean Callanan8ed9f512009-12-19 02:59:52 +0000192 ret |= mask;
193
194 mask <<= 1;
195 }
196
197 return ret;
198}
199
200/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201/// name of the field.
202///
203/// @param rec - The record from which to extract the value.
204/// @param name - The name of the field in the record.
205/// @return - The field, as translated by byteFromBitsInit().
206static uint8_t byteFromRec(const Record* rec, const std::string &name) {
David Greene05bce0b2011-07-29 22:43:06 +0000207 BitsInit* bits = rec->getValueAsBitsInit(name);
Sean Callanan8ed9f512009-12-19 02:59:52 +0000208 return byteFromBitsInit(*bits);
209}
210
211RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212 const CodeGenInstruction &insn,
213 InstrUID uid) {
214 UID = uid;
215
216 Rec = insn.TheDef;
217 Name = Rec->getName();
218 Spec = &tables.specForUID(UID);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000219
Sean Callanan8ed9f512009-12-19 02:59:52 +0000220 if (!Rec->isSubClassOf("X86Inst")) {
221 ShouldBeEmitted = false;
222 return;
223 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000224
Sean Callanan8ed9f512009-12-19 02:59:52 +0000225 Prefix = byteFromRec(Rec, "Prefix");
226 Opcode = byteFromRec(Rec, "Opcode");
227 Form = byteFromRec(Rec, "FormBits");
228 SegOvr = byteFromRec(Rec, "SegOvrBits");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000229
Sean Callanan8ed9f512009-12-19 02:59:52 +0000230 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
Craig Topper930a1eb2012-02-27 01:54:29 +0000231 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
Sean Callanan8ed9f512009-12-19 02:59:52 +0000232 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
Sean Callanana21e2ea2011-03-15 01:23:15 +0000233 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
Bruno Cardoso Lopes99405df2010-06-08 22:51:23 +0000234 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
Craig Topperb53fa8b2011-10-16 07:55:05 +0000235 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
Sean Callanana21e2ea2011-03-15 01:23:15 +0000236 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
Craig Toppere6a3a292011-12-30 05:20:36 +0000237 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
Craig Topper6744a172011-10-04 06:30:42 +0000238 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
Sean Callanan8ed9f512009-12-19 02:59:52 +0000239 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
240 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000241
Sean Callanan8ed9f512009-12-19 02:59:52 +0000242 Name = Rec->getName();
243 AsmString = Rec->getValueAsString("AsmString");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000244
Chris Lattnerc240bb02010-11-01 04:03:32 +0000245 Operands = &insn.Operands.OperandList;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000246
Kevin Enderby98f213c2011-09-02 18:03:03 +0000247 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
248 (Name.find("CRC32") != Name.npos);
Sean Callanana21e2ea2011-03-15 01:23:15 +0000249 HasFROperands = hasFROperands();
Craig Topper8a312fb2012-09-19 06:37:45 +0000250 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
Craig Topper17730842011-10-16 03:51:13 +0000251
Eli Friedman71052592011-07-16 02:41:28 +0000252 // Check for 64-bit inst which does not require REX
Craig Topper4da632e2011-09-23 06:57:25 +0000253 Is32Bit = false;
Eli Friedman71052592011-07-16 02:41:28 +0000254 Is64Bit = false;
255 // FIXME: Is there some better way to check for In64BitMode?
256 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
257 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
Craig Topper4da632e2011-09-23 06:57:25 +0000258 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
259 Is32Bit = true;
260 break;
261 }
Eli Friedman71052592011-07-16 02:41:28 +0000262 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
263 Is64Bit = true;
264 break;
265 }
266 }
267 // FIXME: These instructions aren't marked as 64-bit in any way
Craig Toppere6c97ff2012-07-30 04:48:12 +0000268 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
269 Rec->getName() == "MASKMOVDQU64" ||
270 Rec->getName() == "POPFS64" ||
271 Rec->getName() == "POPGS64" ||
272 Rec->getName() == "PUSHFS64" ||
Eli Friedman71052592011-07-16 02:41:28 +0000273 Rec->getName() == "PUSHGS64" ||
274 Rec->getName() == "REX64_PREFIX" ||
Craig Toppere6c97ff2012-07-30 04:48:12 +0000275 Rec->getName().find("MOV64") != Name.npos ||
Eli Friedman71052592011-07-16 02:41:28 +0000276 Rec->getName().find("PUSH64") != Name.npos ||
277 Rec->getName().find("POP64") != Name.npos;
278
Sean Callanan8ed9f512009-12-19 02:59:52 +0000279 ShouldBeEmitted = true;
280}
Craig Toppere6c97ff2012-07-30 04:48:12 +0000281
Sean Callanan8ed9f512009-12-19 02:59:52 +0000282void RecognizableInstr::processInstr(DisassemblerTables &tables,
Craig Topper5aba78b2012-07-12 06:52:41 +0000283 const CodeGenInstruction &insn,
284 InstrUID uid)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000285{
Daniel Dunbar40728862010-05-20 20:20:32 +0000286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288 return;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000289
Sean Callanan8ed9f512009-12-19 02:59:52 +0000290 RecognizableInstr recogInstr(tables, insn, uid);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000291
Sean Callanan8ed9f512009-12-19 02:59:52 +0000292 recogInstr.emitInstructionSpecifier(tables);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000293
Sean Callanan8ed9f512009-12-19 02:59:52 +0000294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
296}
297
298InstructionContext RecognizableInstr::insnContext() const {
299 InstructionContext insnContext;
300
Craig Topperb53fa8b2011-10-16 07:55:05 +0000301 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
Craig Topperc8eb8802011-11-06 23:04:08 +0000302 if (HasVEX_LPrefix && HasVEX_WPrefix) {
303 if (HasOpSizePrefix)
304 insnContext = IC_VEX_L_W_OPSIZE;
305 else
306 llvm_unreachable("Don't support VEX.L and VEX.W together");
307 } else if (HasOpSizePrefix && HasVEX_LPrefix)
Sean Callanana21e2ea2011-03-15 01:23:15 +0000308 insnContext = IC_VEX_L_OPSIZE;
309 else if (HasOpSizePrefix && HasVEX_WPrefix)
310 insnContext = IC_VEX_W_OPSIZE;
311 else if (HasOpSizePrefix)
312 insnContext = IC_VEX_OPSIZE;
Craig Topperee62e4f2011-10-16 16:50:08 +0000313 else if (HasVEX_LPrefix &&
314 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
Sean Callanana21e2ea2011-03-15 01:23:15 +0000315 insnContext = IC_VEX_L_XS;
Craig Topper75485d62011-10-23 07:34:00 +0000316 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
317 Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD))
Sean Callanana21e2ea2011-03-15 01:23:15 +0000319 insnContext = IC_VEX_L_XD;
Craig Topperee62e4f2011-10-16 16:50:08 +0000320 else if (HasVEX_WPrefix &&
321 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
Sean Callanana21e2ea2011-03-15 01:23:15 +0000322 insnContext = IC_VEX_W_XS;
Craig Topper75485d62011-10-23 07:34:00 +0000323 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
324 Prefix == X86Local::T8XD ||
325 Prefix == X86Local::TAXD))
Sean Callanana21e2ea2011-03-15 01:23:15 +0000326 insnContext = IC_VEX_W_XD;
327 else if (HasVEX_WPrefix)
328 insnContext = IC_VEX_W;
329 else if (HasVEX_LPrefix)
330 insnContext = IC_VEX_L;
Craig Topper75485d62011-10-23 07:34:00 +0000331 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
332 Prefix == X86Local::TAXD)
Sean Callanana21e2ea2011-03-15 01:23:15 +0000333 insnContext = IC_VEX_XD;
Craig Topperee62e4f2011-10-16 16:50:08 +0000334 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
Sean Callanana21e2ea2011-03-15 01:23:15 +0000335 insnContext = IC_VEX_XS;
336 else
337 insnContext = IC_VEX;
Eli Friedman71052592011-07-16 02:41:28 +0000338 } else if (Is64Bit || HasREX_WPrefix) {
Sean Callanan8ed9f512009-12-19 02:59:52 +0000339 if (HasREX_WPrefix && HasOpSizePrefix)
340 insnContext = IC_64BIT_REXW_OPSIZE;
Craig Topper75485d62011-10-23 07:34:00 +0000341 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
342 Prefix == X86Local::T8XD ||
343 Prefix == X86Local::TAXD))
Craig Toppere1b4a1a2011-10-01 19:54:56 +0000344 insnContext = IC_64BIT_XD_OPSIZE;
Craig Topperee62e4f2011-10-16 16:50:08 +0000345 else if (HasOpSizePrefix &&
346 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
Craig Topper29480fd2011-10-11 04:34:23 +0000347 insnContext = IC_64BIT_XS_OPSIZE;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000348 else if (HasOpSizePrefix)
349 insnContext = IC_64BIT_OPSIZE;
Craig Topper930a1eb2012-02-27 01:54:29 +0000350 else if (HasAdSizePrefix)
351 insnContext = IC_64BIT_ADSIZE;
Craig Topperee62e4f2011-10-16 16:50:08 +0000352 else if (HasREX_WPrefix &&
353 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
Sean Callanan8ed9f512009-12-19 02:59:52 +0000354 insnContext = IC_64BIT_REXW_XS;
Craig Topper75485d62011-10-23 07:34:00 +0000355 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
356 Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD))
Sean Callanan8ed9f512009-12-19 02:59:52 +0000358 insnContext = IC_64BIT_REXW_XD;
Craig Topper75485d62011-10-23 07:34:00 +0000359 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360 Prefix == X86Local::TAXD)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000361 insnContext = IC_64BIT_XD;
Craig Topperee62e4f2011-10-16 16:50:08 +0000362 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000363 insnContext = IC_64BIT_XS;
364 else if (HasREX_WPrefix)
365 insnContext = IC_64BIT_REXW;
366 else
367 insnContext = IC_64BIT;
368 } else {
Craig Topper75485d62011-10-23 07:34:00 +0000369 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
370 Prefix == X86Local::T8XD ||
371 Prefix == X86Local::TAXD))
Craig Toppere1b4a1a2011-10-01 19:54:56 +0000372 insnContext = IC_XD_OPSIZE;
Craig Topperee62e4f2011-10-16 16:50:08 +0000373 else if (HasOpSizePrefix &&
374 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
Craig Topper29480fd2011-10-11 04:34:23 +0000375 insnContext = IC_XS_OPSIZE;
Kevin Enderby98f213c2011-09-02 18:03:03 +0000376 else if (HasOpSizePrefix)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000377 insnContext = IC_OPSIZE;
Craig Topper930a1eb2012-02-27 01:54:29 +0000378 else if (HasAdSizePrefix)
379 insnContext = IC_ADSIZE;
Craig Topper75485d62011-10-23 07:34:00 +0000380 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
381 Prefix == X86Local::TAXD)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000382 insnContext = IC_XD;
Craig Topperee62e4f2011-10-16 16:50:08 +0000383 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
384 Prefix == X86Local::REP)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000385 insnContext = IC_XS;
386 else
387 insnContext = IC;
388 }
389
390 return insnContext;
391}
Craig Toppere6c97ff2012-07-30 04:48:12 +0000392
Sean Callanan8ed9f512009-12-19 02:59:52 +0000393RecognizableInstr::filter_ret RecognizableInstr::filter() const {
Sean Callanana21e2ea2011-03-15 01:23:15 +0000394 ///////////////////
395 // FILTER_STRONG
396 //
Craig Toppere6c97ff2012-07-30 04:48:12 +0000397
Sean Callanan8ed9f512009-12-19 02:59:52 +0000398 // Filter out intrinsics
Craig Toppere6c97ff2012-07-30 04:48:12 +0000399
Craig Topper24fd0dd2012-07-30 05:39:34 +0000400 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000401
Sean Callanan8ed9f512009-12-19 02:59:52 +0000402 if (Form == X86Local::Pseudo ||
Craig Topper03819792011-09-11 21:41:45 +0000403 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
Sean Callanan8ed9f512009-12-19 02:59:52 +0000404 return FILTER_STRONG;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000405
Craig Toppere6c97ff2012-07-30 04:48:12 +0000406
Kevin Enderbyfaf72ff2012-03-09 17:52:49 +0000407 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
408 // printed as a separate "instruction".
Craig Toppere6c97ff2012-07-30 04:48:12 +0000409
Craig Topper787a88f2011-11-19 05:48:20 +0000410 if (Name.find("_Int") != Name.npos ||
Craig Topper49d86c92012-07-30 06:48:11 +0000411 Name.find("Int_") != Name.npos)
Sean Callanana21e2ea2011-03-15 01:23:15 +0000412 return FILTER_STRONG;
413
414 // Filter out instructions with segment override prefixes.
415 // They're too messy to handle now and we'll special case them if needed.
Craig Toppere6c97ff2012-07-30 04:48:12 +0000416
Sean Callanana21e2ea2011-03-15 01:23:15 +0000417 if (SegOvr)
418 return FILTER_STRONG;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000419
Sean Callanana21e2ea2011-03-15 01:23:15 +0000420
421 /////////////////
422 // FILTER_WEAK
423 //
424
Craig Toppere6c97ff2012-07-30 04:48:12 +0000425
Sean Callanan8ed9f512009-12-19 02:59:52 +0000426 // Filter out instructions with a LOCK prefix;
427 // prefer forms that do not have the prefix
428 if (HasLockPrefix)
429 return FILTER_WEAK;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000430
Sean Callanana21e2ea2011-03-15 01:23:15 +0000431 // Filter out alternate forms of AVX instructions
432 if (Name.find("_alt") != Name.npos ||
433 Name.find("XrYr") != Name.npos ||
Craig Toppere1b4a1a2011-10-01 19:54:56 +0000434 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
Sean Callanana21e2ea2011-03-15 01:23:15 +0000435 Name.find("_64mr") != Name.npos ||
436 Name.find("Xrr") != Name.npos ||
437 Name.find("rr64") != Name.npos)
438 return FILTER_WEAK;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000439
440 // Special cases.
Dale Johannesen86097c32010-09-07 18:10:56 +0000441
Sean Callanan8ed9f512009-12-19 02:59:52 +0000442 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
443 return FILTER_WEAK;
444 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
445 return FILTER_WEAK;
446
447 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
448 return FILTER_WEAK;
449 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
450 return FILTER_WEAK;
451 if (Name.find("Fs") != Name.npos)
452 return FILTER_WEAK;
Craig Topper787a88f2011-11-19 05:48:20 +0000453 if (Name == "PUSH64i16" ||
Sean Callanan8ed9f512009-12-19 02:59:52 +0000454 Name == "MOVPQI2QImr" ||
Sean Callanana21e2ea2011-03-15 01:23:15 +0000455 Name == "VMOVPQI2QImr" ||
Sean Callanan8ed9f512009-12-19 02:59:52 +0000456 Name == "MMX_MOVD64rrv164" ||
Sean Callanan8ed9f512009-12-19 02:59:52 +0000457 Name == "MOV64ri64i32" ||
Craig Topper787a88f2011-11-19 05:48:20 +0000458 Name == "VMASKMOVDQU64" ||
459 Name == "VEXTRACTPSrr64" ||
460 Name == "VMOVQd64rr" ||
461 Name == "VMOVQs64rr")
Sean Callanan8ed9f512009-12-19 02:59:52 +0000462 return FILTER_WEAK;
463
Stefanus Du Toit23306de2013-06-18 17:08:10 +0000464 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
465 // For now, just prefer the REP versions.
466 if (Name == "XACQUIRE_PREFIX" ||
467 Name == "XRELEASE_PREFIX")
468 return FILTER_WEAK;
469
Sean Callanan8ed9f512009-12-19 02:59:52 +0000470 if (HasFROperands && Name.find("MOV") != Name.npos &&
Craig Toppere6c97ff2012-07-30 04:48:12 +0000471 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
Sean Callanan8ed9f512009-12-19 02:59:52 +0000472 (Name.find("to") != Name.npos)))
Craig Topper50c5c822012-07-30 05:10:05 +0000473 return FILTER_STRONG;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000474
475 return FILTER_NORMAL;
476}
Sean Callanana21e2ea2011-03-15 01:23:15 +0000477
478bool RecognizableInstr::hasFROperands() const {
479 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
480 unsigned numOperands = OperandList.size();
481
482 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
483 const std::string &recName = OperandList[operandIndex].Rec->getName();
Craig Toppere6c97ff2012-07-30 04:48:12 +0000484
Sean Callanana21e2ea2011-03-15 01:23:15 +0000485 if (recName.find("FR") != recName.npos)
486 return true;
487 }
488 return false;
489}
490
Craig Topper5aba78b2012-07-12 06:52:41 +0000491void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
492 unsigned &physicalOperandIndex,
493 unsigned &numPhysicalOperands,
494 const unsigned *operandMapping,
495 OperandEncoding (*encodingFromString)
496 (const std::string&,
497 bool hasOpSizePrefix)) {
Sean Callanan8ed9f512009-12-19 02:59:52 +0000498 if (optional) {
499 if (physicalOperandIndex >= numPhysicalOperands)
500 return;
501 } else {
502 assert(physicalOperandIndex < numPhysicalOperands);
503 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000504
Sean Callanan8ed9f512009-12-19 02:59:52 +0000505 while (operandMapping[operandIndex] != operandIndex) {
506 Spec->operands[operandIndex].encoding = ENCODING_DUP;
507 Spec->operands[operandIndex].type =
508 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
509 ++operandIndex;
510 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000511
Sean Callanan8ed9f512009-12-19 02:59:52 +0000512 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
Sean Callanana21e2ea2011-03-15 01:23:15 +0000513
Sean Callanan8ed9f512009-12-19 02:59:52 +0000514 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
515 HasOpSizePrefix);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000516 Spec->operands[operandIndex].type = typeFromString(typeName,
Sean Callanana21e2ea2011-03-15 01:23:15 +0000517 IsSSE,
518 HasREX_WPrefix,
519 HasOpSizePrefix);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000520
Sean Callanan8ed9f512009-12-19 02:59:52 +0000521 ++operandIndex;
522 ++physicalOperandIndex;
523}
524
525void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
526 Spec->name = Name;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000527
Craig Topper24fd0dd2012-07-30 05:39:34 +0000528 if (!ShouldBeEmitted)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000529 return;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000530
Sean Callanan8ed9f512009-12-19 02:59:52 +0000531 switch (filter()) {
532 case FILTER_WEAK:
533 Spec->filtered = true;
534 break;
535 case FILTER_STRONG:
536 ShouldBeEmitted = false;
537 return;
538 case FILTER_NORMAL:
539 break;
540 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000541
Sean Callanan8ed9f512009-12-19 02:59:52 +0000542 Spec->insnContext = insnContext();
Craig Toppere6c97ff2012-07-30 04:48:12 +0000543
Chris Lattnerc240bb02010-11-01 04:03:32 +0000544 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000545
Sean Callanan8ed9f512009-12-19 02:59:52 +0000546 unsigned numOperands = OperandList.size();
547 unsigned numPhysicalOperands = 0;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000548
Sean Callanan8ed9f512009-12-19 02:59:52 +0000549 // operandMapping maps from operands in OperandList to their originals.
550 // If operandMapping[i] != i, then the entry is a duplicate.
551 unsigned operandMapping[X86_MAX_OPERANDS];
Craig Topper06f554d2011-12-30 06:23:39 +0000552 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000553
Craig Topper5aba78b2012-07-12 06:52:41 +0000554 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
Sean Callanan8ed9f512009-12-19 02:59:52 +0000555 if (OperandList[operandIndex].Constraints.size()) {
Chris Lattnerc240bb02010-11-01 04:03:32 +0000556 const CGIOperandList::ConstraintInfo &Constraint =
Chris Lattnera7d479c2010-02-10 01:45:28 +0000557 OperandList[operandIndex].Constraints[0];
558 if (Constraint.isTied()) {
Craig Topper5aba78b2012-07-12 06:52:41 +0000559 operandMapping[operandIndex] = operandIndex;
560 operandMapping[Constraint.getTiedOperand()] = operandIndex;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000561 } else {
562 ++numPhysicalOperands;
563 operandMapping[operandIndex] = operandIndex;
564 }
565 } else {
566 ++numPhysicalOperands;
567 operandMapping[operandIndex] = operandIndex;
568 }
Sean Callanan8ed9f512009-12-19 02:59:52 +0000569 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000570
Sean Callanan8ed9f512009-12-19 02:59:52 +0000571#define HANDLE_OPERAND(class) \
572 handleOperand(false, \
573 operandIndex, \
574 physicalOperandIndex, \
575 numPhysicalOperands, \
576 operandMapping, \
577 class##EncodingFromString);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000578
Sean Callanan8ed9f512009-12-19 02:59:52 +0000579#define HANDLE_OPTIONAL(class) \
580 handleOperand(true, \
581 operandIndex, \
582 physicalOperandIndex, \
583 numPhysicalOperands, \
584 operandMapping, \
585 class##EncodingFromString);
Craig Toppere6c97ff2012-07-30 04:48:12 +0000586
Sean Callanan8ed9f512009-12-19 02:59:52 +0000587 // operandIndex should always be < numOperands
Craig Topper5aba78b2012-07-12 06:52:41 +0000588 unsigned operandIndex = 0;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000589 // physicalOperandIndex should always be < numPhysicalOperands
590 unsigned physicalOperandIndex = 0;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000591
Sean Callanan8ed9f512009-12-19 02:59:52 +0000592 switch (Form) {
593 case X86Local::RawFrm:
594 // Operand 1 (optional) is an address or immediate.
595 // Operand 2 (optional) is an immediate.
Craig Toppere6c97ff2012-07-30 04:48:12 +0000596 assert(numPhysicalOperands <= 2 &&
Sean Callanan8ed9f512009-12-19 02:59:52 +0000597 "Unexpected number of operands for RawFrm");
598 HANDLE_OPTIONAL(relocation)
599 HANDLE_OPTIONAL(immediate)
600 break;
601 case X86Local::AddRegFrm:
602 // Operand 1 is added to the opcode.
603 // Operand 2 (optional) is an address.
604 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
605 "Unexpected number of operands for AddRegFrm");
606 HANDLE_OPERAND(opcodeModifier)
607 HANDLE_OPTIONAL(relocation)
608 break;
609 case X86Local::MRMDestReg:
610 // Operand 1 is a register operand in the R/M field.
611 // Operand 2 is a register operand in the Reg/Opcode field.
Craig Topper3daa5c22011-08-30 07:09:35 +0000612 // - In AVX, there is a register operand in the VEX.vvvv field here -
Sean Callanan8ed9f512009-12-19 02:59:52 +0000613 // Operand 3 (optional) is an immediate.
Craig Topper3daa5c22011-08-30 07:09:35 +0000614 if (HasVEX_4VPrefix)
615 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
616 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
617 else
618 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
619 "Unexpected number of operands for MRMDestRegFrm");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000620
Sean Callanan8ed9f512009-12-19 02:59:52 +0000621 HANDLE_OPERAND(rmRegister)
Craig Topper3daa5c22011-08-30 07:09:35 +0000622
623 if (HasVEX_4VPrefix)
624 // FIXME: In AVX, the register below becomes the one encoded
625 // in ModRMVEX and the one above the one in the VEX.VVVV field
626 HANDLE_OPERAND(vvvvRegister)
Craig Toppere6c97ff2012-07-30 04:48:12 +0000627
Sean Callanan8ed9f512009-12-19 02:59:52 +0000628 HANDLE_OPERAND(roRegister)
629 HANDLE_OPTIONAL(immediate)
630 break;
631 case X86Local::MRMDestMem:
632 // Operand 1 is a memory operand (possibly SIB-extended)
633 // Operand 2 is a register operand in the Reg/Opcode field.
Craig Topper3daa5c22011-08-30 07:09:35 +0000634 // - In AVX, there is a register operand in the VEX.vvvv field here -
Sean Callanan8ed9f512009-12-19 02:59:52 +0000635 // Operand 3 (optional) is an immediate.
Craig Topper3daa5c22011-08-30 07:09:35 +0000636 if (HasVEX_4VPrefix)
637 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
638 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
639 else
640 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
641 "Unexpected number of operands for MRMDestMemFrm");
Sean Callanan8ed9f512009-12-19 02:59:52 +0000642 HANDLE_OPERAND(memory)
Craig Topper3daa5c22011-08-30 07:09:35 +0000643
644 if (HasVEX_4VPrefix)
645 // FIXME: In AVX, the register below becomes the one encoded
646 // in ModRMVEX and the one above the one in the VEX.VVVV field
647 HANDLE_OPERAND(vvvvRegister)
Craig Toppere6c97ff2012-07-30 04:48:12 +0000648
Sean Callanan8ed9f512009-12-19 02:59:52 +0000649 HANDLE_OPERAND(roRegister)
650 HANDLE_OPTIONAL(immediate)
651 break;
652 case X86Local::MRMSrcReg:
653 // Operand 1 is a register operand in the Reg/Opcode field.
654 // Operand 2 is a register operand in the R/M field.
Sean Callanana21e2ea2011-03-15 01:23:15 +0000655 // - In AVX, there is a register operand in the VEX.vvvv field here -
Sean Callanan8ed9f512009-12-19 02:59:52 +0000656 // Operand 3 (optional) is an immediate.
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000657 // Operand 4 (optional) is an immediate.
Bruno Cardoso Lopes99405df2010-06-08 22:51:23 +0000658
Craig Topperb53fa8b2011-10-16 07:55:05 +0000659 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
Craig Topper06f554d2011-12-30 06:23:39 +0000660 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
Craig Toppere6c97ff2012-07-30 04:48:12 +0000661 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
Sean Callanana21e2ea2011-03-15 01:23:15 +0000662 else
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000663 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
Sean Callanana21e2ea2011-03-15 01:23:15 +0000664 "Unexpected number of operands for MRMSrcRegFrm");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000665
Sean Callanana21e2ea2011-03-15 01:23:15 +0000666 HANDLE_OPERAND(roRegister)
Craig Topper17730842011-10-16 03:51:13 +0000667
Craig Topperb53fa8b2011-10-16 07:55:05 +0000668 if (HasVEX_4VPrefix)
Bruno Cardoso Lopesc902a592010-06-11 23:50:47 +0000669 // FIXME: In AVX, the register below becomes the one encoded
670 // in ModRMVEX and the one above the one in the VEX.VVVV field
Sean Callanana21e2ea2011-03-15 01:23:15 +0000671 HANDLE_OPERAND(vvvvRegister)
Craig Topper17730842011-10-16 03:51:13 +0000672
Craig Toppere6a3a292011-12-30 05:20:36 +0000673 if (HasMemOp4Prefix)
674 HANDLE_OPERAND(immediate)
675
Sean Callanana21e2ea2011-03-15 01:23:15 +0000676 HANDLE_OPERAND(rmRegister)
Craig Topper17730842011-10-16 03:51:13 +0000677
Craig Topperb53fa8b2011-10-16 07:55:05 +0000678 if (HasVEX_4VOp3Prefix)
Craig Topper17730842011-10-16 03:51:13 +0000679 HANDLE_OPERAND(vvvvRegister)
680
Craig Topper06f554d2011-12-30 06:23:39 +0000681 if (!HasMemOp4Prefix)
682 HANDLE_OPTIONAL(immediate)
683 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000684 HANDLE_OPTIONAL(immediate)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000685 break;
686 case X86Local::MRMSrcMem:
687 // Operand 1 is a register operand in the Reg/Opcode field.
688 // Operand 2 is a memory operand (possibly SIB-extended)
Sean Callanana21e2ea2011-03-15 01:23:15 +0000689 // - In AVX, there is a register operand in the VEX.vvvv field here -
Sean Callanan8ed9f512009-12-19 02:59:52 +0000690 // Operand 3 (optional) is an immediate.
Craig Topperb53fa8b2011-10-16 07:55:05 +0000691
692 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
Craig Topper06f554d2011-12-30 06:23:39 +0000693 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
Craig Toppere6c97ff2012-07-30 04:48:12 +0000694 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
Sean Callanana21e2ea2011-03-15 01:23:15 +0000695 else
696 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
697 "Unexpected number of operands for MRMSrcMemFrm");
Craig Toppere6c97ff2012-07-30 04:48:12 +0000698
Sean Callanan8ed9f512009-12-19 02:59:52 +0000699 HANDLE_OPERAND(roRegister)
Bruno Cardoso Lopesc902a592010-06-11 23:50:47 +0000700
Craig Topperb53fa8b2011-10-16 07:55:05 +0000701 if (HasVEX_4VPrefix)
Bruno Cardoso Lopesc902a592010-06-11 23:50:47 +0000702 // FIXME: In AVX, the register below becomes the one encoded
703 // in ModRMVEX and the one above the one in the VEX.VVVV field
Sean Callanana21e2ea2011-03-15 01:23:15 +0000704 HANDLE_OPERAND(vvvvRegister)
Bruno Cardoso Lopesc902a592010-06-11 23:50:47 +0000705
Craig Toppere6a3a292011-12-30 05:20:36 +0000706 if (HasMemOp4Prefix)
707 HANDLE_OPERAND(immediate)
708
Sean Callanan8ed9f512009-12-19 02:59:52 +0000709 HANDLE_OPERAND(memory)
Craig Topper17730842011-10-16 03:51:13 +0000710
Craig Topperb53fa8b2011-10-16 07:55:05 +0000711 if (HasVEX_4VOp3Prefix)
Craig Topper17730842011-10-16 03:51:13 +0000712 HANDLE_OPERAND(vvvvRegister)
713
Craig Topper06f554d2011-12-30 06:23:39 +0000714 if (!HasMemOp4Prefix)
715 HANDLE_OPTIONAL(immediate)
716 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
Sean Callanan8ed9f512009-12-19 02:59:52 +0000717 break;
718 case X86Local::MRM0r:
719 case X86Local::MRM1r:
720 case X86Local::MRM2r:
721 case X86Local::MRM3r:
722 case X86Local::MRM4r:
723 case X86Local::MRM5r:
724 case X86Local::MRM6r:
725 case X86Local::MRM7r:
726 // Operand 1 is a register operand in the R/M field.
727 // Operand 2 (optional) is an immediate or relocation.
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000728 // Operand 3 (optional) is an immediate.
Sean Callanana21e2ea2011-03-15 01:23:15 +0000729 if (HasVEX_4VPrefix)
730 assert(numPhysicalOperands <= 3 &&
Craig Topper566f2332011-10-15 20:46:47 +0000731 "Unexpected number of operands for MRMnRFrm with VEX_4V");
Sean Callanana21e2ea2011-03-15 01:23:15 +0000732 else
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000733 assert(numPhysicalOperands <= 3 &&
Sean Callanana21e2ea2011-03-15 01:23:15 +0000734 "Unexpected number of operands for MRMnRFrm");
735 if (HasVEX_4VPrefix)
Craig Topper566f2332011-10-15 20:46:47 +0000736 HANDLE_OPERAND(vvvvRegister)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000737 HANDLE_OPTIONAL(rmRegister)
738 HANDLE_OPTIONAL(relocation)
Benjamin Kramer1386e9b2012-05-29 19:05:25 +0000739 HANDLE_OPTIONAL(immediate)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000740 break;
741 case X86Local::MRM0m:
742 case X86Local::MRM1m:
743 case X86Local::MRM2m:
744 case X86Local::MRM3m:
745 case X86Local::MRM4m:
746 case X86Local::MRM5m:
747 case X86Local::MRM6m:
748 case X86Local::MRM7m:
749 // Operand 1 is a memory operand (possibly SIB-extended)
750 // Operand 2 (optional) is an immediate or relocation.
Craig Topper566f2332011-10-15 20:46:47 +0000751 if (HasVEX_4VPrefix)
752 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
753 "Unexpected number of operands for MRMnMFrm");
754 else
755 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
756 "Unexpected number of operands for MRMnMFrm");
757 if (HasVEX_4VPrefix)
758 HANDLE_OPERAND(vvvvRegister)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000759 HANDLE_OPERAND(memory)
760 HANDLE_OPTIONAL(relocation)
761 break;
Sean Callanan6aeb2e32010-10-04 22:45:51 +0000762 case X86Local::RawFrmImm8:
763 // operand 1 is a 16-bit immediate
764 // operand 2 is an 8-bit immediate
765 assert(numPhysicalOperands == 2 &&
766 "Unexpected number of operands for X86Local::RawFrmImm8");
767 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(immediate)
769 break;
770 case X86Local::RawFrmImm16:
771 // operand 1 is a 16-bit immediate
772 // operand 2 is a 16-bit immediate
773 HANDLE_OPERAND(immediate)
774 HANDLE_OPERAND(immediate)
775 break;
Kevin Enderby12dccae2013-03-11 21:17:13 +0000776 case X86Local::MRM_F8:
777 if (Opcode == 0xc6) {
778 assert(numPhysicalOperands == 1 &&
779 "Unexpected number of operands for X86Local::MRM_F8");
780 HANDLE_OPERAND(immediate)
781 } else if (Opcode == 0xc7) {
782 assert(numPhysicalOperands == 1 &&
783 "Unexpected number of operands for X86Local::MRM_F8");
784 HANDLE_OPERAND(relocation)
785 }
786 break;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000787 case X86Local::MRMInitReg:
788 // Ignored.
789 break;
790 }
Craig Toppere6c97ff2012-07-30 04:48:12 +0000791
Sean Callanan8ed9f512009-12-19 02:59:52 +0000792 #undef HANDLE_OPERAND
793 #undef HANDLE_OPTIONAL
794}
795
796void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
797 // Special cases where the LLVM tables are not complete
798
Sean Callanan9492be82010-02-12 23:39:46 +0000799#define MAP(from, to) \
800 case X86Local::MRM_##from: \
801 filter = new ExactFilter(0x##from); \
802 break;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000803
804 OpcodeType opcodeType = (OpcodeType)-1;
Craig Toppere6c97ff2012-07-30 04:48:12 +0000805
806 ModRMFilter* filter = NULL;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000807 uint8_t opcodeToSet = 0;
808
809 switch (Prefix) {
810 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
811 case X86Local::XD:
812 case X86Local::XS:
813 case X86Local::TB:
814 opcodeType = TWOBYTE;
815
816 switch (Opcode) {
Sean Callanan95a5a7d2010-02-13 01:48:34 +0000817 default:
818 if (needsModRMForDecode(Form))
819 filter = new ModFilter(isRegFormat(Form));
820 else
821 filter = new DumbFilter();
822 break;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000823#define EXTENSION_TABLE(n) case 0x##n:
824 TWO_BYTE_EXTENSION_TABLES
825#undef EXTENSION_TABLE
826 switch (Form) {
827 default:
828 llvm_unreachable("Unhandled two-byte extended opcode");
829 case X86Local::MRM0r:
830 case X86Local::MRM1r:
831 case X86Local::MRM2r:
832 case X86Local::MRM3r:
833 case X86Local::MRM4r:
834 case X86Local::MRM5r:
835 case X86Local::MRM6r:
836 case X86Local::MRM7r:
837 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
838 break;
839 case X86Local::MRM0m:
840 case X86Local::MRM1m:
841 case X86Local::MRM2m:
842 case X86Local::MRM3m:
843 case X86Local::MRM4m:
844 case X86Local::MRM5m:
845 case X86Local::MRM6m:
846 case X86Local::MRM7m:
847 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
848 break;
Sean Callanan9492be82010-02-12 23:39:46 +0000849 MRM_MAPPING
Sean Callanan8ed9f512009-12-19 02:59:52 +0000850 } // switch (Form)
851 break;
Sean Callanan95a5a7d2010-02-13 01:48:34 +0000852 } // switch (Opcode)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000853 opcodeToSet = Opcode;
854 break;
855 case X86Local::T8:
Craig Topperee62e4f2011-10-16 16:50:08 +0000856 case X86Local::T8XD:
857 case X86Local::T8XS:
Sean Callanan8ed9f512009-12-19 02:59:52 +0000858 opcodeType = THREEBYTE_38;
Craig Topper566f2332011-10-15 20:46:47 +0000859 switch (Opcode) {
860 default:
861 if (needsModRMForDecode(Form))
862 filter = new ModFilter(isRegFormat(Form));
863 else
864 filter = new DumbFilter();
865 break;
866#define EXTENSION_TABLE(n) case 0x##n:
867 THREE_BYTE_38_EXTENSION_TABLES
868#undef EXTENSION_TABLE
869 switch (Form) {
870 default:
871 llvm_unreachable("Unhandled two-byte extended opcode");
872 case X86Local::MRM0r:
873 case X86Local::MRM1r:
874 case X86Local::MRM2r:
875 case X86Local::MRM3r:
876 case X86Local::MRM4r:
877 case X86Local::MRM5r:
878 case X86Local::MRM6r:
879 case X86Local::MRM7r:
880 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
881 break;
882 case X86Local::MRM0m:
883 case X86Local::MRM1m:
884 case X86Local::MRM2m:
885 case X86Local::MRM3m:
886 case X86Local::MRM4m:
887 case X86Local::MRM5m:
888 case X86Local::MRM6m:
889 case X86Local::MRM7m:
890 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
891 break;
892 MRM_MAPPING
893 } // switch (Form)
894 break;
895 } // switch (Opcode)
Sean Callanan8ed9f512009-12-19 02:59:52 +0000896 opcodeToSet = Opcode;
897 break;
Chris Lattner0d8db8e2010-02-12 02:06:33 +0000898 case X86Local::P_TA:
Craig Topper75485d62011-10-23 07:34:00 +0000899 case X86Local::TAXD:
Sean Callanan8ed9f512009-12-19 02:59:52 +0000900 opcodeType = THREEBYTE_3A;
901 if (needsModRMForDecode(Form))
902 filter = new ModFilter(isRegFormat(Form));
903 else
904 filter = new DumbFilter();
905 opcodeToSet = Opcode;
906 break;
Joerg Sonnenberger4a8ac8d2011-04-04 16:58:13 +0000907 case X86Local::A6:
908 opcodeType = THREEBYTE_A6;
909 if (needsModRMForDecode(Form))
910 filter = new ModFilter(isRegFormat(Form));
911 else
912 filter = new DumbFilter();
913 opcodeToSet = Opcode;
914 break;
915 case X86Local::A7:
916 opcodeType = THREEBYTE_A7;
917 if (needsModRMForDecode(Form))
918 filter = new ModFilter(isRegFormat(Form));
919 else
920 filter = new DumbFilter();
921 opcodeToSet = Opcode;
922 break;
Sean Callanan8ed9f512009-12-19 02:59:52 +0000923 case X86Local::D8:
924 case X86Local::D9:
925 case X86Local::DA:
926 case X86Local::DB:
927 case X86Local::DC:
928 case X86Local::DD:
929 case X86Local::DE:
930 case X86Local::DF:
931 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
932 opcodeType = ONEBYTE;
933 if (Form == X86Local::AddRegFrm) {
934 Spec->modifierType = MODIFIER_MODRM;
935 Spec->modifierBase = Opcode;
936 filter = new AddRegEscapeFilter(Opcode);
937 } else {
938 filter = new EscapeFilter(true, Opcode);
939 }
940 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
941 break;
Craig Topper842f58f2011-09-11 20:23:20 +0000942 case X86Local::REP:
Sean Callanan8ed9f512009-12-19 02:59:52 +0000943 default:
944 opcodeType = ONEBYTE;
945 switch (Opcode) {
946#define EXTENSION_TABLE(n) case 0x##n:
947 ONE_BYTE_EXTENSION_TABLES
948#undef EXTENSION_TABLE
949 switch (Form) {
950 default:
951 llvm_unreachable("Fell through the cracks of a single-byte "
952 "extended opcode");
953 case X86Local::MRM0r:
954 case X86Local::MRM1r:
955 case X86Local::MRM2r:
956 case X86Local::MRM3r:
957 case X86Local::MRM4r:
958 case X86Local::MRM5r:
959 case X86Local::MRM6r:
960 case X86Local::MRM7r:
961 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
962 break;
963 case X86Local::MRM0m:
964 case X86Local::MRM1m:
965 case X86Local::MRM2m:
966 case X86Local::MRM3m:
967 case X86Local::MRM4m:
968 case X86Local::MRM5m:
969 case X86Local::MRM6m:
970 case X86Local::MRM7m:
971 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
972 break;
Sean Callanan9492be82010-02-12 23:39:46 +0000973 MRM_MAPPING
Sean Callanan8ed9f512009-12-19 02:59:52 +0000974 } // switch (Form)
975 break;
976 case 0xd8:
977 case 0xd9:
978 case 0xda:
979 case 0xdb:
980 case 0xdc:
981 case 0xdd:
982 case 0xde:
983 case 0xdf:
984 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
985 break;
986 default:
987 if (needsModRMForDecode(Form))
988 filter = new ModFilter(isRegFormat(Form));
989 else
990 filter = new DumbFilter();
991 break;
992 } // switch (Opcode)
993 opcodeToSet = Opcode;
994 } // switch (Prefix)
995
996 assert(opcodeType != (OpcodeType)-1 &&
997 "Opcode type not set");
998 assert(filter && "Filter not set");
999
1000 if (Form == X86Local::AddRegFrm) {
1001 if(Spec->modifierType != MODIFIER_MODRM) {
1002 assert(opcodeToSet < 0xf9 &&
1003 "Not enough room for all ADDREG_FRM operands");
Craig Toppere6c97ff2012-07-30 04:48:12 +00001004
Sean Callanan8ed9f512009-12-19 02:59:52 +00001005 uint8_t currentOpcode;
1006
1007 for (currentOpcode = opcodeToSet;
1008 currentOpcode < opcodeToSet + 8;
1009 ++currentOpcode)
Craig Toppere6c97ff2012-07-30 04:48:12 +00001010 tables.setTableFields(opcodeType,
1011 insnContext(),
1012 currentOpcode,
1013 *filter,
Craig Topper6744a172011-10-04 06:30:42 +00001014 UID, Is32Bit, IgnoresVEX_L);
Craig Toppere6c97ff2012-07-30 04:48:12 +00001015
Sean Callanan8ed9f512009-12-19 02:59:52 +00001016 Spec->modifierType = MODIFIER_OPCODE;
1017 Spec->modifierBase = opcodeToSet;
1018 } else {
1019 // modifierBase was set where MODIFIER_MODRM was set
Craig Toppere6c97ff2012-07-30 04:48:12 +00001020 tables.setTableFields(opcodeType,
1021 insnContext(),
1022 opcodeToSet,
1023 *filter,
Craig Topper6744a172011-10-04 06:30:42 +00001024 UID, Is32Bit, IgnoresVEX_L);
Sean Callanan8ed9f512009-12-19 02:59:52 +00001025 }
1026 } else {
1027 tables.setTableFields(opcodeType,
1028 insnContext(),
1029 opcodeToSet,
1030 *filter,
Craig Topper6744a172011-10-04 06:30:42 +00001031 UID, Is32Bit, IgnoresVEX_L);
Craig Toppere6c97ff2012-07-30 04:48:12 +00001032
Sean Callanan8ed9f512009-12-19 02:59:52 +00001033 Spec->modifierType = MODIFIER_NONE;
1034 Spec->modifierBase = opcodeToSet;
1035 }
Craig Toppere6c97ff2012-07-30 04:48:12 +00001036
Sean Callanan8ed9f512009-12-19 02:59:52 +00001037 delete filter;
Craig Toppere6c97ff2012-07-30 04:48:12 +00001038
Sean Callanan9492be82010-02-12 23:39:46 +00001039#undef MAP
Sean Callanan8ed9f512009-12-19 02:59:52 +00001040}
1041
1042#define TYPE(str, type) if (s == str) return type;
1043OperandType RecognizableInstr::typeFromString(const std::string &s,
1044 bool isSSE,
1045 bool hasREX_WPrefix,
1046 bool hasOpSizePrefix) {
1047 if (isSSE) {
Craig Toppere6c97ff2012-07-30 04:48:12 +00001048 // For SSE instructions, we ignore the OpSize prefix and force operand
Sean Callanan8ed9f512009-12-19 02:59:52 +00001049 // sizes.
1050 TYPE("GR16", TYPE_R16)
1051 TYPE("GR32", TYPE_R32)
1052 TYPE("GR64", TYPE_R64)
1053 }
1054 if(hasREX_WPrefix) {
1055 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1056 // is special.
1057 TYPE("GR32", TYPE_R32)
1058 }
1059 if(!hasOpSizePrefix) {
1060 // For instructions without an OpSize prefix, a declared 16-bit register or
1061 // immediate encoding is special.
1062 TYPE("GR16", TYPE_R16)
1063 TYPE("i16imm", TYPE_IMM16)
1064 }
1065 TYPE("i16mem", TYPE_Mv)
1066 TYPE("i16imm", TYPE_IMMv)
1067 TYPE("i16i8imm", TYPE_IMMv)
1068 TYPE("GR16", TYPE_Rv)
1069 TYPE("i32mem", TYPE_Mv)
1070 TYPE("i32imm", TYPE_IMMv)
1071 TYPE("i32i8imm", TYPE_IMM32)
Kevin Enderbyc37d4bb2011-07-27 23:01:50 +00001072 TYPE("u32u8imm", TYPE_IMM32)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001073 TYPE("GR32", TYPE_Rv)
1074 TYPE("i64mem", TYPE_Mv)
1075 TYPE("i64i32imm", TYPE_IMM64)
1076 TYPE("i64i8imm", TYPE_IMM64)
1077 TYPE("GR64", TYPE_R64)
1078 TYPE("i8mem", TYPE_M8)
1079 TYPE("i8imm", TYPE_IMM8)
1080 TYPE("GR8", TYPE_R8)
1081 TYPE("VR128", TYPE_XMM128)
1082 TYPE("f128mem", TYPE_M128)
Chris Lattnerb2ef4c12010-09-29 02:57:56 +00001083 TYPE("f256mem", TYPE_M256)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001084 TYPE("FR64", TYPE_XMM64)
1085 TYPE("f64mem", TYPE_M64FP)
Chris Lattnerb2ef4c12010-09-29 02:57:56 +00001086 TYPE("sdmem", TYPE_M64FP)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001087 TYPE("FR32", TYPE_XMM32)
1088 TYPE("f32mem", TYPE_M32FP)
Chris Lattnerb2ef4c12010-09-29 02:57:56 +00001089 TYPE("ssmem", TYPE_M32FP)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001090 TYPE("RST", TYPE_ST)
1091 TYPE("i128mem", TYPE_M128)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001092 TYPE("i256mem", TYPE_M256)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001093 TYPE("i64i32imm_pcrel", TYPE_REL64)
Chris Lattner9fc05222010-07-07 22:27:31 +00001094 TYPE("i16imm_pcrel", TYPE_REL16)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001095 TYPE("i32imm_pcrel", TYPE_REL32)
Sean Callanan5edca812010-04-07 21:42:19 +00001096 TYPE("SSECC", TYPE_IMM3)
Craig Topper769bbfd2012-04-03 05:20:24 +00001097 TYPE("AVXCC", TYPE_IMM5)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001098 TYPE("brtarget", TYPE_RELv)
Owen Andersonc2666002010-12-13 19:31:11 +00001099 TYPE("uncondbrtarget", TYPE_RELv)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001100 TYPE("brtarget8", TYPE_REL8)
1101 TYPE("f80mem", TYPE_M80FP)
Sean Callanan7fb35a22009-12-22 21:12:55 +00001102 TYPE("lea32mem", TYPE_LEA)
1103 TYPE("lea64_32mem", TYPE_LEA)
1104 TYPE("lea64mem", TYPE_LEA)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001105 TYPE("VR64", TYPE_MM64)
1106 TYPE("i64imm", TYPE_IMMv)
1107 TYPE("opaque32mem", TYPE_M1616)
1108 TYPE("opaque48mem", TYPE_M1632)
1109 TYPE("opaque80mem", TYPE_M1664)
1110 TYPE("opaque512mem", TYPE_M512)
1111 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1112 TYPE("DEBUG_REG", TYPE_DEBUGREG)
Sean Callanan1a8b7892010-05-06 20:59:00 +00001113 TYPE("CONTROL_REG", TYPE_CONTROLREG)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001114 TYPE("offset8", TYPE_MOFFS8)
1115 TYPE("offset16", TYPE_MOFFS16)
1116 TYPE("offset32", TYPE_MOFFS32)
1117 TYPE("offset64", TYPE_MOFFS64)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001118 TYPE("VR256", TYPE_XMM256)
Craig Topper7ea16b02011-10-06 06:44:41 +00001119 TYPE("GR16_NOAX", TYPE_Rv)
1120 TYPE("GR32_NOAX", TYPE_Rv)
1121 TYPE("GR64_NOAX", TYPE_R64)
Craig Topper75dc33a2012-07-18 04:11:12 +00001122 TYPE("vx32mem", TYPE_M32)
1123 TYPE("vy32mem", TYPE_M32)
1124 TYPE("vx64mem", TYPE_M64)
1125 TYPE("vy64mem", TYPE_M64)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001126 errs() << "Unhandled type string " << s << "\n";
1127 llvm_unreachable("Unhandled type string");
1128}
1129#undef TYPE
1130
1131#define ENCODING(str, encoding) if (s == str) return encoding;
1132OperandEncoding RecognizableInstr::immediateEncodingFromString
1133 (const std::string &s,
1134 bool hasOpSizePrefix) {
1135 if(!hasOpSizePrefix) {
1136 // For instructions without an OpSize prefix, a declared 16-bit register or
1137 // immediate encoding is special.
1138 ENCODING("i16imm", ENCODING_IW)
1139 }
1140 ENCODING("i32i8imm", ENCODING_IB)
Kevin Enderbyc37d4bb2011-07-27 23:01:50 +00001141 ENCODING("u32u8imm", ENCODING_IB)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001142 ENCODING("SSECC", ENCODING_IB)
Craig Topper769bbfd2012-04-03 05:20:24 +00001143 ENCODING("AVXCC", ENCODING_IB)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001144 ENCODING("i16imm", ENCODING_Iv)
1145 ENCODING("i16i8imm", ENCODING_IB)
1146 ENCODING("i32imm", ENCODING_Iv)
1147 ENCODING("i64i32imm", ENCODING_ID)
1148 ENCODING("i64i8imm", ENCODING_IB)
1149 ENCODING("i8imm", ENCODING_IB)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001150 // This is not a typo. Instructions like BLENDVPD put
1151 // register IDs in 8-bit immediates nowadays.
1152 ENCODING("VR256", ENCODING_IB)
1153 ENCODING("VR128", ENCODING_IB)
Craig Topperbf404372012-08-31 15:40:30 +00001154 ENCODING("FR32", ENCODING_IB)
1155 ENCODING("FR64", ENCODING_IB)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001156 errs() << "Unhandled immediate encoding " << s << "\n";
1157 llvm_unreachable("Unhandled immediate encoding");
1158}
1159
1160OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1161 (const std::string &s,
1162 bool hasOpSizePrefix) {
1163 ENCODING("GR16", ENCODING_RM)
1164 ENCODING("GR32", ENCODING_RM)
1165 ENCODING("GR64", ENCODING_RM)
1166 ENCODING("GR8", ENCODING_RM)
1167 ENCODING("VR128", ENCODING_RM)
1168 ENCODING("FR64", ENCODING_RM)
1169 ENCODING("FR32", ENCODING_RM)
1170 ENCODING("VR64", ENCODING_RM)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001171 ENCODING("VR256", ENCODING_RM)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001172 errs() << "Unhandled R/M register encoding " << s << "\n";
1173 llvm_unreachable("Unhandled R/M register encoding");
1174}
1175
1176OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1177 (const std::string &s,
1178 bool hasOpSizePrefix) {
1179 ENCODING("GR16", ENCODING_REG)
1180 ENCODING("GR32", ENCODING_REG)
1181 ENCODING("GR64", ENCODING_REG)
1182 ENCODING("GR8", ENCODING_REG)
1183 ENCODING("VR128", ENCODING_REG)
1184 ENCODING("FR64", ENCODING_REG)
1185 ENCODING("FR32", ENCODING_REG)
1186 ENCODING("VR64", ENCODING_REG)
1187 ENCODING("SEGMENT_REG", ENCODING_REG)
1188 ENCODING("DEBUG_REG", ENCODING_REG)
Sean Callanan1a8b7892010-05-06 20:59:00 +00001189 ENCODING("CONTROL_REG", ENCODING_REG)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001190 ENCODING("VR256", ENCODING_REG)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001191 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1192 llvm_unreachable("Unhandled reg/opcode register encoding");
1193}
1194
Sean Callanana21e2ea2011-03-15 01:23:15 +00001195OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1196 (const std::string &s,
1197 bool hasOpSizePrefix) {
Craig Topper54a11172011-10-14 07:06:56 +00001198 ENCODING("GR32", ENCODING_VVVV)
1199 ENCODING("GR64", ENCODING_VVVV)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001200 ENCODING("FR32", ENCODING_VVVV)
1201 ENCODING("FR64", ENCODING_VVVV)
1202 ENCODING("VR128", ENCODING_VVVV)
1203 ENCODING("VR256", ENCODING_VVVV)
1204 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1205 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1206}
1207
Sean Callanan8ed9f512009-12-19 02:59:52 +00001208OperandEncoding RecognizableInstr::memoryEncodingFromString
1209 (const std::string &s,
1210 bool hasOpSizePrefix) {
1211 ENCODING("i16mem", ENCODING_RM)
1212 ENCODING("i32mem", ENCODING_RM)
1213 ENCODING("i64mem", ENCODING_RM)
1214 ENCODING("i8mem", ENCODING_RM)
Chris Lattnerb2ef4c12010-09-29 02:57:56 +00001215 ENCODING("ssmem", ENCODING_RM)
1216 ENCODING("sdmem", ENCODING_RM)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001217 ENCODING("f128mem", ENCODING_RM)
Chris Lattnerb2ef4c12010-09-29 02:57:56 +00001218 ENCODING("f256mem", ENCODING_RM)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001219 ENCODING("f64mem", ENCODING_RM)
1220 ENCODING("f32mem", ENCODING_RM)
1221 ENCODING("i128mem", ENCODING_RM)
Sean Callanana21e2ea2011-03-15 01:23:15 +00001222 ENCODING("i256mem", ENCODING_RM)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001223 ENCODING("f80mem", ENCODING_RM)
1224 ENCODING("lea32mem", ENCODING_RM)
1225 ENCODING("lea64_32mem", ENCODING_RM)
1226 ENCODING("lea64mem", ENCODING_RM)
1227 ENCODING("opaque32mem", ENCODING_RM)
1228 ENCODING("opaque48mem", ENCODING_RM)
1229 ENCODING("opaque80mem", ENCODING_RM)
1230 ENCODING("opaque512mem", ENCODING_RM)
Craig Topper75dc33a2012-07-18 04:11:12 +00001231 ENCODING("vx32mem", ENCODING_RM)
1232 ENCODING("vy32mem", ENCODING_RM)
1233 ENCODING("vx64mem", ENCODING_RM)
1234 ENCODING("vy64mem", ENCODING_RM)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001235 errs() << "Unhandled memory encoding " << s << "\n";
1236 llvm_unreachable("Unhandled memory encoding");
1237}
1238
1239OperandEncoding RecognizableInstr::relocationEncodingFromString
1240 (const std::string &s,
1241 bool hasOpSizePrefix) {
1242 if(!hasOpSizePrefix) {
1243 // For instructions without an OpSize prefix, a declared 16-bit register or
1244 // immediate encoding is special.
1245 ENCODING("i16imm", ENCODING_IW)
1246 }
1247 ENCODING("i16imm", ENCODING_Iv)
1248 ENCODING("i16i8imm", ENCODING_IB)
1249 ENCODING("i32imm", ENCODING_Iv)
1250 ENCODING("i32i8imm", ENCODING_IB)
1251 ENCODING("i64i32imm", ENCODING_ID)
1252 ENCODING("i64i8imm", ENCODING_IB)
1253 ENCODING("i8imm", ENCODING_IB)
1254 ENCODING("i64i32imm_pcrel", ENCODING_ID)
Chris Lattner9fc05222010-07-07 22:27:31 +00001255 ENCODING("i16imm_pcrel", ENCODING_IW)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001256 ENCODING("i32imm_pcrel", ENCODING_ID)
1257 ENCODING("brtarget", ENCODING_Iv)
1258 ENCODING("brtarget8", ENCODING_IB)
1259 ENCODING("i64imm", ENCODING_IO)
1260 ENCODING("offset8", ENCODING_Ia)
1261 ENCODING("offset16", ENCODING_Ia)
1262 ENCODING("offset32", ENCODING_Ia)
1263 ENCODING("offset64", ENCODING_Ia)
1264 errs() << "Unhandled relocation encoding " << s << "\n";
1265 llvm_unreachable("Unhandled relocation encoding");
1266}
1267
1268OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1269 (const std::string &s,
1270 bool hasOpSizePrefix) {
1271 ENCODING("RST", ENCODING_I)
1272 ENCODING("GR32", ENCODING_Rv)
1273 ENCODING("GR64", ENCODING_RO)
1274 ENCODING("GR16", ENCODING_Rv)
1275 ENCODING("GR8", ENCODING_RB)
Craig Topper7ea16b02011-10-06 06:44:41 +00001276 ENCODING("GR16_NOAX", ENCODING_Rv)
1277 ENCODING("GR32_NOAX", ENCODING_Rv)
1278 ENCODING("GR64_NOAX", ENCODING_RO)
Sean Callanan8ed9f512009-12-19 02:59:52 +00001279 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1280 llvm_unreachable("Unhandled opcode modifier encoding");
1281}
Daniel Dunbar9e6d1d12009-12-19 04:16:48 +00001282#undef ENCODING