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Jia Liu31d157a2012-02-18 12:03:15 +00001//===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
Bob Wilson5bafff32009-06-22 23:27:02 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the ARM NEON instruction set.
11//
12//===----------------------------------------------------------------------===//
13
Jim Grosbach460a9052011-10-07 23:56:00 +000014
15//===----------------------------------------------------------------------===//
16// NEON-specific Operands.
17//===----------------------------------------------------------------------===//
Jim Grosbach698f3b02011-10-17 21:00:11 +000018def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
20}
21
Jim Grosbach0e387b22011-10-17 22:26:03 +000022def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
26}
Jim Grosbachea461102011-10-17 23:09:09 +000027def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
31}
Jim Grosbach6248a542011-10-18 00:22:00 +000032def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
36}
37def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
41}
Jim Grosbach9b087852011-12-19 23:51:07 +000042def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
46}
Evan Chengeaa192a2011-11-15 02:12:34 +000047def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
50}
Jim Grosbachf2f5bc62011-10-18 16:18:11 +000051def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
55}
Jim Grosbach0e387b22011-10-17 22:26:03 +000056
Jim Grosbach460a9052011-10-07 23:56:00 +000057def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
62}]> {
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
66}
67def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
69}]> {
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
73}
74def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
76}]> {
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
80}
81
Jim Grosbachbd1cff52011-11-29 23:33:40 +000082// Register list of one D register.
Jim Grosbach862019c2011-10-18 23:02:30 +000083def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
Jim Grosbach6029b6d2011-11-29 23:51:09 +000086 let RenderMethod = "addVecListOperands";
Jim Grosbach862019c2011-10-18 23:02:30 +000087}
88def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
90}
Jim Grosbach280dfad2011-10-21 18:54:25 +000091// Register list of two sequential D registers.
Jim Grosbach28f08c92012-03-05 19:33:30 +000092def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
96}
Jim Grosbachc0fc4502012-03-06 22:01:44 +000097def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
Jim Grosbach28f08c92012-03-05 19:33:30 +000098 let ParserMatchClass = VecListDPairAsmOperand;
99}
Jim Grosbachcdcfa282011-10-21 20:02:19 +0000100// Register list of three sequential D registers.
101def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
Jim Grosbach6029b6d2011-11-29 23:51:09 +0000104 let RenderMethod = "addVecListOperands";
Jim Grosbachcdcfa282011-10-21 20:02:19 +0000105}
106def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
108}
Jim Grosbachb6310312011-10-21 20:35:01 +0000109// Register list of four sequential D registers.
110def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
Jim Grosbach6029b6d2011-11-29 23:51:09 +0000113 let RenderMethod = "addVecListOperands";
Jim Grosbachb6310312011-10-21 20:35:01 +0000114}
115def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
117}
Jim Grosbach4661d4c2011-10-21 22:21:10 +0000118// Register list of two D registers spaced by 2 (two sequential Q registers).
Jim Grosbachc3384c92012-03-05 21:43:40 +0000119def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
Jim Grosbach4661d4c2011-10-21 22:21:10 +0000121 let ParserMethod = "parseVectorList";
Jim Grosbach6029b6d2011-11-29 23:51:09 +0000122 let RenderMethod = "addVecListOperands";
Jim Grosbach4661d4c2011-10-21 22:21:10 +0000123}
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000124def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
Jim Grosbachc3384c92012-03-05 21:43:40 +0000125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
Jim Grosbach4661d4c2011-10-21 22:21:10 +0000126}
Jim Grosbachc387fc62012-01-23 23:20:46 +0000127// Register list of three D registers spaced by 2 (three Q registers).
128def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
132}
133def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
135}
Jim Grosbach8abe7e32012-01-24 00:43:17 +0000136// Register list of three D registers spaced by 2 (three Q registers).
137def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
141}
142def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
144}
Jim Grosbach862019c2011-10-18 23:02:30 +0000145
Jim Grosbach98b05a52011-11-30 01:09:44 +0000146// Register list of one D register, with "all lanes" subscripting.
147def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
151}
152def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
154}
Jim Grosbach13af2222011-11-30 18:21:25 +0000155// Register list of two D registers, with "all lanes" subscripting.
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000156def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
Jim Grosbach13af2222011-11-30 18:21:25 +0000158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
160}
Jim Grosbachc0fc4502012-03-06 22:01:44 +0000161def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
Jim Grosbach13af2222011-11-30 18:21:25 +0000164}
Jim Grosbach3471d4f2011-12-21 00:38:54 +0000165// Register list of two D registers spaced by 2 (two sequential Q registers).
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000166def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
Jim Grosbach3471d4f2011-12-21 00:38:54 +0000168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
170}
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000171def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
Jim Grosbach3471d4f2011-12-21 00:38:54 +0000172 "printVectorListTwoSpacedAllLanes"> {
Jim Grosbach4d0983a2012-03-06 23:10:38 +0000173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
Jim Grosbach3471d4f2011-12-21 00:38:54 +0000174}
Jim Grosbach5e59f7e2012-01-24 23:47:04 +0000175// Register list of three D registers, with "all lanes" subscripting.
176def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
180}
181def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
184}
185// Register list of three D registers spaced by 2 (three sequential Q regs).
186def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
190}
191def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
194}
Jim Grosbacha57a36a2012-01-25 00:01:08 +0000195// Register list of four D registers, with "all lanes" subscripting.
196def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
200}
201def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
203}
204// Register list of four D registers spaced by 2 (four sequential Q regs).
205def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
209}
210def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
213}
Jim Grosbach5e59f7e2012-01-24 23:47:04 +0000214
Jim Grosbach98b05a52011-11-30 01:09:44 +0000215
Jim Grosbach7636bf62011-12-02 00:35:16 +0000216// Register list of one D register, with byte lane subscripting.
217def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
221}
222def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
225}
Jim Grosbach799ca9d2011-12-14 23:35:06 +0000226// ...with half-word lane subscripting.
227def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
231}
232def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
235}
236// ...with word lane subscripting.
237def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
241}
242def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
245}
Jim Grosbach3a678af2012-01-23 21:53:26 +0000246
Jim Grosbach95fad1c2011-12-20 19:21:26 +0000247// Register list of two D registers with byte lane subscripting.
Jim Grosbach9b1b3902011-12-14 23:25:46 +0000248def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
252}
253def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
256}
Jim Grosbach799ca9d2011-12-14 23:35:06 +0000257// ...with half-word lane subscripting.
258def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
262}
263def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
266}
267// ...with word lane subscripting.
268def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
272}
273def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
276}
Jim Grosbach95fad1c2011-12-20 19:21:26 +0000277// Register list of two Q registers with half-word lane subscripting.
278def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
282}
283def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
286}
287// ...with word lane subscripting.
288def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
292}
293def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
296}
Jim Grosbach7636bf62011-12-02 00:35:16 +0000297
Jim Grosbach3a678af2012-01-23 21:53:26 +0000298
299// Register list of three D registers with byte lane subscripting.
300def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
304}
305def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
308}
309// ...with half-word lane subscripting.
310def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
314}
315def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
318}
319// ...with word lane subscripting.
320def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
324}
325def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
328}
329// Register list of three Q registers with half-word lane subscripting.
330def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
334}
335def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
338}
339// ...with word lane subscripting.
340def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
344}
345def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
348}
349
Jim Grosbache983a132012-01-24 18:37:25 +0000350// Register list of four D registers with byte lane subscripting.
351def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
355}
356def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
359}
360// ...with half-word lane subscripting.
361def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
365}
366def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
369}
370// ...with word lane subscripting.
371def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
375}
376def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
379}
380// Register list of four Q registers with half-word lane subscripting.
381def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
385}
386def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
389}
390// ...with word lane subscripting.
391def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
395}
396def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
399}
400
Jim Grosbach3a678af2012-01-23 21:53:26 +0000401
Bob Wilson5bafff32009-06-22 23:27:02 +0000402//===----------------------------------------------------------------------===//
403// NEON-specific DAG Nodes.
404//===----------------------------------------------------------------------===//
405
406def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
Owen Andersonc24cb352010-11-08 23:21:22 +0000407def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
Bob Wilson5bafff32009-06-22 23:27:02 +0000408
409def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
Owen Andersonc24cb352010-11-08 23:21:22 +0000410def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
Bob Wilson5bafff32009-06-22 23:27:02 +0000411def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
Owen Andersonc24cb352010-11-08 23:21:22 +0000412def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
413def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
Bob Wilson5bafff32009-06-22 23:27:02 +0000414def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
415def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
Owen Andersonc24cb352010-11-08 23:21:22 +0000416def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
417def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
Bob Wilson5bafff32009-06-22 23:27:02 +0000418def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
419def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
420
421// Types for vector shift by immediates. The "SHX" version is for long and
422// narrow operations where the source and destination vectors have different
423// types. The "SHINS" version is for shift and insert operations.
424def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
425 SDTCisVT<2, i32>]>;
426def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
427 SDTCisVT<2, i32>]>;
428def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
429 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
430
431def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
432def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
433def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
434def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
435def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
436def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
437def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
438
439def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
440def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
441def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
442
443def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
444def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
445def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
446def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
447def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
448def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
449
450def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
451def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
452def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
453
454def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
455def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
456
457def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
458 SDTCisVT<2, i32>]>;
459def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
460def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
461
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000462def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
463def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
464def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
Evan Chengeaa192a2011-11-15 02:12:34 +0000465def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000466
Owen Andersond9668172010-11-03 22:44:51 +0000467def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
468 SDTCisVT<2, i32>]>;
469def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
Owen Anderson080c0922010-11-05 19:27:46 +0000470def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
Owen Andersond9668172010-11-03 22:44:51 +0000471
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000472def NEONvbsl : SDNode<"ARMISD::VBSL",
473 SDTypeProfile<1, 3, [SDTCisVec<0>,
474 SDTCisSameAs<0, 1>,
475 SDTCisSameAs<0, 2>,
476 SDTCisSameAs<0, 3>]>>;
477
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000478def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
479
Bob Wilson0ce37102009-08-14 05:08:32 +0000480// VDUPLANE can produce a quad-register result from a double-register source,
481// so the result is not constrained to match the source.
482def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
483 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
484 SDTCisVT<2, i32>]>>;
Bob Wilson5bafff32009-06-22 23:27:02 +0000485
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000486def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
487 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
488def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
489
Bob Wilsond8e17572009-08-12 22:31:50 +0000490def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
491def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
492def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
493def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
494
Anton Korobeynikov62e84f12009-08-21 12:40:50 +0000495def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
Bob Wilson9abe19d2010-02-17 00:31:29 +0000496 SDTCisSameAs<0, 2>,
497 SDTCisSameAs<0, 3>]>;
Anton Korobeynikov051cfd62009-08-21 12:41:42 +0000498def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
499def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
500def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
Anton Korobeynikov62e84f12009-08-21 12:40:50 +0000501
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000502def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
503 SDTCisSameAs<1, 2>]>;
504def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
505def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
506
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000507def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
508 SDTCisSameAs<0, 2>]>;
509def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
510def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
511
Bob Wilsoncba270d2010-07-13 21:16:48 +0000512def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
513 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
Daniel Dunbar425f6342010-07-31 21:08:54 +0000514 unsigned EltBits = 0;
Bob Wilsoncba270d2010-07-13 21:16:48 +0000515 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
516 return (EltBits == 32 && EltVal == 0);
517}]>;
518
519def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
520 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
Daniel Dunbar425f6342010-07-31 21:08:54 +0000521 unsigned EltBits = 0;
Bob Wilsoncba270d2010-07-13 21:16:48 +0000522 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
523 return (EltBits == 8 && EltVal == 0xff);
524}]>;
525
Bob Wilson5bafff32009-06-22 23:27:02 +0000526//===----------------------------------------------------------------------===//
Bob Wilson5bafff32009-06-22 23:27:02 +0000527// NEON load / store instructions
528//===----------------------------------------------------------------------===//
529
Bob Wilson9d4ebc02010-09-16 00:31:02 +0000530// Use VLDM to load a Q register as a D register pair.
531// This is a pseudo instruction that is expanded to VLDMD after reg alloc.
Bill Wendling73fe34a2010-11-16 01:16:36 +0000532def VLDMQIA
Jakob Stoklund Olesen5b2f9132012-03-28 21:20:32 +0000533 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
Bill Wendling73fe34a2010-11-16 01:16:36 +0000534 IIC_fpLoad_m, "",
Jakob Stoklund Olesen5b2f9132012-03-28 21:20:32 +0000535 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
Evan Cheng69b9f982010-05-13 01:12:06 +0000536
Bob Wilson9d4ebc02010-09-16 00:31:02 +0000537// Use VSTM to store a Q register as a D register pair.
538// This is a pseudo instruction that is expanded to VSTMD after reg alloc.
Bill Wendling73fe34a2010-11-16 01:16:36 +0000539def VSTMQIA
Jakob Stoklund Olesen5b2f9132012-03-28 21:20:32 +0000540 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
Bill Wendling73fe34a2010-11-16 01:16:36 +0000541 IIC_fpStore_m, "",
Jakob Stoklund Olesen5b2f9132012-03-28 21:20:32 +0000542 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
Evan Cheng69b9f982010-05-13 01:12:06 +0000543
Bob Wilsonffde0802010-09-02 16:00:54 +0000544// Classes for VLD* pseudo-instructions with multi-register operands.
545// These are expanded to real instructions after register allocation.
Bob Wilson9d84fb32010-09-14 20:59:49 +0000546class VLDQPseudo<InstrItinClass itin>
547 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
548class VLDQWBPseudo<InstrItinClass itin>
Bob Wilsonffde0802010-09-02 16:00:54 +0000549 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
Bob Wilson9d84fb32010-09-14 20:59:49 +0000550 (ins addrmode6:$addr, am6offset:$offset), itin,
Bob Wilsonffde0802010-09-02 16:00:54 +0000551 "$addr.addr = $wb">;
Jim Grosbach10b90a92011-10-24 21:45:13 +0000552class VLDQWBfixedPseudo<InstrItinClass itin>
553 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
554 (ins addrmode6:$addr), itin,
555 "$addr.addr = $wb">;
556class VLDQWBregisterPseudo<InstrItinClass itin>
557 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
558 (ins addrmode6:$addr, rGPR:$offset), itin,
559 "$addr.addr = $wb">;
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000560
Bob Wilson9d84fb32010-09-14 20:59:49 +0000561class VLDQQPseudo<InstrItinClass itin>
562 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
563class VLDQQWBPseudo<InstrItinClass itin>
Bob Wilsonffde0802010-09-02 16:00:54 +0000564 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
Bob Wilson9d84fb32010-09-14 20:59:49 +0000565 (ins addrmode6:$addr, am6offset:$offset), itin,
Bob Wilsonffde0802010-09-02 16:00:54 +0000566 "$addr.addr = $wb">;
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000567class VLDQQWBfixedPseudo<InstrItinClass itin>
568 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
569 (ins addrmode6:$addr), itin,
570 "$addr.addr = $wb">;
571class VLDQQWBregisterPseudo<InstrItinClass itin>
572 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
573 (ins addrmode6:$addr, rGPR:$offset), itin,
574 "$addr.addr = $wb">;
575
576
Bob Wilson7de68142011-02-07 17:43:15 +0000577class VLDQQQQPseudo<InstrItinClass itin>
Bob Wilson9a450082011-08-05 07:24:09 +0000578 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
579 "$src = $dst">;
Bob Wilson9d84fb32010-09-14 20:59:49 +0000580class VLDQQQQWBPseudo<InstrItinClass itin>
Bob Wilsonf5721912010-09-03 18:16:02 +0000581 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
Bob Wilson9d84fb32010-09-14 20:59:49 +0000582 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
Bob Wilsonf5721912010-09-03 18:16:02 +0000583 "$addr.addr = $wb, $src = $dst">;
Bob Wilsonffde0802010-09-02 16:00:54 +0000584
Bob Wilson2a0e9742010-11-27 06:35:16 +0000585let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
586
Bob Wilson205a5ca2009-07-08 18:11:30 +0000587// VLD1 : Vector Load (multiple single elements)
Bob Wilson621f1952010-03-23 05:25:43 +0000588class VLD1D<bits<4> op7_4, string Dt>
Jim Grosbach6b09c772011-10-20 15:04:25 +0000589 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
Owen Andersonf431eda2010-11-02 23:47:29 +0000590 (ins addrmode6:$Rn), IIC_VLD1,
Jim Grosbach6b09c772011-10-20 15:04:25 +0000591 "vld1", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000592 let Rm = 0b1111;
593 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000594 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersond9aa7d32010-11-02 00:05:05 +0000595}
Bob Wilson621f1952010-03-23 05:25:43 +0000596class VLD1Q<bits<4> op7_4, string Dt>
Jim Grosbach28f08c92012-03-05 19:33:30 +0000597 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
Owen Andersonf431eda2010-11-02 23:47:29 +0000598 (ins addrmode6:$Rn), IIC_VLD1x2,
Jim Grosbach280dfad2011-10-21 18:54:25 +0000599 "vld1", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000600 let Rm = 0b1111;
601 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000602 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersond9aa7d32010-11-02 00:05:05 +0000603}
Bob Wilson205a5ca2009-07-08 18:11:30 +0000604
Owen Andersond9aa7d32010-11-02 00:05:05 +0000605def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
606def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
607def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
608def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
Bob Wilson205a5ca2009-07-08 18:11:30 +0000609
Owen Andersond9aa7d32010-11-02 00:05:05 +0000610def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
611def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
612def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
613def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
Bob Wilson99493b22010-03-20 17:59:03 +0000614
615// ...with address register writeback:
Jim Grosbach10b90a92011-10-24 21:45:13 +0000616multiclass VLD1DWB<bits<4> op7_4, string Dt> {
617 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
618 (ins addrmode6:$Rn), IIC_VLD1u,
619 "vld1", Dt, "$Vd, $Rn!",
620 "$Rn.addr = $wb", []> {
621 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
622 let Inst{4} = Rn{4};
623 let DecoderMethod = "DecodeVLDInstruction";
Jim Grosbach12431322011-10-24 22:16:58 +0000624 let AsmMatchConverter = "cvtVLDwbFixed";
Jim Grosbach10b90a92011-10-24 21:45:13 +0000625 }
626 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
627 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
628 "vld1", Dt, "$Vd, $Rn, $Rm",
629 "$Rn.addr = $wb", []> {
630 let Inst{4} = Rn{4};
631 let DecoderMethod = "DecodeVLDInstruction";
Jim Grosbach12431322011-10-24 22:16:58 +0000632 let AsmMatchConverter = "cvtVLDwbRegister";
Jim Grosbach10b90a92011-10-24 21:45:13 +0000633 }
Owen Andersone85bd772010-11-02 00:24:52 +0000634}
Jim Grosbach10b90a92011-10-24 21:45:13 +0000635multiclass VLD1QWB<bits<4> op7_4, string Dt> {
Jim Grosbach28f08c92012-03-05 19:33:30 +0000636 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
Jim Grosbach10b90a92011-10-24 21:45:13 +0000637 (ins addrmode6:$Rn), IIC_VLD1x2u,
638 "vld1", Dt, "$Vd, $Rn!",
639 "$Rn.addr = $wb", []> {
640 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
641 let Inst{5-4} = Rn{5-4};
642 let DecoderMethod = "DecodeVLDInstruction";
Jim Grosbach12431322011-10-24 22:16:58 +0000643 let AsmMatchConverter = "cvtVLDwbFixed";
Jim Grosbach10b90a92011-10-24 21:45:13 +0000644 }
Jim Grosbach28f08c92012-03-05 19:33:30 +0000645 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
Jim Grosbach10b90a92011-10-24 21:45:13 +0000646 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
647 "vld1", Dt, "$Vd, $Rn, $Rm",
648 "$Rn.addr = $wb", []> {
649 let Inst{5-4} = Rn{5-4};
650 let DecoderMethod = "DecodeVLDInstruction";
Jim Grosbach12431322011-10-24 22:16:58 +0000651 let AsmMatchConverter = "cvtVLDwbRegister";
Jim Grosbach10b90a92011-10-24 21:45:13 +0000652 }
Owen Andersone85bd772010-11-02 00:24:52 +0000653}
Bob Wilson99493b22010-03-20 17:59:03 +0000654
Jim Grosbach10b90a92011-10-24 21:45:13 +0000655defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
656defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
657defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
658defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
659defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
660defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
661defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
662defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
Bob Wilson99493b22010-03-20 17:59:03 +0000663
Jim Grosbachfe7b4992011-10-21 16:14:12 +0000664// ...with 3 registers
Bob Wilson95808322010-03-18 20:18:39 +0000665class VLD1D3<bits<4> op7_4, string Dt>
Jim Grosbachcdcfa282011-10-21 20:02:19 +0000666 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
Owen Andersonf431eda2010-11-02 23:47:29 +0000667 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
Jim Grosbachcdcfa282011-10-21 20:02:19 +0000668 "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000669 let Rm = 0b1111;
670 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000671 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersone85bd772010-11-02 00:24:52 +0000672}
Jim Grosbach59216752011-10-24 23:26:05 +0000673multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
674 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
675 (ins addrmode6:$Rn), IIC_VLD1x2u,
676 "vld1", Dt, "$Vd, $Rn!",
677 "$Rn.addr = $wb", []> {
678 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
Owen Andersonb3727fe2011-10-28 20:43:24 +0000679 let Inst{4} = Rn{4};
Jim Grosbach59216752011-10-24 23:26:05 +0000680 let DecoderMethod = "DecodeVLDInstruction";
681 let AsmMatchConverter = "cvtVLDwbFixed";
682 }
683 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
684 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
685 "vld1", Dt, "$Vd, $Rn, $Rm",
686 "$Rn.addr = $wb", []> {
Owen Andersonb3727fe2011-10-28 20:43:24 +0000687 let Inst{4} = Rn{4};
Jim Grosbach59216752011-10-24 23:26:05 +0000688 let DecoderMethod = "DecodeVLDInstruction";
689 let AsmMatchConverter = "cvtVLDwbRegister";
690 }
Owen Andersone85bd772010-11-02 00:24:52 +0000691}
Bob Wilson052ba452010-03-22 18:22:06 +0000692
Owen Andersone85bd772010-11-02 00:24:52 +0000693def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
694def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
695def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
696def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
Bob Wilson052ba452010-03-22 18:22:06 +0000697
Jim Grosbach59216752011-10-24 23:26:05 +0000698defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
699defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
700defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
701defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
Bob Wilson052ba452010-03-22 18:22:06 +0000702
Jim Grosbach59216752011-10-24 23:26:05 +0000703def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
Bob Wilsonffde0802010-09-02 16:00:54 +0000704
Jim Grosbachfe7b4992011-10-21 16:14:12 +0000705// ...with 4 registers
Bob Wilson052ba452010-03-22 18:22:06 +0000706class VLD1D4<bits<4> op7_4, string Dt>
Jim Grosbachb6310312011-10-21 20:35:01 +0000707 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
Owen Andersonf431eda2010-11-02 23:47:29 +0000708 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
Jim Grosbachb6310312011-10-21 20:35:01 +0000709 "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000710 let Rm = 0b1111;
711 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000712 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersone85bd772010-11-02 00:24:52 +0000713}
Jim Grosbach399cdca2011-10-25 00:14:01 +0000714multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
715 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
716 (ins addrmode6:$Rn), IIC_VLD1x2u,
717 "vld1", Dt, "$Vd, $Rn!",
718 "$Rn.addr = $wb", []> {
719 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
720 let Inst{5-4} = Rn{5-4};
721 let DecoderMethod = "DecodeVLDInstruction";
722 let AsmMatchConverter = "cvtVLDwbFixed";
723 }
724 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
725 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
726 "vld1", Dt, "$Vd, $Rn, $Rm",
727 "$Rn.addr = $wb", []> {
728 let Inst{5-4} = Rn{5-4};
729 let DecoderMethod = "DecodeVLDInstruction";
730 let AsmMatchConverter = "cvtVLDwbRegister";
731 }
Owen Andersone85bd772010-11-02 00:24:52 +0000732}
Johnny Chend7283d92010-02-23 20:51:23 +0000733
Owen Andersone85bd772010-11-02 00:24:52 +0000734def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
735def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
736def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
737def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
Bob Wilson99493b22010-03-20 17:59:03 +0000738
Jim Grosbach399cdca2011-10-25 00:14:01 +0000739defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
740defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
741defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
742defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
Bob Wilson9f7d60f2009-08-12 17:04:56 +0000743
Jim Grosbach399cdca2011-10-25 00:14:01 +0000744def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
Bob Wilsonffde0802010-09-02 16:00:54 +0000745
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000746// VLD2 : Vector Load (multiple 2-element structures)
Jim Grosbach2af50d92011-12-09 19:07:20 +0000747class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
748 InstrItinClass itin>
Jim Grosbach4661d4c2011-10-21 22:21:10 +0000749 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
Jim Grosbach2af50d92011-12-09 19:07:20 +0000750 (ins addrmode6:$Rn), itin,
Jim Grosbach224180e2011-10-21 23:58:57 +0000751 "vld2", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000752 let Rm = 0b1111;
753 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000754 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersoncf667be2010-11-02 01:24:55 +0000755}
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000756
Jim Grosbach28f08c92012-03-05 19:33:30 +0000757def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
758def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
759def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000760
Jim Grosbach2af50d92011-12-09 19:07:20 +0000761def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
762def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
763def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
Bob Wilson3bf12ab2009-10-06 22:01:59 +0000764
Evan Chengd2ca8132010-10-09 01:03:04 +0000765def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
766def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
767def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
Bob Wilsonffde0802010-09-02 16:00:54 +0000768
Bob Wilson92cb9322010-03-20 20:10:51 +0000769// ...with address register writeback:
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000770multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
771 RegisterOperand VdTy, InstrItinClass itin> {
772 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
773 (ins addrmode6:$Rn), itin,
774 "vld2", Dt, "$Vd, $Rn!",
775 "$Rn.addr = $wb", []> {
776 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
777 let Inst{5-4} = Rn{5-4};
778 let DecoderMethod = "DecodeVLDInstruction";
779 let AsmMatchConverter = "cvtVLDwbFixed";
780 }
781 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
782 (ins addrmode6:$Rn, rGPR:$Rm), itin,
783 "vld2", Dt, "$Vd, $Rn, $Rm",
784 "$Rn.addr = $wb", []> {
785 let Inst{5-4} = Rn{5-4};
786 let DecoderMethod = "DecodeVLDInstruction";
787 let AsmMatchConverter = "cvtVLDwbRegister";
788 }
Owen Andersoncf667be2010-11-02 01:24:55 +0000789}
Bob Wilson92cb9322010-03-20 20:10:51 +0000790
Jim Grosbach28f08c92012-03-05 19:33:30 +0000791defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
792defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
793defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
Bob Wilson92cb9322010-03-20 20:10:51 +0000794
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000795defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
796defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
797defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
Bob Wilson92cb9322010-03-20 20:10:51 +0000798
Jim Grosbacha4e3c7f2011-12-09 21:28:25 +0000799def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
800def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
801def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
802def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
803def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
804def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
Bob Wilsonffde0802010-09-02 16:00:54 +0000805
Jim Grosbachfe7b4992011-10-21 16:14:12 +0000806// ...with double-spaced registers
Jim Grosbachc3384c92012-03-05 21:43:40 +0000807def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
808def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
809def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
810defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
811defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
812defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
Johnny Chend7283d92010-02-23 20:51:23 +0000813
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000814// VLD3 : Vector Load (multiple 3-element structures)
Bob Wilson00bf1d92010-03-20 18:14:26 +0000815class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersoncf667be2010-11-02 01:24:55 +0000816 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
Owen Andersonf431eda2010-11-02 23:47:29 +0000817 (ins addrmode6:$Rn), IIC_VLD3,
818 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
819 let Rm = 0b1111;
820 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000821 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersoncf667be2010-11-02 01:24:55 +0000822}
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000823
Owen Andersoncf667be2010-11-02 01:24:55 +0000824def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
825def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
826def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000827
Bob Wilson9d84fb32010-09-14 20:59:49 +0000828def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
829def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
830def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000831
Bob Wilson92cb9322010-03-20 20:10:51 +0000832// ...with address register writeback:
833class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
834 : NLdSt<0, 0b10, op11_8, op7_4,
Owen Andersoncf667be2010-11-02 01:24:55 +0000835 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +0000836 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
837 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
838 "$Rn.addr = $wb", []> {
839 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000840 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersoncf667be2010-11-02 01:24:55 +0000841}
Bob Wilson92cb9322010-03-20 20:10:51 +0000842
Owen Andersoncf667be2010-11-02 01:24:55 +0000843def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
844def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
845def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
Bob Wilson92cb9322010-03-20 20:10:51 +0000846
Evan Cheng84f69e82010-10-09 01:45:34 +0000847def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
848def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
849def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000850
Bob Wilson7de68142011-02-07 17:43:15 +0000851// ...with double-spaced registers:
Owen Andersoncf667be2010-11-02 01:24:55 +0000852def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
853def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
854def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
855def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
856def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
857def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
Bob Wilson00bf1d92010-03-20 18:14:26 +0000858
Evan Cheng84f69e82010-10-09 01:45:34 +0000859def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
860def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
861def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000862
Bob Wilson92cb9322010-03-20 20:10:51 +0000863// ...alternate versions to be allocated odd register numbers:
Bob Wilson7de68142011-02-07 17:43:15 +0000864def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
865def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
866def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
867
Evan Cheng84f69e82010-10-09 01:45:34 +0000868def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
869def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
870def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
Bob Wilsonff8952e2009-10-07 17:24:55 +0000871
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000872// VLD4 : Vector Load (multiple 4-element structures)
Bob Wilson00bf1d92010-03-20 18:14:26 +0000873class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
874 : NLdSt<0, 0b10, op11_8, op7_4,
Owen Andersoncf667be2010-11-02 01:24:55 +0000875 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
Owen Andersonf431eda2010-11-02 23:47:29 +0000876 (ins addrmode6:$Rn), IIC_VLD4,
877 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
878 let Rm = 0b1111;
879 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000880 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersoncf667be2010-11-02 01:24:55 +0000881}
Bob Wilson4a3d35a2009-08-05 00:49:09 +0000882
Owen Andersoncf667be2010-11-02 01:24:55 +0000883def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
884def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
885def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
Bob Wilson243fcc52009-09-01 04:26:28 +0000886
Bob Wilson9d84fb32010-09-14 20:59:49 +0000887def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
888def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
889def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000890
Bob Wilson92cb9322010-03-20 20:10:51 +0000891// ...with address register writeback:
892class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
893 : NLdSt<0, 0b10, op11_8, op7_4,
Owen Andersoncf667be2010-11-02 01:24:55 +0000894 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
Bob Wilson6eb08dd2011-02-07 17:43:12 +0000895 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
Owen Andersonf431eda2010-11-02 23:47:29 +0000896 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
897 "$Rn.addr = $wb", []> {
898 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +0000899 let DecoderMethod = "DecodeVLDInstruction";
Owen Andersoncf667be2010-11-02 01:24:55 +0000900}
Bob Wilson92cb9322010-03-20 20:10:51 +0000901
Owen Andersoncf667be2010-11-02 01:24:55 +0000902def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
903def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
904def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
Bob Wilson92cb9322010-03-20 20:10:51 +0000905
Bob Wilson6eb08dd2011-02-07 17:43:12 +0000906def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
907def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
908def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000909
Bob Wilson7de68142011-02-07 17:43:15 +0000910// ...with double-spaced registers:
Owen Andersoncf667be2010-11-02 01:24:55 +0000911def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
912def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
913def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
914def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
915def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
916def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
Bob Wilson00bf1d92010-03-20 18:14:26 +0000917
Bob Wilson6eb08dd2011-02-07 17:43:12 +0000918def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
919def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
920def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
Bob Wilsonf5721912010-09-03 18:16:02 +0000921
Bob Wilson92cb9322010-03-20 20:10:51 +0000922// ...alternate versions to be allocated odd register numbers:
Bob Wilson6eb08dd2011-02-07 17:43:12 +0000923def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
924def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
925def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
926
927def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
928def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
929def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
Bob Wilsonb07c1712009-10-07 21:53:04 +0000930
Bob Wilsonb796bbb2010-11-01 22:04:05 +0000931} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
932
Bob Wilson8466fa12010-09-13 23:01:35 +0000933// Classes for VLD*LN pseudo-instructions with multi-register operands.
934// These are expanded to real instructions after register allocation.
935class VLDQLNPseudo<InstrItinClass itin>
936 : PseudoNLdSt<(outs QPR:$dst),
937 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
938 itin, "$src = $dst">;
939class VLDQLNWBPseudo<InstrItinClass itin>
940 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
941 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
942 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
943class VLDQQLNPseudo<InstrItinClass itin>
944 : PseudoNLdSt<(outs QQPR:$dst),
945 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
946 itin, "$src = $dst">;
947class VLDQQLNWBPseudo<InstrItinClass itin>
948 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
949 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
950 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
951class VLDQQQQLNPseudo<InstrItinClass itin>
952 : PseudoNLdSt<(outs QQQQPR:$dst),
953 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
954 itin, "$src = $dst">;
955class VLDQQQQLNWBPseudo<InstrItinClass itin>
956 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
957 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
958 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
959
Bob Wilsonb07c1712009-10-07 21:53:04 +0000960// VLD1LN : Vector Load (single element to one lane)
Bob Wilsonb796bbb2010-11-01 22:04:05 +0000961class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
962 PatFrag LoadOp>
Owen Andersond138d702010-11-02 20:47:39 +0000963 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
Owen Andersonf431eda2010-11-02 23:47:29 +0000964 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
965 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000966 "$src = $Vd",
967 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
Owen Andersonf431eda2010-11-02 23:47:29 +0000968 (i32 (LoadOp addrmode6:$Rn)),
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000969 imm:$lane))]> {
Owen Andersonf431eda2010-11-02 23:47:29 +0000970 let Rm = 0b1111;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000971 let DecoderMethod = "DecodeVLD1LN";
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000972}
Mon P Wang183c6272011-05-09 17:47:27 +0000973class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
974 PatFrag LoadOp>
975 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
976 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
977 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
978 "$src = $Vd",
979 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
980 (i32 (LoadOp addrmode6oneL32:$Rn)),
981 imm:$lane))]> {
982 let Rm = 0b1111;
Owen Anderson7a2e1772011-08-15 18:44:44 +0000983 let DecoderMethod = "DecodeVLD1LN";
Mon P Wang183c6272011-05-09 17:47:27 +0000984}
Bob Wilsonb796bbb2010-11-01 22:04:05 +0000985class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
986 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
987 (i32 (LoadOp addrmode6:$addr)),
988 imm:$lane))];
989}
990
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000991def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
992 let Inst{7-5} = lane{2-0};
993}
994def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
995 let Inst{7-6} = lane{1-0};
Jim Grosbacheeaf1c12011-12-19 18:31:43 +0000996 let Inst{5-4} = Rn{5-4};
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000997}
Mon P Wang183c6272011-05-09 17:47:27 +0000998def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
Owen Andersonf0ea0f22010-11-02 20:40:59 +0000999 let Inst{7} = lane{0};
Jim Grosbacheeaf1c12011-12-19 18:31:43 +00001000 let Inst{5-4} = Rn{5-4};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001001}
Bob Wilsonb796bbb2010-11-01 22:04:05 +00001002
1003def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1004def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1005def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1006
Bob Wilson746fa172010-12-10 22:13:32 +00001007def : Pat<(vector_insert (v2f32 DPR:$src),
1008 (f32 (load addrmode6:$addr)), imm:$lane),
1009 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1010def : Pat<(vector_insert (v4f32 QPR:$src),
1011 (f32 (load addrmode6:$addr)), imm:$lane),
1012 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1013
Bob Wilsonb796bbb2010-11-01 22:04:05 +00001014let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1015
1016// ...with address register writeback:
1017class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001018 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001019 (ins addrmode6:$Rn, am6offset:$Rm,
Bob Wilsonb796bbb2010-11-01 22:04:05 +00001020 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001021 "\\{$Vd[$lane]\\}, $Rn$Rm",
Owen Anderson7a2e1772011-08-15 18:44:44 +00001022 "$src = $Vd, $Rn.addr = $wb", []> {
1023 let DecoderMethod = "DecodeVLD1LN";
1024}
Bob Wilsonb796bbb2010-11-01 22:04:05 +00001025
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001026def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1027 let Inst{7-5} = lane{2-0};
1028}
1029def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1030 let Inst{7-6} = lane{1-0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001031 let Inst{4} = Rn{4};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001032}
1033def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1034 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001035 let Inst{5} = Rn{4};
1036 let Inst{4} = Rn{4};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001037}
Bob Wilsonb796bbb2010-11-01 22:04:05 +00001038
1039def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1040def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1041def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
Bob Wilson7708c222009-10-07 18:09:32 +00001042
Bob Wilson243fcc52009-09-01 04:26:28 +00001043// VLD2LN : Vector Load (single 2-element structure to one lane)
Bob Wilson39842552010-03-22 16:43:10 +00001044class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001045 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
Owen Andersonf431eda2010-11-02 23:47:29 +00001046 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1047 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001048 "$src1 = $Vd, $src2 = $dst2", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001049 let Rm = 0b1111;
1050 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00001051 let DecoderMethod = "DecodeVLD2LN";
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001052}
Bob Wilson243fcc52009-09-01 04:26:28 +00001053
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001054def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1055 let Inst{7-5} = lane{2-0};
1056}
1057def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1058 let Inst{7-6} = lane{1-0};
1059}
1060def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1061 let Inst{7} = lane{0};
1062}
Bob Wilson30aea9d2009-10-08 18:56:10 +00001063
Evan Chengd2ca8132010-10-09 01:03:04 +00001064def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1065def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1066def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001067
Bob Wilson41315282010-03-20 20:39:53 +00001068// ...with double-spaced registers:
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001069def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1070 let Inst{7-6} = lane{1-0};
1071}
1072def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1073 let Inst{7} = lane{0};
1074}
Bob Wilson30aea9d2009-10-08 18:56:10 +00001075
Evan Chengd2ca8132010-10-09 01:03:04 +00001076def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1077def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
Bob Wilson243fcc52009-09-01 04:26:28 +00001078
Bob Wilsona1023642010-03-20 20:47:18 +00001079// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00001080class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001081 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001082 (ins addrmode6:$Rn, am6offset:$Rm,
Evan Chengd2ca8132010-10-09 01:03:04 +00001083 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001084 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1085 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1086 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00001087 let DecoderMethod = "DecodeVLD2LN";
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001088}
Bob Wilsona1023642010-03-20 20:47:18 +00001089
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001090def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1091 let Inst{7-5} = lane{2-0};
1092}
1093def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1094 let Inst{7-6} = lane{1-0};
1095}
1096def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1097 let Inst{7} = lane{0};
1098}
Bob Wilsona1023642010-03-20 20:47:18 +00001099
Evan Chengd2ca8132010-10-09 01:03:04 +00001100def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1101def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1102def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001103
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001104def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1105 let Inst{7-6} = lane{1-0};
1106}
1107def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1108 let Inst{7} = lane{0};
1109}
Bob Wilsona1023642010-03-20 20:47:18 +00001110
Evan Chengd2ca8132010-10-09 01:03:04 +00001111def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1112def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001113
Bob Wilson243fcc52009-09-01 04:26:28 +00001114// VLD3LN : Vector Load (single 3-element structure to one lane)
Bob Wilson39842552010-03-22 16:43:10 +00001115class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001116 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
Owen Andersonf431eda2010-11-02 23:47:29 +00001117 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
Evan Cheng84f69e82010-10-09 01:45:34 +00001118 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001119 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001120 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001121 let Rm = 0b1111;
Owen Anderson7a2e1772011-08-15 18:44:44 +00001122 let DecoderMethod = "DecodeVLD3LN";
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001123}
Bob Wilson243fcc52009-09-01 04:26:28 +00001124
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001125def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1126 let Inst{7-5} = lane{2-0};
1127}
1128def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1129 let Inst{7-6} = lane{1-0};
1130}
1131def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1132 let Inst{7} = lane{0};
1133}
Bob Wilson0bf7d992009-10-08 22:27:33 +00001134
Evan Cheng84f69e82010-10-09 01:45:34 +00001135def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1136def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1137def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001138
Bob Wilson41315282010-03-20 20:39:53 +00001139// ...with double-spaced registers:
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001140def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1141 let Inst{7-6} = lane{1-0};
1142}
1143def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1144 let Inst{7} = lane{0};
1145}
Bob Wilson0bf7d992009-10-08 22:27:33 +00001146
Evan Cheng84f69e82010-10-09 01:45:34 +00001147def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1148def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
Bob Wilson243fcc52009-09-01 04:26:28 +00001149
Bob Wilsona1023642010-03-20 20:47:18 +00001150// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00001151class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001152 : NLdStLn<1, 0b10, op11_8, op7_4,
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001153 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001154 (ins addrmode6:$Rn, am6offset:$Rm,
Bob Wilsona1023642010-03-20 20:47:18 +00001155 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
Evan Cheng84f69e82010-10-09 01:45:34 +00001156 IIC_VLD3lnu, "vld3", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001157 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1158 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
Owen Anderson7a2e1772011-08-15 18:44:44 +00001159 []> {
1160 let DecoderMethod = "DecodeVLD3LN";
1161}
Bob Wilsona1023642010-03-20 20:47:18 +00001162
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001163def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1164 let Inst{7-5} = lane{2-0};
1165}
1166def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1167 let Inst{7-6} = lane{1-0};
1168}
1169def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001170 let Inst{7} = lane{0};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001171}
Bob Wilsona1023642010-03-20 20:47:18 +00001172
Evan Cheng84f69e82010-10-09 01:45:34 +00001173def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1174def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1175def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001176
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001177def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1178 let Inst{7-6} = lane{1-0};
1179}
1180def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001181 let Inst{7} = lane{0};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001182}
Bob Wilsona1023642010-03-20 20:47:18 +00001183
Evan Cheng84f69e82010-10-09 01:45:34 +00001184def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1185def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001186
Bob Wilson243fcc52009-09-01 04:26:28 +00001187// VLD4LN : Vector Load (single 4-element structure to one lane)
Bob Wilson39842552010-03-22 16:43:10 +00001188class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001189 : NLdStLn<1, 0b10, op11_8, op7_4,
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001190 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
Owen Andersonf431eda2010-11-02 23:47:29 +00001191 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
Evan Cheng10dc63f2010-10-09 04:07:58 +00001192 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001193 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001194 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001195 let Rm = 0b1111;
Jim Grosbach3346dce2011-12-19 18:11:17 +00001196 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00001197 let DecoderMethod = "DecodeVLD4LN";
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001198}
Bob Wilson243fcc52009-09-01 04:26:28 +00001199
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001200def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1201 let Inst{7-5} = lane{2-0};
1202}
1203def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1204 let Inst{7-6} = lane{1-0};
1205}
1206def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001207 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001208 let Inst{5} = Rn{5};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001209}
Bob Wilson62e053e2009-10-08 22:53:57 +00001210
Evan Cheng10dc63f2010-10-09 04:07:58 +00001211def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1212def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1213def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001214
Bob Wilson41315282010-03-20 20:39:53 +00001215// ...with double-spaced registers:
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001216def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1217 let Inst{7-6} = lane{1-0};
1218}
1219def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001220 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001221 let Inst{5} = Rn{5};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001222}
Bob Wilson62e053e2009-10-08 22:53:57 +00001223
Evan Cheng10dc63f2010-10-09 04:07:58 +00001224def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1225def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
Bob Wilsonb07c1712009-10-07 21:53:04 +00001226
Bob Wilsona1023642010-03-20 20:47:18 +00001227// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00001228class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersond138d702010-11-02 20:47:39 +00001229 : NLdStLn<1, 0b10, op11_8, op7_4,
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001230 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001231 (ins addrmode6:$Rn, am6offset:$Rm,
Bob Wilsona1023642010-03-20 20:47:18 +00001232 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
Bob Wilson6eb08dd2011-02-07 17:43:12 +00001233 IIC_VLD4lnu, "vld4", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001234"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1235"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001236 []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001237 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00001238 let DecoderMethod = "DecodeVLD4LN" ;
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001239}
Bob Wilsona1023642010-03-20 20:47:18 +00001240
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001241def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1242 let Inst{7-5} = lane{2-0};
1243}
1244def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1245 let Inst{7-6} = lane{1-0};
1246}
1247def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001248 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001249 let Inst{5} = Rn{5};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001250}
Bob Wilsona1023642010-03-20 20:47:18 +00001251
Evan Cheng10dc63f2010-10-09 04:07:58 +00001252def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1253def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1254def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001255
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001256def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1257 let Inst{7-6} = lane{1-0};
1258}
1259def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
Jim Grosbach3346dce2011-12-19 18:11:17 +00001260 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001261 let Inst{5} = Rn{5};
Owen Andersonf0ea0f22010-11-02 20:40:59 +00001262}
Bob Wilsona1023642010-03-20 20:47:18 +00001263
Evan Cheng10dc63f2010-10-09 04:07:58 +00001264def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1265def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00001266
Bob Wilson2a0e9742010-11-27 06:35:16 +00001267} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1268
Bob Wilsonb07c1712009-10-07 21:53:04 +00001269// VLD1DUP : Vector Load (single element to all lanes)
Bob Wilsonf3d2f9d2010-11-28 06:51:15 +00001270class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
Jim Grosbach98b05a52011-11-30 01:09:44 +00001271 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1272 (ins addrmode6dup:$Rn),
1273 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1274 [(set VecListOneDAllLanes:$Vd,
1275 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
Bob Wilson2a0e9742010-11-27 06:35:16 +00001276 let Rm = 0b1111;
Bob Wilsonbce55772010-11-27 07:12:02 +00001277 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001278 let DecoderMethod = "DecodeVLD1DupInstruction";
Bob Wilson2a0e9742010-11-27 06:35:16 +00001279}
Bob Wilsonf3d2f9d2010-11-28 06:51:15 +00001280def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1281def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1282def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
Bob Wilson2a0e9742010-11-27 06:35:16 +00001283
Bob Wilson746fa172010-12-10 22:13:32 +00001284def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1285 (VLD1DUPd32 addrmode6:$addr)>;
Bob Wilson746fa172010-12-10 22:13:32 +00001286
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001287class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1288 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001289 (ins addrmode6dup:$Rn), IIC_VLD1dup,
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001290 "vld1", Dt, "$Vd, $Rn", "",
1291 [(set VecListDPairAllLanes:$Vd,
1292 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
Bob Wilson2a0e9742010-11-27 06:35:16 +00001293 let Rm = 0b1111;
Bob Wilsonbce55772010-11-27 07:12:02 +00001294 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001295 let DecoderMethod = "DecodeVLD1DupInstruction";
Bob Wilson2a0e9742010-11-27 06:35:16 +00001296}
1297
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001298def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1299def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1300def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
Bob Wilson2a0e9742010-11-27 06:35:16 +00001301
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001302def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1303 (VLD1DUPq32 addrmode6:$addr)>;
1304
1305let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
Bob Wilson2a0e9742010-11-27 06:35:16 +00001306// ...with address register writeback:
Jim Grosbach096334e2011-11-30 19:35:44 +00001307multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1308 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1309 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1310 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1311 "vld1", Dt, "$Vd, $Rn!",
1312 "$Rn.addr = $wb", []> {
1313 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1314 let Inst{4} = Rn{4};
1315 let DecoderMethod = "DecodeVLD1DupInstruction";
1316 let AsmMatchConverter = "cvtVLDwbFixed";
1317 }
1318 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1319 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1320 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1321 "vld1", Dt, "$Vd, $Rn, $Rm",
1322 "$Rn.addr = $wb", []> {
1323 let Inst{4} = Rn{4};
1324 let DecoderMethod = "DecodeVLD1DupInstruction";
1325 let AsmMatchConverter = "cvtVLDwbRegister";
1326 }
Bob Wilsonbce55772010-11-27 07:12:02 +00001327}
Jim Grosbach096334e2011-11-30 19:35:44 +00001328multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1329 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001330 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
Jim Grosbach096334e2011-11-30 19:35:44 +00001331 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1332 "vld1", Dt, "$Vd, $Rn!",
1333 "$Rn.addr = $wb", []> {
1334 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1335 let Inst{4} = Rn{4};
1336 let DecoderMethod = "DecodeVLD1DupInstruction";
1337 let AsmMatchConverter = "cvtVLDwbFixed";
1338 }
1339 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001340 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
Jim Grosbach096334e2011-11-30 19:35:44 +00001341 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1342 "vld1", Dt, "$Vd, $Rn, $Rm",
1343 "$Rn.addr = $wb", []> {
1344 let Inst{4} = Rn{4};
1345 let DecoderMethod = "DecodeVLD1DupInstruction";
1346 let AsmMatchConverter = "cvtVLDwbRegister";
1347 }
Bob Wilsonbce55772010-11-27 07:12:02 +00001348}
Bob Wilson2a0e9742010-11-27 06:35:16 +00001349
Jim Grosbach096334e2011-11-30 19:35:44 +00001350defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1351defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1352defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
Bob Wilson2a0e9742010-11-27 06:35:16 +00001353
Jim Grosbach096334e2011-11-30 19:35:44 +00001354defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1355defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1356defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
Bob Wilson2a0e9742010-11-27 06:35:16 +00001357
Bob Wilsonb07c1712009-10-07 21:53:04 +00001358// VLD2DUP : Vector Load (single 2-element structure to all lanes)
Jim Grosbach3471d4f2011-12-21 00:38:54 +00001359class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1360 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001361 (ins addrmode6dup:$Rn), IIC_VLD2dup,
Jim Grosbach3471d4f2011-12-21 00:38:54 +00001362 "vld2", Dt, "$Vd, $Rn", "", []> {
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001363 let Rm = 0b1111;
1364 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001365 let DecoderMethod = "DecodeVLD2DupInstruction";
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001366}
1367
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001368def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1369def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1370def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001371
Jim Grosbach4d0983a2012-03-06 23:10:38 +00001372// ...with double-spaced registers
1373def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1374def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1375def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001376
1377// ...with address register writeback:
Jim Grosbache6949b12011-12-21 19:40:55 +00001378multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1379 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1380 (outs VdTy:$Vd, GPR:$wb),
1381 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1382 "vld2", Dt, "$Vd, $Rn!",
1383 "$Rn.addr = $wb", []> {
1384 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1385 let Inst{4} = Rn{4};
1386 let DecoderMethod = "DecodeVLD2DupInstruction";
1387 let AsmMatchConverter = "cvtVLDwbFixed";
1388 }
1389 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1390 (outs VdTy:$Vd, GPR:$wb),
1391 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1392 "vld2", Dt, "$Vd, $Rn, $Rm",
1393 "$Rn.addr = $wb", []> {
1394 let Inst{4} = Rn{4};
1395 let DecoderMethod = "DecodeVLD2DupInstruction";
1396 let AsmMatchConverter = "cvtVLDwbRegister";
1397 }
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001398}
1399
Jim Grosbachc0fc4502012-03-06 22:01:44 +00001400defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1401defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1402defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001403
Jim Grosbach4d0983a2012-03-06 23:10:38 +00001404defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1405defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1406defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +00001407
Bob Wilsonb07c1712009-10-07 21:53:04 +00001408// VLD3DUP : Vector Load (single 3-element structure to all lanes)
Bob Wilson86c6d802010-11-29 19:35:29 +00001409class VLD3DUP<bits<4> op7_4, string Dt>
1410 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001411 (ins addrmode6dup:$Rn), IIC_VLD3dup,
Bob Wilson86c6d802010-11-29 19:35:29 +00001412 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1413 let Rm = 0b1111;
Owen Andersonef2865a2011-08-15 23:38:54 +00001414 let Inst{4} = 0;
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001415 let DecoderMethod = "DecodeVLD3DupInstruction";
Bob Wilson86c6d802010-11-29 19:35:29 +00001416}
1417
1418def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1419def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1420def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1421
1422def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1423def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1424def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1425
1426// ...with double-spaced registers (not used for codegen):
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00001427def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1428def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1429def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
Bob Wilson86c6d802010-11-29 19:35:29 +00001430
1431// ...with address register writeback:
1432class VLD3DUPWB<bits<4> op7_4, string Dt>
1433 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001434 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
Bob Wilson86c6d802010-11-29 19:35:29 +00001435 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1436 "$Rn.addr = $wb", []> {
Owen Andersonef2865a2011-08-15 23:38:54 +00001437 let Inst{4} = 0;
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001438 let DecoderMethod = "DecodeVLD3DupInstruction";
Bob Wilson86c6d802010-11-29 19:35:29 +00001439}
1440
1441def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1442def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1443def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1444
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00001445def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1446def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1447def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
Bob Wilson86c6d802010-11-29 19:35:29 +00001448
1449def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1450def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1451def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1452
Bob Wilsonb07c1712009-10-07 21:53:04 +00001453// VLD4DUP : Vector Load (single 4-element structure to all lanes)
Bob Wilson6c4c9822010-11-30 00:00:35 +00001454class VLD4DUP<bits<4> op7_4, string Dt>
1455 : NLdSt<1, 0b10, 0b1111, op7_4,
1456 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001457 (ins addrmode6dup:$Rn), IIC_VLD4dup,
Bob Wilson6c4c9822010-11-30 00:00:35 +00001458 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1459 let Rm = 0b1111;
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001460 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001461 let DecoderMethod = "DecodeVLD4DupInstruction";
Bob Wilson6c4c9822010-11-30 00:00:35 +00001462}
1463
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001464def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1465def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1466def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
Bob Wilson6c4c9822010-11-30 00:00:35 +00001467
1468def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1469def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1470def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1471
1472// ...with double-spaced registers (not used for codegen):
Jim Grosbach6cd6a682012-01-24 23:47:07 +00001473def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1474def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1475def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
Bob Wilson6c4c9822010-11-30 00:00:35 +00001476
1477// ...with address register writeback:
1478class VLD4DUPWB<bits<4> op7_4, string Dt>
1479 : NLdSt<1, 0b10, 0b1111, op7_4,
1480 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001481 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
Bob Wilson6c4c9822010-11-30 00:00:35 +00001482 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001483 "$Rn.addr = $wb", []> {
1484 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001485 let DecoderMethod = "DecodeVLD4DupInstruction";
Bob Wilson6c4c9822010-11-30 00:00:35 +00001486}
1487
Bob Wilson8e0c7b52010-11-30 00:00:42 +00001488def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1489def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1490def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1491
Jim Grosbach6cd6a682012-01-24 23:47:07 +00001492def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1493def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1494def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
Bob Wilson6c4c9822010-11-30 00:00:35 +00001495
1496def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1497def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1498def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1499
Evan Cheng5fd1c9b2010-05-19 06:07:03 +00001500} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
Bob Wilsondbd3c0e2009-08-12 00:49:01 +00001501
Evan Cheng5fd1c9b2010-05-19 06:07:03 +00001502let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
Bob Wilson25eb5012010-03-20 20:54:36 +00001503
Bob Wilson709d5922010-08-25 23:27:42 +00001504// Classes for VST* pseudo-instructions with multi-register operands.
1505// These are expanded to real instructions after register allocation.
Bob Wilson9d84fb32010-09-14 20:59:49 +00001506class VSTQPseudo<InstrItinClass itin>
1507 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1508class VSTQWBPseudo<InstrItinClass itin>
Bob Wilsone5ce4f62010-08-28 05:12:57 +00001509 : PseudoNLdSt<(outs GPR:$wb),
Bob Wilson9d84fb32010-09-14 20:59:49 +00001510 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
Bob Wilsone5ce4f62010-08-28 05:12:57 +00001511 "$addr.addr = $wb">;
Jim Grosbach4334e032011-10-31 21:50:31 +00001512class VSTQWBfixedPseudo<InstrItinClass itin>
1513 : PseudoNLdSt<(outs GPR:$wb),
1514 (ins addrmode6:$addr, QPR:$src), itin,
1515 "$addr.addr = $wb">;
1516class VSTQWBregisterPseudo<InstrItinClass itin>
1517 : PseudoNLdSt<(outs GPR:$wb),
1518 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1519 "$addr.addr = $wb">;
Bob Wilson9d84fb32010-09-14 20:59:49 +00001520class VSTQQPseudo<InstrItinClass itin>
1521 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1522class VSTQQWBPseudo<InstrItinClass itin>
Bob Wilson709d5922010-08-25 23:27:42 +00001523 : PseudoNLdSt<(outs GPR:$wb),
Bob Wilson9d84fb32010-09-14 20:59:49 +00001524 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
Bob Wilson709d5922010-08-25 23:27:42 +00001525 "$addr.addr = $wb">;
Jim Grosbach6d567302012-01-20 19:16:00 +00001526class VSTQQWBfixedPseudo<InstrItinClass itin>
1527 : PseudoNLdSt<(outs GPR:$wb),
1528 (ins addrmode6:$addr, QQPR:$src), itin,
1529 "$addr.addr = $wb">;
1530class VSTQQWBregisterPseudo<InstrItinClass itin>
1531 : PseudoNLdSt<(outs GPR:$wb),
1532 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1533 "$addr.addr = $wb">;
1534
Bob Wilson7de68142011-02-07 17:43:15 +00001535class VSTQQQQPseudo<InstrItinClass itin>
1536 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
Bob Wilson9d84fb32010-09-14 20:59:49 +00001537class VSTQQQQWBPseudo<InstrItinClass itin>
Bob Wilson709d5922010-08-25 23:27:42 +00001538 : PseudoNLdSt<(outs GPR:$wb),
Evan Cheng60ff8792010-10-11 22:03:18 +00001539 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
Bob Wilson709d5922010-08-25 23:27:42 +00001540 "$addr.addr = $wb">;
1541
Bob Wilson11d98992010-03-23 06:20:33 +00001542// VST1 : Vector Store (multiple single elements)
1543class VST1D<bits<4> op7_4, string Dt>
Jim Grosbach6b09c772011-10-20 15:04:25 +00001544 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1545 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001546 let Rm = 0b1111;
1547 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001548 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001549}
Bob Wilson11d98992010-03-23 06:20:33 +00001550class VST1Q<bits<4> op7_4, string Dt>
Jim Grosbach28f08c92012-03-05 19:33:30 +00001551 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
Jim Grosbach742c4ba2011-11-12 00:31:53 +00001552 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001553 let Rm = 0b1111;
1554 let Inst{5-4} = Rn{5-4};
Jim Grosbach4d061382011-11-11 23:51:31 +00001555 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001556}
Bob Wilson11d98992010-03-23 06:20:33 +00001557
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001558def VST1d8 : VST1D<{0,0,0,?}, "8">;
1559def VST1d16 : VST1D<{0,1,0,?}, "16">;
1560def VST1d32 : VST1D<{1,0,0,?}, "32">;
1561def VST1d64 : VST1D<{1,1,0,?}, "64">;
Bob Wilson11d98992010-03-23 06:20:33 +00001562
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001563def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1564def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1565def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1566def VST1q64 : VST1Q<{1,1,?,?}, "64">;
Bob Wilson11d98992010-03-23 06:20:33 +00001567
Bob Wilson25eb5012010-03-20 20:54:36 +00001568// ...with address register writeback:
Jim Grosbach4334e032011-10-31 21:50:31 +00001569multiclass VST1DWB<bits<4> op7_4, string Dt> {
1570 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1571 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1572 "vst1", Dt, "$Vd, $Rn!",
1573 "$Rn.addr = $wb", []> {
1574 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1575 let Inst{4} = Rn{4};
1576 let DecoderMethod = "DecodeVSTInstruction";
1577 let AsmMatchConverter = "cvtVSTwbFixed";
1578 }
1579 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1580 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1581 IIC_VLD1u,
1582 "vst1", Dt, "$Vd, $Rn, $Rm",
1583 "$Rn.addr = $wb", []> {
1584 let Inst{4} = Rn{4};
1585 let DecoderMethod = "DecodeVSTInstruction";
1586 let AsmMatchConverter = "cvtVSTwbRegister";
1587 }
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001588}
Jim Grosbach4334e032011-10-31 21:50:31 +00001589multiclass VST1QWB<bits<4> op7_4, string Dt> {
1590 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
Jim Grosbach28f08c92012-03-05 19:33:30 +00001591 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
Jim Grosbach4334e032011-10-31 21:50:31 +00001592 "vst1", Dt, "$Vd, $Rn!",
1593 "$Rn.addr = $wb", []> {
1594 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1595 let Inst{5-4} = Rn{5-4};
1596 let DecoderMethod = "DecodeVSTInstruction";
1597 let AsmMatchConverter = "cvtVSTwbFixed";
1598 }
1599 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
Jim Grosbach28f08c92012-03-05 19:33:30 +00001600 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
Jim Grosbach4334e032011-10-31 21:50:31 +00001601 IIC_VLD1x2u,
1602 "vst1", Dt, "$Vd, $Rn, $Rm",
1603 "$Rn.addr = $wb", []> {
1604 let Inst{5-4} = Rn{5-4};
1605 let DecoderMethod = "DecodeVSTInstruction";
1606 let AsmMatchConverter = "cvtVSTwbRegister";
1607 }
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001608}
Bob Wilson25eb5012010-03-20 20:54:36 +00001609
Jim Grosbach4334e032011-10-31 21:50:31 +00001610defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1611defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1612defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1613defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
Bob Wilson25eb5012010-03-20 20:54:36 +00001614
Jim Grosbach4334e032011-10-31 21:50:31 +00001615defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1616defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1617defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1618defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
Bob Wilson25eb5012010-03-20 20:54:36 +00001619
Jim Grosbachfe7b4992011-10-21 16:14:12 +00001620// ...with 3 registers
Bob Wilson95808322010-03-18 20:18:39 +00001621class VST1D3<bits<4> op7_4, string Dt>
Johnny Chenf50e83f2010-02-24 02:57:20 +00001622 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
Jim Grosbachd5ca2012011-11-29 22:38:04 +00001623 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1624 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001625 let Rm = 0b1111;
1626 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001627 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001628}
Jim Grosbachd5ca2012011-11-29 22:38:04 +00001629multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1630 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1631 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1632 "vst1", Dt, "$Vd, $Rn!",
1633 "$Rn.addr = $wb", []> {
1634 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1635 let Inst{5-4} = Rn{5-4};
1636 let DecoderMethod = "DecodeVSTInstruction";
1637 let AsmMatchConverter = "cvtVSTwbFixed";
1638 }
1639 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1640 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1641 IIC_VLD1x3u,
1642 "vst1", Dt, "$Vd, $Rn, $Rm",
1643 "$Rn.addr = $wb", []> {
1644 let Inst{5-4} = Rn{5-4};
1645 let DecoderMethod = "DecodeVSTInstruction";
1646 let AsmMatchConverter = "cvtVSTwbRegister";
1647 }
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001648}
Bob Wilson052ba452010-03-22 18:22:06 +00001649
Jim Grosbachd5ca2012011-11-29 22:38:04 +00001650def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1651def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1652def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1653def VST1d64T : VST1D3<{1,1,0,?}, "64">;
Bob Wilson052ba452010-03-22 18:22:06 +00001654
Jim Grosbachd5ca2012011-11-29 22:38:04 +00001655defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1656defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1657defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1658defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
Bob Wilson052ba452010-03-22 18:22:06 +00001659
Jim Grosbachd5ca2012011-11-29 22:38:04 +00001660def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1661def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1662def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
Bob Wilson01ba4612010-08-26 18:51:29 +00001663
Jim Grosbachfe7b4992011-10-21 16:14:12 +00001664// ...with 4 registers
Bob Wilson052ba452010-03-22 18:22:06 +00001665class VST1D4<bits<4> op7_4, string Dt>
1666 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
Jim Grosbach4c7edb32011-11-29 22:58:48 +00001667 (ins addrmode6:$Rn, VecListFourD:$Vd),
1668 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001669 []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001670 let Rm = 0b1111;
1671 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001672 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001673}
Jim Grosbach4c7edb32011-11-29 22:58:48 +00001674multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1675 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1676 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1677 "vst1", Dt, "$Vd, $Rn!",
1678 "$Rn.addr = $wb", []> {
1679 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1680 let Inst{5-4} = Rn{5-4};
1681 let DecoderMethod = "DecodeVSTInstruction";
1682 let AsmMatchConverter = "cvtVSTwbFixed";
1683 }
1684 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1685 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1686 IIC_VLD1x4u,
1687 "vst1", Dt, "$Vd, $Rn, $Rm",
1688 "$Rn.addr = $wb", []> {
1689 let Inst{5-4} = Rn{5-4};
1690 let DecoderMethod = "DecodeVSTInstruction";
1691 let AsmMatchConverter = "cvtVSTwbRegister";
1692 }
Owen Andersoncfebe3a2010-11-02 21:06:06 +00001693}
Bob Wilson25eb5012010-03-20 20:54:36 +00001694
Jim Grosbach4c7edb32011-11-29 22:58:48 +00001695def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1696def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1697def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1698def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
Bob Wilson25eb5012010-03-20 20:54:36 +00001699
Jim Grosbach4c7edb32011-11-29 22:58:48 +00001700defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1701defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1702defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1703defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
Bob Wilson9f7d60f2009-08-12 17:04:56 +00001704
Jim Grosbach4c7edb32011-11-29 22:58:48 +00001705def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1706def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1707def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
Bob Wilson70e48b22010-08-26 05:33:30 +00001708
Bob Wilsonb36ec862009-08-06 18:47:44 +00001709// VST2 : Vector Store (multiple 2-element structures)
Jim Grosbach20accfc2011-12-14 20:59:15 +00001710class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1711 InstrItinClass itin>
Jim Grosbache90ac9b2011-12-14 19:35:22 +00001712 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
Jim Grosbach20accfc2011-12-14 20:59:15 +00001713 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001714 let Rm = 0b1111;
1715 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001716 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersond2f37942010-11-02 21:16:58 +00001717}
Bob Wilsonb36ec862009-08-06 18:47:44 +00001718
Jim Grosbach28f08c92012-03-05 19:33:30 +00001719def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1720def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1721def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
Bob Wilsonb36ec862009-08-06 18:47:44 +00001722
Jim Grosbach20accfc2011-12-14 20:59:15 +00001723def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1724def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1725def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
Bob Wilsond2855752009-10-07 18:47:39 +00001726
Evan Cheng60ff8792010-10-11 22:03:18 +00001727def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1728def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1729def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
Bob Wilsone5ce4f62010-08-28 05:12:57 +00001730
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001731// ...with address register writeback:
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001732multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1733 RegisterOperand VdTy> {
1734 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1735 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1736 "vst2", Dt, "$Vd, $Rn!",
1737 "$Rn.addr = $wb", []> {
1738 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
Jim Grosbachec04a3f2011-12-14 21:49:24 +00001739 let Inst{5-4} = Rn{5-4};
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001740 let DecoderMethod = "DecodeVSTInstruction";
1741 let AsmMatchConverter = "cvtVSTwbFixed";
1742 }
1743 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1744 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1745 "vst2", Dt, "$Vd, $Rn, $Rm",
1746 "$Rn.addr = $wb", []> {
Jim Grosbachec04a3f2011-12-14 21:49:24 +00001747 let Inst{5-4} = Rn{5-4};
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001748 let DecoderMethod = "DecodeVSTInstruction";
1749 let AsmMatchConverter = "cvtVSTwbRegister";
1750 }
Owen Andersond2f37942010-11-02 21:16:58 +00001751}
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001752multiclass VST2QWB<bits<4> op7_4, string Dt> {
1753 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1755 "vst2", Dt, "$Vd, $Rn!",
1756 "$Rn.addr = $wb", []> {
1757 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
Jim Grosbachec04a3f2011-12-14 21:49:24 +00001758 let Inst{5-4} = Rn{5-4};
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001759 let DecoderMethod = "DecodeVSTInstruction";
1760 let AsmMatchConverter = "cvtVSTwbFixed";
1761 }
1762 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1763 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1764 IIC_VLD1u,
1765 "vst2", Dt, "$Vd, $Rn, $Rm",
1766 "$Rn.addr = $wb", []> {
Jim Grosbachec04a3f2011-12-14 21:49:24 +00001767 let Inst{5-4} = Rn{5-4};
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001768 let DecoderMethod = "DecodeVSTInstruction";
1769 let AsmMatchConverter = "cvtVSTwbRegister";
1770 }
Owen Andersond2f37942010-11-02 21:16:58 +00001771}
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001772
Jim Grosbach28f08c92012-03-05 19:33:30 +00001773defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1774defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1775defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001776
Jim Grosbachbb3a2e42011-12-14 21:32:11 +00001777defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1778defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1779defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001780
Jim Grosbach6d567302012-01-20 19:16:00 +00001781def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1782def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1783def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1784def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1785def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1786def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
Bob Wilsone5ce4f62010-08-28 05:12:57 +00001787
Jim Grosbachfe7b4992011-10-21 16:14:12 +00001788// ...with double-spaced registers
Jim Grosbachc3384c92012-03-05 21:43:40 +00001789def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1790def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1791def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1792defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1793defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1794defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
Johnny Chenf50e83f2010-02-24 02:57:20 +00001795
Bob Wilsonb36ec862009-08-06 18:47:44 +00001796// VST3 : Vector Store (multiple 3-element structures)
Bob Wilson068b18b2010-03-20 21:15:48 +00001797class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1798 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
Owen Andersonf431eda2010-11-02 23:47:29 +00001799 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1800 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1801 let Rm = 0b1111;
1802 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001803 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersona1a45fd2010-11-02 21:47:03 +00001804}
Bob Wilsonb36ec862009-08-06 18:47:44 +00001805
Owen Andersona1a45fd2010-11-02 21:47:03 +00001806def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1807def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1808def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
Bob Wilsonb36ec862009-08-06 18:47:44 +00001809
Evan Cheng60ff8792010-10-11 22:03:18 +00001810def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1811def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1812def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
Bob Wilson01ba4612010-08-26 18:51:29 +00001813
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001814// ...with address register writeback:
1815class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1816 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001817 (ins addrmode6:$Rn, am6offset:$Rm,
Owen Andersona1a45fd2010-11-02 21:47:03 +00001818 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
Owen Andersonf431eda2010-11-02 23:47:29 +00001819 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1820 "$Rn.addr = $wb", []> {
1821 let Inst{4} = Rn{4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001822 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersona1a45fd2010-11-02 21:47:03 +00001823}
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001824
Owen Andersona1a45fd2010-11-02 21:47:03 +00001825def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1826def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1827def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001828
Evan Cheng60ff8792010-10-11 22:03:18 +00001829def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1830def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1831def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
Bob Wilson01ba4612010-08-26 18:51:29 +00001832
Bob Wilson7de68142011-02-07 17:43:15 +00001833// ...with double-spaced registers:
Owen Andersona1a45fd2010-11-02 21:47:03 +00001834def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1835def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1836def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1837def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1838def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1839def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
Bob Wilson068b18b2010-03-20 21:15:48 +00001840
Evan Cheng60ff8792010-10-11 22:03:18 +00001841def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1842def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1843def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
Bob Wilson01ba4612010-08-26 18:51:29 +00001844
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001845// ...alternate versions to be allocated odd register numbers:
Bob Wilson7de68142011-02-07 17:43:15 +00001846def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1847def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1848def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1849
Evan Cheng60ff8792010-10-11 22:03:18 +00001850def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1851def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1852def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
Bob Wilson66a70632009-10-07 20:30:08 +00001853
Bob Wilsonb36ec862009-08-06 18:47:44 +00001854// VST4 : Vector Store (multiple 4-element structures)
Bob Wilson068b18b2010-03-20 21:15:48 +00001855class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1856 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
Owen Andersonf431eda2010-11-02 23:47:29 +00001857 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1858 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
Owen Andersona1a45fd2010-11-02 21:47:03 +00001859 "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00001860 let Rm = 0b1111;
1861 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001862 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersona1a45fd2010-11-02 21:47:03 +00001863}
Bob Wilsonb36ec862009-08-06 18:47:44 +00001864
Owen Andersona1a45fd2010-11-02 21:47:03 +00001865def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1866def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1867def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
Bob Wilson8a3198b2009-09-01 18:51:56 +00001868
Evan Cheng60ff8792010-10-11 22:03:18 +00001869def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1870def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1871def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
Bob Wilson709d5922010-08-25 23:27:42 +00001872
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001873// ...with address register writeback:
1874class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1875 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00001876 (ins addrmode6:$Rn, am6offset:$Rm,
Owen Andersona1a45fd2010-11-02 21:47:03 +00001877 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
Owen Andersonf431eda2010-11-02 23:47:29 +00001878 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1879 "$Rn.addr = $wb", []> {
1880 let Inst{5-4} = Rn{5-4};
Owen Anderson8d7d2e12011-08-09 20:55:18 +00001881 let DecoderMethod = "DecodeVSTInstruction";
Owen Andersona1a45fd2010-11-02 21:47:03 +00001882}
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001883
Owen Andersona1a45fd2010-11-02 21:47:03 +00001884def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1885def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1886def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001887
Evan Cheng60ff8792010-10-11 22:03:18 +00001888def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1889def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1890def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
Bob Wilson709d5922010-08-25 23:27:42 +00001891
Bob Wilson7de68142011-02-07 17:43:15 +00001892// ...with double-spaced registers:
Owen Andersona1a45fd2010-11-02 21:47:03 +00001893def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1894def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1895def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1896def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1897def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1898def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
Bob Wilson068b18b2010-03-20 21:15:48 +00001899
Evan Cheng60ff8792010-10-11 22:03:18 +00001900def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1901def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1902def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
Bob Wilson709d5922010-08-25 23:27:42 +00001903
Bob Wilson4f4f93f2010-03-20 21:45:18 +00001904// ...alternate versions to be allocated odd register numbers:
Bob Wilson7de68142011-02-07 17:43:15 +00001905def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1906def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1907def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1908
Evan Cheng60ff8792010-10-11 22:03:18 +00001909def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1910def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1911def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
Bob Wilsonb07c1712009-10-07 21:53:04 +00001912
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001913} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1914
Bob Wilson8466fa12010-09-13 23:01:35 +00001915// Classes for VST*LN pseudo-instructions with multi-register operands.
1916// These are expanded to real instructions after register allocation.
1917class VSTQLNPseudo<InstrItinClass itin>
1918 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1919 itin, "">;
1920class VSTQLNWBPseudo<InstrItinClass itin>
1921 : PseudoNLdSt<(outs GPR:$wb),
1922 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1923 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1924class VSTQQLNPseudo<InstrItinClass itin>
1925 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1926 itin, "">;
1927class VSTQQLNWBPseudo<InstrItinClass itin>
1928 : PseudoNLdSt<(outs GPR:$wb),
1929 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1930 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1931class VSTQQQQLNPseudo<InstrItinClass itin>
1932 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1933 itin, "">;
1934class VSTQQQQLNWBPseudo<InstrItinClass itin>
1935 : PseudoNLdSt<(outs GPR:$wb),
1936 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1937 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1938
Bob Wilsonb07c1712009-10-07 21:53:04 +00001939// VST1LN : Vector Store (single element from one lane)
Bob Wilsond168cef2010-11-03 16:24:53 +00001940class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001941 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
Owen Andersone95c9462010-11-02 21:54:45 +00001942 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
Richard Barton6e9d66c2012-03-28 10:18:11 +00001943 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
Bob Wilsond168cef2010-11-03 16:24:53 +00001944 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
Richard Barton6e9d66c2012-03-28 10:18:11 +00001945 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
Mon P Wang183c6272011-05-09 17:47:27 +00001946 let Rm = 0b1111;
Owen Anderson7a2e1772011-08-15 18:44:44 +00001947 let DecoderMethod = "DecodeVST1LN";
Mon P Wang183c6272011-05-09 17:47:27 +00001948}
Bob Wilsond168cef2010-11-03 16:24:53 +00001949class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1950 : VSTQLNPseudo<IIC_VST1ln> {
1951 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1952 addrmode6:$addr)];
1953}
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001954
Bob Wilsond168cef2010-11-03 16:24:53 +00001955def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001956 NEONvgetlaneu, addrmode6> {
Owen Andersone95c9462010-11-02 21:54:45 +00001957 let Inst{7-5} = lane{2-0};
1958}
Bob Wilsond168cef2010-11-03 16:24:53 +00001959def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001960 NEONvgetlaneu, addrmode6> {
Owen Andersone95c9462010-11-02 21:54:45 +00001961 let Inst{7-6} = lane{1-0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001962 let Inst{4} = Rn{5};
Owen Andersone95c9462010-11-02 21:54:45 +00001963}
Mon P Wang183c6272011-05-09 17:47:27 +00001964
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00001965def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001966 addrmode6oneL32> {
Owen Andersone95c9462010-11-02 21:54:45 +00001967 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00001968 let Inst{5-4} = Rn{5-4};
Owen Andersone95c9462010-11-02 21:54:45 +00001969}
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001970
Bob Wilsond168cef2010-11-03 16:24:53 +00001971def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1972def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1973def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001974
Bob Wilson746fa172010-12-10 22:13:32 +00001975def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1976 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1977def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1978 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1979
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001980// ...with address register writeback:
Bob Wilsonda525062011-02-25 06:42:42 +00001981class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001982 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
Owen Andersone95c9462010-11-02 21:54:45 +00001983 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
Richard Barton6e9d66c2012-03-28 10:18:11 +00001984 (ins AdrMode:$Rn, am6offset:$Rm,
Owen Andersone95c9462010-11-02 21:54:45 +00001985 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00001986 "\\{$Vd[$lane]\\}, $Rn$Rm",
Bob Wilsonda525062011-02-25 06:42:42 +00001987 "$Rn.addr = $wb",
1988 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
Richard Barton6e9d66c2012-03-28 10:18:11 +00001989 AdrMode:$Rn, am6offset:$Rm))]> {
Owen Anderson7a2e1772011-08-15 18:44:44 +00001990 let DecoderMethod = "DecodeVST1LN";
1991}
Bob Wilsonda525062011-02-25 06:42:42 +00001992class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1993 : VSTQLNWBPseudo<IIC_VST1lnu> {
1994 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1995 addrmode6:$addr, am6offset:$offset))];
1996}
Bob Wilsond0c6bc22010-11-02 21:18:25 +00001997
Bob Wilsonda525062011-02-25 06:42:42 +00001998def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
Richard Barton6e9d66c2012-03-28 10:18:11 +00001999 NEONvgetlaneu, addrmode6> {
Owen Andersone95c9462010-11-02 21:54:45 +00002000 let Inst{7-5} = lane{2-0};
2001}
Bob Wilsonda525062011-02-25 06:42:42 +00002002def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
Richard Barton6e9d66c2012-03-28 10:18:11 +00002003 NEONvgetlaneu, addrmode6> {
Owen Andersone95c9462010-11-02 21:54:45 +00002004 let Inst{7-6} = lane{1-0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002005 let Inst{4} = Rn{5};
Owen Andersone95c9462010-11-02 21:54:45 +00002006}
Bob Wilsonda525062011-02-25 06:42:42 +00002007def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
Richard Barton6e9d66c2012-03-28 10:18:11 +00002008 extractelt, addrmode6oneL32> {
Owen Andersone95c9462010-11-02 21:54:45 +00002009 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002010 let Inst{5-4} = Rn{5-4};
Owen Andersone95c9462010-11-02 21:54:45 +00002011}
Bob Wilsond0c6bc22010-11-02 21:18:25 +00002012
Bob Wilsonda525062011-02-25 06:42:42 +00002013def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2014def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2015def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2016
2017let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
Bob Wilson63c90632009-10-07 20:49:18 +00002018
Bob Wilson8a3198b2009-09-01 18:51:56 +00002019// VST2LN : Vector Store (single 2-element structure from one lane)
Bob Wilson39842552010-03-22 16:43:10 +00002020class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002021 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
Owen Andersonf431eda2010-11-02 23:47:29 +00002022 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2023 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
Owen Andersonb20594f2010-11-02 22:18:18 +00002024 "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00002025 let Rm = 0b1111;
2026 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00002027 let DecoderMethod = "DecodeVST2LN";
Owen Andersonb20594f2010-11-02 22:18:18 +00002028}
Bob Wilson8a3198b2009-09-01 18:51:56 +00002029
Owen Andersonb20594f2010-11-02 22:18:18 +00002030def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2031 let Inst{7-5} = lane{2-0};
2032}
2033def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2034 let Inst{7-6} = lane{1-0};
2035}
2036def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2037 let Inst{7} = lane{0};
2038}
Bob Wilsonc5c6edb2009-10-08 23:38:24 +00002039
Evan Cheng60ff8792010-10-11 22:03:18 +00002040def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2041def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2042def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002043
Bob Wilson41315282010-03-20 20:39:53 +00002044// ...with double-spaced registers:
Owen Andersonb20594f2010-11-02 22:18:18 +00002045def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2046 let Inst{7-6} = lane{1-0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002047 let Inst{4} = Rn{4};
Owen Andersonb20594f2010-11-02 22:18:18 +00002048}
2049def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2050 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002051 let Inst{4} = Rn{4};
Owen Andersonb20594f2010-11-02 22:18:18 +00002052}
Bob Wilsonc5c6edb2009-10-08 23:38:24 +00002053
Evan Cheng60ff8792010-10-11 22:03:18 +00002054def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2055def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
Bob Wilson8a3198b2009-09-01 18:51:56 +00002056
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002057// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00002058class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002059 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
Jim Grosbach9b1b3902011-12-14 23:25:46 +00002060 (ins addrmode6:$Rn, am6offset:$Rm,
2061 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2062 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2063 "$Rn.addr = $wb", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00002064 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00002065 let DecoderMethod = "DecodeVST2LN";
Owen Andersonb20594f2010-11-02 22:18:18 +00002066}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002067
Owen Andersonb20594f2010-11-02 22:18:18 +00002068def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2069 let Inst{7-5} = lane{2-0};
2070}
2071def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2072 let Inst{7-6} = lane{1-0};
2073}
2074def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2075 let Inst{7} = lane{0};
2076}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002077
Evan Cheng60ff8792010-10-11 22:03:18 +00002078def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2079def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2080def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002081
Owen Andersonb20594f2010-11-02 22:18:18 +00002082def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2083 let Inst{7-6} = lane{1-0};
2084}
2085def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2086 let Inst{7} = lane{0};
2087}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002088
Evan Cheng60ff8792010-10-11 22:03:18 +00002089def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2090def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002091
Bob Wilson8a3198b2009-09-01 18:51:56 +00002092// VST3LN : Vector Store (single 3-element structure from one lane)
Bob Wilson39842552010-03-22 16:43:10 +00002093class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002094 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
Owen Andersonf431eda2010-11-02 23:47:29 +00002095 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
Evan Cheng60ff8792010-10-11 22:03:18 +00002096 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00002097 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2098 let Rm = 0b1111;
Owen Anderson7a2e1772011-08-15 18:44:44 +00002099 let DecoderMethod = "DecodeVST3LN";
Owen Andersonb20594f2010-11-02 22:18:18 +00002100}
Bob Wilson8a3198b2009-09-01 18:51:56 +00002101
Owen Andersonb20594f2010-11-02 22:18:18 +00002102def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2103 let Inst{7-5} = lane{2-0};
2104}
2105def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2106 let Inst{7-6} = lane{1-0};
2107}
2108def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2109 let Inst{7} = lane{0};
2110}
Bob Wilson8cdb2692009-10-08 23:51:31 +00002111
Evan Cheng60ff8792010-10-11 22:03:18 +00002112def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2113def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2114def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002115
Bob Wilson41315282010-03-20 20:39:53 +00002116// ...with double-spaced registers:
Owen Andersonb20594f2010-11-02 22:18:18 +00002117def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2118 let Inst{7-6} = lane{1-0};
2119}
2120def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2121 let Inst{7} = lane{0};
2122}
Bob Wilson8cdb2692009-10-08 23:51:31 +00002123
Evan Cheng60ff8792010-10-11 22:03:18 +00002124def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2125def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
Bob Wilson8a3198b2009-09-01 18:51:56 +00002126
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002127// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00002128class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002129 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00002130 (ins addrmode6:$Rn, am6offset:$Rm,
Owen Andersonb20594f2010-11-02 22:18:18 +00002131 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
Evan Cheng60ff8792010-10-11 22:03:18 +00002132 IIC_VST3lnu, "vst3", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00002133 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
Owen Anderson7a2e1772011-08-15 18:44:44 +00002134 "$Rn.addr = $wb", []> {
2135 let DecoderMethod = "DecodeVST3LN";
2136}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002137
Owen Andersonb20594f2010-11-02 22:18:18 +00002138def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2139 let Inst{7-5} = lane{2-0};
2140}
2141def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2142 let Inst{7-6} = lane{1-0};
2143}
2144def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2145 let Inst{7} = lane{0};
2146}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002147
Evan Cheng60ff8792010-10-11 22:03:18 +00002148def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2149def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2150def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002151
Owen Andersonb20594f2010-11-02 22:18:18 +00002152def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2153 let Inst{7-6} = lane{1-0};
2154}
2155def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2156 let Inst{7} = lane{0};
2157}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002158
Evan Cheng60ff8792010-10-11 22:03:18 +00002159def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2160def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002161
Bob Wilson8a3198b2009-09-01 18:51:56 +00002162// VST4LN : Vector Store (single 4-element structure from one lane)
Bob Wilson39842552010-03-22 16:43:10 +00002163class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002164 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
Owen Andersonf431eda2010-11-02 23:47:29 +00002165 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
Evan Cheng60ff8792010-10-11 22:03:18 +00002166 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00002167 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
Owen Andersonb20594f2010-11-02 22:18:18 +00002168 "", []> {
Owen Andersonf431eda2010-11-02 23:47:29 +00002169 let Rm = 0b1111;
2170 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00002171 let DecoderMethod = "DecodeVST4LN";
Owen Andersonb20594f2010-11-02 22:18:18 +00002172}
Bob Wilson8a3198b2009-09-01 18:51:56 +00002173
Owen Andersonb20594f2010-11-02 22:18:18 +00002174def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2175 let Inst{7-5} = lane{2-0};
2176}
2177def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2178 let Inst{7-6} = lane{1-0};
2179}
2180def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2181 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002182 let Inst{5} = Rn{5};
Owen Andersonb20594f2010-11-02 22:18:18 +00002183}
Bob Wilson56311392009-10-09 00:01:36 +00002184
Evan Cheng60ff8792010-10-11 22:03:18 +00002185def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2186def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2187def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002188
Bob Wilson41315282010-03-20 20:39:53 +00002189// ...with double-spaced registers:
Owen Andersonb20594f2010-11-02 22:18:18 +00002190def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2191 let Inst{7-6} = lane{1-0};
2192}
2193def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2194 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002195 let Inst{5} = Rn{5};
Owen Andersonb20594f2010-11-02 22:18:18 +00002196}
Bob Wilson56311392009-10-09 00:01:36 +00002197
Evan Cheng60ff8792010-10-11 22:03:18 +00002198def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2199def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
Bob Wilson56311392009-10-09 00:01:36 +00002200
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002201// ...with address register writeback:
Bob Wilson39842552010-03-22 16:43:10 +00002202class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
Owen Andersonb20594f2010-11-02 22:18:18 +00002203 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
Owen Andersonf431eda2010-11-02 23:47:29 +00002204 (ins addrmode6:$Rn, am6offset:$Rm,
Owen Andersonb20594f2010-11-02 22:18:18 +00002205 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
Evan Cheng60ff8792010-10-11 22:03:18 +00002206 IIC_VST4lnu, "vst4", Dt,
Owen Andersonf431eda2010-11-02 23:47:29 +00002207 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2208 "$Rn.addr = $wb", []> {
2209 let Inst{4} = Rn{4};
Owen Anderson7a2e1772011-08-15 18:44:44 +00002210 let DecoderMethod = "DecodeVST4LN";
Owen Andersonb20594f2010-11-02 22:18:18 +00002211}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002212
Owen Andersonb20594f2010-11-02 22:18:18 +00002213def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2214 let Inst{7-5} = lane{2-0};
2215}
2216def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2217 let Inst{7-6} = lane{1-0};
2218}
2219def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2220 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002221 let Inst{5} = Rn{5};
Owen Andersonb20594f2010-11-02 22:18:18 +00002222}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002223
Evan Cheng60ff8792010-10-11 22:03:18 +00002224def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2225def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2226def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002227
Owen Andersonb20594f2010-11-02 22:18:18 +00002228def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2229 let Inst{7-6} = lane{1-0};
2230}
2231def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2232 let Inst{7} = lane{0};
Owen Andersonf431eda2010-11-02 23:47:29 +00002233 let Inst{5} = Rn{5};
Owen Andersonb20594f2010-11-02 22:18:18 +00002234}
Bob Wilsond5fadaf2010-03-20 21:57:36 +00002235
Evan Cheng60ff8792010-10-11 22:03:18 +00002236def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2237def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
Bob Wilson8466fa12010-09-13 23:01:35 +00002238
Evan Cheng5fd1c9b2010-05-19 06:07:03 +00002239} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
Bob Wilsonb36ec862009-08-06 18:47:44 +00002240
Bob Wilson205a5ca2009-07-08 18:11:30 +00002241
Bob Wilson5bafff32009-06-22 23:27:02 +00002242//===----------------------------------------------------------------------===//
2243// NEON pattern fragments
2244//===----------------------------------------------------------------------===//
2245
2246// Extract D sub-registers of Q registers.
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002247def DSubReg_i8_reg : SDNodeXForm<imm, [{
Jakob Stoklund Olesen7bb31e32010-05-24 17:13:28 +00002248 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2249 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002250}]>;
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002251def DSubReg_i16_reg : SDNodeXForm<imm, [{
Jakob Stoklund Olesen7bb31e32010-05-24 17:13:28 +00002252 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2253 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002254}]>;
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002255def DSubReg_i32_reg : SDNodeXForm<imm, [{
Jakob Stoklund Olesen7bb31e32010-05-24 17:13:28 +00002256 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2257 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002258}]>;
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002259def DSubReg_f64_reg : SDNodeXForm<imm, [{
Jakob Stoklund Olesen7bb31e32010-05-24 17:13:28 +00002260 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2261 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002262}]>;
2263
Anton Korobeynikov2324bdc2009-08-28 23:41:26 +00002264// Extract S sub-registers of Q/D registers.
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002265def SSubReg_f32_reg : SDNodeXForm<imm, [{
Jakob Stoklund Olesen7bb31e32010-05-24 17:13:28 +00002266 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2267 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00002268}]>;
2269
Bob Wilson5bafff32009-06-22 23:27:02 +00002270// Translate lane numbers from Q registers to D subregs.
2271def SubReg_i8_lane : SDNodeXForm<imm, [{
Owen Anderson825b72b2009-08-11 20:47:22 +00002272 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002273}]>;
2274def SubReg_i16_lane : SDNodeXForm<imm, [{
Owen Anderson825b72b2009-08-11 20:47:22 +00002275 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002276}]>;
2277def SubReg_i32_lane : SDNodeXForm<imm, [{
Owen Anderson825b72b2009-08-11 20:47:22 +00002278 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
Bob Wilson5bafff32009-06-22 23:27:02 +00002279}]>;
2280
2281//===----------------------------------------------------------------------===//
2282// Instruction Classes
2283//===----------------------------------------------------------------------===//
2284
Bob Wilson4711d5c2010-12-13 23:02:37 +00002285// Basic 2-register operations: double- and quad-register.
Bob Wilson5bafff32009-06-22 23:27:02 +00002286class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Bob Wilson3c0f96e2010-02-17 22:23:11 +00002287 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2288 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
Owen Andersonca6945e2010-12-01 00:28:25 +00002289 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2290 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2291 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002292class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Bob Wilson3c0f96e2010-02-17 22:23:11 +00002293 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2294 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
Owen Andersonca6945e2010-12-01 00:28:25 +00002295 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2296 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2297 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002298
Bob Wilson69bfbd62010-02-17 22:42:54 +00002299// Basic 2-register intrinsics, both double- and quad-register.
Bob Wilson5bafff32009-06-22 23:27:02 +00002300class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Johnny Chenfa80bec2010-03-25 20:39:04 +00002301 bits<2> op17_16, bits<5> op11_7, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002302 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002303 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Andersonca6945e2010-12-01 00:28:25 +00002304 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2305 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2306 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002307class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
David Goodwin127221f2009-09-23 21:38:08 +00002308 bits<2> op17_16, bits<5> op11_7, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002309 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002310 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Andersonca6945e2010-12-01 00:28:25 +00002311 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2312 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2313 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002314
Bob Wilson973a0742010-08-30 20:02:30 +00002315// Narrow 2-register operations.
2316class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2317 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2318 InstrItinClass itin, string OpcodeStr, string Dt,
2319 ValueType TyD, ValueType TyQ, SDNode OpNode>
Owen Andersonca6945e2010-12-01 00:28:25 +00002320 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2321 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2322 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
Bob Wilson973a0742010-08-30 20:02:30 +00002323
Bob Wilson5bafff32009-06-22 23:27:02 +00002324// Narrow 2-register intrinsics.
2325class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2326 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002327 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002328 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
Owen Andersonca6945e2010-12-01 00:28:25 +00002329 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2330 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2331 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002332
Bob Wilsonb31a11b2010-08-20 04:54:02 +00002333// Long 2-register operations (currently only used for VMOVL).
2334class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2335 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2336 InstrItinClass itin, string OpcodeStr, string Dt,
2337 ValueType TyQ, ValueType TyD, SDNode OpNode>
Owen Andersonca6945e2010-12-01 00:28:25 +00002338 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2339 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2340 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002341
Bob Wilson04063562010-12-15 22:14:12 +00002342// Long 2-register intrinsics.
2343class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2344 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002346 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
Bob Wilson04063562010-12-15 22:14:12 +00002347 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2348 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2349 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2350
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00002351// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
Evan Chengf81bf152009-11-23 21:57:23 +00002352class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
Owen Andersonca6945e2010-12-01 00:28:25 +00002353 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002354 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
Owen Andersonca6945e2010-12-01 00:28:25 +00002355 OpcodeStr, Dt, "$Vd, $Vm",
2356 "$src1 = $Vd, $src2 = $Vm", []>;
David Goodwin127221f2009-09-23 21:38:08 +00002357class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
Evan Chengf81bf152009-11-23 21:57:23 +00002358 InstrItinClass itin, string OpcodeStr, string Dt>
Owen Andersonca6945e2010-12-01 00:28:25 +00002359 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2360 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2361 "$src1 = $Vd, $src2 = $Vm", []>;
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00002362
Bob Wilson4711d5c2010-12-13 23:02:37 +00002363// Basic 3-register operations: double- and quad-register.
Bob Wilson5bafff32009-06-22 23:27:02 +00002364class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002365 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson9abe19d2010-02-17 00:31:29 +00002366 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Bob Wilson5bafff32009-06-22 23:27:02 +00002367 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersond451f882010-10-21 20:21:49 +00002368 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2369 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2370 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002371 // All of these have a two-operand InstAlias.
2372 let TwoOperandAliasConstraint = "$Vn = $Vd";
Evan Chengf81bf152009-11-23 21:57:23 +00002373 let isCommutable = Commutable;
2374}
2375// Same as N3VD but no data type.
2376class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2377 InstrItinClass itin, string OpcodeStr,
2378 ValueType ResTy, ValueType OpTy,
2379 SDNode OpNode, bit Commutable>
2380 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
Jim Grosbachefaeb412010-11-19 22:36:02 +00002381 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2382 OpcodeStr, "$Vd, $Vn, $Vm", "",
2383 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002384 // All of these have a two-operand InstAlias.
2385 let TwoOperandAliasConstraint = "$Vn = $Vd";
Bob Wilson5bafff32009-06-22 23:27:02 +00002386 let isCommutable = Commutable;
2387}
Johnny Chen897dd0c2010-03-27 01:03:13 +00002388
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002389class N3VDSL<bits<2> op21_20, bits<4> op11_8,
Evan Chengf81bf152009-11-23 21:57:23 +00002390 InstrItinClass itin, string OpcodeStr, string Dt,
2391 ValueType Ty, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002392 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
Jim Grosbach970f7872011-10-18 18:01:52 +00002393 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2394 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002395 [(set (Ty DPR:$Vd),
2396 (Ty (ShOp (Ty DPR:$Vn),
2397 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00002398 // All of these have a two-operand InstAlias.
2399 let TwoOperandAliasConstraint = "$Vn = $Vd";
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002400 let isCommutable = 0;
2401}
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002402class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
Evan Chengf81bf152009-11-23 21:57:23 +00002403 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002404 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
Jim Grosbach970f7872011-10-18 18:01:52 +00002405 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2406 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
Owen Andersonca6945e2010-12-01 00:28:25 +00002407 [(set (Ty DPR:$Vd),
2408 (Ty (ShOp (Ty DPR:$Vn),
2409 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00002410 // All of these have a two-operand InstAlias.
2411 let TwoOperandAliasConstraint = "$Vn = $Vd";
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002412 let isCommutable = 0;
2413}
2414
Bob Wilson5bafff32009-06-22 23:27:02 +00002415class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002416 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson9abe19d2010-02-17 00:31:29 +00002417 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Bob Wilson5bafff32009-06-22 23:27:02 +00002418 : N3V<op24, op23, op21_20, op11_8, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002419 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2420 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2421 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002422 // All of these have a two-operand InstAlias.
2423 let TwoOperandAliasConstraint = "$Vn = $Vd";
Evan Chengf81bf152009-11-23 21:57:23 +00002424 let isCommutable = Commutable;
2425}
2426class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2427 InstrItinClass itin, string OpcodeStr,
Bob Wilson9abe19d2010-02-17 00:31:29 +00002428 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
Evan Chengf81bf152009-11-23 21:57:23 +00002429 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002430 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2431 OpcodeStr, "$Vd, $Vn, $Vm", "",
2432 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002433 // All of these have a two-operand InstAlias.
2434 let TwoOperandAliasConstraint = "$Vn = $Vd";
Bob Wilson5bafff32009-06-22 23:27:02 +00002435 let isCommutable = Commutable;
2436}
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002437class N3VQSL<bits<2> op21_20, bits<4> op11_8,
Evan Chengf81bf152009-11-23 21:57:23 +00002438 InstrItinClass itin, string OpcodeStr, string Dt,
David Goodwin658ea602009-09-25 18:38:29 +00002439 ValueType ResTy, ValueType OpTy, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002440 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002441 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2442 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002443 [(set (ResTy QPR:$Vd),
2444 (ResTy (ShOp (ResTy QPR:$Vn),
2445 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002446 imm:$lane)))))]> {
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00002447 // All of these have a two-operand InstAlias.
2448 let TwoOperandAliasConstraint = "$Vn = $Vd";
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002449 let isCommutable = 0;
2450}
Bob Wilson9abe19d2010-02-17 00:31:29 +00002451class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
Evan Chengf81bf152009-11-23 21:57:23 +00002452 ValueType ResTy, ValueType OpTy, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002453 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002454 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2455 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002456 [(set (ResTy QPR:$Vd),
2457 (ResTy (ShOp (ResTy QPR:$Vn),
2458 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002459 imm:$lane)))))]> {
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00002460 // All of these have a two-operand InstAlias.
2461 let TwoOperandAliasConstraint = "$Vn = $Vd";
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002462 let isCommutable = 0;
2463}
Bob Wilson5bafff32009-06-22 23:27:02 +00002464
2465// Basic 3-register intrinsics, both double- and quad-register.
2466class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00002467 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002468 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
Bob Wilson10bc69c2010-03-27 03:56:52 +00002469 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersond451f882010-10-21 20:21:49 +00002470 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2471 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2472 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002473 // All of these have a two-operand InstAlias.
2474 let TwoOperandAliasConstraint = "$Vn = $Vd";
Bob Wilson5bafff32009-06-22 23:27:02 +00002475 let isCommutable = Commutable;
2476}
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002477class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002478 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002479 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
Jim Grosbach0a037402011-10-18 18:12:09 +00002480 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2481 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002482 [(set (Ty DPR:$Vd),
2483 (Ty (IntOp (Ty DPR:$Vn),
2484 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002485 imm:$lane)))))]> {
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002486 let isCommutable = 0;
2487}
David Goodwin658ea602009-09-25 18:38:29 +00002488class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002489 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002490 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
Jim Grosbach0a037402011-10-18 18:12:09 +00002491 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2492 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002493 [(set (Ty DPR:$Vd),
2494 (Ty (IntOp (Ty DPR:$Vn),
2495 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002496 let isCommutable = 0;
2497}
Owen Anderson3557d002010-10-26 20:56:57 +00002498class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2499 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002500 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson3557d002010-10-26 20:56:57 +00002501 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2502 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2503 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2504 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
Jim Grosbachd83c9ea2012-04-20 23:30:14 +00002505 let TwoOperandAliasConstraint = "$Vm = $Vd";
Owen Andersonac922622010-10-26 21:13:59 +00002506 let isCommutable = 0;
Owen Anderson3557d002010-10-26 20:56:57 +00002507}
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002508
Bob Wilson5bafff32009-06-22 23:27:02 +00002509class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00002510 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002511 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
Bob Wilson10bc69c2010-03-27 03:56:52 +00002512 : N3V<op24, op23, op21_20, op11_8, 1, op4,
Owen Andersond451f882010-10-21 20:21:49 +00002513 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2514 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2515 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002516 // All of these have a two-operand InstAlias.
2517 let TwoOperandAliasConstraint = "$Vn = $Vd";
Bob Wilson5bafff32009-06-22 23:27:02 +00002518 let isCommutable = Commutable;
2519}
Jim Grosbach1251e1a2010-11-18 01:39:50 +00002520class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002521 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002522 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002523 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002524 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2525 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002526 [(set (ResTy QPR:$Vd),
2527 (ResTy (IntOp (ResTy QPR:$Vn),
2528 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002529 imm:$lane)))))]> {
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002530 let isCommutable = 0;
2531}
David Goodwin658ea602009-09-25 18:38:29 +00002532class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002533 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002534 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002535 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002536 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2537 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002538 [(set (ResTy QPR:$Vd),
2539 (ResTy (IntOp (ResTy QPR:$Vn),
2540 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002541 imm:$lane)))))]> {
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002542 let isCommutable = 0;
2543}
Owen Anderson3557d002010-10-26 20:56:57 +00002544class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2545 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002546 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson3557d002010-10-26 20:56:57 +00002547 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2548 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2549 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2550 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
Jim Grosbachd83c9ea2012-04-20 23:30:14 +00002551 let TwoOperandAliasConstraint = "$Vm = $Vd";
Owen Andersonac922622010-10-26 21:13:59 +00002552 let isCommutable = 0;
Owen Anderson3557d002010-10-26 20:56:57 +00002553}
Bob Wilson5bafff32009-06-22 23:27:02 +00002554
Bob Wilson4711d5c2010-12-13 23:02:37 +00002555// Multiply-Add/Sub operations: double- and quad-register.
Bob Wilson5bafff32009-06-22 23:27:02 +00002556class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002557 InstrItinClass itin, string OpcodeStr, string Dt,
Evan Cheng48575f62010-12-05 22:04:16 +00002558 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
Bob Wilson5bafff32009-06-22 23:27:02 +00002559 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Anderson18341e92010-10-22 18:54:37 +00002560 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2561 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2562 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2563 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2564
David Goodwin658ea602009-09-25 18:38:29 +00002565class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002566 string OpcodeStr, string Dt,
Evan Cheng48575f62010-12-05 22:04:16 +00002567 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002568 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00002569 (outs DPR:$Vd),
Jim Grosbach91200882011-10-18 18:27:07 +00002570 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002571 NVMulSLFrm, itin,
Jim Grosbach91200882011-10-18 18:27:07 +00002572 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002573 [(set (Ty DPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002574 (Ty (ShOp (Ty DPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002575 (Ty (MulOp DPR:$Vn,
2576 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002577 imm:$lane)))))))]>;
David Goodwin658ea602009-09-25 18:38:29 +00002578class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002579 string OpcodeStr, string Dt,
2580 ValueType Ty, SDNode MulOp, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002581 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
Owen Anderson18341e92010-10-22 18:54:37 +00002582 (outs DPR:$Vd),
Jim Grosbach91200882011-10-18 18:27:07 +00002583 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002584 NVMulSLFrm, itin,
Jim Grosbach91200882011-10-18 18:27:07 +00002585 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Anderson18341e92010-10-22 18:54:37 +00002586 [(set (Ty DPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002587 (Ty (ShOp (Ty DPR:$src1),
Owen Anderson18341e92010-10-22 18:54:37 +00002588 (Ty (MulOp DPR:$Vn,
2589 (Ty (NEONvduplane (Ty DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002590 imm:$lane)))))))]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002591
Bob Wilson5bafff32009-06-22 23:27:02 +00002592class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002593 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
Evan Cheng48575f62010-12-05 22:04:16 +00002594 SDPatternOperator MulOp, SDPatternOperator OpNode>
Bob Wilson5bafff32009-06-22 23:27:02 +00002595 : N3V<op24, op23, op21_20, op11_8, 1, op4,
Owen Anderson18341e92010-10-22 18:54:37 +00002596 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2597 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2598 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2599 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
David Goodwin658ea602009-09-25 18:38:29 +00002600class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002601 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Evan Cheng48575f62010-12-05 22:04:16 +00002602 SDPatternOperator MulOp, SDPatternOperator ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002603 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00002604 (outs QPR:$Vd),
Jim Grosbach91200882011-10-18 18:27:07 +00002605 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002606 NVMulSLFrm, itin,
Jim Grosbach91200882011-10-18 18:27:07 +00002607 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002608 [(set (ResTy QPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002609 (ResTy (ShOp (ResTy QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002610 (ResTy (MulOp QPR:$Vn,
2611 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002612 imm:$lane)))))))]>;
David Goodwin658ea602009-09-25 18:38:29 +00002613class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002614 string OpcodeStr, string Dt,
2615 ValueType ResTy, ValueType OpTy,
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002616 SDNode MulOp, SDNode ShOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002617 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00002618 (outs QPR:$Vd),
Jim Grosbach91200882011-10-18 18:27:07 +00002619 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002620 NVMulSLFrm, itin,
Jim Grosbach91200882011-10-18 18:27:07 +00002621 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002622 [(set (ResTy QPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002623 (ResTy (ShOp (ResTy QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002624 (ResTy (MulOp QPR:$Vn,
2625 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002626 imm:$lane)))))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002627
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002628// Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2629class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2630 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002631 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002632 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Anderson410aebc2010-10-25 20:52:57 +00002633 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2634 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2635 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2636 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002637class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2638 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002639 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002640 : N3V<op24, op23, op21_20, op11_8, 1, op4,
Owen Anderson410aebc2010-10-25 20:52:57 +00002641 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2642 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2643 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2644 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002645
Bob Wilson5bafff32009-06-22 23:27:02 +00002646// Neon 3-argument intrinsics, both double- and quad-register.
2647// The destination register is also used as the first source operand register.
2648class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002649 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002650 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Bob Wilson5bafff32009-06-22 23:27:02 +00002651 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002652 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2653 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2654 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2655 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002656class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002657 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002658 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Bob Wilson5bafff32009-06-22 23:27:02 +00002659 : N3V<op24, op23, op21_20, op11_8, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002660 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2661 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2662 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2663 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002664
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002665// Long Multiply-Add/Sub operations.
2666class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2667 InstrItinClass itin, string OpcodeStr, string Dt,
2668 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2669 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Anderson92205842010-10-22 19:05:25 +00002670 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2671 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2672 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2673 (TyQ (MulOp (TyD DPR:$Vn),
2674 (TyD DPR:$Vm)))))]>;
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002675class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2676 InstrItinClass itin, string OpcodeStr, string Dt,
2677 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002678 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
Jim Grosbachaead5792011-10-18 20:14:56 +00002679 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002680 NVMulSLFrm, itin,
Jim Grosbachaead5792011-10-18 20:14:56 +00002681 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002682 [(set QPR:$Vd,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002683 (OpNode (TyQ QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002684 (TyQ (MulOp (TyD DPR:$Vn),
2685 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002686 imm:$lane))))))]>;
2687class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2688 InstrItinClass itin, string OpcodeStr, string Dt,
2689 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002690 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
Jim Grosbachaead5792011-10-18 20:14:56 +00002691 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002692 NVMulSLFrm, itin,
Jim Grosbachaead5792011-10-18 20:14:56 +00002693 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002694 [(set QPR:$Vd,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002695 (OpNode (TyQ QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002696 (TyQ (MulOp (TyD DPR:$Vn),
2697 (TyD (NEONvduplane (TyD DPR_8:$Vm),
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002698 imm:$lane))))))]>;
2699
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002700// Long Intrinsic-Op vector operations with explicit extend (VABAL).
2701class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2702 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002703 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002704 SDNode OpNode>
2705 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Anderson5258b612010-10-25 21:29:04 +00002706 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2707 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2708 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2709 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2710 (TyD DPR:$Vm)))))))]>;
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002711
Bob Wilson5bafff32009-06-22 23:27:02 +00002712// Neon Long 3-argument intrinsic. The destination register is
2713// a quad-register and is also used as the first source operand register.
2714class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002715 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002716 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
Bob Wilson5bafff32009-06-22 23:27:02 +00002717 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Anderson9b264972010-10-22 19:35:48 +00002718 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2719 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2720 [(set QPR:$Vd,
2721 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
David Goodwin658ea602009-09-25 18:38:29 +00002722class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002723 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002724 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002725 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00002726 (outs QPR:$Vd),
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002727 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002728 NVMulSLFrm, itin,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002729 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002730 [(set (ResTy QPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002731 (ResTy (IntOp (ResTy QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002732 (OpTy DPR:$Vn),
2733 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002734 imm:$lane)))))]>;
Bob Wilson9abe19d2010-02-17 00:31:29 +00002735class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2736 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002737 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002738 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00002739 (outs QPR:$Vd),
Jim Grosbache873d2a2011-10-18 17:16:30 +00002740 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002741 NVMulSLFrm, itin,
Jim Grosbache873d2a2011-10-18 17:16:30 +00002742 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
Owen Andersonca6945e2010-12-01 00:28:25 +00002743 [(set (ResTy QPR:$Vd),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002744 (ResTy (IntOp (ResTy QPR:$src1),
Owen Andersonca6945e2010-12-01 00:28:25 +00002745 (OpTy DPR:$Vn),
2746 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002747 imm:$lane)))))]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00002748
Bob Wilson5bafff32009-06-22 23:27:02 +00002749// Narrowing 3-register intrinsics.
2750class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002751 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002752 SDPatternOperator IntOp, bit Commutable>
Bob Wilson5bafff32009-06-22 23:27:02 +00002753 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002754 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2755 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2756 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
Bob Wilson5bafff32009-06-22 23:27:02 +00002757 let isCommutable = Commutable;
2758}
2759
Bob Wilson04d6c282010-08-29 05:57:34 +00002760// Long 3-register operations.
2761class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2762 InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002763 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2764 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002765 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2766 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2767 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002768 let isCommutable = Commutable;
2769}
2770class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2771 InstrItinClass itin, string OpcodeStr, string Dt,
2772 ValueType TyQ, ValueType TyD, SDNode OpNode>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002773 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002774 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2775 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002776 [(set QPR:$Vd,
2777 (TyQ (OpNode (TyD DPR:$Vn),
2778 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002779class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2780 InstrItinClass itin, string OpcodeStr, string Dt,
2781 ValueType TyQ, ValueType TyD, SDNode OpNode>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002782 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002783 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2784 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002785 [(set QPR:$Vd,
2786 (TyQ (OpNode (TyD DPR:$Vn),
2787 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
Bob Wilsond0b69cf2010-09-01 23:50:19 +00002788
2789// Long 3-register operations with explicitly extended operands.
2790class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2791 InstrItinClass itin, string OpcodeStr, string Dt,
2792 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2793 bit Commutable>
Bob Wilson04d6c282010-08-29 05:57:34 +00002794 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002795 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2796 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2797 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2798 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
Owen Andersone0e6dc32010-10-21 18:09:17 +00002799 let isCommutable = Commutable;
Bob Wilson04d6c282010-08-29 05:57:34 +00002800}
2801
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002802// Long 3-register intrinsics with explicit extend (VABDL).
2803class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2804 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002805 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002806 bit Commutable>
2807 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002808 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2809 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2810 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2811 (TyD DPR:$Vm))))))]> {
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00002812 let isCommutable = Commutable;
2813}
2814
Bob Wilson5bafff32009-06-22 23:27:02 +00002815// Long 3-register intrinsics.
2816class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002817 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002818 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
Bob Wilson5bafff32009-06-22 23:27:02 +00002819 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002820 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2821 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2822 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
Bob Wilson5bafff32009-06-22 23:27:02 +00002823 let isCommutable = Commutable;
2824}
David Goodwin658ea602009-09-25 18:38:29 +00002825class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
Evan Chengf81bf152009-11-23 21:57:23 +00002826 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002827 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002828 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002829 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2830 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002831 [(set (ResTy QPR:$Vd),
2832 (ResTy (IntOp (OpTy DPR:$Vn),
2833 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002834 imm:$lane)))))]>;
Bob Wilson9abe19d2010-02-17 00:31:29 +00002835class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2836 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002837 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Anderson6a7d36a2011-03-30 23:45:29 +00002838 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
Jim Grosbacha7d2e752011-10-18 20:21:17 +00002839 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2840 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
Owen Andersonca6945e2010-12-01 00:28:25 +00002841 [(set (ResTy QPR:$Vd),
2842 (ResTy (IntOp (OpTy DPR:$Vn),
2843 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00002844 imm:$lane)))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002845
Bob Wilson04d6c282010-08-29 05:57:34 +00002846// Wide 3-register operations.
2847class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2848 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2849 SDNode OpNode, SDNode ExtOp, bit Commutable>
Bob Wilson5bafff32009-06-22 23:27:02 +00002850 : N3V<op24, op23, op21_20, op11_8, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00002851 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2852 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2853 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2854 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
Jim Grosbachd8b3ed82012-04-20 18:12:54 +00002855 // All of these have a two-operand InstAlias.
2856 let TwoOperandAliasConstraint = "$Vn = $Vd";
Bob Wilson5bafff32009-06-22 23:27:02 +00002857 let isCommutable = Commutable;
2858}
2859
2860// Pairwise long 2-register intrinsics, both double- and quad-register.
2861class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Chengf81bf152009-11-23 21:57:23 +00002862 bits<2> op17_16, bits<5> op11_7, bit op4,
2863 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002864 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Andersonca6945e2010-12-01 00:28:25 +00002865 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2866 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2867 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002868class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Chengf81bf152009-11-23 21:57:23 +00002869 bits<2> op17_16, bits<5> op11_7, bit op4,
2870 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002871 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Owen Andersonca6945e2010-12-01 00:28:25 +00002872 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2873 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2874 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002875
2876// Pairwise long 2-register accumulate intrinsics,
2877// both double- and quad-register.
2878// The destination register is also used as the first source operand register.
2879class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Chengf81bf152009-11-23 21:57:23 +00002880 bits<2> op17_16, bits<5> op11_7, bit op4,
2881 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002882 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Bob Wilson5bafff32009-06-22 23:27:02 +00002883 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
Owen Andersonbc4118b2010-10-26 18:18:03 +00002884 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2885 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2886 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002887class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
Evan Chengf81bf152009-11-23 21:57:23 +00002888 bits<2> op17_16, bits<5> op11_7, bit op4,
2889 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002890 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
Bob Wilson5bafff32009-06-22 23:27:02 +00002891 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
Owen Andersonbc4118b2010-10-26 18:18:03 +00002892 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2893 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2894 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002895
2896// Shift by immediate,
2897// both double- and quad-register.
Jim Grosbachd83c9ea2012-04-20 23:30:14 +00002898let TwoOperandAliasConstraint = "$Vm = $Vd" in {
Bob Wilson507df402009-10-21 02:15:46 +00002899class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendling7c6b6082011-03-08 23:48:09 +00002900 Format f, InstrItinClass itin, Operand ImmTy,
2901 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
Bob Wilson507df402009-10-21 02:15:46 +00002902 : N2VImm<op24, op23, op11_8, op7, 0, op4,
Bill Wendling7c6b6082011-03-08 23:48:09 +00002903 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
Owen Andersonca6945e2010-12-01 00:28:25 +00002904 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2905 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
Bob Wilson507df402009-10-21 02:15:46 +00002906class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendling7c6b6082011-03-08 23:48:09 +00002907 Format f, InstrItinClass itin, Operand ImmTy,
2908 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
Bob Wilson507df402009-10-21 02:15:46 +00002909 : N2VImm<op24, op23, op11_8, op7, 1, op4,
Bill Wendling7c6b6082011-03-08 23:48:09 +00002910 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
Owen Andersonca6945e2010-12-01 00:28:25 +00002911 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2912 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
Jim Grosbachd83c9ea2012-04-20 23:30:14 +00002913}
Bob Wilson5bafff32009-06-22 23:27:02 +00002914
Johnny Chen6c8648b2010-03-17 23:26:50 +00002915// Long shift by immediate.
2916class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2917 string OpcodeStr, string Dt,
Jim Grosbach4e413952011-12-07 00:02:17 +00002918 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
Johnny Chen6c8648b2010-03-17 23:26:50 +00002919 : N2VImm<op24, op23, op11_8, op7, op6, op4,
Jim Grosbach4e413952011-12-07 00:02:17 +00002920 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
Owen Andersonca6945e2010-12-01 00:28:25 +00002921 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2922 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
Johnny Chen6c8648b2010-03-17 23:26:50 +00002923 (i32 imm:$SIMM))))]>;
2924
Bob Wilson5bafff32009-06-22 23:27:02 +00002925// Narrow shift by immediate.
Bob Wilson507df402009-10-21 02:15:46 +00002926class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002927 InstrItinClass itin, string OpcodeStr, string Dt,
Bill Wendlinga656b632011-03-01 01:00:59 +00002928 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
Bob Wilson507df402009-10-21 02:15:46 +00002929 : N2VImm<op24, op23, op11_8, op7, op6, op4,
Bill Wendlinga656b632011-03-01 01:00:59 +00002930 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
Owen Andersonca6945e2010-12-01 00:28:25 +00002931 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2932 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
Bob Wilson5bafff32009-06-22 23:27:02 +00002933 (i32 imm:$SIMM))))]>;
2934
2935// Shift right by immediate and accumulate,
2936// both double- and quad-register.
Jim Grosbache1d866e2012-04-23 21:00:49 +00002937let TwoOperandAliasConstraint = "$Vm = $Vd" in {
Bob Wilson507df402009-10-21 02:15:46 +00002938class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendlingc04a9de2011-03-09 00:00:35 +00002939 Operand ImmTy, string OpcodeStr, string Dt,
2940 ValueType Ty, SDNode ShOp>
Owen Andersondd31ed62010-10-27 17:29:29 +00002941 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
Bill Wendlingc04a9de2011-03-09 00:00:35 +00002942 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
Owen Andersondd31ed62010-10-27 17:29:29 +00002943 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2944 [(set DPR:$Vd, (Ty (add DPR:$src1,
2945 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
Bob Wilson507df402009-10-21 02:15:46 +00002946class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendlingc04a9de2011-03-09 00:00:35 +00002947 Operand ImmTy, string OpcodeStr, string Dt,
2948 ValueType Ty, SDNode ShOp>
Owen Andersondd31ed62010-10-27 17:29:29 +00002949 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
Bill Wendlingc04a9de2011-03-09 00:00:35 +00002950 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
Owen Andersondd31ed62010-10-27 17:29:29 +00002951 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2952 [(set QPR:$Vd, (Ty (add QPR:$src1,
2953 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
Jim Grosbache1d866e2012-04-23 21:00:49 +00002954}
Bob Wilson5bafff32009-06-22 23:27:02 +00002955
2956// Shift by immediate and insert,
2957// both double- and quad-register.
Jim Grosbache1d866e2012-04-23 21:00:49 +00002958let TwoOperandAliasConstraint = "$Vm = $Vd" in {
Bob Wilson507df402009-10-21 02:15:46 +00002959class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendling620d0cc2011-03-09 00:33:17 +00002960 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2961 ValueType Ty,SDNode ShOp>
Owen Anderson0745c382010-10-27 17:40:08 +00002962 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
Bill Wendling620d0cc2011-03-09 00:33:17 +00002963 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
Owen Anderson0745c382010-10-27 17:40:08 +00002964 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2965 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
Bob Wilson507df402009-10-21 02:15:46 +00002966class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Bill Wendling620d0cc2011-03-09 00:33:17 +00002967 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2968 ValueType Ty,SDNode ShOp>
Owen Anderson0745c382010-10-27 17:40:08 +00002969 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
Bill Wendling620d0cc2011-03-09 00:33:17 +00002970 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
Owen Anderson0745c382010-10-27 17:40:08 +00002971 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2972 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
Jim Grosbache1d866e2012-04-23 21:00:49 +00002973}
Bob Wilson5bafff32009-06-22 23:27:02 +00002974
2975// Convert, with fractional bits immediate,
2976// both double- and quad-register.
Bob Wilson507df402009-10-21 02:15:46 +00002977class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002978 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002979 SDPatternOperator IntOp>
Bob Wilson507df402009-10-21 02:15:46 +00002980 : N2VImm<op24, op23, op11_8, op7, 0, op4,
Owen Anderson498ec202010-10-27 22:49:00 +00002981 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2982 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2983 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
Bob Wilson507df402009-10-21 02:15:46 +00002984class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00002985 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00002986 SDPatternOperator IntOp>
Bob Wilson507df402009-10-21 02:15:46 +00002987 : N2VImm<op24, op23, op11_8, op7, 1, op4,
Owen Anderson498ec202010-10-27 22:49:00 +00002988 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2989 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2990 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00002991
2992//===----------------------------------------------------------------------===//
2993// Multiclasses
2994//===----------------------------------------------------------------------===//
2995
Bob Wilson916ac5b2009-10-03 04:44:16 +00002996// Abbreviations used in multiclass suffixes:
2997// Q = quarter int (8 bit) elements
2998// H = half int (16 bit) elements
2999// S = single int (32 bit) elements
3000// D = double int (64 bit) elements
3001
Bob Wilson094dd802010-12-18 00:42:58 +00003002// Neon 2-register vector operations and intrinsics.
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003003
Bob Wilson094dd802010-12-18 00:42:58 +00003004// Neon 2-register comparisons.
3005// source operand element sizes of 8, 16 and 32 bits:
Johnny Chen363ac582010-02-23 01:42:58 +00003006multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3007 bits<5> op11_7, bit op4, string opc, string Dt,
Owen Andersonc24cb352010-11-08 23:21:22 +00003008 string asm, SDNode OpNode> {
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003009 // 64-bit vector types.
3010 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003011 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003012 opc, !strconcat(Dt, "8"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003013 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003014 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003015 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003016 opc, !strconcat(Dt, "16"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003017 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003018 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003019 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003020 opc, !strconcat(Dt, "32"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003021 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003022 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003023 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003024 opc, "f32", asm, "",
Bob Wilson3deb4512010-12-18 00:04:33 +00003025 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003026 let Inst{10} = 1; // overwrite F = 1
3027 }
3028
3029 // 128-bit vector types.
3030 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003031 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003032 opc, !strconcat(Dt, "8"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003033 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003034 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003035 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003036 opc, !strconcat(Dt, "16"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003037 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003038 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003039 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003040 opc, !strconcat(Dt, "32"), asm, "",
Owen Andersonca6945e2010-12-01 00:28:25 +00003041 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003042 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
Owen Andersonca6945e2010-12-01 00:28:25 +00003043 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
Owen Andersonc24cb352010-11-08 23:21:22 +00003044 opc, "f32", asm, "",
Bob Wilson3deb4512010-12-18 00:04:33 +00003045 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
Johnny Chenec5a4cd2010-02-23 00:33:12 +00003046 let Inst{10} = 1; // overwrite F = 1
3047 }
3048}
3049
Bob Wilson094dd802010-12-18 00:42:58 +00003050
3051// Neon 2-register vector intrinsics,
3052// element sizes of 8, 16 and 32 bits:
3053multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3054 bits<5> op11_7, bit op4,
3055 InstrItinClass itinD, InstrItinClass itinQ,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003056 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Bob Wilson094dd802010-12-18 00:42:58 +00003057 // 64-bit vector types.
3058 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3059 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3060 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3061 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3062 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3063 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3064
3065 // 128-bit vector types.
3066 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3067 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3068 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3069 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3070 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3071 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3072}
3073
3074
3075// Neon Narrowing 2-register vector operations,
3076// source operand element sizes of 16, 32 and 64 bits:
3077multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3078 bits<5> op11_7, bit op6, bit op4,
3079 InstrItinClass itin, string OpcodeStr, string Dt,
3080 SDNode OpNode> {
3081 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3082 itin, OpcodeStr, !strconcat(Dt, "16"),
3083 v8i8, v8i16, OpNode>;
3084 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3085 itin, OpcodeStr, !strconcat(Dt, "32"),
3086 v4i16, v4i32, OpNode>;
3087 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3088 itin, OpcodeStr, !strconcat(Dt, "64"),
3089 v2i32, v2i64, OpNode>;
3090}
3091
3092// Neon Narrowing 2-register vector intrinsics,
3093// source operand element sizes of 16, 32 and 64 bits:
3094multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3095 bits<5> op11_7, bit op6, bit op4,
3096 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003097 SDPatternOperator IntOp> {
Bob Wilson094dd802010-12-18 00:42:58 +00003098 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3099 itin, OpcodeStr, !strconcat(Dt, "16"),
3100 v8i8, v8i16, IntOp>;
3101 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3102 itin, OpcodeStr, !strconcat(Dt, "32"),
3103 v4i16, v4i32, IntOp>;
3104 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3105 itin, OpcodeStr, !strconcat(Dt, "64"),
3106 v2i32, v2i64, IntOp>;
3107}
3108
3109
3110// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3111// source operand element sizes of 16, 32 and 64 bits:
3112multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3113 string OpcodeStr, string Dt, SDNode OpNode> {
3114 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3115 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3116 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3117 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3118 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3119 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3120}
3121
3122
Bob Wilson5bafff32009-06-22 23:27:02 +00003123// Neon 3-register vector operations.
3124
3125// First with only element sizes of 8, 16 and 32 bits:
3126multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin127221f2009-09-23 21:38:08 +00003127 InstrItinClass itinD16, InstrItinClass itinD32,
3128 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003129 string OpcodeStr, string Dt,
3130 SDNode OpNode, bit Commutable = 0> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003131 // 64-bit vector types.
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003132 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003133 OpcodeStr, !strconcat(Dt, "8"),
3134 v8i8, v8i8, OpNode, Commutable>;
David Goodwin127221f2009-09-23 21:38:08 +00003135 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003136 OpcodeStr, !strconcat(Dt, "16"),
3137 v4i16, v4i16, OpNode, Commutable>;
David Goodwin127221f2009-09-23 21:38:08 +00003138 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003139 OpcodeStr, !strconcat(Dt, "32"),
3140 v2i32, v2i32, OpNode, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003141
3142 // 128-bit vector types.
David Goodwin127221f2009-09-23 21:38:08 +00003143 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003144 OpcodeStr, !strconcat(Dt, "8"),
3145 v16i8, v16i8, OpNode, Commutable>;
David Goodwin127221f2009-09-23 21:38:08 +00003146 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003147 OpcodeStr, !strconcat(Dt, "16"),
3148 v8i16, v8i16, OpNode, Commutable>;
David Goodwin127221f2009-09-23 21:38:08 +00003149 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003150 OpcodeStr, !strconcat(Dt, "32"),
3151 v4i32, v4i32, OpNode, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003152}
3153
Jim Grosbach45755a72011-12-05 20:09:44 +00003154multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
Jim Grosbach422faab2011-12-05 20:12:26 +00003155 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3156 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
Jim Grosbach45755a72011-12-05 20:09:44 +00003157 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
Jim Grosbach422faab2011-12-05 20:12:26 +00003158 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
Evan Chengac0869d2009-11-21 06:21:52 +00003159 v4i32, v2i32, ShOp>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003160}
3161
Bob Wilson5bafff32009-06-22 23:27:02 +00003162// ....then also with element size 64 bits:
3163multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin127221f2009-09-23 21:38:08 +00003164 InstrItinClass itinD, InstrItinClass itinQ,
Evan Chengf81bf152009-11-23 21:57:23 +00003165 string OpcodeStr, string Dt,
3166 SDNode OpNode, bit Commutable = 0>
David Goodwin127221f2009-09-23 21:38:08 +00003167 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
Evan Chengf81bf152009-11-23 21:57:23 +00003168 OpcodeStr, Dt, OpNode, Commutable> {
David Goodwin127221f2009-09-23 21:38:08 +00003169 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
Evan Chengf81bf152009-11-23 21:57:23 +00003170 OpcodeStr, !strconcat(Dt, "64"),
3171 v1i64, v1i64, OpNode, Commutable>;
David Goodwin127221f2009-09-23 21:38:08 +00003172 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
Evan Chengf81bf152009-11-23 21:57:23 +00003173 OpcodeStr, !strconcat(Dt, "64"),
3174 v2i64, v2i64, OpNode, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003175}
3176
3177
Bob Wilson5bafff32009-06-22 23:27:02 +00003178// Neon 3-register vector intrinsics.
3179
3180// First with only element sizes of 16 and 32 bits:
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003181multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
David Goodwin658ea602009-09-25 18:38:29 +00003182 InstrItinClass itinD16, InstrItinClass itinD32,
3183 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003184 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003185 SDPatternOperator IntOp, bit Commutable = 0> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003186 // 64-bit vector types.
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003187 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003188 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003189 v4i16, v4i16, IntOp, Commutable>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003190 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
Evan Chengf81bf152009-11-23 21:57:23 +00003191 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003192 v2i32, v2i32, IntOp, Commutable>;
3193
3194 // 128-bit vector types.
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003195 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
Evan Chengf81bf152009-11-23 21:57:23 +00003196 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003197 v8i16, v8i16, IntOp, Commutable>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003198 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003199 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003200 v4i32, v4i32, IntOp, Commutable>;
3201}
Owen Anderson3557d002010-10-26 20:56:57 +00003202multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3203 InstrItinClass itinD16, InstrItinClass itinD32,
3204 InstrItinClass itinQ16, InstrItinClass itinQ32,
3205 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003206 SDPatternOperator IntOp> {
Owen Anderson3557d002010-10-26 20:56:57 +00003207 // 64-bit vector types.
3208 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3209 OpcodeStr, !strconcat(Dt, "16"),
Owen Andersonac922622010-10-26 21:13:59 +00003210 v4i16, v4i16, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003211 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3212 OpcodeStr, !strconcat(Dt, "32"),
Owen Andersonac922622010-10-26 21:13:59 +00003213 v2i32, v2i32, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003214
3215 // 128-bit vector types.
3216 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3217 OpcodeStr, !strconcat(Dt, "16"),
Owen Andersonac922622010-10-26 21:13:59 +00003218 v8i16, v8i16, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003219 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3220 OpcodeStr, !strconcat(Dt, "32"),
Owen Andersonac922622010-10-26 21:13:59 +00003221 v4i32, v4i32, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003222}
Bob Wilson5bafff32009-06-22 23:27:02 +00003223
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003224multiclass N3VIntSL_HS<bits<4> op11_8,
David Goodwin658ea602009-09-25 18:38:29 +00003225 InstrItinClass itinD16, InstrItinClass itinD32,
3226 InstrItinClass itinQ16, InstrItinClass itinQ32,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003227 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Evan Chengac0869d2009-11-21 06:21:52 +00003228 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003229 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
Evan Chengac0869d2009-11-21 06:21:52 +00003230 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
Evan Chengf81bf152009-11-23 21:57:23 +00003231 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
Evan Chengac0869d2009-11-21 06:21:52 +00003232 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003233 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
Evan Chengac0869d2009-11-21 06:21:52 +00003234 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003235 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003236}
3237
Bob Wilson5bafff32009-06-22 23:27:02 +00003238// ....then also with element size of 8 bits:
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003239multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
David Goodwin658ea602009-09-25 18:38:29 +00003240 InstrItinClass itinD16, InstrItinClass itinD32,
3241 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003242 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003243 SDPatternOperator IntOp, bit Commutable = 0>
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003244 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003245 OpcodeStr, Dt, IntOp, Commutable> {
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003246 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003247 OpcodeStr, !strconcat(Dt, "8"),
3248 v8i8, v8i8, IntOp, Commutable>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003249 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
Evan Chengf81bf152009-11-23 21:57:23 +00003250 OpcodeStr, !strconcat(Dt, "8"),
3251 v16i8, v16i8, IntOp, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003252}
Owen Anderson3557d002010-10-26 20:56:57 +00003253multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3254 InstrItinClass itinD16, InstrItinClass itinD32,
3255 InstrItinClass itinQ16, InstrItinClass itinQ32,
3256 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003257 SDPatternOperator IntOp>
Owen Anderson3557d002010-10-26 20:56:57 +00003258 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
Owen Andersonac922622010-10-26 21:13:59 +00003259 OpcodeStr, Dt, IntOp> {
Owen Anderson3557d002010-10-26 20:56:57 +00003260 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3261 OpcodeStr, !strconcat(Dt, "8"),
Owen Andersonac922622010-10-26 21:13:59 +00003262 v8i8, v8i8, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003263 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3264 OpcodeStr, !strconcat(Dt, "8"),
Owen Andersonac922622010-10-26 21:13:59 +00003265 v16i8, v16i8, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003266}
3267
Bob Wilson5bafff32009-06-22 23:27:02 +00003268
3269// ....then also with element size of 64 bits:
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003270multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
David Goodwin658ea602009-09-25 18:38:29 +00003271 InstrItinClass itinD16, InstrItinClass itinD32,
3272 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003273 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003274 SDPatternOperator IntOp, bit Commutable = 0>
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003275 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003276 OpcodeStr, Dt, IntOp, Commutable> {
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003277 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003278 OpcodeStr, !strconcat(Dt, "64"),
3279 v1i64, v1i64, IntOp, Commutable>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003280 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003281 OpcodeStr, !strconcat(Dt, "64"),
3282 v2i64, v2i64, IntOp, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003283}
Owen Anderson3557d002010-10-26 20:56:57 +00003284multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3285 InstrItinClass itinD16, InstrItinClass itinD32,
3286 InstrItinClass itinQ16, InstrItinClass itinQ32,
3287 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003288 SDPatternOperator IntOp>
Owen Anderson3557d002010-10-26 20:56:57 +00003289 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
Owen Andersonac922622010-10-26 21:13:59 +00003290 OpcodeStr, Dt, IntOp> {
Owen Anderson3557d002010-10-26 20:56:57 +00003291 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3292 OpcodeStr, !strconcat(Dt, "64"),
Owen Andersonac922622010-10-26 21:13:59 +00003293 v1i64, v1i64, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003294 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3295 OpcodeStr, !strconcat(Dt, "64"),
Owen Andersonac922622010-10-26 21:13:59 +00003296 v2i64, v2i64, IntOp>;
Owen Anderson3557d002010-10-26 20:56:57 +00003297}
Bob Wilson5bafff32009-06-22 23:27:02 +00003298
Bob Wilson5bafff32009-06-22 23:27:02 +00003299// Neon Narrowing 3-register vector intrinsics,
3300// source operand element sizes of 16, 32 and 64 bits:
3301multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003302 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003303 SDPatternOperator IntOp, bit Commutable = 0> {
Evan Chengf81bf152009-11-23 21:57:23 +00003304 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3305 OpcodeStr, !strconcat(Dt, "16"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003306 v8i8, v8i16, IntOp, Commutable>;
Evan Chengf81bf152009-11-23 21:57:23 +00003307 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3308 OpcodeStr, !strconcat(Dt, "32"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003309 v4i16, v4i32, IntOp, Commutable>;
Evan Chengf81bf152009-11-23 21:57:23 +00003310 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3311 OpcodeStr, !strconcat(Dt, "64"),
Bob Wilson5bafff32009-06-22 23:27:02 +00003312 v2i32, v2i64, IntOp, Commutable>;
3313}
3314
3315
Bob Wilson04d6c282010-08-29 05:57:34 +00003316// Neon Long 3-register vector operations.
3317
3318multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3319 InstrItinClass itin16, InstrItinClass itin32,
3320 string OpcodeStr, string Dt,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003321 SDNode OpNode, bit Commutable = 0> {
Bob Wilson04d6c282010-08-29 05:57:34 +00003322 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3323 OpcodeStr, !strconcat(Dt, "8"),
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003324 v8i16, v8i8, OpNode, Commutable>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003325 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003326 OpcodeStr, !strconcat(Dt, "16"),
3327 v4i32, v4i16, OpNode, Commutable>;
3328 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3329 OpcodeStr, !strconcat(Dt, "32"),
3330 v2i64, v2i32, OpNode, Commutable>;
3331}
3332
3333multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3334 InstrItinClass itin, string OpcodeStr, string Dt,
3335 SDNode OpNode> {
3336 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3337 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3338 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3339 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3340}
3341
3342multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3343 InstrItinClass itin16, InstrItinClass itin32,
3344 string OpcodeStr, string Dt,
3345 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3346 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3347 OpcodeStr, !strconcat(Dt, "8"),
3348 v8i16, v8i8, OpNode, ExtOp, Commutable>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003349 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003350 OpcodeStr, !strconcat(Dt, "16"),
3351 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3352 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3353 OpcodeStr, !strconcat(Dt, "32"),
3354 v2i64, v2i32, OpNode, ExtOp, Commutable>;
Bob Wilson04d6c282010-08-29 05:57:34 +00003355}
3356
Bob Wilson5bafff32009-06-22 23:27:02 +00003357// Neon Long 3-register vector intrinsics.
3358
3359// First with only element sizes of 16 and 32 bits:
3360multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003361 InstrItinClass itin16, InstrItinClass itin32,
3362 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003363 SDPatternOperator IntOp, bit Commutable = 0> {
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003364 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
Evan Chengf81bf152009-11-23 21:57:23 +00003365 OpcodeStr, !strconcat(Dt, "16"),
3366 v4i32, v4i16, IntOp, Commutable>;
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003367 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
Evan Chengf81bf152009-11-23 21:57:23 +00003368 OpcodeStr, !strconcat(Dt, "32"),
3369 v2i64, v2i32, IntOp, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003370}
3371
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003372multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
Evan Chengf81bf152009-11-23 21:57:23 +00003373 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003374 SDPatternOperator IntOp> {
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003375 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
Evan Chengf81bf152009-11-23 21:57:23 +00003376 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
David Goodwin658ea602009-09-25 18:38:29 +00003377 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
Evan Chengf81bf152009-11-23 21:57:23 +00003378 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003379}
3380
Bob Wilson5bafff32009-06-22 23:27:02 +00003381// ....then also with element size of 8 bits:
3382multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003383 InstrItinClass itin16, InstrItinClass itin32,
3384 string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003385 SDPatternOperator IntOp, bit Commutable = 0>
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003386 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
Evan Chengf81bf152009-11-23 21:57:23 +00003387 IntOp, Commutable> {
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003388 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
Evan Chengf81bf152009-11-23 21:57:23 +00003389 OpcodeStr, !strconcat(Dt, "8"),
3390 v8i16, v8i8, IntOp, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003391}
3392
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003393// ....with explicit extend (VABDL).
3394multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3395 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003396 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003397 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3398 OpcodeStr, !strconcat(Dt, "8"),
3399 v8i16, v8i8, IntOp, ExtOp, Commutable>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003400 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003401 OpcodeStr, !strconcat(Dt, "16"),
3402 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3403 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3404 OpcodeStr, !strconcat(Dt, "32"),
3405 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3406}
3407
Bob Wilson5bafff32009-06-22 23:27:02 +00003408
3409// Neon Wide 3-register vector intrinsics,
3410// source operand element sizes of 8, 16 and 32 bits:
Bob Wilson04d6c282010-08-29 05:57:34 +00003411multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3412 string OpcodeStr, string Dt,
3413 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3414 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3415 OpcodeStr, !strconcat(Dt, "8"),
3416 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3417 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3418 OpcodeStr, !strconcat(Dt, "16"),
3419 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3420 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3421 OpcodeStr, !strconcat(Dt, "32"),
3422 v2i64, v2i32, OpNode, ExtOp, Commutable>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003423}
3424
3425
3426// Neon Multiply-Op vector operations,
3427// element sizes of 8, 16 and 32 bits:
3428multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
David Goodwin658ea602009-09-25 18:38:29 +00003429 InstrItinClass itinD16, InstrItinClass itinD32,
3430 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003431 string OpcodeStr, string Dt, SDNode OpNode> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003432 // 64-bit vector types.
David Goodwin658ea602009-09-25 18:38:29 +00003433 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003434 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
David Goodwin658ea602009-09-25 18:38:29 +00003435 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003436 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
David Goodwin658ea602009-09-25 18:38:29 +00003437 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
Evan Chengf81bf152009-11-23 21:57:23 +00003438 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003439
3440 // 128-bit vector types.
David Goodwin658ea602009-09-25 18:38:29 +00003441 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
Evan Chengf81bf152009-11-23 21:57:23 +00003442 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
David Goodwin658ea602009-09-25 18:38:29 +00003443 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
Evan Chengf81bf152009-11-23 21:57:23 +00003444 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
David Goodwin658ea602009-09-25 18:38:29 +00003445 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003446 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003447}
3448
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003449multiclass N3VMulOpSL_HS<bits<4> op11_8,
David Goodwin658ea602009-09-25 18:38:29 +00003450 InstrItinClass itinD16, InstrItinClass itinD32,
3451 InstrItinClass itinQ16, InstrItinClass itinQ32,
Evan Chengf81bf152009-11-23 21:57:23 +00003452 string OpcodeStr, string Dt, SDNode ShOp> {
David Goodwin658ea602009-09-25 18:38:29 +00003453 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
Evan Chengf81bf152009-11-23 21:57:23 +00003454 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
David Goodwin658ea602009-09-25 18:38:29 +00003455 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
Evan Chengf81bf152009-11-23 21:57:23 +00003456 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
David Goodwin658ea602009-09-25 18:38:29 +00003457 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003458 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3459 mul, ShOp>;
David Goodwin658ea602009-09-25 18:38:29 +00003460 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003461 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3462 mul, ShOp>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003463}
Bob Wilson5bafff32009-06-22 23:27:02 +00003464
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003465// Neon Intrinsic-Op vector operations,
3466// element sizes of 8, 16 and 32 bits:
3467multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3468 InstrItinClass itinD, InstrItinClass itinQ,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003469 string OpcodeStr, string Dt, SDPatternOperator IntOp,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003470 SDNode OpNode> {
3471 // 64-bit vector types.
3472 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3473 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3474 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3475 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3476 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3477 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3478
3479 // 128-bit vector types.
3480 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3481 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3482 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3483 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3484 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3485 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3486}
3487
Bob Wilson5bafff32009-06-22 23:27:02 +00003488// Neon 3-argument intrinsics,
3489// element sizes of 8, 16 and 32 bits:
3490multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003491 InstrItinClass itinD, InstrItinClass itinQ,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003492 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003493 // 64-bit vector types.
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003494 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003495 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003496 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003497 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003498 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003499 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003500
3501 // 128-bit vector types.
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003502 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003503 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003504 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003505 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00003506 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003507 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003508}
3509
3510
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003511// Neon Long Multiply-Op vector operations,
3512// element sizes of 8, 16 and 32 bits:
3513multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3514 InstrItinClass itin16, InstrItinClass itin32,
3515 string OpcodeStr, string Dt, SDNode MulOp,
3516 SDNode OpNode> {
3517 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3518 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3519 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3520 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3521 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3522 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3523}
3524
3525multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3526 string Dt, SDNode MulOp, SDNode OpNode> {
3527 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3528 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3529 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3530 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3531}
3532
3533
Bob Wilson5bafff32009-06-22 23:27:02 +00003534// Neon Long 3-argument intrinsics.
3535
3536// First with only element sizes of 16 and 32 bits:
3537multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
Anton Korobeynikov95102072010-04-07 18:21:04 +00003538 InstrItinClass itin16, InstrItinClass itin32,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003539 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Anton Korobeynikov95102072010-04-07 18:21:04 +00003540 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
Evan Chengf81bf152009-11-23 21:57:23 +00003541 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
Anton Korobeynikov95102072010-04-07 18:21:04 +00003542 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
Evan Chengf81bf152009-11-23 21:57:23 +00003543 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003544}
3545
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003546multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003547 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
David Goodwin658ea602009-09-25 18:38:29 +00003548 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
Evan Chengf81bf152009-11-23 21:57:23 +00003549 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
David Goodwin658ea602009-09-25 18:38:29 +00003550 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00003551 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003552}
3553
Bob Wilson5bafff32009-06-22 23:27:02 +00003554// ....then also with element size of 8 bits:
3555multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
Anton Korobeynikov95102072010-04-07 18:21:04 +00003556 InstrItinClass itin16, InstrItinClass itin32,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003557 string OpcodeStr, string Dt, SDPatternOperator IntOp>
Anton Korobeynikov95102072010-04-07 18:21:04 +00003558 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3559 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
Evan Chengf81bf152009-11-23 21:57:23 +00003560 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003561}
3562
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003563// ....with explicit extend (VABAL).
3564multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3565 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003566 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00003567 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3568 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3569 IntOp, ExtOp, OpNode>;
3570 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3571 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3572 IntOp, ExtOp, OpNode>;
3573 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3574 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3575 IntOp, ExtOp, OpNode>;
3576}
3577
Bob Wilson5bafff32009-06-22 23:27:02 +00003578
Bob Wilson5bafff32009-06-22 23:27:02 +00003579// Neon Pairwise long 2-register intrinsics,
3580// element sizes of 8, 16 and 32 bits:
3581multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3582 bits<5> op11_7, bit op4,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003583 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003584 // 64-bit vector types.
3585 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003586 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003587 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003588 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003589 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003590 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003591
3592 // 128-bit vector types.
3593 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003594 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003595 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003596 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003597 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003598 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003599}
3600
3601
3602// Neon Pairwise long 2-register accumulate intrinsics,
3603// element sizes of 8, 16 and 32 bits:
3604multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3605 bits<5> op11_7, bit op4,
Jim Grosbacha4fba5e2012-07-10 00:51:13 +00003606 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003607 // 64-bit vector types.
3608 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003609 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003610 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003611 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003612 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003613 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003614
3615 // 128-bit vector types.
3616 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003617 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003618 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003619 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003620 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003621 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003622}
3623
3624
3625// Neon 2-register vector shift by immediate,
Johnny Chen0a3dc102010-03-26 01:07:59 +00003626// with f of either N2RegVShLFrm or N2RegVShRFrm
Bob Wilson5bafff32009-06-22 23:27:02 +00003627// element sizes of 8, 16, 32 and 64 bits:
Bill Wendling7c6b6082011-03-08 23:48:09 +00003628multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3629 InstrItinClass itin, string OpcodeStr, string Dt,
3630 SDNode OpNode> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003631 // 64-bit vector types.
Bill Wendling7c6b6082011-03-08 23:48:09 +00003632 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003633 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003634 let Inst{21-19} = 0b001; // imm6 = 001xxx
3635 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003636 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003637 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003638 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3639 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003640 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003641 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003642 let Inst{21} = 0b1; // imm6 = 1xxxxx
3643 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003644 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003645 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
Bob Wilson507df402009-10-21 02:15:46 +00003646 // imm6 = xxxxxx
Bob Wilson5bafff32009-06-22 23:27:02 +00003647
3648 // 128-bit vector types.
Bill Wendling7c6b6082011-03-08 23:48:09 +00003649 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003650 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003651 let Inst{21-19} = 0b001; // imm6 = 001xxx
3652 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003653 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003654 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003655 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3656 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003657 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
Evan Chengf81bf152009-11-23 21:57:23 +00003658 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003659 let Inst{21} = 0b1; // imm6 = 1xxxxx
3660 }
Bill Wendling7c6b6082011-03-08 23:48:09 +00003661 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3662 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3663 // imm6 = xxxxxx
3664}
3665multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3666 InstrItinClass itin, string OpcodeStr, string Dt,
Jim Grosbach22378fd2012-04-05 07:23:53 +00003667 string baseOpc, SDNode OpNode> {
Bill Wendling7c6b6082011-03-08 23:48:09 +00003668 // 64-bit vector types.
3669 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3670 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3671 let Inst{21-19} = 0b001; // imm6 = 001xxx
3672 }
3673 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3674 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3675 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3676 }
3677 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3678 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3679 let Inst{21} = 0b1; // imm6 = 1xxxxx
3680 }
3681 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3682 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3683 // imm6 = xxxxxx
3684
3685 // 128-bit vector types.
3686 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3687 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3688 let Inst{21-19} = 0b001; // imm6 = 001xxx
3689 }
3690 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3691 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3692 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3693 }
3694 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3695 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3696 let Inst{21} = 0b1; // imm6 = 1xxxxx
3697 }
3698 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
Evan Chengf81bf152009-11-23 21:57:23 +00003699 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
Bob Wilson507df402009-10-21 02:15:46 +00003700 // imm6 = xxxxxx
Bob Wilson5bafff32009-06-22 23:27:02 +00003701}
3702
Bob Wilson5bafff32009-06-22 23:27:02 +00003703// Neon Shift-Accumulate vector operations,
3704// element sizes of 8, 16, 32 and 64 bits:
3705multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
Evan Chengf81bf152009-11-23 21:57:23 +00003706 string OpcodeStr, string Dt, SDNode ShOp> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003707 // 64-bit vector types.
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003708 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
Evan Chengf81bf152009-11-23 21:57:23 +00003709 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003710 let Inst{21-19} = 0b001; // imm6 = 001xxx
3711 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003712 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
Evan Chengf81bf152009-11-23 21:57:23 +00003713 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003714 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3715 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003716 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
Evan Chengf81bf152009-11-23 21:57:23 +00003717 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003718 let Inst{21} = 0b1; // imm6 = 1xxxxx
3719 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003720 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
Evan Chengf81bf152009-11-23 21:57:23 +00003721 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
Bob Wilson507df402009-10-21 02:15:46 +00003722 // imm6 = xxxxxx
Bob Wilson5bafff32009-06-22 23:27:02 +00003723
3724 // 128-bit vector types.
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003725 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
Evan Chengf81bf152009-11-23 21:57:23 +00003726 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003727 let Inst{21-19} = 0b001; // imm6 = 001xxx
3728 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003729 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
Evan Chengf81bf152009-11-23 21:57:23 +00003730 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003731 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3732 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003733 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
Evan Chengf81bf152009-11-23 21:57:23 +00003734 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
Bob Wilson507df402009-10-21 02:15:46 +00003735 let Inst{21} = 0b1; // imm6 = 1xxxxx
3736 }
Bill Wendlingc04a9de2011-03-09 00:00:35 +00003737 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
Evan Chengf81bf152009-11-23 21:57:23 +00003738 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
Bob Wilson507df402009-10-21 02:15:46 +00003739 // imm6 = xxxxxx
Bob Wilson5bafff32009-06-22 23:27:02 +00003740}
3741
Bob Wilson5bafff32009-06-22 23:27:02 +00003742// Neon Shift-Insert vector operations,
Johnny Chen0a3dc102010-03-26 01:07:59 +00003743// with f of either N2RegVShLFrm or N2RegVShRFrm
Bob Wilson5bafff32009-06-22 23:27:02 +00003744// element sizes of 8, 16, 32 and 64 bits:
Bill Wendling620d0cc2011-03-09 00:33:17 +00003745multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3746 string OpcodeStr> {
Bob Wilson5bafff32009-06-22 23:27:02 +00003747 // 64-bit vector types.
Bill Wendling620d0cc2011-03-09 00:33:17 +00003748 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3749 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003750 let Inst{21-19} = 0b001; // imm6 = 001xxx
3751 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003752 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3753 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003754 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3755 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003756 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3757 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003758 let Inst{21} = 0b1; // imm6 = 1xxxxx
3759 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003760 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3761 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
Bob Wilson507df402009-10-21 02:15:46 +00003762 // imm6 = xxxxxx
Bob Wilson5bafff32009-06-22 23:27:02 +00003763
3764 // 128-bit vector types.
Bill Wendling620d0cc2011-03-09 00:33:17 +00003765 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3766 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003767 let Inst{21-19} = 0b001; // imm6 = 001xxx
3768 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003769 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3770 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003771 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3772 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003773 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3774 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
Bob Wilson507df402009-10-21 02:15:46 +00003775 let Inst{21} = 0b1; // imm6 = 1xxxxx
3776 }
Bill Wendling620d0cc2011-03-09 00:33:17 +00003777 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3778 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3779 // imm6 = xxxxxx
3780}
3781multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3782 string OpcodeStr> {
3783 // 64-bit vector types.
3784 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3785 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3786 let Inst{21-19} = 0b001; // imm6 = 001xxx
3787 }
3788 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3789 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3790 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3791 }
3792 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3793 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3794 let Inst{21} = 0b1; // imm6 = 1xxxxx
3795 }
3796 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3797 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3798 // imm6 = xxxxxx
3799
3800 // 128-bit vector types.
3801 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3802 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3803 let Inst{21-19} = 0b001; // imm6 = 001xxx
3804 }
3805 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3806 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3807 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3808 }
3809 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3810 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3811 let Inst{21} = 0b1; // imm6 = 1xxxxx
3812 }
3813 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3814 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
Bob Wilson507df402009-10-21 02:15:46 +00003815 // imm6 = xxxxxx
3816}
3817
3818// Neon Shift Long operations,
3819// element sizes of 8, 16, 32 bits:
3820multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
Evan Chengf81bf152009-11-23 21:57:23 +00003821 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003822 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Jim Grosbach3b8991c2011-12-07 01:07:24 +00003823 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003824 let Inst{21-19} = 0b001; // imm6 = 001xxx
3825 }
3826 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Jim Grosbach3b8991c2011-12-07 01:07:24 +00003827 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003828 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3829 }
3830 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
Jim Grosbach3b8991c2011-12-07 01:07:24 +00003831 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003832 let Inst{21} = 0b1; // imm6 = 1xxxxx
3833 }
3834}
3835
3836// Neon Shift Narrow operations,
3837// element sizes of 16, 32, 64 bits:
3838multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
Evan Chengf81bf152009-11-23 21:57:23 +00003839 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
Bob Wilson507df402009-10-21 02:15:46 +00003840 SDNode OpNode> {
3841 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Bill Wendlinga656b632011-03-01 01:00:59 +00003842 OpcodeStr, !strconcat(Dt, "16"),
Bill Wendling3116dce2011-03-07 23:38:41 +00003843 v8i8, v8i16, shr_imm8, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003844 let Inst{21-19} = 0b001; // imm6 = 001xxx
3845 }
3846 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Bill Wendlinga656b632011-03-01 01:00:59 +00003847 OpcodeStr, !strconcat(Dt, "32"),
Bill Wendling3116dce2011-03-07 23:38:41 +00003848 v4i16, v4i32, shr_imm16, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003849 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3850 }
3851 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
Bill Wendlinga656b632011-03-01 01:00:59 +00003852 OpcodeStr, !strconcat(Dt, "64"),
Bill Wendling3116dce2011-03-07 23:38:41 +00003853 v2i32, v2i64, shr_imm32, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00003854 let Inst{21} = 0b1; // imm6 = 1xxxxx
3855 }
Bob Wilson5bafff32009-06-22 23:27:02 +00003856}
3857
3858//===----------------------------------------------------------------------===//
3859// Instruction Definitions.
3860//===----------------------------------------------------------------------===//
3861
3862// Vector Add Operations.
3863
3864// VADD : Vector Add (integer and floating-point)
Evan Chengf81bf152009-11-23 21:57:23 +00003865defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
Evan Chengac0869d2009-11-21 06:21:52 +00003866 add, 1>;
Evan Chengf81bf152009-11-23 21:57:23 +00003867def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
Evan Chengac0869d2009-11-21 06:21:52 +00003868 v2f32, v2f32, fadd, 1>;
Evan Chengf81bf152009-11-23 21:57:23 +00003869def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
Evan Chengac0869d2009-11-21 06:21:52 +00003870 v4f32, v4f32, fadd, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003871// VADDL : Vector Add Long (Q = D + D)
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003872defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3873 "vaddl", "s", add, sext, 1>;
3874defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3875 "vaddl", "u", add, zext, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003876// VADDW : Vector Add Wide (Q = Q + D)
Bob Wilson04d6c282010-08-29 05:57:34 +00003877defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3878defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003879// VHADD : Vector Halving Add
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003880defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3881 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3882 "vhadd", "s", int_arm_neon_vhadds, 1>;
3883defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3884 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3885 "vhadd", "u", int_arm_neon_vhaddu, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003886// VRHADD : Vector Rounding Halving Add
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003887defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3888 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3889 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3890defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3891 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3892 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003893// VQADD : Vector Saturating Add
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003894defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3895 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3896 "vqadd", "s", int_arm_neon_vqadds, 1>;
3897defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3898 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3899 "vqadd", "u", int_arm_neon_vqaddu, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003900// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
Evan Chengf81bf152009-11-23 21:57:23 +00003901defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3902 int_arm_neon_vaddhn, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003903// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
Evan Chengf81bf152009-11-23 21:57:23 +00003904defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3905 int_arm_neon_vraddhn, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00003906
3907// Vector Multiply Operations.
3908
3909// VMUL : Vector Multiply (integer, polynomial and floating-point)
Evan Chengac0869d2009-11-21 06:21:52 +00003910defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00003911 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003912def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3913 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3914def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3915 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
Evan Cheng08cec1e2010-10-11 23:41:41 +00003916def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
Bob Wilson9abe19d2010-02-17 00:31:29 +00003917 v2f32, v2f32, fmul, 1>;
Evan Cheng08cec1e2010-10-11 23:41:41 +00003918def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
Bob Wilson9abe19d2010-02-17 00:31:29 +00003919 v4f32, v4f32, fmul, 1>;
Jim Grosbach45755a72011-12-05 20:09:44 +00003920defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
Bob Wilson9abe19d2010-02-17 00:31:29 +00003921def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3922def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3923 v2f32, fmul>;
3924
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003925def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3926 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3927 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3928 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003929 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003930 (SubReg_i16_lane imm:$lane)))>;
3931def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3932 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3933 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3934 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003935 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003936 (SubReg_i32_lane imm:$lane)))>;
3937def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3938 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3939 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3940 (v2f32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003941 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003942 (SubReg_i32_lane imm:$lane)))>;
3943
Bob Wilson5bafff32009-06-22 23:27:02 +00003944// VQDMULH : Vector Saturating Doubling Multiply Returning High Half
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003945defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
Jim Grosbach1251e1a2010-11-18 01:39:50 +00003946 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Chengf81bf152009-11-23 21:57:23 +00003947 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
David Goodwin658ea602009-09-25 18:38:29 +00003948defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3949 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Chengf81bf152009-11-23 21:57:23 +00003950 "vqdmulh", "s", int_arm_neon_vqdmulh>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003951def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
Evan Chengac0869d2009-11-21 06:21:52 +00003952 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3953 imm:$lane)))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003954 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3955 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003956 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003957 (SubReg_i16_lane imm:$lane)))>;
3958def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
Evan Chengac0869d2009-11-21 06:21:52 +00003959 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3960 imm:$lane)))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003961 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3962 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003963 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003964 (SubReg_i32_lane imm:$lane)))>;
3965
Bob Wilson5bafff32009-06-22 23:27:02 +00003966// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00003967defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3968 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
Evan Chengf81bf152009-11-23 21:57:23 +00003969 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
David Goodwin658ea602009-09-25 18:38:29 +00003970defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3971 IIC_VMULi16Q, IIC_VMULi32Q,
Evan Chengf81bf152009-11-23 21:57:23 +00003972 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003973def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
Evan Chengac0869d2009-11-21 06:21:52 +00003974 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3975 imm:$lane)))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003976 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3977 (v4i16 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003978 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003979 (SubReg_i16_lane imm:$lane)))>;
3980def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
Evan Chengac0869d2009-11-21 06:21:52 +00003981 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3982 imm:$lane)))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003983 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3984 (v2i32 (EXTRACT_SUBREG QPR:$src2,
Bob Wilson9abe19d2010-02-17 00:31:29 +00003985 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003986 (SubReg_i32_lane imm:$lane)))>;
3987
Bob Wilson5bafff32009-06-22 23:27:02 +00003988// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003989defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3990 "vmull", "s", NEONvmulls, 1>;
3991defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3992 "vmull", "u", NEONvmullu, 1>;
Evan Chengf81bf152009-11-23 21:57:23 +00003993def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
Evan Chengac0869d2009-11-21 06:21:52 +00003994 v8i16, v8i8, int_arm_neon_vmullp, 1>;
Bob Wilsond0b69cf2010-09-01 23:50:19 +00003995defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3996defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00003997
Bob Wilson5bafff32009-06-22 23:27:02 +00003998// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
Anton Korobeynikovecc64062010-04-07 18:21:10 +00003999defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4000 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4001defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4002 "vqdmull", "s", int_arm_neon_vqdmull>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004003
4004// Vector Multiply-Accumulate and Multiply-Subtract Operations.
4005
4006// VMLA : Vector Multiply Accumulate (integer and floating-point)
David Goodwin658ea602009-09-25 18:38:29 +00004007defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00004008 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4009def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004010 v2f32, fmul_su, fadd_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004011 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004012def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004013 v4f32, fmul_su, fadd_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004014 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
David Goodwin658ea602009-09-25 18:38:29 +00004015defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00004016 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4017def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004018 v2f32, fmul_su, fadd_mlx>,
4019 Requires<[HasNEON, UseFPVMLx]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004020def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004021 v4f32, v2f32, fmul_su, fadd_mlx>,
4022 Requires<[HasNEON, UseFPVMLx]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004023
4024def : Pat<(v8i16 (add (v8i16 QPR:$src1),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004025 (mul (v8i16 QPR:$src2),
4026 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4027 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004028 (v4i16 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004029 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004030 (SubReg_i16_lane imm:$lane)))>;
4031
4032def : Pat<(v4i32 (add (v4i32 QPR:$src1),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004033 (mul (v4i32 QPR:$src2),
4034 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4035 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004036 (v2i32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004037 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004038 (SubReg_i32_lane imm:$lane)))>;
4039
Evan Cheng48575f62010-12-05 22:04:16 +00004040def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4041 (fmul_su (v4f32 QPR:$src2),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004042 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004043 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4044 (v4f32 QPR:$src2),
4045 (v2f32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004046 (DSubReg_i32_reg imm:$lane))),
Evan Cheng48575f62010-12-05 22:04:16 +00004047 (SubReg_i32_lane imm:$lane)))>,
4048 Requires<[HasNEON, UseFPVMLx]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004049
Bob Wilson5bafff32009-06-22 23:27:02 +00004050// VMLAL : Vector Multiply Accumulate Long (Q += D * D)
Bob Wilsond0b69cf2010-09-01 23:50:19 +00004051defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4052 "vmlal", "s", NEONvmulls, add>;
4053defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4054 "vmlal", "u", NEONvmullu, add>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004055
Bob Wilsond0b69cf2010-09-01 23:50:19 +00004056defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4057defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004058
Bob Wilson5bafff32009-06-22 23:27:02 +00004059// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
Anton Korobeynikov95102072010-04-07 18:21:04 +00004060defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00004061 "vqdmlal", "s", int_arm_neon_vqdmlal>;
Evan Chengf81bf152009-11-23 21:57:23 +00004062defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004063
Bob Wilson5bafff32009-06-22 23:27:02 +00004064// VMLS : Vector Multiply Subtract (integer and floating-point)
Bob Wilson8f07b9e2009-10-03 04:41:21 +00004065defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00004066 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4067def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004068 v2f32, fmul_su, fsub_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004069 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004070def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004071 v4f32, fmul_su, fsub_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004072 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
David Goodwin658ea602009-09-25 18:38:29 +00004073defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
Evan Chengf81bf152009-11-23 21:57:23 +00004074 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4075def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004076 v2f32, fmul_su, fsub_mlx>,
4077 Requires<[HasNEON, UseFPVMLx]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004078def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
Evan Cheng48575f62010-12-05 22:04:16 +00004079 v4f32, v2f32, fmul_su, fsub_mlx>,
4080 Requires<[HasNEON, UseFPVMLx]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004081
4082def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004083 (mul (v8i16 QPR:$src2),
4084 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4085 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004086 (v4i16 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004087 (DSubReg_i16_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004088 (SubReg_i16_lane imm:$lane)))>;
4089
4090def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004091 (mul (v4i32 QPR:$src2),
4092 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4093 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004094 (v2i32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004095 (DSubReg_i32_reg imm:$lane))),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004096 (SubReg_i32_lane imm:$lane)))>;
4097
Evan Cheng48575f62010-12-05 22:04:16 +00004098def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4099 (fmul_su (v4f32 QPR:$src2),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004100 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4101 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004102 (v2f32 (EXTRACT_SUBREG QPR:$src3,
Bob Wilson9abe19d2010-02-17 00:31:29 +00004103 (DSubReg_i32_reg imm:$lane))),
Evan Cheng48575f62010-12-05 22:04:16 +00004104 (SubReg_i32_lane imm:$lane)))>,
4105 Requires<[HasNEON, UseFPVMLx]>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004106
Bob Wilson5bafff32009-06-22 23:27:02 +00004107// VMLSL : Vector Multiply Subtract Long (Q -= D * D)
Bob Wilsond0b69cf2010-09-01 23:50:19 +00004108defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4109 "vmlsl", "s", NEONvmulls, sub>;
4110defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4111 "vmlsl", "u", NEONvmullu, sub>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004112
Bob Wilsond0b69cf2010-09-01 23:50:19 +00004113defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4114defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
Anton Korobeynikov6ca0b9e2009-09-08 15:22:32 +00004115
Bob Wilson5bafff32009-06-22 23:27:02 +00004116// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
Anton Korobeynikov95102072010-04-07 18:21:04 +00004117defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
Anton Korobeynikov0a3e2b52010-04-07 18:20:42 +00004118 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
Evan Chengf81bf152009-11-23 21:57:23 +00004119defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004120
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00004121// Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4122def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4123 v2f32, fmul_su, fadd_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004124 Requires<[HasVFP4,UseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00004125
4126def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4127 v4f32, fmul_su, fadd_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004128 Requires<[HasVFP4,UseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00004129
4130// Fused Vector Multiply Subtract (floating-point)
4131def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4132 v2f32, fmul_su, fsub_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004133 Requires<[HasVFP4,UseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00004134def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4135 v4f32, fmul_su, fsub_mlx>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004136 Requires<[HasVFP4,UseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00004137
Evan Cheng3aef2ff2012-04-10 21:40:28 +00004138// Match @llvm.fma.* intrinsics
Lang Hames77878002012-04-27 18:51:24 +00004139def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
Evan Cheng3aef2ff2012-04-10 21:40:28 +00004140 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004141 Requires<[HasVFP4]>;
Lang Hames77878002012-04-27 18:51:24 +00004142def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
Evan Cheng3aef2ff2012-04-10 21:40:28 +00004143 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
Evan Chengbee78fe2012-04-11 05:33:07 +00004144 Requires<[HasVFP4]>;
Lang Hames77878002012-04-27 18:51:24 +00004145def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
Evan Cheng14b4c032012-04-11 06:59:47 +00004146 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4147 Requires<[HasVFP4]>;
Lang Hames77878002012-04-27 18:51:24 +00004148def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
Evan Cheng14b4c032012-04-11 06:59:47 +00004149 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4150 Requires<[HasVFP4]>;
Evan Cheng3aef2ff2012-04-10 21:40:28 +00004151
Bob Wilson5bafff32009-06-22 23:27:02 +00004152// Vector Subtract Operations.
4153
4154// VSUB : Vector Subtract (integer and floating-point)
Evan Chengac0869d2009-11-21 06:21:52 +00004155defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
Evan Chengf81bf152009-11-23 21:57:23 +00004156 "vsub", "i", sub, 0>;
4157def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
Evan Chengac0869d2009-11-21 06:21:52 +00004158 v2f32, v2f32, fsub, 0>;
Evan Chengf81bf152009-11-23 21:57:23 +00004159def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
Evan Chengac0869d2009-11-21 06:21:52 +00004160 v4f32, v4f32, fsub, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004161// VSUBL : Vector Subtract Long (Q = D - D)
Bob Wilsond0b69cf2010-09-01 23:50:19 +00004162defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4163 "vsubl", "s", sub, sext, 0>;
4164defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4165 "vsubl", "u", sub, zext, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004166// VSUBW : Vector Subtract Wide (Q = Q - D)
Bob Wilson04d6c282010-08-29 05:57:34 +00004167defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4168defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004169// VHSUB : Vector Halving Subtract
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004170defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004171 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Evan Chengf81bf152009-11-23 21:57:23 +00004172 "vhsub", "s", int_arm_neon_vhsubs, 0>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004173defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004174 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Evan Chengf81bf152009-11-23 21:57:23 +00004175 "vhsub", "u", int_arm_neon_vhsubu, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004176// VQSUB : Vector Saturing Subtract
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004177defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004178 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Evan Chengf81bf152009-11-23 21:57:23 +00004179 "vqsub", "s", int_arm_neon_vqsubs, 0>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004180defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004181 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Evan Chengf81bf152009-11-23 21:57:23 +00004182 "vqsub", "u", int_arm_neon_vqsubu, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004183// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
Evan Chengf81bf152009-11-23 21:57:23 +00004184defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4185 int_arm_neon_vsubhn, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004186// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
Evan Chengf81bf152009-11-23 21:57:23 +00004187defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4188 int_arm_neon_vrsubhn, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004189
4190// Vector Comparisons.
4191
4192// VCEQ : Vector Compare Equal
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004193defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4194 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
Evan Chengf81bf152009-11-23 21:57:23 +00004195def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
Evan Chengac0869d2009-11-21 06:21:52 +00004196 NEONvceq, 1>;
Evan Chengf81bf152009-11-23 21:57:23 +00004197def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
Evan Chengac0869d2009-11-21 06:21:52 +00004198 NEONvceq, 1>;
Owen Andersonc24cb352010-11-08 23:21:22 +00004199
Johnny Chen363ac582010-02-23 01:42:58 +00004200defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
Owen Andersonca6945e2010-12-01 00:28:25 +00004201 "$Vd, $Vm, #0", NEONvceqz>;
Johnny Chenec5a4cd2010-02-23 00:33:12 +00004202
Bob Wilson5bafff32009-06-22 23:27:02 +00004203// VCGE : Vector Compare Greater Than or Equal
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004204defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4205 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004206defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004207 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
Johnny Chen69631b12010-03-24 21:25:07 +00004208def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4209 NEONvcge, 0>;
Evan Chengf81bf152009-11-23 21:57:23 +00004210def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
Evan Chengac0869d2009-11-21 06:21:52 +00004211 NEONvcge, 0>;
Owen Andersonc24cb352010-11-08 23:21:22 +00004212
Johnny Chen363ac582010-02-23 01:42:58 +00004213defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
Owen Andersonca6945e2010-12-01 00:28:25 +00004214 "$Vd, $Vm, #0", NEONvcgez>;
Johnny Chen363ac582010-02-23 01:42:58 +00004215defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
Owen Andersonca6945e2010-12-01 00:28:25 +00004216 "$Vd, $Vm, #0", NEONvclez>;
Johnny Chen363ac582010-02-23 01:42:58 +00004217
Bob Wilson5bafff32009-06-22 23:27:02 +00004218// VCGT : Vector Compare Greater Than
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004219defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4220 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4221defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4222 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
Evan Chengf81bf152009-11-23 21:57:23 +00004223def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
Evan Chengac0869d2009-11-21 06:21:52 +00004224 NEONvcgt, 0>;
Evan Chengf81bf152009-11-23 21:57:23 +00004225def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
Evan Chengac0869d2009-11-21 06:21:52 +00004226 NEONvcgt, 0>;
Owen Andersonc24cb352010-11-08 23:21:22 +00004227
Johnny Chen363ac582010-02-23 01:42:58 +00004228defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
Owen Andersonca6945e2010-12-01 00:28:25 +00004229 "$Vd, $Vm, #0", NEONvcgtz>;
Johnny Chen363ac582010-02-23 01:42:58 +00004230defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
Owen Andersonca6945e2010-12-01 00:28:25 +00004231 "$Vd, $Vm, #0", NEONvcltz>;
Johnny Chen363ac582010-02-23 01:42:58 +00004232
Bob Wilson5bafff32009-06-22 23:27:02 +00004233// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004234def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4235 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4236def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4237 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004238// VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004239def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4240 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4241def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4242 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004243// VTST : Vector Test Bits
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004244defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
Bob Wilson3a4a8322010-01-17 06:35:17 +00004245 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004246
4247// Vector Bitwise Operations.
4248
Bob Wilsoncba270d2010-07-13 21:16:48 +00004249def vnotd : PatFrag<(ops node:$in),
4250 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4251def vnotq : PatFrag<(ops node:$in),
4252 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
Chris Lattnerb26fdcb2010-03-28 08:08:07 +00004253
4254
Bob Wilson5bafff32009-06-22 23:27:02 +00004255// VAND : Vector Bitwise AND
Evan Chengf81bf152009-11-23 21:57:23 +00004256def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4257 v2i32, v2i32, and, 1>;
4258def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4259 v4i32, v4i32, and, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004260
4261// VEOR : Vector Bitwise Exclusive OR
Evan Chengf81bf152009-11-23 21:57:23 +00004262def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4263 v2i32, v2i32, xor, 1>;
4264def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4265 v4i32, v4i32, xor, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004266
4267// VORR : Vector Bitwise OR
Evan Chengf81bf152009-11-23 21:57:23 +00004268def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4269 v2i32, v2i32, or, 1>;
4270def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4271 v4i32, v4i32, or, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004272
Owen Andersond9668172010-11-03 22:44:51 +00004273def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
Jim Grosbachea461102011-10-17 23:09:09 +00004274 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
Owen Andersond9668172010-11-03 22:44:51 +00004275 IIC_VMOVImm,
4276 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4277 [(set DPR:$Vd,
4278 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4279 let Inst{9} = SIMM{9};
4280}
4281
Owen Anderson080c0922010-11-05 19:27:46 +00004282def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
Jim Grosbach6248a542011-10-18 00:22:00 +00004283 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
Owen Andersond9668172010-11-03 22:44:51 +00004284 IIC_VMOVImm,
4285 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4286 [(set DPR:$Vd,
4287 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
Owen Anderson080c0922010-11-05 19:27:46 +00004288 let Inst{10-9} = SIMM{10-9};
Owen Andersond9668172010-11-03 22:44:51 +00004289}
4290
4291def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
Jim Grosbachea461102011-10-17 23:09:09 +00004292 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
Owen Andersond9668172010-11-03 22:44:51 +00004293 IIC_VMOVImm,
4294 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4295 [(set QPR:$Vd,
4296 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4297 let Inst{9} = SIMM{9};
4298}
4299
Owen Anderson080c0922010-11-05 19:27:46 +00004300def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
Jim Grosbach6248a542011-10-18 00:22:00 +00004301 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
Owen Andersond9668172010-11-03 22:44:51 +00004302 IIC_VMOVImm,
4303 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4304 [(set QPR:$Vd,
4305 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
Owen Anderson080c0922010-11-05 19:27:46 +00004306 let Inst{10-9} = SIMM{10-9};
Owen Andersond9668172010-11-03 22:44:51 +00004307}
4308
4309
Bob Wilson5bafff32009-06-22 23:27:02 +00004310// VBIC : Vector Bitwise Bit Clear (AND NOT)
Jim Grosbach27279302012-05-02 21:11:56 +00004311let TwoOperandAliasConstraint = "$Vn = $Vd" in {
Owen Andersonca6945e2010-12-01 00:28:25 +00004312def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4313 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4314 "vbic", "$Vd, $Vn, $Vm", "",
4315 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4316 (vnotd DPR:$Vm))))]>;
4317def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4318 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4319 "vbic", "$Vd, $Vn, $Vm", "",
4320 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4321 (vnotq QPR:$Vm))))]>;
Jim Grosbach27279302012-05-02 21:11:56 +00004322}
Bob Wilson5bafff32009-06-22 23:27:02 +00004323
Owen Anderson080c0922010-11-05 19:27:46 +00004324def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
Jim Grosbachea461102011-10-17 23:09:09 +00004325 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
Owen Anderson080c0922010-11-05 19:27:46 +00004326 IIC_VMOVImm,
4327 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4328 [(set DPR:$Vd,
4329 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4330 let Inst{9} = SIMM{9};
4331}
4332
4333def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
Jim Grosbach6248a542011-10-18 00:22:00 +00004334 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
Owen Anderson080c0922010-11-05 19:27:46 +00004335 IIC_VMOVImm,
4336 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4337 [(set DPR:$Vd,
4338 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4339 let Inst{10-9} = SIMM{10-9};
4340}
4341
4342def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
Jim Grosbachea461102011-10-17 23:09:09 +00004343 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
Owen Anderson080c0922010-11-05 19:27:46 +00004344 IIC_VMOVImm,
4345 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4346 [(set QPR:$Vd,
4347 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4348 let Inst{9} = SIMM{9};
4349}
4350
4351def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
Jim Grosbach6248a542011-10-18 00:22:00 +00004352 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
Owen Anderson080c0922010-11-05 19:27:46 +00004353 IIC_VMOVImm,
4354 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4355 [(set QPR:$Vd,
4356 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4357 let Inst{10-9} = SIMM{10-9};
4358}
4359
Bob Wilson5bafff32009-06-22 23:27:02 +00004360// VORN : Vector Bitwise OR NOT
Owen Andersonca6945e2010-12-01 00:28:25 +00004361def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4362 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4363 "vorn", "$Vd, $Vn, $Vm", "",
4364 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4365 (vnotd DPR:$Vm))))]>;
4366def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4367 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4368 "vorn", "$Vd, $Vn, $Vm", "",
4369 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4370 (vnotq QPR:$Vm))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004371
Bob Wilson7e3f0d22010-07-14 06:31:50 +00004372// VMVN : Vector Bitwise NOT (Immediate)
4373
4374let isReMaterializable = 1 in {
Owen Andersona88ea032010-10-26 17:40:54 +00004375
Owen Andersonca6945e2010-12-01 00:28:25 +00004376def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
Jim Grosbachea461102011-10-17 23:09:09 +00004377 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004378 "vmvn", "i16", "$Vd, $SIMM", "",
4379 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004380 let Inst{9} = SIMM{9};
4381}
4382
Owen Andersonca6945e2010-12-01 00:28:25 +00004383def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
Jim Grosbachea461102011-10-17 23:09:09 +00004384 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004385 "vmvn", "i16", "$Vd, $SIMM", "",
4386 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004387 let Inst{9} = SIMM{9};
4388}
4389
Owen Andersonca6945e2010-12-01 00:28:25 +00004390def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
Jim Grosbach6248a542011-10-18 00:22:00 +00004391 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004392 "vmvn", "i32", "$Vd, $SIMM", "",
4393 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004394 let Inst{11-8} = SIMM{11-8};
4395}
4396
Owen Andersonca6945e2010-12-01 00:28:25 +00004397def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
Jim Grosbach6248a542011-10-18 00:22:00 +00004398 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004399 "vmvn", "i32", "$Vd, $SIMM", "",
4400 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004401 let Inst{11-8} = SIMM{11-8};
4402}
Bob Wilson7e3f0d22010-07-14 06:31:50 +00004403}
4404
Bob Wilson5bafff32009-06-22 23:27:02 +00004405// VMVN : Vector Bitwise NOT
Evan Chengf81bf152009-11-23 21:57:23 +00004406def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00004407 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4408 "vmvn", "$Vd, $Vm", "",
4409 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004410def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00004411 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4412 "vmvn", "$Vd, $Vm", "",
4413 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
Bob Wilsoncba270d2010-07-13 21:16:48 +00004414def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4415def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004416
4417// VBSL : Vector Bitwise Select
Owen Anderson4110b432010-10-25 20:13:13 +00004418def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4419 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
Bob Wilson2cd1a122010-03-27 04:01:23 +00004420 N3RegFrm, IIC_VCNTiD,
Owen Anderson4110b432010-10-25 20:13:13 +00004421 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachf921c0fe2011-06-13 22:54:22 +00004422 [(set DPR:$Vd,
4423 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
Cameron Zwarichc0e6d782011-03-30 23:01:21 +00004424
4425def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4426 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4427 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4428
Owen Anderson4110b432010-10-25 20:13:13 +00004429def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4430 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
Bob Wilson2cd1a122010-03-27 04:01:23 +00004431 N3RegFrm, IIC_VCNTiQ,
Owen Anderson4110b432010-10-25 20:13:13 +00004432 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachf921c0fe2011-06-13 22:54:22 +00004433 [(set QPR:$Vd,
4434 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
Cameron Zwarichc0e6d782011-03-30 23:01:21 +00004435
4436def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4437 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4438 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004439
4440// VBIF : Vector Bitwise Insert if False
Evan Chengf81bf152009-11-23 21:57:23 +00004441// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
Owen Anderson31e6ed82010-10-25 20:17:22 +00004442// FIXME: This instruction's encoding MAY NOT BE correct.
Johnny Chen4814e712010-02-09 23:05:23 +00004443def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004444 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00004445 N3RegFrm, IIC_VBINiD,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004446 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachfe7b4992011-10-21 16:14:12 +00004447 []>;
Johnny Chen4814e712010-02-09 23:05:23 +00004448def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004449 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00004450 N3RegFrm, IIC_VBINiQ,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004451 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachfe7b4992011-10-21 16:14:12 +00004452 []>;
Johnny Chen4814e712010-02-09 23:05:23 +00004453
Bob Wilson5bafff32009-06-22 23:27:02 +00004454// VBIT : Vector Bitwise Insert if True
Evan Chengf81bf152009-11-23 21:57:23 +00004455// like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
Owen Anderson31e6ed82010-10-25 20:17:22 +00004456// FIXME: This instruction's encoding MAY NOT BE correct.
Johnny Chen4814e712010-02-09 23:05:23 +00004457def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004458 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00004459 N3RegFrm, IIC_VBINiD,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004460 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachfe7b4992011-10-21 16:14:12 +00004461 []>;
Johnny Chen4814e712010-02-09 23:05:23 +00004462def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004463 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
Bob Wilson10bc69c2010-03-27 03:56:52 +00004464 N3RegFrm, IIC_VBINiQ,
Owen Anderson31e6ed82010-10-25 20:17:22 +00004465 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
Jim Grosbachfe7b4992011-10-21 16:14:12 +00004466 []>;
Johnny Chen4814e712010-02-09 23:05:23 +00004467
4468// VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
Bob Wilson5bafff32009-06-22 23:27:02 +00004469// for equivalent operations with different register constraints; it just
4470// inserts copies.
4471
4472// Vector Absolute Differences.
4473
4474// VABD : Vector Absolute Difference
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004475defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
Anton Korobeynikov4ac0af82010-04-07 18:20:18 +00004476 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004477 "vabd", "s", int_arm_neon_vabds, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004478defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
Anton Korobeynikov4ac0af82010-04-07 18:20:18 +00004479 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004480 "vabd", "u", int_arm_neon_vabdu, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004481def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004482 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004483def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004484 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004485
4486// VABDL : Vector Absolute Difference Long (Q = | D - D |)
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004487defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4488 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4489defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4490 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004491
4492// VABA : Vector Absolute Difference and Accumulate
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004493defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4494 "vaba", "s", int_arm_neon_vabds, add>;
4495defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4496 "vaba", "u", int_arm_neon_vabdu, add>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004497
4498// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
Bob Wilsoneb0c3d32010-09-03 01:35:08 +00004499defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4500 "vabal", "s", int_arm_neon_vabds, zext, add>;
4501defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4502 "vabal", "u", int_arm_neon_vabdu, zext, add>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004503
4504// Vector Maximum and Minimum.
4505
4506// VMAX : Vector Maximum
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004507defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004508 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004509 "vmax", "s", int_arm_neon_vmaxs, 1>;
4510defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004511 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004512 "vmax", "u", int_arm_neon_vmaxu, 1>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004513def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4514 "vmax", "f32",
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004515 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004516def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4517 "vmax", "f32",
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004518 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4519
4520// VMIN : Vector Minimum
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004521defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4522 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4523 "vmin", "s", int_arm_neon_vmins, 1>;
4524defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4525 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4526 "vmin", "u", int_arm_neon_vminu, 1>;
4527def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4528 "vmin", "f32",
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004529 v2f32, v2f32, int_arm_neon_vmins, 1>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004530def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4531 "vmin", "f32",
Anton Korobeynikovf8b5c632010-04-07 18:20:13 +00004532 v4f32, v4f32, int_arm_neon_vmins, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004533
4534// Vector Pairwise Operations.
4535
4536// VPADD : Vector Pairwise Add
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004537def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4538 "vpadd", "i8",
4539 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4540def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4541 "vpadd", "i16",
4542 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4543def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4544 "vpadd", "i32",
4545 v2i32, v2i32, int_arm_neon_vpadd, 0>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004546def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
Evan Cheng08cec1e2010-10-11 23:41:41 +00004547 IIC_VPBIND, "vpadd", "f32",
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004548 v2f32, v2f32, int_arm_neon_vpadd, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004549
4550// VPADDL : Vector Pairwise Add Long
Evan Chengf81bf152009-11-23 21:57:23 +00004551defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004552 int_arm_neon_vpaddls>;
Evan Chengf81bf152009-11-23 21:57:23 +00004553defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
Bob Wilson5bafff32009-06-22 23:27:02 +00004554 int_arm_neon_vpaddlu>;
4555
4556// VPADAL : Vector Pairwise Add and Accumulate Long
Evan Chengf81bf152009-11-23 21:57:23 +00004557defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004558 int_arm_neon_vpadals>;
Evan Chengf81bf152009-11-23 21:57:23 +00004559defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
Bob Wilson5bafff32009-06-22 23:27:02 +00004560 int_arm_neon_vpadalu>;
4561
4562// VPMAX : Vector Pairwise Maximum
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004563def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004564 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004565def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004566 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004567def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004568 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004569def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004570 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004571def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004572 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004573def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004574 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
Evan Cheng08cec1e2010-10-11 23:41:41 +00004575def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004576 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004577
4578// VPMIN : Vector Pairwise Minimum
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004579def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004580 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004581def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004582 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004583def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004584 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004585def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004586 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004587def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004588 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
Anton Korobeynikov1c03f242010-04-07 18:20:24 +00004589def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004590 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
Evan Cheng08cec1e2010-10-11 23:41:41 +00004591def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004592 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004593
4594// Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4595
4596// VRECPE : Vector Reciprocal Estimate
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004597def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004598 IIC_VUNAD, "vrecpe", "u32",
Bob Wilson5bafff32009-06-22 23:27:02 +00004599 v2i32, v2i32, int_arm_neon_vrecpe>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004600def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004601 IIC_VUNAQ, "vrecpe", "u32",
Bob Wilson5bafff32009-06-22 23:27:02 +00004602 v4i32, v4i32, int_arm_neon_vrecpe>;
David Goodwin127221f2009-09-23 21:38:08 +00004603def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004604 IIC_VUNAD, "vrecpe", "f32",
Bob Wilsonb0abb4d2009-08-11 05:39:44 +00004605 v2f32, v2f32, int_arm_neon_vrecpe>;
David Goodwin127221f2009-09-23 21:38:08 +00004606def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004607 IIC_VUNAQ, "vrecpe", "f32",
Bob Wilsonb0abb4d2009-08-11 05:39:44 +00004608 v4f32, v4f32, int_arm_neon_vrecpe>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004609
4610// VRECPS : Vector Reciprocal Step
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004611def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
Evan Chengf81bf152009-11-23 21:57:23 +00004612 IIC_VRECSD, "vrecps", "f32",
4613 v2f32, v2f32, int_arm_neon_vrecps, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004614def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
Evan Chengf81bf152009-11-23 21:57:23 +00004615 IIC_VRECSQ, "vrecps", "f32",
4616 v4f32, v4f32, int_arm_neon_vrecps, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004617
4618// VRSQRTE : Vector Reciprocal Square Root Estimate
David Goodwin127221f2009-09-23 21:38:08 +00004619def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004620 IIC_VUNAD, "vrsqrte", "u32",
David Goodwin127221f2009-09-23 21:38:08 +00004621 v2i32, v2i32, int_arm_neon_vrsqrte>;
4622def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004623 IIC_VUNAQ, "vrsqrte", "u32",
David Goodwin127221f2009-09-23 21:38:08 +00004624 v4i32, v4i32, int_arm_neon_vrsqrte>;
4625def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004626 IIC_VUNAD, "vrsqrte", "f32",
David Goodwin127221f2009-09-23 21:38:08 +00004627 v2f32, v2f32, int_arm_neon_vrsqrte>;
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004628def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004629 IIC_VUNAQ, "vrsqrte", "f32",
David Goodwin127221f2009-09-23 21:38:08 +00004630 v4f32, v4f32, int_arm_neon_vrsqrte>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004631
4632// VRSQRTS : Vector Reciprocal Square Root Step
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004633def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
Evan Chengf81bf152009-11-23 21:57:23 +00004634 IIC_VRECSD, "vrsqrts", "f32",
4635 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004636def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
Evan Chengf81bf152009-11-23 21:57:23 +00004637 IIC_VRECSQ, "vrsqrts", "f32",
4638 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004639
4640// Vector Shifts.
4641
4642// VSHL : Vector Shift
Owen Anderson3557d002010-10-26 20:56:57 +00004643defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004644 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
Owen Andersonac922622010-10-26 21:13:59 +00004645 "vshl", "s", int_arm_neon_vshifts>;
Owen Anderson3557d002010-10-26 20:56:57 +00004646defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004647 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
Owen Andersonac922622010-10-26 21:13:59 +00004648 "vshl", "u", int_arm_neon_vshiftu>;
Bill Wendling7c6b6082011-03-08 23:48:09 +00004649
Bob Wilson5bafff32009-06-22 23:27:02 +00004650// VSHL : Vector Shift Left (Immediate)
Bill Wendling7c6b6082011-03-08 23:48:09 +00004651defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4652
Bob Wilson5bafff32009-06-22 23:27:02 +00004653// VSHR : Vector Shift Right (Immediate)
Jim Grosbach22378fd2012-04-05 07:23:53 +00004654defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4655 NEONvshrs>;
4656defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4657 NEONvshru>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004658
4659// VSHLL : Vector Shift Left Long
Evan Chengf81bf152009-11-23 21:57:23 +00004660defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4661defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004662
4663// VSHLL : Vector Shift Left Long (with maximum shift count)
Bob Wilson507df402009-10-21 02:15:46 +00004664class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
Evan Chengf81bf152009-11-23 21:57:23 +00004665 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
Jim Grosbach4e413952011-12-07 00:02:17 +00004666 ValueType OpTy, Operand ImmTy, SDNode OpNode>
Evan Chengf81bf152009-11-23 21:57:23 +00004667 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
Jim Grosbach4e413952011-12-07 00:02:17 +00004668 ResTy, OpTy, ImmTy, OpNode> {
Bob Wilson507df402009-10-21 02:15:46 +00004669 let Inst{21-16} = op21_16;
Owen Anderson8d7d2e12011-08-09 20:55:18 +00004670 let DecoderMethod = "DecodeVSHLMaxInstruction";
Bob Wilson507df402009-10-21 02:15:46 +00004671}
Evan Chengf81bf152009-11-23 21:57:23 +00004672def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
Jim Grosbach3b8991c2011-12-07 01:07:24 +00004673 v8i16, v8i8, imm8, NEONvshlli>;
Evan Chengf81bf152009-11-23 21:57:23 +00004674def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
Jim Grosbach3b8991c2011-12-07 01:07:24 +00004675 v4i32, v4i16, imm16, NEONvshlli>;
Evan Chengf81bf152009-11-23 21:57:23 +00004676def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
Jim Grosbach3b8991c2011-12-07 01:07:24 +00004677 v2i64, v2i32, imm32, NEONvshlli>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004678
4679// VSHRN : Vector Shift Right and Narrow
Evan Chengef0ccad2010-10-01 21:48:06 +00004680defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
Bob Wilson9abe19d2010-02-17 00:31:29 +00004681 NEONvshrn>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004682
4683// VRSHL : Vector Rounding Shift
Owen Anderson632c2352010-10-26 21:58:41 +00004684defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004685 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson632c2352010-10-26 21:58:41 +00004686 "vrshl", "s", int_arm_neon_vrshifts>;
4687defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004688 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson632c2352010-10-26 21:58:41 +00004689 "vrshl", "u", int_arm_neon_vrshiftu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004690// VRSHR : Vector Rounding Shift Right
Jim Grosbach22378fd2012-04-05 07:23:53 +00004691defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
4692 NEONvrshrs>;
4693defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
4694 NEONvrshru>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004695
4696// VRSHRN : Vector Rounding Shift Right and Narrow
Evan Chengf81bf152009-11-23 21:57:23 +00004697defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
Bob Wilson507df402009-10-21 02:15:46 +00004698 NEONvrshrn>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004699
4700// VQSHL : Vector Saturating Shift
Owen Anderson86ed2322010-10-26 22:50:46 +00004701defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004702 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson86ed2322010-10-26 22:50:46 +00004703 "vqshl", "s", int_arm_neon_vqshifts>;
4704defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004705 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson86ed2322010-10-26 22:50:46 +00004706 "vqshl", "u", int_arm_neon_vqshiftu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004707// VQSHL : Vector Saturating Shift Left (Immediate)
Bill Wendling7c6b6082011-03-08 23:48:09 +00004708defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4709defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4710
Bob Wilson5bafff32009-06-22 23:27:02 +00004711// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
Bill Wendling7c6b6082011-03-08 23:48:09 +00004712defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004713
4714// VQSHRN : Vector Saturating Shift Right and Narrow
Evan Chengf81bf152009-11-23 21:57:23 +00004715defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
Bob Wilson507df402009-10-21 02:15:46 +00004716 NEONvqshrns>;
Evan Chengf81bf152009-11-23 21:57:23 +00004717defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
Bob Wilson507df402009-10-21 02:15:46 +00004718 NEONvqshrnu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004719
4720// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
Evan Chengf81bf152009-11-23 21:57:23 +00004721defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
Bob Wilson507df402009-10-21 02:15:46 +00004722 NEONvqshrnsu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004723
4724// VQRSHL : Vector Saturating Rounding Shift
Owen Anderson86ed2322010-10-26 22:50:46 +00004725defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004726 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson86ed2322010-10-26 22:50:46 +00004727 "vqrshl", "s", int_arm_neon_vqrshifts>;
4728defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
Johnny Chen9ee9d7d2010-03-26 23:49:07 +00004729 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
Owen Anderson86ed2322010-10-26 22:50:46 +00004730 "vqrshl", "u", int_arm_neon_vqrshiftu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004731
4732// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
Evan Chengf81bf152009-11-23 21:57:23 +00004733defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
Bob Wilson507df402009-10-21 02:15:46 +00004734 NEONvqrshrns>;
Evan Chengf81bf152009-11-23 21:57:23 +00004735defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
Bob Wilson507df402009-10-21 02:15:46 +00004736 NEONvqrshrnu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004737
4738// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
Evan Chengf81bf152009-11-23 21:57:23 +00004739defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
Bob Wilson507df402009-10-21 02:15:46 +00004740 NEONvqrshrnsu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004741
4742// VSRA : Vector Shift Right and Accumulate
Evan Chengf81bf152009-11-23 21:57:23 +00004743defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4744defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004745// VRSRA : Vector Rounding Shift Right and Accumulate
Evan Chengf81bf152009-11-23 21:57:23 +00004746defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4747defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004748
4749// VSLI : Vector Shift Left and Insert
Bill Wendling620d0cc2011-03-09 00:33:17 +00004750defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4751
Bob Wilson5bafff32009-06-22 23:27:02 +00004752// VSRI : Vector Shift Right and Insert
Bill Wendling620d0cc2011-03-09 00:33:17 +00004753defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
Bob Wilson5bafff32009-06-22 23:27:02 +00004754
4755// Vector Absolute and Saturating Absolute.
4756
4757// VABS : Vector Absolute Value
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004758defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004759 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004760 int_arm_neon_vabs>;
David Goodwin127221f2009-09-23 21:38:08 +00004761def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004762 IIC_VUNAD, "vabs", "f32",
Bob Wilsonb0abb4d2009-08-11 05:39:44 +00004763 v2f32, v2f32, int_arm_neon_vabs>;
David Goodwin127221f2009-09-23 21:38:08 +00004764def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004765 IIC_VUNAQ, "vabs", "f32",
Bob Wilsonb0abb4d2009-08-11 05:39:44 +00004766 v4f32, v4f32, int_arm_neon_vabs>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004767
4768// VQABS : Vector Saturating Absolute Value
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004769defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004770 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004771 int_arm_neon_vqabs>;
4772
4773// Vector Negate.
4774
Bob Wilsoncba270d2010-07-13 21:16:48 +00004775def vnegd : PatFrag<(ops node:$in),
4776 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4777def vnegq : PatFrag<(ops node:$in),
4778 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004779
Evan Chengf81bf152009-11-23 21:57:23 +00004780class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonca6945e2010-12-01 00:28:25 +00004781 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4782 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4783 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00004784class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonca6945e2010-12-01 00:28:25 +00004785 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4786 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4787 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004788
Chris Lattner0a00ed92010-03-28 08:39:10 +00004789// VNEG : Vector Negate (integer)
Evan Chengf81bf152009-11-23 21:57:23 +00004790def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4791def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4792def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4793def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4794def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4795def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004796
4797// VNEG : Vector Negate (floating-point)
Bob Wilson3c0f96e2010-02-17 22:23:11 +00004798def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00004799 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4800 "vneg", "f32", "$Vd, $Vm", "",
4801 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004802def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
Owen Andersonca6945e2010-12-01 00:28:25 +00004803 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4804 "vneg", "f32", "$Vd, $Vm", "",
4805 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004806
Bob Wilsoncba270d2010-07-13 21:16:48 +00004807def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4808def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4809def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4810def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4811def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4812def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004813
4814// VQNEG : Vector Saturating Negate
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004815defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004816 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004817 int_arm_neon_vqneg>;
4818
4819// Vector Bit Counting Operations.
4820
4821// VCLS : Vector Count Leading Sign Bits
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004822defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004823 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
Bob Wilson5bafff32009-06-22 23:27:02 +00004824 int_arm_neon_vcls>;
4825// VCLZ : Vector Count Leading Zeros
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004826defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004827 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
Joel Jones06a6a302012-07-13 23:25:25 +00004828 ctlz>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004829// VCNT : Vector Count One Bits
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004830def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004831 IIC_VCNTiD, "vcnt", "8",
Joel Jones7c82e6a2012-07-18 00:02:16 +00004832 v8i8, v8i8, ctpop>;
David Goodwin127221f2009-09-23 21:38:08 +00004833def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
Evan Chengf81bf152009-11-23 21:57:23 +00004834 IIC_VCNTiQ, "vcnt", "8",
Joel Jones7c82e6a2012-07-18 00:02:16 +00004835 v16i8, v16i8, ctpop>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004836
Jim Grosbachfe7b4992011-10-21 16:14:12 +00004837// Vector Swap
Johnny Chend8836042010-02-24 20:06:07 +00004838def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
Jim Grosbacha45e3742012-03-30 18:53:01 +00004839 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
4840 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
Lang Hames2cc494b2012-02-13 23:37:19 +00004841 []>;
Johnny Chend8836042010-02-24 20:06:07 +00004842def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
Jim Grosbacha45e3742012-03-30 18:53:01 +00004843 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
4844 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
Lang Hames2cc494b2012-02-13 23:37:19 +00004845 []>;
Johnny Chend8836042010-02-24 20:06:07 +00004846
Bob Wilson5bafff32009-06-22 23:27:02 +00004847// Vector Move Operations.
4848
4849// VMOV : Vector Move (Register)
Owen Anderson43967a92011-07-15 18:46:47 +00004850def : InstAlias<"vmov${p} $Vd, $Vm",
4851 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4852def : InstAlias<"vmov${p} $Vd, $Vm",
4853 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004854
Bob Wilson5bafff32009-06-22 23:27:02 +00004855// VMOV : Vector Move (Immediate)
4856
Evan Cheng47006be2010-05-17 21:54:50 +00004857let isReMaterializable = 1 in {
Owen Andersonca6945e2010-12-01 00:28:25 +00004858def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
Jim Grosbach0e387b22011-10-17 22:26:03 +00004859 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004860 "vmov", "i8", "$Vd, $SIMM", "",
4861 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4862def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
Jim Grosbach0e387b22011-10-17 22:26:03 +00004863 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004864 "vmov", "i8", "$Vd, $SIMM", "",
4865 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004866
Owen Andersonca6945e2010-12-01 00:28:25 +00004867def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
Jim Grosbachea461102011-10-17 23:09:09 +00004868 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004869 "vmov", "i16", "$Vd, $SIMM", "",
4870 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
Jim Grosbach1251e1a2010-11-18 01:39:50 +00004871 let Inst{9} = SIMM{9};
Owen Andersona88ea032010-10-26 17:40:54 +00004872}
4873
Owen Andersonca6945e2010-12-01 00:28:25 +00004874def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
Jim Grosbachea461102011-10-17 23:09:09 +00004875 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004876 "vmov", "i16", "$Vd, $SIMM", "",
4877 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004878 let Inst{9} = SIMM{9};
4879}
Bob Wilson5bafff32009-06-22 23:27:02 +00004880
Owen Andersonca6945e2010-12-01 00:28:25 +00004881def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
Jim Grosbach6248a542011-10-18 00:22:00 +00004882 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004883 "vmov", "i32", "$Vd, $SIMM", "",
4884 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004885 let Inst{11-8} = SIMM{11-8};
4886}
4887
Owen Andersonca6945e2010-12-01 00:28:25 +00004888def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
Jim Grosbach6248a542011-10-18 00:22:00 +00004889 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004890 "vmov", "i32", "$Vd, $SIMM", "",
4891 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
Owen Andersona88ea032010-10-26 17:40:54 +00004892 let Inst{11-8} = SIMM{11-8};
4893}
Bob Wilson5bafff32009-06-22 23:27:02 +00004894
Owen Andersonca6945e2010-12-01 00:28:25 +00004895def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
Jim Grosbachf2f5bc62011-10-18 16:18:11 +00004896 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004897 "vmov", "i64", "$Vd, $SIMM", "",
4898 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4899def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
Jim Grosbachf2f5bc62011-10-18 16:18:11 +00004900 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
Owen Andersonca6945e2010-12-01 00:28:25 +00004901 "vmov", "i64", "$Vd, $SIMM", "",
4902 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
Evan Chengeaa192a2011-11-15 02:12:34 +00004903
4904def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4905 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4906 "vmov", "f32", "$Vd, $SIMM", "",
4907 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4908def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4909 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4910 "vmov", "f32", "$Vd, $SIMM", "",
4911 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
Evan Cheng47006be2010-05-17 21:54:50 +00004912} // isReMaterializable
Bob Wilson5bafff32009-06-22 23:27:02 +00004913
4914// VMOV : Vector Get Lane (move scalar to ARM core register)
4915
Johnny Chen131c4a52009-11-23 17:48:17 +00004916def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
Jim Grosbach687656c2011-10-18 20:10:47 +00004917 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4918 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004919 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4920 imm:$lane))]> {
4921 let Inst{21} = lane{2};
4922 let Inst{6-5} = lane{1-0};
4923}
Johnny Chen131c4a52009-11-23 17:48:17 +00004924def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
Jim Grosbach687656c2011-10-18 20:10:47 +00004925 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4926 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004927 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4928 imm:$lane))]> {
4929 let Inst{21} = lane{1};
4930 let Inst{6} = lane{0};
4931}
Johnny Chen131c4a52009-11-23 17:48:17 +00004932def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
Jim Grosbach687656c2011-10-18 20:10:47 +00004933 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4934 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004935 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4936 imm:$lane))]> {
4937 let Inst{21} = lane{2};
4938 let Inst{6-5} = lane{1-0};
4939}
Johnny Chen131c4a52009-11-23 17:48:17 +00004940def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
Jim Grosbach687656c2011-10-18 20:10:47 +00004941 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4942 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004943 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4944 imm:$lane))]> {
4945 let Inst{21} = lane{1};
4946 let Inst{6} = lane{0};
4947}
Johnny Chen131c4a52009-11-23 17:48:17 +00004948def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
Jim Grosbach687656c2011-10-18 20:10:47 +00004949 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4950 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004951 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4952 imm:$lane))]> {
4953 let Inst{21} = lane{0};
4954}
Bob Wilson5bafff32009-06-22 23:27:02 +00004955// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4956def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4957 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004958 (DSubReg_i8_reg imm:$lane))),
Bob Wilson5bafff32009-06-22 23:27:02 +00004959 (SubReg_i8_lane imm:$lane))>;
4960def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4961 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004962 (DSubReg_i16_reg imm:$lane))),
Bob Wilson5bafff32009-06-22 23:27:02 +00004963 (SubReg_i16_lane imm:$lane))>;
4964def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4965 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004966 (DSubReg_i8_reg imm:$lane))),
Bob Wilson5bafff32009-06-22 23:27:02 +00004967 (SubReg_i8_lane imm:$lane))>;
4968def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4969 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004970 (DSubReg_i16_reg imm:$lane))),
Bob Wilson5bafff32009-06-22 23:27:02 +00004971 (SubReg_i16_lane imm:$lane))>;
4972def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4973 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004974 (DSubReg_i32_reg imm:$lane))),
Bob Wilson5bafff32009-06-22 23:27:02 +00004975 (SubReg_i32_lane imm:$lane))>;
Anton Korobeynikov2324bdc2009-08-28 23:41:26 +00004976def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004977 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
Anton Korobeynikove56f9082009-09-12 22:21:08 +00004978 (SSubReg_f32_reg imm:$src2))>;
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004979def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
Bob Wilson9abe19d2010-02-17 00:31:29 +00004980 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
Anton Korobeynikove56f9082009-09-12 22:21:08 +00004981 (SSubReg_f32_reg imm:$src2))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004982//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004983// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004984def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00004985 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00004986
4987
4988// VMOV : Vector Set Lane (move ARM core register to scalar)
4989
Owen Andersond2fbdb72010-10-27 21:28:09 +00004990let Constraints = "$src1 = $V" in {
4991def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
Jim Grosbach687656c2011-10-18 20:10:47 +00004992 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4993 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
Owen Andersond2fbdb72010-10-27 21:28:09 +00004994 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4995 GPR:$R, imm:$lane))]> {
4996 let Inst{21} = lane{2};
4997 let Inst{6-5} = lane{1-0};
4998}
4999def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
Jim Grosbach687656c2011-10-18 20:10:47 +00005000 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5001 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
Owen Andersond2fbdb72010-10-27 21:28:09 +00005002 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5003 GPR:$R, imm:$lane))]> {
5004 let Inst{21} = lane{1};
5005 let Inst{6} = lane{0};
5006}
5007def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
Jim Grosbach687656c2011-10-18 20:10:47 +00005008 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5009 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
Owen Andersond2fbdb72010-10-27 21:28:09 +00005010 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5011 GPR:$R, imm:$lane))]> {
5012 let Inst{21} = lane{0};
5013}
Bob Wilson5bafff32009-06-22 23:27:02 +00005014}
5015def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
Jim Grosbach1251e1a2010-11-18 01:39:50 +00005016 (v16i8 (INSERT_SUBREG QPR:$src1,
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005017 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005018 (DSubReg_i8_reg imm:$lane))),
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005019 GPR:$src2, (SubReg_i8_lane imm:$lane))),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005020 (DSubReg_i8_reg imm:$lane)))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005021def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
Jim Grosbach1251e1a2010-11-18 01:39:50 +00005022 (v8i16 (INSERT_SUBREG QPR:$src1,
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005023 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005024 (DSubReg_i16_reg imm:$lane))),
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005025 GPR:$src2, (SubReg_i16_lane imm:$lane))),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005026 (DSubReg_i16_reg imm:$lane)))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005027def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
Jim Grosbach1251e1a2010-11-18 01:39:50 +00005028 (v4i32 (INSERT_SUBREG QPR:$src1,
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005029 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005030 (DSubReg_i32_reg imm:$lane))),
Chris Lattnerd10a53d2010-03-08 18:51:21 +00005031 GPR:$src2, (SubReg_i32_lane imm:$lane))),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005032 (DSubReg_i32_reg imm:$lane)))>;
5033
Anton Korobeynikovd91aafd2009-08-30 19:06:39 +00005034def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
Anton Korobeynikov3a639a02009-11-02 00:11:39 +00005035 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5036 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005037def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
Anton Korobeynikov3a639a02009-11-02 00:11:39 +00005038 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5039 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005040
5041//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005042// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005043def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
Anton Korobeynikov06af2ba2009-08-08 14:06:07 +00005044 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005045
Anton Korobeynikovfdf189a2009-08-27 14:38:44 +00005046def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005047 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
Chris Lattner77144e72010-03-15 00:52:43 +00005048def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005049 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
Anton Korobeynikovfdf189a2009-08-27 14:38:44 +00005050def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005051 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
Anton Korobeynikovfdf189a2009-08-27 14:38:44 +00005052
Anton Korobeynikovb5cdf872009-08-27 16:10:17 +00005053def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5054 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5055def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5056 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5057def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5058 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5059
5060def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5061 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5062 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005063 dsub_0)>;
Anton Korobeynikovb5cdf872009-08-27 16:10:17 +00005064def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5065 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5066 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005067 dsub_0)>;
Anton Korobeynikovb5cdf872009-08-27 16:10:17 +00005068def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5069 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5070 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
Jakob Stoklund Olesen558661d2010-05-24 16:54:32 +00005071 dsub_0)>;
Anton Korobeynikovb5cdf872009-08-27 16:10:17 +00005072
Bob Wilson5bafff32009-06-22 23:27:02 +00005073// VDUP : Vector Duplicate (from ARM core register to all elements)
5074
Evan Chengf81bf152009-11-23 21:57:23 +00005075class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
Owen Andersonca6945e2010-12-01 00:28:25 +00005076 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5077 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5078 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00005079class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
Owen Andersonca6945e2010-12-01 00:28:25 +00005080 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5081 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5082 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005083
Evan Chengf81bf152009-11-23 21:57:23 +00005084def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5085def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5086def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
5087def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5088def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5089def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005090
Jim Grosbach958108a2011-03-11 20:44:08 +00005091def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
5092def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005093
5094// VDUP : Vector Duplicate Lane (from scalar to all elements)
5095
Johnny Chene4614f72010-03-25 17:01:27 +00005096class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
Jim Grosbach460a9052011-10-07 23:56:00 +00005097 ValueType Ty, Operand IdxTy>
5098 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5099 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
Owen Andersonca6945e2010-12-01 00:28:25 +00005100 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005101
Johnny Chene4614f72010-03-25 17:01:27 +00005102class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
Jim Grosbach460a9052011-10-07 23:56:00 +00005103 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5104 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5105 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
Owen Andersonca6945e2010-12-01 00:28:25 +00005106 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
Jim Grosbach460a9052011-10-07 23:56:00 +00005107 VectorIndex32:$lane)))]>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005108
Bob Wilson507df402009-10-21 02:15:46 +00005109// Inst{19-16} is partially specified depending on the element size.
5110
Jim Grosbach460a9052011-10-07 23:56:00 +00005111def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5112 bits<3> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005113 let Inst{19-17} = lane{2-0};
5114}
Jim Grosbach460a9052011-10-07 23:56:00 +00005115def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5116 bits<2> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005117 let Inst{19-18} = lane{1-0};
5118}
Jim Grosbach460a9052011-10-07 23:56:00 +00005119def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5120 bits<1> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005121 let Inst{19} = lane{0};
5122}
Jim Grosbach460a9052011-10-07 23:56:00 +00005123def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5124 bits<3> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005125 let Inst{19-17} = lane{2-0};
5126}
Jim Grosbach460a9052011-10-07 23:56:00 +00005127def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5128 bits<2> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005129 let Inst{19-18} = lane{1-0};
5130}
Jim Grosbach460a9052011-10-07 23:56:00 +00005131def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5132 bits<1> lane;
Owen Andersonf587a932010-10-27 19:25:54 +00005133 let Inst{19} = lane{0};
5134}
Jim Grosbach8b8515c2011-03-11 20:31:17 +00005135
5136def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5137 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5138
5139def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5140 (VDUPLN32q DPR:$Vm, imm:$lane)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005141
Bob Wilson0ce37102009-08-14 05:08:32 +00005142def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5143 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5144 (DSubReg_i8_reg imm:$lane))),
5145 (SubReg_i8_lane imm:$lane)))>;
5146def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5147 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5148 (DSubReg_i16_reg imm:$lane))),
5149 (SubReg_i16_lane imm:$lane)))>;
5150def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5151 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5152 (DSubReg_i32_reg imm:$lane))),
5153 (SubReg_i32_lane imm:$lane)))>;
5154def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
Jim Grosbach8b8515c2011-03-11 20:31:17 +00005155 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
Bob Wilson0ce37102009-08-14 05:08:32 +00005156 (DSubReg_i32_reg imm:$lane))),
5157 (SubReg_i32_lane imm:$lane)))>;
5158
Jim Grosbach65dc3032010-10-06 21:16:16 +00005159def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
Johnny Chenda1aea42009-11-23 21:00:43 +00005160 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
Jim Grosbach65dc3032010-10-06 21:16:16 +00005161def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
Johnny Chenda1aea42009-11-23 21:00:43 +00005162 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
Anton Korobeynikov32a1b252009-08-07 22:36:50 +00005163
Bob Wilson5bafff32009-06-22 23:27:02 +00005164// VMOVN : Vector Narrowing Move
Evan Chengcae6a122010-10-01 20:50:58 +00005165defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
Bob Wilson973a0742010-08-30 20:02:30 +00005166 "vmovn", "i", trunc>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005167// VQMOVN : Vector Saturating Narrowing Move
Evan Chengf81bf152009-11-23 21:57:23 +00005168defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5169 "vqmovn", "s", int_arm_neon_vqmovns>;
5170defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5171 "vqmovn", "u", int_arm_neon_vqmovnu>;
5172defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5173 "vqmovun", "s", int_arm_neon_vqmovnsu>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005174// VMOVL : Vector Lengthening Move
Bob Wilsonb31a11b2010-08-20 04:54:02 +00005175defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5176defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
Bob Wilson1e9ccd62012-01-20 20:59:56 +00005177def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5178def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5179def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005180
5181// Vector Conversions.
5182
Johnny Chen9e088762010-03-17 17:52:21 +00005183// VCVT : Vector Convert Between Floating-Point and Integers
Johnny Chen6c8648b2010-03-17 23:26:50 +00005184def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5185 v2i32, v2f32, fp_to_sint>;
5186def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5187 v2i32, v2f32, fp_to_uint>;
5188def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5189 v2f32, v2i32, sint_to_fp>;
5190def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5191 v2f32, v2i32, uint_to_fp>;
Johnny Chen9e088762010-03-17 17:52:21 +00005192
Johnny Chen6c8648b2010-03-17 23:26:50 +00005193def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5194 v4i32, v4f32, fp_to_sint>;
5195def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5196 v4i32, v4f32, fp_to_uint>;
5197def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5198 v4f32, v4i32, sint_to_fp>;
5199def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5200 v4f32, v4i32, uint_to_fp>;
Bob Wilson5bafff32009-06-22 23:27:02 +00005201
5202// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
Owen Andersonb589be92011-11-15 19:55:00 +00005203let DecoderMethod = "DecodeVCVTD" in {
Evan Chengf81bf152009-11-23 21:57:23 +00005204def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005205 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
Evan Chengf81bf152009-11-23 21:57:23 +00005206def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005207 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
Evan Chengf81bf152009-11-23 21:57:23 +00005208def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005209 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
Evan Chengf81bf152009-11-23 21:57:23 +00005210def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005211 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
Owen Andersonb589be92011-11-15 19:55:00 +00005212}
Bob Wilson5bafff32009-06-22 23:27:02 +00005213
Owen Andersonb589be92011-11-15 19:55:00 +00005214let DecoderMethod = "DecodeVCVTQ" in {
Evan Chengf81bf152009-11-23 21:57:23 +00005215def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005216 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
Evan Chengf81bf152009-11-23 21:57:23 +00005217def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005218 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
Evan Chengf81bf152009-11-23 21:57:23 +00005219def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005220 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
Evan Chengf81bf152009-11-23 21:57:23 +00005221def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
Bob Wilson5bafff32009-06-22 23:27:02 +00005222 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
Owen Andersonb589be92011-11-15 19:55:00 +00005223}
Bob Wilson5bafff32009-06-22 23:27:02 +00005224
Bob Wilson04063562010-12-15 22:14:12 +00005225// VCVT : Vector Convert Between Half-Precision and Single-Precision.
5226def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5227 IIC_VUNAQ, "vcvt", "f16.f32",
5228 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5229 Requires<[HasNEON, HasFP16]>;
5230def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5231 IIC_VUNAQ, "vcvt", "f32.f16",
5232 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5233 Requires<[HasNEON, HasFP16]>;
5234
Bob Wilsond8e17572009-08-12 22:31:50 +00005235// Vector Reverse.
Bob Wilson8bb9e482009-07-26 00:39:34 +00005236
5237// VREV64 : Vector Reverse elements within 64-bit doublewords
5238
Evan Chengf81bf152009-11-23 21:57:23 +00005239class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005240 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5241 (ins DPR:$Vm), IIC_VMOVD,
5242 OpcodeStr, Dt, "$Vd, $Vm", "",
5243 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00005244class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005245 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5246 (ins QPR:$Vm), IIC_VMOVQ,
5247 OpcodeStr, Dt, "$Vd, $Vm", "",
5248 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005249
Evan Chengf81bf152009-11-23 21:57:23 +00005250def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5251def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5252def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
Jim Grosbach1558df72011-03-11 20:18:05 +00005253def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005254
Evan Chengf81bf152009-11-23 21:57:23 +00005255def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5256def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5257def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
Jim Grosbach1558df72011-03-11 20:18:05 +00005258def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005259
5260// VREV32 : Vector Reverse elements within 32-bit words
5261
Evan Chengf81bf152009-11-23 21:57:23 +00005262class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005263 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5264 (ins DPR:$Vm), IIC_VMOVD,
5265 OpcodeStr, Dt, "$Vd, $Vm", "",
5266 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00005267class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005268 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5269 (ins QPR:$Vm), IIC_VMOVQ,
5270 OpcodeStr, Dt, "$Vd, $Vm", "",
5271 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005272
Evan Chengf81bf152009-11-23 21:57:23 +00005273def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5274def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005275
Evan Chengf81bf152009-11-23 21:57:23 +00005276def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5277def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005278
5279// VREV16 : Vector Reverse elements within 16-bit halfwords
5280
Evan Chengf81bf152009-11-23 21:57:23 +00005281class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005282 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5283 (ins DPR:$Vm), IIC_VMOVD,
5284 OpcodeStr, Dt, "$Vd, $Vm", "",
5285 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
Evan Chengf81bf152009-11-23 21:57:23 +00005286class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
Owen Andersonaa545242010-11-21 06:47:06 +00005287 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5288 (ins QPR:$Vm), IIC_VMOVQ,
5289 OpcodeStr, Dt, "$Vd, $Vm", "",
5290 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005291
Evan Chengf81bf152009-11-23 21:57:23 +00005292def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5293def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
Bob Wilson8bb9e482009-07-26 00:39:34 +00005294
Bob Wilsonde95c1b82009-08-19 17:03:43 +00005295// Other Vector Shuffles.
5296
Bob Wilson5e8b8332011-01-07 04:59:04 +00005297// Aligned extractions: really just dropping registers
5298
5299class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5300 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5301 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5302
5303def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5304
5305def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5306
5307def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5308
5309def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5310
5311def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5312
5313
Bob Wilsonde95c1b82009-08-19 17:03:43 +00005314// VEXT : Vector Extract
5315
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00005316
5317// All of these have a two-operand InstAlias.
5318let TwoOperandAliasConstraint = "$Vn = $Vd" in {
Jim Grosbach587f5062011-12-02 23:34:39 +00005319class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
Owen Andersonaa545242010-11-21 06:47:06 +00005320 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
Jim Grosbach587f5062011-12-02 23:34:39 +00005321 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
Owen Andersonaa545242010-11-21 06:47:06 +00005322 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5323 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
Jim Grosbach587f5062011-12-02 23:34:39 +00005324 (Ty DPR:$Vm), imm:$index)))]> {
Owen Anderson3eff4af2010-10-27 23:56:39 +00005325 bits<4> index;
5326 let Inst{11-8} = index{3-0};
5327}
Anton Korobeynikov5da894f2009-08-21 12:40:21 +00005328
Jim Grosbach587f5062011-12-02 23:34:39 +00005329class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
Owen Andersonaa545242010-11-21 06:47:06 +00005330 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
Jim Grosbache40ab242011-12-02 22:57:57 +00005331 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
Owen Andersonaa545242010-11-21 06:47:06 +00005332 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5333 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
Jim Grosbach587f5062011-12-02 23:34:39 +00005334 (Ty QPR:$Vm), imm:$index)))]> {
Owen Anderson3eff4af2010-10-27 23:56:39 +00005335 bits<4> index;
5336 let Inst{11-8} = index{3-0};
5337}
Jim Grosbach8e3c17a2012-04-20 23:46:33 +00005338}
Anton Korobeynikov5da894f2009-08-21 12:40:21 +00005339
Jim Grosbach587f5062011-12-02 23:34:39 +00005340def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
Owen Anderson7a258252010-11-03 18:16:27 +00005341 let Inst{11-8} = index{3-0};
5342}
Jim Grosbach587f5062011-12-02 23:34:39 +00005343def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
Owen Anderson7a258252010-11-03 18:16:27 +00005344 let Inst{11-9} = index{2-0};
5345 let Inst{8} = 0b0;
5346}
Jim Grosbach587f5062011-12-02 23:34:39 +00005347def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
Owen Anderson7a258252010-11-03 18:16:27 +00005348 let Inst{11-10} = index{1-0};
5349 let Inst{9-8} = 0b00;
5350}
Owen Anderson167eb1f2011-07-15 17:48:05 +00005351def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5352 (v2f32 DPR:$Vm),
5353 (i32 imm:$index))),
5354 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
Anton Korobeynikov5da894f2009-08-21 12:40:21 +00005355
Jim Grosbach587f5062011-12-02 23:34:39 +00005356def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
Owen Anderson7a258252010-11-03 18:16:27 +00005357 let Inst{11-8} = index{3-0};
5358}
Jim Grosbach587f5062011-12-02 23:34:39 +00005359def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
Owen Anderson7a258252010-11-03 18:16:27 +00005360 let Inst{11-9} = index{2-0};
5361 let Inst{8} = 0b0;
5362}
Jim Grosbach587f5062011-12-02 23:34:39 +00005363def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
Owen Anderson7a258252010-11-03 18:16:27 +00005364 let Inst{11-10} = index{1-0};
5365 let Inst{9-8} = 0b00;
5366}
Jim Grosbach8759c3f2011-12-08 22:19:04 +00005367def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
Jim Grosbach587f5062011-12-02 23:34:39 +00005368 let Inst{11} = index{0};
5369 let Inst{10-8} = 0b000;
5370}
Owen Anderson167eb1f2011-07-15 17:48:05 +00005371def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5372 (v4f32 QPR:$Vm),
5373 (i32 imm:$index))),
5374 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
Bob Wilsonde95c1b82009-08-19 17:03:43 +00005375
Bob Wilson64efd902009-08-08 05:53:00 +00005376// VTRN : Vector Transpose
5377
Evan Chengf81bf152009-11-23 21:57:23 +00005378def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5379def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5380def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
Bob Wilson64efd902009-08-08 05:53:00 +00005381
Evan Chengf81bf152009-11-23 21:57:23 +00005382def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5383def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5384def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
Bob Wilson64efd902009-08-08 05:53:00 +00005385
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00005386// VUZP : Vector Unzip (Deinterleave)
5387
Evan Chengf81bf152009-11-23 21:57:23 +00005388def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5389def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
Jim Grosbach18355472012-04-11 17:40:18 +00005390// vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5391def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5392 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00005393
Evan Chengf81bf152009-11-23 21:57:23 +00005394def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5395def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5396def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00005397
5398// VZIP : Vector Zip (Interleave)
5399
Evan Chengf81bf152009-11-23 21:57:23 +00005400def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5401def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
Jim Grosbach6073b302012-04-11 16:53:25 +00005402// vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5403def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5404 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
Bob Wilsonb6ab51e2009-08-08 06:13:25 +00005405
Evan Chengf81bf152009-11-23 21:57:23 +00005406def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5407def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5408def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
Bob Wilson64efd902009-08-08 05:53:00 +00005409
Bob Wilson114a2662009-08-12 20:51:55 +00005410// Vector Table Lookup and Table Extension.
5411
5412// VTBL : Vector Table Lookup
Owen Anderson8d7d2e12011-08-09 20:55:18 +00005413let DecoderMethod = "DecodeTBLInstruction" in {
Bob Wilson114a2662009-08-12 20:51:55 +00005414def VTBL1
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005415 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
Jim Grosbach862019c2011-10-18 23:02:30 +00005416 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5417 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5418 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
Evan Cheng0d92f5f2009-10-01 08:22:27 +00005419let hasExtraSrcRegAllocReq = 1 in {
Bob Wilson114a2662009-08-12 20:51:55 +00005420def VTBL2
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005421 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
Jim Grosbach28f08c92012-03-05 19:33:30 +00005422 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
Jim Grosbach60d99a52011-12-15 22:27:11 +00005423 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
Bob Wilson114a2662009-08-12 20:51:55 +00005424def VTBL3
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005425 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
Jim Grosbach60d99a52011-12-15 22:27:11 +00005426 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5427 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
Bob Wilson114a2662009-08-12 20:51:55 +00005428def VTBL4
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005429 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
Jim Grosbach60d99a52011-12-15 22:27:11 +00005430 (ins VecListFourD:$Vn, DPR:$Vm),
Johnny Chen79c4d822010-03-29 01:14:22 +00005431 NVTBLFrm, IIC_VTB4,
Jim Grosbach60d99a52011-12-15 22:27:11 +00005432 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
Evan Cheng0d92f5f2009-10-01 08:22:27 +00005433} // hasExtraSrcRegAllocReq = 1
Bob Wilson114a2662009-08-12 20:51:55 +00005434
Bob Wilsonbd916c52010-09-13 23:55:10 +00005435def VTBL3Pseudo
Jim Grosbach7cd27292010-10-06 20:36:55 +00005436 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
Bob Wilsonbd916c52010-09-13 23:55:10 +00005437def VTBL4Pseudo
Jim Grosbach7cd27292010-10-06 20:36:55 +00005438 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
Bob Wilsonbd916c52010-09-13 23:55:10 +00005439
Bob Wilson114a2662009-08-12 20:51:55 +00005440// VTBX : Vector Table Extension
5441def VTBX1
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005442 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
Jim Grosbachd0b61472011-10-20 14:48:50 +00005443 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5444 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005445 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
Jim Grosbachd0b61472011-10-20 14:48:50 +00005446 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
Evan Cheng0d92f5f2009-10-01 08:22:27 +00005447let hasExtraSrcRegAllocReq = 1 in {
Bob Wilson114a2662009-08-12 20:51:55 +00005448def VTBX2
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005449 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
Jim Grosbach28f08c92012-03-05 19:33:30 +00005450 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
Jim Grosbach60d99a52011-12-15 22:27:11 +00005451 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
Bob Wilson114a2662009-08-12 20:51:55 +00005452def VTBX3
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005453 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
Jim Grosbach60d99a52011-12-15 22:27:11 +00005454 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
Johnny Chen79c4d822010-03-29 01:14:22 +00005455 NVTBLFrm, IIC_VTBX3,
Jim Grosbach60d99a52011-12-15 22:27:11 +00005456 "vtbx", "8", "$Vd, $Vn, $Vm",
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005457 "$orig = $Vd", []>;
Bob Wilson114a2662009-08-12 20:51:55 +00005458def VTBX4
Jim Grosbach60d99a52011-12-15 22:27:11 +00005459 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5460 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5461 "vtbx", "8", "$Vd, $Vn, $Vm",
Owen Andersoncfd0e1f2010-10-28 00:18:46 +00005462 "$orig = $Vd", []>;
Evan Cheng0d92f5f2009-10-01 08:22:27 +00005463} // hasExtraSrcRegAllocReq = 1
Bob Wilson114a2662009-08-12 20:51:55 +00005464
Bob Wilsonbd916c52010-09-13 23:55:10 +00005465def VTBX3Pseudo
5466 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
Jim Grosbach7cd27292010-10-06 20:36:55 +00005467 IIC_VTBX3, "$orig = $dst", []>;
Bob Wilsonbd916c52010-09-13 23:55:10 +00005468def VTBX4Pseudo
5469 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
Jim Grosbach7cd27292010-10-06 20:36:55 +00005470 IIC_VTBX4, "$orig = $dst", []>;
Owen Anderson8d7d2e12011-08-09 20:55:18 +00005471} // DecoderMethod = "DecodeTBLInstruction"
Bob Wilsonbd916c52010-09-13 23:55:10 +00005472
Bob Wilson5bafff32009-06-22 23:27:02 +00005473//===----------------------------------------------------------------------===//
Evan Cheng1d2426c2009-08-07 19:30:41 +00005474// NEON instructions for single-precision FP math
5475//===----------------------------------------------------------------------===//
5476
Bob Wilson0e6d5402010-12-13 23:02:31 +00005477class N2VSPat<SDNode OpNode, NeonI Inst>
5478 : NEONFPPat<(f32 (OpNode SPR:$a)),
Bob Wilson1e6f5962010-12-13 21:58:05 +00005479 (EXTRACT_SUBREG
Bob Wilson4711d5c2010-12-13 23:02:37 +00005480 (v2f32 (COPY_TO_REGCLASS (Inst
5481 (INSERT_SUBREG
Bob Wilson0e6d5402010-12-13 23:02:31 +00005482 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5483 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
Bob Wilson3c0f96e2010-02-17 22:23:11 +00005484
5485class N3VSPat<SDNode OpNode, NeonI Inst>
5486 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
Bob Wilson4711d5c2010-12-13 23:02:37 +00005487 (EXTRACT_SUBREG
5488 (v2f32 (COPY_TO_REGCLASS (Inst
5489 (INSERT_SUBREG
5490 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5491 SPR:$a, ssub_0),
5492 (INSERT_SUBREG
5493 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5494 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
Bob Wilson3c0f96e2010-02-17 22:23:11 +00005495
5496class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5497 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
Bob Wilson4711d5c2010-12-13 23:02:37 +00005498 (EXTRACT_SUBREG
5499 (v2f32 (COPY_TO_REGCLASS (Inst
5500 (INSERT_SUBREG
5501 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5502 SPR:$acc, ssub_0),
5503 (INSERT_SUBREG
5504 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5505 SPR:$a, ssub_0),
5506 (INSERT_SUBREG
5507 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5508 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
Bob Wilson3c0f96e2010-02-17 22:23:11 +00005509
Bob Wilson4711d5c2010-12-13 23:02:37 +00005510def : N3VSPat<fadd, VADDfd>;
5511def : N3VSPat<fsub, VSUBfd>;
5512def : N3VSPat<fmul, VMULfd>;
5513def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
Evan Chengbee78fe2012-04-11 05:33:07 +00005514 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
Bob Wilson4711d5c2010-12-13 23:02:37 +00005515def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
Evan Chengbee78fe2012-04-11 05:33:07 +00005516 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00005517def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
Evan Chengbee78fe2012-04-11 05:33:07 +00005518 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
Anton Korobeynikov4b4e6222012-01-22 12:07:33 +00005519def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
Evan Chengbee78fe2012-04-11 05:33:07 +00005520 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
Bob Wilson0e6d5402010-12-13 23:02:31 +00005521def : N2VSPat<fabs, VABSfd>;
Bob Wilson0e6d5402010-12-13 23:02:31 +00005522def : N2VSPat<fneg, VNEGfd>;
Bob Wilson4711d5c2010-12-13 23:02:37 +00005523def : N3VSPat<NEONfmax, VMAXfd>;
5524def : N3VSPat<NEONfmin, VMINfd>;
Bob Wilson0e6d5402010-12-13 23:02:31 +00005525def : N2VSPat<arm_ftosi, VCVTf2sd>;
5526def : N2VSPat<arm_ftoui, VCVTf2ud>;
5527def : N2VSPat<arm_sitof, VCVTs2fd>;
5528def : N2VSPat<arm_uitof, VCVTu2fd>;
David Goodwin338268c2009-08-10 22:17:39 +00005529
Evan Cheng1d2426c2009-08-07 19:30:41 +00005530//===----------------------------------------------------------------------===//
Bob Wilson5bafff32009-06-22 23:27:02 +00005531// Non-Instruction Patterns
5532//===----------------------------------------------------------------------===//
5533
5534// bit_convert
5535def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5536def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5537def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5538def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5539def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5540def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5541def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5542def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5543def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5544def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5545def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5546def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5547def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5548def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5549def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5550def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5551def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5552def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5553def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5554def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5555def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5556def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5557def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5558def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5559def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5560def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5561def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5562def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5563def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5564def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5565
5566def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5567def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5568def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5569def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5570def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5571def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5572def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5573def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5574def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5575def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5576def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5577def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5578def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5579def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5580def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5581def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5582def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5583def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5584def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5585def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5586def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5587def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5588def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5589def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5590def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5591def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5592def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5593def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5594def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5595def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
Jim Grosbachef448762011-11-14 23:11:19 +00005596
James Molloy873fd5f2012-02-20 09:24:05 +00005597// Vector lengthening move with load, matching extending loads.
5598
5599// extload, zextload and sextload for a standard lengthening load. Example:
Tim Northover37abe8d2012-04-26 08:46:29 +00005600// Lengthen_Single<"8", "i16", "i8"> =
5601// Pat<(v8i16 (extloadvi8 addrmode6oneL32:$addr))
5602// (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5603// (f64 (IMPLICIT_DEF)), (i32 0)))>;
James Molloy873fd5f2012-02-20 09:24:05 +00005604multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
5605 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005606 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005607 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005608 (VLD1LNd32 addrmode6oneL32:$addr,
5609 (f64 (IMPLICIT_DEF)), (i32 0)))>;
James Molloy873fd5f2012-02-20 09:24:05 +00005610 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005611 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005612 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005613 (VLD1LNd32 addrmode6oneL32:$addr,
5614 (f64 (IMPLICIT_DEF)), (i32 0)))>;
James Molloy873fd5f2012-02-20 09:24:05 +00005615 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005616 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005617 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005618 (VLD1LNd32 addrmode6oneL32:$addr,
5619 (f64 (IMPLICIT_DEF)), (i32 0)))>;
James Molloy873fd5f2012-02-20 09:24:05 +00005620}
5621
5622// extload, zextload and sextload for a lengthening load which only uses
5623// half the lanes available. Example:
5624// Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
Tim Northover37abe8d2012-04-26 08:46:29 +00005625// Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
5626// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5627// (f64 (IMPLICIT_DEF)), (i32 0))),
James Molloy873fd5f2012-02-20 09:24:05 +00005628// dsub_0)>;
5629multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
5630 string InsnLanes, string InsnTy> {
5631 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005632 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005633 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005634 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
James Molloy873fd5f2012-02-20 09:24:05 +00005635 dsub_0)>;
5636 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005637 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005638 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005639 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
James Molloy873fd5f2012-02-20 09:24:05 +00005640 dsub_0)>;
5641 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005642 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005643 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005644 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
James Molloy873fd5f2012-02-20 09:24:05 +00005645 dsub_0)>;
5646}
5647
5648// extload, zextload and sextload for a lengthening load followed by another
5649// lengthening load, to quadruple the initial length.
James Molloy72aadc02012-04-17 08:18:00 +00005650//
James Molloy873fd5f2012-02-20 09:24:05 +00005651// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
5652// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005653// (EXTRACT_SUBREG (VMOVLuv4i32
Tim Northover37abe8d2012-04-26 08:46:29 +00005654// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5655// (f64 (IMPLICIT_DEF)),
5656// (i32 0))),
James Molloy873fd5f2012-02-20 09:24:05 +00005657// dsub_0)),
Tim Northover37abe8d2012-04-26 08:46:29 +00005658// dsub_0)>;
James Molloy873fd5f2012-02-20 09:24:05 +00005659multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
5660 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
James Molloy72aadc02012-04-17 08:18:00 +00005661 string Insn2Ty> {
5662 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005663 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy72aadc02012-04-17 08:18:00 +00005664 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5665 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005666 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5667 dsub_0))>;
James Molloy72aadc02012-04-17 08:18:00 +00005668 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005669 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy72aadc02012-04-17 08:18:00 +00005670 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5671 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005672 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5673 dsub_0))>;
James Molloy72aadc02012-04-17 08:18:00 +00005674 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005675 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy72aadc02012-04-17 08:18:00 +00005676 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5677 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005678 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5679 dsub_0))>;
James Molloy72aadc02012-04-17 08:18:00 +00005680}
5681
5682// extload, zextload and sextload for a lengthening load followed by another
5683// lengthening load, to quadruple the initial length, but which ends up only
5684// requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
5685//
5686// Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
Tim Northover37abe8d2012-04-26 08:46:29 +00005687// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
5688// (EXTRACT_SUBREG (VMOVLuv4i32
5689// (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
5690// (f64 (IMPLICIT_DEF)), (i32 0))),
5691// dsub_0)),
5692// dsub_0)>;
James Molloy72aadc02012-04-17 08:18:00 +00005693multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
5694 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
5695 string Insn2Ty> {
James Molloy873fd5f2012-02-20 09:24:05 +00005696 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005697 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005698 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5699 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005700 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5701 dsub_0)),
James Molloy72aadc02012-04-17 08:18:00 +00005702 dsub_0)>;
James Molloy873fd5f2012-02-20 09:24:05 +00005703 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005704 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005705 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
5706 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005707 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5708 dsub_0)),
James Molloy72aadc02012-04-17 08:18:00 +00005709 dsub_0)>;
James Molloy873fd5f2012-02-20 09:24:05 +00005710 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
Tim Northover37abe8d2012-04-26 08:46:29 +00005711 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005712 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
5713 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
Tim Northover37abe8d2012-04-26 08:46:29 +00005714 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
5715 dsub_0)),
James Molloy72aadc02012-04-17 08:18:00 +00005716 dsub_0)>;
James Molloy873fd5f2012-02-20 09:24:05 +00005717}
5718
5719defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
5720defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32
5721defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64
5722
5723defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
5724defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
5725defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
5726
James Molloy72aadc02012-04-17 08:18:00 +00005727// Double lengthening - v4i8 -> v4i16 -> v4i32
5728defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
James Molloy873fd5f2012-02-20 09:24:05 +00005729// v2i8 -> v2i16 -> v2i32
James Molloy72aadc02012-04-17 08:18:00 +00005730defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
James Molloy873fd5f2012-02-20 09:24:05 +00005731// v2i16 -> v2i32 -> v2i64
James Molloy72aadc02012-04-17 08:18:00 +00005732defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
James Molloy873fd5f2012-02-20 09:24:05 +00005733
5734// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
Tim Northover37abe8d2012-04-26 08:46:29 +00005735def : Pat<(v2i64 (extloadvi8 addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005736 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
Tim Northover37abe8d2012-04-26 08:46:29 +00005737 (VLD1LNd32 addrmode6oneL32:$addr,
5738 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
5739def : Pat<(v2i64 (zextloadvi8 addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005740 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
Tim Northover37abe8d2012-04-26 08:46:29 +00005741 (VLD1LNd32 addrmode6oneL32:$addr,
5742 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
5743def : Pat<(v2i64 (sextloadvi8 addrmode6oneL32:$addr)),
James Molloy873fd5f2012-02-20 09:24:05 +00005744 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
Tim Northover37abe8d2012-04-26 08:46:29 +00005745 (VLD1LNd32 addrmode6oneL32:$addr,
5746 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
Jim Grosbachef448762011-11-14 23:11:19 +00005747
5748//===----------------------------------------------------------------------===//
5749// Assembler aliases
5750//
Jim Grosbach485d8bf2011-12-13 20:08:32 +00005751
Jim Grosbach21d7fb82011-12-09 23:34:09 +00005752def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5753 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5754def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5755 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5756
Jim Grosbach43329832011-12-09 21:46:04 +00005757// VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
Jim Grosbach78d13e12012-01-24 17:23:29 +00005758defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005759 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005760defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005761 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005762defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
Jim Grosbach43329832011-12-09 21:46:04 +00005763 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005764defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
Jim Grosbach43329832011-12-09 21:46:04 +00005765 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005766defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005767 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005768defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005769 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005770defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005771 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005772defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
Jim Grosbachef448762011-11-14 23:11:19 +00005773 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005774// ... two-operand aliases
Jim Grosbach78d13e12012-01-24 17:23:29 +00005775defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005776 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005777defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005778 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005779defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005780 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005781defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005782 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005783defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005784 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00005785defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
Jim Grosbach9fa0a742011-12-07 23:08:12 +00005786 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
Jim Grosbache052b9a2011-11-14 23:32:59 +00005787
Jim Grosbach872eedb2011-12-02 22:01:52 +00005788// VLD1 single-lane pseudo-instructions. These need special handling for
5789// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbach8b31f952012-01-23 19:39:08 +00005790def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005791 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005792def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005793 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005794def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005795 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach872eedb2011-12-02 22:01:52 +00005796
Jim Grosbach8b31f952012-01-23 19:39:08 +00005797def VLD1LNdWB_fixed_Asm_8 :
5798 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005799 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005800def VLD1LNdWB_fixed_Asm_16 :
5801 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005802 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005803def VLD1LNdWB_fixed_Asm_32 :
5804 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005805 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005806def VLD1LNdWB_register_Asm_8 :
5807 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
Jim Grosbach872eedb2011-12-02 22:01:52 +00005808 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5809 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005810def VLD1LNdWB_register_Asm_16 :
5811 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005812 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
Jim Grosbach872eedb2011-12-02 22:01:52 +00005813 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005814def VLD1LNdWB_register_Asm_32 :
5815 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005816 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
Jim Grosbach872eedb2011-12-02 22:01:52 +00005817 rGPR:$Rm, pred:$p)>;
Jim Grosbach84defb52011-12-02 22:34:51 +00005818
5819
5820// VST1 single-lane pseudo-instructions. These need special handling for
5821// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbach8b31f952012-01-23 19:39:08 +00005822def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005823 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005824def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005825 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005826def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005827 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach84defb52011-12-02 22:34:51 +00005828
Jim Grosbach8b31f952012-01-23 19:39:08 +00005829def VST1LNdWB_fixed_Asm_8 :
5830 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005831 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005832def VST1LNdWB_fixed_Asm_16 :
5833 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005834 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005835def VST1LNdWB_fixed_Asm_32 :
5836 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005837 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005838def VST1LNdWB_register_Asm_8 :
5839 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
Jim Grosbach84defb52011-12-02 22:34:51 +00005840 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5841 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005842def VST1LNdWB_register_Asm_16 :
5843 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005844 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
Jim Grosbach84defb52011-12-02 22:34:51 +00005845 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005846def VST1LNdWB_register_Asm_32 :
5847 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005848 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
Jim Grosbach84defb52011-12-02 22:34:51 +00005849 rGPR:$Rm, pred:$p)>;
Jim Grosbach1ceef1a2011-12-07 01:50:36 +00005850
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005851// VLD2 single-lane pseudo-instructions. These need special handling for
5852// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbach8b31f952012-01-23 19:39:08 +00005853def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005854 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005855def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005856 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005857def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005858 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005859def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005860 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005861def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005862 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005863
Jim Grosbach8b31f952012-01-23 19:39:08 +00005864def VLD2LNdWB_fixed_Asm_8 :
5865 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005866 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005867def VLD2LNdWB_fixed_Asm_16 :
5868 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005869 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005870def VLD2LNdWB_fixed_Asm_32 :
5871 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005872 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005873def VLD2LNqWB_fixed_Asm_16 :
5874 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005875 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005876def VLD2LNqWB_fixed_Asm_32 :
5877 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005878 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005879def VLD2LNdWB_register_Asm_8 :
5880 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005881 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5882 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005883def VLD2LNdWB_register_Asm_16 :
5884 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005885 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005886 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005887def VLD2LNdWB_register_Asm_32 :
5888 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005889 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005890 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005891def VLD2LNqWB_register_Asm_16 :
5892 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005893 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5894 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005895def VLD2LNqWB_register_Asm_32 :
5896 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach95fad1c2011-12-20 19:21:26 +00005897 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5898 rGPR:$Rm, pred:$p)>;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005899
5900
5901// VST2 single-lane pseudo-instructions. These need special handling for
5902// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbach8b31f952012-01-23 19:39:08 +00005903def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005904 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005905def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005906 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005907def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005908 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005909def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
Jim Grosbach5b484312011-12-20 20:46:29 +00005910 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005911def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
Jim Grosbach5b484312011-12-20 20:46:29 +00005912 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005913
Jim Grosbach8b31f952012-01-23 19:39:08 +00005914def VST2LNdWB_fixed_Asm_8 :
5915 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005916 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005917def VST2LNdWB_fixed_Asm_16 :
5918 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005919 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005920def VST2LNdWB_fixed_Asm_32 :
5921 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005922 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005923def VST2LNqWB_fixed_Asm_16 :
5924 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
Jim Grosbach5b484312011-12-20 20:46:29 +00005925 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005926def VST2LNqWB_fixed_Asm_32 :
5927 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
Jim Grosbach5b484312011-12-20 20:46:29 +00005928 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005929def VST2LNdWB_register_Asm_8 :
5930 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005931 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5932 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005933def VST2LNdWB_register_Asm_16 :
5934 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005935 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005936 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005937def VST2LNdWB_register_Asm_32 :
5938 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach799ca9d2011-12-14 23:35:06 +00005939 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005940 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005941def VST2LNqWB_register_Asm_16 :
5942 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
Jim Grosbach5b484312011-12-20 20:46:29 +00005943 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5944 rGPR:$Rm, pred:$p)>;
Jim Grosbach8b31f952012-01-23 19:39:08 +00005945def VST2LNqWB_register_Asm_32 :
5946 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
Jim Grosbach5b484312011-12-20 20:46:29 +00005947 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5948 rGPR:$Rm, pred:$p)>;
Jim Grosbach9b1b3902011-12-14 23:25:46 +00005949
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005950// VLD3 all-lanes pseudo-instructions. These need special handling for
5951// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005952def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005953 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005954def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005955 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005956def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005957 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005958def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005959 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005960def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005961 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00005962def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
Jim Grosbach5e59f7e2012-01-24 23:47:04 +00005963 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5964
5965def VLD3DUPdWB_fixed_Asm_8 :
5966 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
5967 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5968def VLD3DUPdWB_fixed_Asm_16 :
5969 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
5970 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5971def VLD3DUPdWB_fixed_Asm_32 :
5972 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
5973 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
5974def VLD3DUPqWB_fixed_Asm_8 :
5975 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
5976 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5977def VLD3DUPqWB_fixed_Asm_16 :
5978 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
5979 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5980def VLD3DUPqWB_fixed_Asm_32 :
5981 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
5982 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
5983def VLD3DUPdWB_register_Asm_8 :
5984 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
5985 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5986 rGPR:$Rm, pred:$p)>;
5987def VLD3DUPdWB_register_Asm_16 :
5988 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
5989 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5990 rGPR:$Rm, pred:$p)>;
5991def VLD3DUPdWB_register_Asm_32 :
5992 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
5993 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
5994 rGPR:$Rm, pred:$p)>;
5995def VLD3DUPqWB_register_Asm_8 :
5996 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
5997 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
5998 rGPR:$Rm, pred:$p)>;
5999def VLD3DUPqWB_register_Asm_16 :
6000 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6001 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6002 rGPR:$Rm, pred:$p)>;
6003def VLD3DUPqWB_register_Asm_32 :
6004 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6005 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6006 rGPR:$Rm, pred:$p)>;
6007
Jim Grosbach8b31f952012-01-23 19:39:08 +00006008
Jim Grosbach3a678af2012-01-23 21:53:26 +00006009// VLD3 single-lane pseudo-instructions. These need special handling for
6010// the lane index that an InstAlias can't handle, so we use these instead.
6011def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6012 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6013def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6014 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6015def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6016 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6017def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6018 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6019def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6020 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6021
6022def VLD3LNdWB_fixed_Asm_8 :
6023 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6024 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6025def VLD3LNdWB_fixed_Asm_16 :
6026 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6027 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6028def VLD3LNdWB_fixed_Asm_32 :
6029 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6030 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6031def VLD3LNqWB_fixed_Asm_16 :
6032 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6033 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6034def VLD3LNqWB_fixed_Asm_32 :
6035 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6036 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6037def VLD3LNdWB_register_Asm_8 :
6038 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6039 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6040 rGPR:$Rm, pred:$p)>;
6041def VLD3LNdWB_register_Asm_16 :
6042 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6043 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6044 rGPR:$Rm, pred:$p)>;
6045def VLD3LNdWB_register_Asm_32 :
6046 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6047 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6048 rGPR:$Rm, pred:$p)>;
6049def VLD3LNqWB_register_Asm_16 :
6050 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6051 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6052 rGPR:$Rm, pred:$p)>;
6053def VLD3LNqWB_register_Asm_32 :
6054 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6055 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6056 rGPR:$Rm, pred:$p)>;
6057
Jim Grosbach7b426ce2012-01-24 00:12:39 +00006058// VLD3 multiple structure pseudo-instructions. These need special handling for
Jim Grosbachc387fc62012-01-23 23:20:46 +00006059// the vector operands that the normal instructions don't yet model.
6060// FIXME: Remove these when the register classes and instructions are updated.
6061def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6062 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6063def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6064 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6065def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6066 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6067def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6068 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6069def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6070 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6071def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6072 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6073
6074def VLD3dWB_fixed_Asm_8 :
6075 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6076 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6077def VLD3dWB_fixed_Asm_16 :
6078 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6079 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6080def VLD3dWB_fixed_Asm_32 :
6081 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6082 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6083def VLD3qWB_fixed_Asm_8 :
6084 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6085 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6086def VLD3qWB_fixed_Asm_16 :
6087 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6088 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6089def VLD3qWB_fixed_Asm_32 :
6090 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6091 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6092def VLD3dWB_register_Asm_8 :
6093 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6094 (ins VecListThreeD:$list, addrmode6:$addr,
6095 rGPR:$Rm, pred:$p)>;
6096def VLD3dWB_register_Asm_16 :
6097 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6098 (ins VecListThreeD:$list, addrmode6:$addr,
6099 rGPR:$Rm, pred:$p)>;
6100def VLD3dWB_register_Asm_32 :
6101 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6102 (ins VecListThreeD:$list, addrmode6:$addr,
6103 rGPR:$Rm, pred:$p)>;
6104def VLD3qWB_register_Asm_8 :
6105 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6106 (ins VecListThreeQ:$list, addrmode6:$addr,
6107 rGPR:$Rm, pred:$p)>;
6108def VLD3qWB_register_Asm_16 :
6109 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6110 (ins VecListThreeQ:$list, addrmode6:$addr,
6111 rGPR:$Rm, pred:$p)>;
6112def VLD3qWB_register_Asm_32 :
6113 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6114 (ins VecListThreeQ:$list, addrmode6:$addr,
6115 rGPR:$Rm, pred:$p)>;
6116
Jim Grosbach4adb1822012-01-24 00:07:41 +00006117// VST3 single-lane pseudo-instructions. These need special handling for
6118// the lane index that an InstAlias can't handle, so we use these instead.
6119def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6120 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6121def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6122 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6123def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6124 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6125def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6126 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6127def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6128 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6129
6130def VST3LNdWB_fixed_Asm_8 :
6131 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6132 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6133def VST3LNdWB_fixed_Asm_16 :
6134 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6135 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6136def VST3LNdWB_fixed_Asm_32 :
6137 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6138 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6139def VST3LNqWB_fixed_Asm_16 :
6140 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6141 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6142def VST3LNqWB_fixed_Asm_32 :
6143 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6144 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6145def VST3LNdWB_register_Asm_8 :
6146 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6147 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6148 rGPR:$Rm, pred:$p)>;
6149def VST3LNdWB_register_Asm_16 :
6150 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6151 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6152 rGPR:$Rm, pred:$p)>;
6153def VST3LNdWB_register_Asm_32 :
6154 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6155 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6156 rGPR:$Rm, pred:$p)>;
6157def VST3LNqWB_register_Asm_16 :
6158 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6159 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6160 rGPR:$Rm, pred:$p)>;
6161def VST3LNqWB_register_Asm_32 :
6162 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6163 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6164 rGPR:$Rm, pred:$p)>;
6165
6166
Jim Grosbach7b426ce2012-01-24 00:12:39 +00006167// VST3 multiple structure pseudo-instructions. These need special handling for
Jim Grosbachd7433e22012-01-23 23:45:44 +00006168// the vector operands that the normal instructions don't yet model.
6169// FIXME: Remove these when the register classes and instructions are updated.
6170def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6171 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6172def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6173 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6174def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6175 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6176def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6177 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6178def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6179 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6180def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6181 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6182
6183def VST3dWB_fixed_Asm_8 :
6184 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6185 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6186def VST3dWB_fixed_Asm_16 :
6187 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6188 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6189def VST3dWB_fixed_Asm_32 :
6190 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6191 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6192def VST3qWB_fixed_Asm_8 :
6193 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6194 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6195def VST3qWB_fixed_Asm_16 :
6196 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6197 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6198def VST3qWB_fixed_Asm_32 :
6199 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6200 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6201def VST3dWB_register_Asm_8 :
6202 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6203 (ins VecListThreeD:$list, addrmode6:$addr,
6204 rGPR:$Rm, pred:$p)>;
6205def VST3dWB_register_Asm_16 :
6206 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6207 (ins VecListThreeD:$list, addrmode6:$addr,
6208 rGPR:$Rm, pred:$p)>;
6209def VST3dWB_register_Asm_32 :
6210 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6211 (ins VecListThreeD:$list, addrmode6:$addr,
6212 rGPR:$Rm, pred:$p)>;
6213def VST3qWB_register_Asm_8 :
6214 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6215 (ins VecListThreeQ:$list, addrmode6:$addr,
6216 rGPR:$Rm, pred:$p)>;
6217def VST3qWB_register_Asm_16 :
6218 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6219 (ins VecListThreeQ:$list, addrmode6:$addr,
6220 rGPR:$Rm, pred:$p)>;
6221def VST3qWB_register_Asm_32 :
6222 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6223 (ins VecListThreeQ:$list, addrmode6:$addr,
6224 rGPR:$Rm, pred:$p)>;
6225
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006226// VLD4 all-lanes pseudo-instructions. These need special handling for
6227// the lane index that an InstAlias can't handle, so we use these instead.
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006228def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006229 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006230def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006231 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006232def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006233 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006234def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006235 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006236def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006237 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
Jim Grosbachc92ba4e2012-04-23 22:04:10 +00006238def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
Jim Grosbacha57a36a2012-01-25 00:01:08 +00006239 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6240
6241def VLD4DUPdWB_fixed_Asm_8 :
6242 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6243 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6244def VLD4DUPdWB_fixed_Asm_16 :
6245 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6246 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6247def VLD4DUPdWB_fixed_Asm_32 :
6248 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6249 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6250def VLD4DUPqWB_fixed_Asm_8 :
6251 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6252 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6253def VLD4DUPqWB_fixed_Asm_16 :
6254 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6255 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6256def VLD4DUPqWB_fixed_Asm_32 :
6257 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6258 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6259def VLD4DUPdWB_register_Asm_8 :
6260 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6261 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6262 rGPR:$Rm, pred:$p)>;
6263def VLD4DUPdWB_register_Asm_16 :
6264 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6265 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6266 rGPR:$Rm, pred:$p)>;
6267def VLD4DUPdWB_register_Asm_32 :
6268 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6269 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6270 rGPR:$Rm, pred:$p)>;
6271def VLD4DUPqWB_register_Asm_8 :
6272 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6273 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6274 rGPR:$Rm, pred:$p)>;
6275def VLD4DUPqWB_register_Asm_16 :
6276 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6277 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6278 rGPR:$Rm, pred:$p)>;
6279def VLD4DUPqWB_register_Asm_32 :
6280 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6281 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6282 rGPR:$Rm, pred:$p)>;
6283
6284
Jim Grosbache983a132012-01-24 18:37:25 +00006285// VLD4 single-lane pseudo-instructions. These need special handling for
6286// the lane index that an InstAlias can't handle, so we use these instead.
6287def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6288 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6289def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6290 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6291def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6292 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6293def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6294 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6295def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6296 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6297
6298def VLD4LNdWB_fixed_Asm_8 :
6299 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6300 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6301def VLD4LNdWB_fixed_Asm_16 :
6302 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6303 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6304def VLD4LNdWB_fixed_Asm_32 :
6305 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6306 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6307def VLD4LNqWB_fixed_Asm_16 :
6308 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6309 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6310def VLD4LNqWB_fixed_Asm_32 :
6311 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6312 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6313def VLD4LNdWB_register_Asm_8 :
6314 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6315 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6316 rGPR:$Rm, pred:$p)>;
6317def VLD4LNdWB_register_Asm_16 :
6318 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6319 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6320 rGPR:$Rm, pred:$p)>;
6321def VLD4LNdWB_register_Asm_32 :
6322 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6323 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6324 rGPR:$Rm, pred:$p)>;
6325def VLD4LNqWB_register_Asm_16 :
6326 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6327 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6328 rGPR:$Rm, pred:$p)>;
6329def VLD4LNqWB_register_Asm_32 :
6330 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6331 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6332 rGPR:$Rm, pred:$p)>;
6333
Jim Grosbachc387fc62012-01-23 23:20:46 +00006334
6335
Jim Grosbach8abe7e32012-01-24 00:43:17 +00006336// VLD4 multiple structure pseudo-instructions. These need special handling for
6337// the vector operands that the normal instructions don't yet model.
6338// FIXME: Remove these when the register classes and instructions are updated.
6339def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6340 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6341def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6342 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6343def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6344 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6345def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6346 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6347def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6348 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6349def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6350 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6351
6352def VLD4dWB_fixed_Asm_8 :
6353 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6354 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6355def VLD4dWB_fixed_Asm_16 :
6356 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6357 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6358def VLD4dWB_fixed_Asm_32 :
6359 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6360 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6361def VLD4qWB_fixed_Asm_8 :
6362 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6363 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6364def VLD4qWB_fixed_Asm_16 :
6365 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6366 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6367def VLD4qWB_fixed_Asm_32 :
6368 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6369 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6370def VLD4dWB_register_Asm_8 :
6371 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6372 (ins VecListFourD:$list, addrmode6:$addr,
6373 rGPR:$Rm, pred:$p)>;
6374def VLD4dWB_register_Asm_16 :
6375 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6376 (ins VecListFourD:$list, addrmode6:$addr,
6377 rGPR:$Rm, pred:$p)>;
6378def VLD4dWB_register_Asm_32 :
6379 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6380 (ins VecListFourD:$list, addrmode6:$addr,
6381 rGPR:$Rm, pred:$p)>;
6382def VLD4qWB_register_Asm_8 :
6383 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6384 (ins VecListFourQ:$list, addrmode6:$addr,
6385 rGPR:$Rm, pred:$p)>;
6386def VLD4qWB_register_Asm_16 :
6387 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6388 (ins VecListFourQ:$list, addrmode6:$addr,
6389 rGPR:$Rm, pred:$p)>;
6390def VLD4qWB_register_Asm_32 :
6391 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6392 (ins VecListFourQ:$list, addrmode6:$addr,
6393 rGPR:$Rm, pred:$p)>;
6394
Jim Grosbach88a54de2012-01-24 18:53:13 +00006395// VST4 single-lane pseudo-instructions. These need special handling for
6396// the lane index that an InstAlias can't handle, so we use these instead.
6397def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6398 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6399def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6400 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6401def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6402 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6403def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6404 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6405def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6406 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6407
6408def VST4LNdWB_fixed_Asm_8 :
6409 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6410 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6411def VST4LNdWB_fixed_Asm_16 :
6412 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6413 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6414def VST4LNdWB_fixed_Asm_32 :
6415 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6416 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6417def VST4LNqWB_fixed_Asm_16 :
6418 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6419 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6420def VST4LNqWB_fixed_Asm_32 :
6421 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6422 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6423def VST4LNdWB_register_Asm_8 :
6424 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6425 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6426 rGPR:$Rm, pred:$p)>;
6427def VST4LNdWB_register_Asm_16 :
6428 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6429 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6430 rGPR:$Rm, pred:$p)>;
6431def VST4LNdWB_register_Asm_32 :
6432 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6433 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6434 rGPR:$Rm, pred:$p)>;
6435def VST4LNqWB_register_Asm_16 :
6436 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6437 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6438 rGPR:$Rm, pred:$p)>;
6439def VST4LNqWB_register_Asm_32 :
6440 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6441 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6442 rGPR:$Rm, pred:$p)>;
6443
Jim Grosbach539aab72012-01-24 00:58:13 +00006444
6445// VST4 multiple structure pseudo-instructions. These need special handling for
6446// the vector operands that the normal instructions don't yet model.
6447// FIXME: Remove these when the register classes and instructions are updated.
6448def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6449 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6450def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6451 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6452def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6453 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6454def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6455 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6456def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6457 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6458def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6459 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6460
6461def VST4dWB_fixed_Asm_8 :
6462 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6463 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6464def VST4dWB_fixed_Asm_16 :
6465 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6466 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6467def VST4dWB_fixed_Asm_32 :
6468 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6469 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6470def VST4qWB_fixed_Asm_8 :
6471 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6472 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6473def VST4qWB_fixed_Asm_16 :
6474 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6475 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6476def VST4qWB_fixed_Asm_32 :
6477 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6478 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6479def VST4dWB_register_Asm_8 :
6480 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6481 (ins VecListFourD:$list, addrmode6:$addr,
6482 rGPR:$Rm, pred:$p)>;
6483def VST4dWB_register_Asm_16 :
6484 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6485 (ins VecListFourD:$list, addrmode6:$addr,
6486 rGPR:$Rm, pred:$p)>;
6487def VST4dWB_register_Asm_32 :
6488 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6489 (ins VecListFourD:$list, addrmode6:$addr,
6490 rGPR:$Rm, pred:$p)>;
6491def VST4qWB_register_Asm_8 :
6492 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6493 (ins VecListFourQ:$list, addrmode6:$addr,
6494 rGPR:$Rm, pred:$p)>;
6495def VST4qWB_register_Asm_16 :
6496 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6497 (ins VecListFourQ:$list, addrmode6:$addr,
6498 rGPR:$Rm, pred:$p)>;
6499def VST4qWB_register_Asm_32 :
6500 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6501 (ins VecListFourQ:$list, addrmode6:$addr,
6502 rGPR:$Rm, pred:$p)>;
6503
Jim Grosbach1ceef1a2011-12-07 01:50:36 +00006504// VMOV takes an optional datatype suffix
Jim Grosbach78d13e12012-01-24 17:23:29 +00006505defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
Jim Grosbach1ceef1a2011-12-07 01:50:36 +00006506 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00006507defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
Jim Grosbach1ceef1a2011-12-07 01:50:36 +00006508 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6509
Jim Grosbach470855b2011-12-07 17:51:15 +00006510// VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6511// D-register versions.
Jim Grosbacha738da72011-12-15 22:56:33 +00006512def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6513 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6514def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6515 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6516def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6517 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6518def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6519 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6520def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6521 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6522def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6523 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6524def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6525 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6526// Q-register versions.
6527def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6528 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6529def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6530 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6531def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6532 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6533def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6534 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6535def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6536 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6537def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6538 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6539def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6540 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6541
6542// VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6543// D-register versions.
Jim Grosbach470855b2011-12-07 17:51:15 +00006544def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
6545 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6546def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
6547 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6548def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
6549 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6550def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
6551 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6552def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
6553 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6554def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
6555 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6556def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
6557 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6558// Q-register versions.
6559def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
6560 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6561def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
6562 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6563def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
6564 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6565def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
6566 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6567def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
6568 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6569def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
6570 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6571def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
6572 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
Jim Grosbacha44f2c42011-12-08 00:43:47 +00006573
Jim Grosbach5f669fa2011-12-21 23:09:28 +00006574// VSWP allows, but does not require, a type suffix.
Jim Grosbach78d13e12012-01-24 17:23:29 +00006575defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
Jim Grosbach5f669fa2011-12-21 23:09:28 +00006576 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
Jim Grosbach78d13e12012-01-24 17:23:29 +00006577defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
Jim Grosbach5f669fa2011-12-21 23:09:28 +00006578 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6579
Jim Grosbachc94206e2012-02-28 19:11:07 +00006580// VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
6581defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6582 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6583defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6584 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6585defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6586 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6587defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
6588 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6589defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
6590 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6591defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
6592 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6593
Jim Grosbach9b087852011-12-19 23:51:07 +00006594// "vmov Rd, #-imm" can be handled via "vmvn".
6595def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6596 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6597def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6598 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6599def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6600 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6601def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6602 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6603
Jim Grosbach485d8bf2011-12-13 20:08:32 +00006604// 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6605// these should restrict to just the Q register variants, but the register
6606// classes are enough to match correctly regardless, so we keep it simple
6607// and just use MnemonicAlias.
6608def : NEONMnemonicAlias<"vbicq", "vbic">;
6609def : NEONMnemonicAlias<"vandq", "vand">;
6610def : NEONMnemonicAlias<"veorq", "veor">;
6611def : NEONMnemonicAlias<"vorrq", "vorr">;
6612
6613def : NEONMnemonicAlias<"vmovq", "vmov">;
6614def : NEONMnemonicAlias<"vmvnq", "vmvn">;
Jim Grosbachddecfe52011-12-16 00:12:22 +00006615// Explicit versions for floating point so that the FPImm variants get
6616// handled early. The parser gets confused otherwise.
6617def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6618def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
Jim Grosbach485d8bf2011-12-13 20:08:32 +00006619
6620def : NEONMnemonicAlias<"vaddq", "vadd">;
6621def : NEONMnemonicAlias<"vsubq", "vsub">;
6622
6623def : NEONMnemonicAlias<"vminq", "vmin">;
6624def : NEONMnemonicAlias<"vmaxq", "vmax">;
6625
6626def : NEONMnemonicAlias<"vmulq", "vmul">;
6627
6628def : NEONMnemonicAlias<"vabsq", "vabs">;
6629
6630def : NEONMnemonicAlias<"vshlq", "vshl">;
6631def : NEONMnemonicAlias<"vshrq", "vshr">;
6632
6633def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6634
6635def : NEONMnemonicAlias<"vcleq", "vcle">;
6636def : NEONMnemonicAlias<"vceqq", "vceq">;
Jim Grosbach4553fa32011-12-21 23:04:33 +00006637
6638def : NEONMnemonicAlias<"vzipq", "vzip">;
6639def : NEONMnemonicAlias<"vswpq", "vswp">;
Jim Grosbachf7c66fa2011-12-21 23:52:37 +00006640
6641def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6642def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
Jim Grosbach51222d12012-01-20 18:09:51 +00006643
6644
6645// Alias for loading floating point immediates that aren't representable
6646// using the vmov.f32 encoding but the bitpattern is representable using
6647// the .i32 encoding.
6648def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6649 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
6650def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6651 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;