Jia Liu | 31d157a | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===// |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the ARM NEON instruction set. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 14 | |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | // NEON-specific Operands. |
| 17 | //===----------------------------------------------------------------------===// |
Jim Grosbach | 698f3b0 | 2011-10-17 21:00:11 +0000 | [diff] [blame] | 18 | def nModImm : Operand<i32> { |
| 19 | let PrintMethod = "printNEONModImmOperand"; |
| 20 | } |
| 21 | |
Jim Grosbach | 0e387b2 | 2011-10-17 22:26:03 +0000 | [diff] [blame] | 22 | def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; } |
| 23 | def nImmSplatI8 : Operand<i32> { |
| 24 | let PrintMethod = "printNEONModImmOperand"; |
| 25 | let ParserMatchClass = nImmSplatI8AsmOperand; |
| 26 | } |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 27 | def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; } |
| 28 | def nImmSplatI16 : Operand<i32> { |
| 29 | let PrintMethod = "printNEONModImmOperand"; |
| 30 | let ParserMatchClass = nImmSplatI16AsmOperand; |
| 31 | } |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 32 | def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; } |
| 33 | def nImmSplatI32 : Operand<i32> { |
| 34 | let PrintMethod = "printNEONModImmOperand"; |
| 35 | let ParserMatchClass = nImmSplatI32AsmOperand; |
| 36 | } |
| 37 | def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; } |
| 38 | def nImmVMOVI32 : Operand<i32> { |
| 39 | let PrintMethod = "printNEONModImmOperand"; |
| 40 | let ParserMatchClass = nImmVMOVI32AsmOperand; |
| 41 | } |
Jim Grosbach | 9b08785 | 2011-12-19 23:51:07 +0000 | [diff] [blame] | 42 | def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; } |
| 43 | def nImmVMOVI32Neg : Operand<i32> { |
| 44 | let PrintMethod = "printNEONModImmOperand"; |
| 45 | let ParserMatchClass = nImmVMOVI32NegAsmOperand; |
| 46 | } |
Evan Cheng | eaa192a | 2011-11-15 02:12:34 +0000 | [diff] [blame] | 47 | def nImmVMOVF32 : Operand<i32> { |
| 48 | let PrintMethod = "printFPImmOperand"; |
| 49 | let ParserMatchClass = FPImmOperand; |
| 50 | } |
Jim Grosbach | f2f5bc6 | 2011-10-18 16:18:11 +0000 | [diff] [blame] | 51 | def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; } |
| 52 | def nImmSplatI64 : Operand<i32> { |
| 53 | let PrintMethod = "printNEONModImmOperand"; |
| 54 | let ParserMatchClass = nImmSplatI64AsmOperand; |
| 55 | } |
Jim Grosbach | 0e387b2 | 2011-10-17 22:26:03 +0000 | [diff] [blame] | 56 | |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 57 | def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } |
| 58 | def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } |
| 59 | def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; } |
| 60 | def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{ |
| 61 | return ((uint64_t)Imm) < 8; |
| 62 | }]> { |
| 63 | let ParserMatchClass = VectorIndex8Operand; |
| 64 | let PrintMethod = "printVectorIndex"; |
| 65 | let MIOperandInfo = (ops i32imm); |
| 66 | } |
| 67 | def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{ |
| 68 | return ((uint64_t)Imm) < 4; |
| 69 | }]> { |
| 70 | let ParserMatchClass = VectorIndex16Operand; |
| 71 | let PrintMethod = "printVectorIndex"; |
| 72 | let MIOperandInfo = (ops i32imm); |
| 73 | } |
| 74 | def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{ |
| 75 | return ((uint64_t)Imm) < 2; |
| 76 | }]> { |
| 77 | let ParserMatchClass = VectorIndex32Operand; |
| 78 | let PrintMethod = "printVectorIndex"; |
| 79 | let MIOperandInfo = (ops i32imm); |
| 80 | } |
| 81 | |
Jim Grosbach | bd1cff5 | 2011-11-29 23:33:40 +0000 | [diff] [blame] | 82 | // Register list of one D register. |
Jim Grosbach | 862019c | 2011-10-18 23:02:30 +0000 | [diff] [blame] | 83 | def VecListOneDAsmOperand : AsmOperandClass { |
| 84 | let Name = "VecListOneD"; |
| 85 | let ParserMethod = "parseVectorList"; |
Jim Grosbach | 6029b6d | 2011-11-29 23:51:09 +0000 | [diff] [blame] | 86 | let RenderMethod = "addVecListOperands"; |
Jim Grosbach | 862019c | 2011-10-18 23:02:30 +0000 | [diff] [blame] | 87 | } |
| 88 | def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> { |
| 89 | let ParserMatchClass = VecListOneDAsmOperand; |
| 90 | } |
Jim Grosbach | 280dfad | 2011-10-21 18:54:25 +0000 | [diff] [blame] | 91 | // Register list of two sequential D registers. |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 92 | def VecListDPairAsmOperand : AsmOperandClass { |
| 93 | let Name = "VecListDPair"; |
| 94 | let ParserMethod = "parseVectorList"; |
| 95 | let RenderMethod = "addVecListOperands"; |
| 96 | } |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 97 | def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> { |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 98 | let ParserMatchClass = VecListDPairAsmOperand; |
| 99 | } |
Jim Grosbach | cdcfa28 | 2011-10-21 20:02:19 +0000 | [diff] [blame] | 100 | // Register list of three sequential D registers. |
| 101 | def VecListThreeDAsmOperand : AsmOperandClass { |
| 102 | let Name = "VecListThreeD"; |
| 103 | let ParserMethod = "parseVectorList"; |
Jim Grosbach | 6029b6d | 2011-11-29 23:51:09 +0000 | [diff] [blame] | 104 | let RenderMethod = "addVecListOperands"; |
Jim Grosbach | cdcfa28 | 2011-10-21 20:02:19 +0000 | [diff] [blame] | 105 | } |
| 106 | def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> { |
| 107 | let ParserMatchClass = VecListThreeDAsmOperand; |
| 108 | } |
Jim Grosbach | b631031 | 2011-10-21 20:35:01 +0000 | [diff] [blame] | 109 | // Register list of four sequential D registers. |
| 110 | def VecListFourDAsmOperand : AsmOperandClass { |
| 111 | let Name = "VecListFourD"; |
| 112 | let ParserMethod = "parseVectorList"; |
Jim Grosbach | 6029b6d | 2011-11-29 23:51:09 +0000 | [diff] [blame] | 113 | let RenderMethod = "addVecListOperands"; |
Jim Grosbach | b631031 | 2011-10-21 20:35:01 +0000 | [diff] [blame] | 114 | } |
| 115 | def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> { |
| 116 | let ParserMatchClass = VecListFourDAsmOperand; |
| 117 | } |
Jim Grosbach | 4661d4c | 2011-10-21 22:21:10 +0000 | [diff] [blame] | 118 | // Register list of two D registers spaced by 2 (two sequential Q registers). |
Jim Grosbach | c3384c9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 119 | def VecListDPairSpacedAsmOperand : AsmOperandClass { |
| 120 | let Name = "VecListDPairSpaced"; |
Jim Grosbach | 4661d4c | 2011-10-21 22:21:10 +0000 | [diff] [blame] | 121 | let ParserMethod = "parseVectorList"; |
Jim Grosbach | 6029b6d | 2011-11-29 23:51:09 +0000 | [diff] [blame] | 122 | let RenderMethod = "addVecListOperands"; |
Jim Grosbach | 4661d4c | 2011-10-21 22:21:10 +0000 | [diff] [blame] | 123 | } |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 124 | def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> { |
Jim Grosbach | c3384c9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 125 | let ParserMatchClass = VecListDPairSpacedAsmOperand; |
Jim Grosbach | 4661d4c | 2011-10-21 22:21:10 +0000 | [diff] [blame] | 126 | } |
Jim Grosbach | c387fc6 | 2012-01-23 23:20:46 +0000 | [diff] [blame] | 127 | // Register list of three D registers spaced by 2 (three Q registers). |
| 128 | def VecListThreeQAsmOperand : AsmOperandClass { |
| 129 | let Name = "VecListThreeQ"; |
| 130 | let ParserMethod = "parseVectorList"; |
| 131 | let RenderMethod = "addVecListOperands"; |
| 132 | } |
| 133 | def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> { |
| 134 | let ParserMatchClass = VecListThreeQAsmOperand; |
| 135 | } |
Jim Grosbach | 8abe7e3 | 2012-01-24 00:43:17 +0000 | [diff] [blame] | 136 | // Register list of three D registers spaced by 2 (three Q registers). |
| 137 | def VecListFourQAsmOperand : AsmOperandClass { |
| 138 | let Name = "VecListFourQ"; |
| 139 | let ParserMethod = "parseVectorList"; |
| 140 | let RenderMethod = "addVecListOperands"; |
| 141 | } |
| 142 | def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> { |
| 143 | let ParserMatchClass = VecListFourQAsmOperand; |
| 144 | } |
Jim Grosbach | 862019c | 2011-10-18 23:02:30 +0000 | [diff] [blame] | 145 | |
Jim Grosbach | 98b05a5 | 2011-11-30 01:09:44 +0000 | [diff] [blame] | 146 | // Register list of one D register, with "all lanes" subscripting. |
| 147 | def VecListOneDAllLanesAsmOperand : AsmOperandClass { |
| 148 | let Name = "VecListOneDAllLanes"; |
| 149 | let ParserMethod = "parseVectorList"; |
| 150 | let RenderMethod = "addVecListOperands"; |
| 151 | } |
| 152 | def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> { |
| 153 | let ParserMatchClass = VecListOneDAllLanesAsmOperand; |
| 154 | } |
Jim Grosbach | 13af222 | 2011-11-30 18:21:25 +0000 | [diff] [blame] | 155 | // Register list of two D registers, with "all lanes" subscripting. |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 156 | def VecListDPairAllLanesAsmOperand : AsmOperandClass { |
| 157 | let Name = "VecListDPairAllLanes"; |
Jim Grosbach | 13af222 | 2011-11-30 18:21:25 +0000 | [diff] [blame] | 158 | let ParserMethod = "parseVectorList"; |
| 159 | let RenderMethod = "addVecListOperands"; |
| 160 | } |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 161 | def VecListDPairAllLanes : RegisterOperand<DPair, |
| 162 | "printVectorListTwoAllLanes"> { |
| 163 | let ParserMatchClass = VecListDPairAllLanesAsmOperand; |
Jim Grosbach | 13af222 | 2011-11-30 18:21:25 +0000 | [diff] [blame] | 164 | } |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 165 | // Register list of two D registers spaced by 2 (two sequential Q registers). |
Jim Grosbach | 4d0983a | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 166 | def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass { |
| 167 | let Name = "VecListDPairSpacedAllLanes"; |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 168 | let ParserMethod = "parseVectorList"; |
| 169 | let RenderMethod = "addVecListOperands"; |
| 170 | } |
Jim Grosbach | 4d0983a | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 171 | def VecListDPairSpacedAllLanes : RegisterOperand<DPair, |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 172 | "printVectorListTwoSpacedAllLanes"> { |
Jim Grosbach | 4d0983a | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 173 | let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand; |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 174 | } |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 175 | // Register list of three D registers, with "all lanes" subscripting. |
| 176 | def VecListThreeDAllLanesAsmOperand : AsmOperandClass { |
| 177 | let Name = "VecListThreeDAllLanes"; |
| 178 | let ParserMethod = "parseVectorList"; |
| 179 | let RenderMethod = "addVecListOperands"; |
| 180 | } |
| 181 | def VecListThreeDAllLanes : RegisterOperand<DPR, |
| 182 | "printVectorListThreeAllLanes"> { |
| 183 | let ParserMatchClass = VecListThreeDAllLanesAsmOperand; |
| 184 | } |
| 185 | // Register list of three D registers spaced by 2 (three sequential Q regs). |
| 186 | def VecListThreeQAllLanesAsmOperand : AsmOperandClass { |
| 187 | let Name = "VecListThreeQAllLanes"; |
| 188 | let ParserMethod = "parseVectorList"; |
| 189 | let RenderMethod = "addVecListOperands"; |
| 190 | } |
| 191 | def VecListThreeQAllLanes : RegisterOperand<DPR, |
| 192 | "printVectorListThreeSpacedAllLanes"> { |
| 193 | let ParserMatchClass = VecListThreeQAllLanesAsmOperand; |
| 194 | } |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 195 | // Register list of four D registers, with "all lanes" subscripting. |
| 196 | def VecListFourDAllLanesAsmOperand : AsmOperandClass { |
| 197 | let Name = "VecListFourDAllLanes"; |
| 198 | let ParserMethod = "parseVectorList"; |
| 199 | let RenderMethod = "addVecListOperands"; |
| 200 | } |
| 201 | def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> { |
| 202 | let ParserMatchClass = VecListFourDAllLanesAsmOperand; |
| 203 | } |
| 204 | // Register list of four D registers spaced by 2 (four sequential Q regs). |
| 205 | def VecListFourQAllLanesAsmOperand : AsmOperandClass { |
| 206 | let Name = "VecListFourQAllLanes"; |
| 207 | let ParserMethod = "parseVectorList"; |
| 208 | let RenderMethod = "addVecListOperands"; |
| 209 | } |
| 210 | def VecListFourQAllLanes : RegisterOperand<DPR, |
| 211 | "printVectorListFourSpacedAllLanes"> { |
| 212 | let ParserMatchClass = VecListFourQAllLanesAsmOperand; |
| 213 | } |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 214 | |
Jim Grosbach | 98b05a5 | 2011-11-30 01:09:44 +0000 | [diff] [blame] | 215 | |
Jim Grosbach | 7636bf6 | 2011-12-02 00:35:16 +0000 | [diff] [blame] | 216 | // Register list of one D register, with byte lane subscripting. |
| 217 | def VecListOneDByteIndexAsmOperand : AsmOperandClass { |
| 218 | let Name = "VecListOneDByteIndexed"; |
| 219 | let ParserMethod = "parseVectorList"; |
| 220 | let RenderMethod = "addVecListIndexedOperands"; |
| 221 | } |
| 222 | def VecListOneDByteIndexed : Operand<i32> { |
| 223 | let ParserMatchClass = VecListOneDByteIndexAsmOperand; |
| 224 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 225 | } |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 226 | // ...with half-word lane subscripting. |
| 227 | def VecListOneDHWordIndexAsmOperand : AsmOperandClass { |
| 228 | let Name = "VecListOneDHWordIndexed"; |
| 229 | let ParserMethod = "parseVectorList"; |
| 230 | let RenderMethod = "addVecListIndexedOperands"; |
| 231 | } |
| 232 | def VecListOneDHWordIndexed : Operand<i32> { |
| 233 | let ParserMatchClass = VecListOneDHWordIndexAsmOperand; |
| 234 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 235 | } |
| 236 | // ...with word lane subscripting. |
| 237 | def VecListOneDWordIndexAsmOperand : AsmOperandClass { |
| 238 | let Name = "VecListOneDWordIndexed"; |
| 239 | let ParserMethod = "parseVectorList"; |
| 240 | let RenderMethod = "addVecListIndexedOperands"; |
| 241 | } |
| 242 | def VecListOneDWordIndexed : Operand<i32> { |
| 243 | let ParserMatchClass = VecListOneDWordIndexAsmOperand; |
| 244 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 245 | } |
Jim Grosbach | 3a678af | 2012-01-23 21:53:26 +0000 | [diff] [blame] | 246 | |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 247 | // Register list of two D registers with byte lane subscripting. |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 248 | def VecListTwoDByteIndexAsmOperand : AsmOperandClass { |
| 249 | let Name = "VecListTwoDByteIndexed"; |
| 250 | let ParserMethod = "parseVectorList"; |
| 251 | let RenderMethod = "addVecListIndexedOperands"; |
| 252 | } |
| 253 | def VecListTwoDByteIndexed : Operand<i32> { |
| 254 | let ParserMatchClass = VecListTwoDByteIndexAsmOperand; |
| 255 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 256 | } |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 257 | // ...with half-word lane subscripting. |
| 258 | def VecListTwoDHWordIndexAsmOperand : AsmOperandClass { |
| 259 | let Name = "VecListTwoDHWordIndexed"; |
| 260 | let ParserMethod = "parseVectorList"; |
| 261 | let RenderMethod = "addVecListIndexedOperands"; |
| 262 | } |
| 263 | def VecListTwoDHWordIndexed : Operand<i32> { |
| 264 | let ParserMatchClass = VecListTwoDHWordIndexAsmOperand; |
| 265 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 266 | } |
| 267 | // ...with word lane subscripting. |
| 268 | def VecListTwoDWordIndexAsmOperand : AsmOperandClass { |
| 269 | let Name = "VecListTwoDWordIndexed"; |
| 270 | let ParserMethod = "parseVectorList"; |
| 271 | let RenderMethod = "addVecListIndexedOperands"; |
| 272 | } |
| 273 | def VecListTwoDWordIndexed : Operand<i32> { |
| 274 | let ParserMatchClass = VecListTwoDWordIndexAsmOperand; |
| 275 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 276 | } |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 277 | // Register list of two Q registers with half-word lane subscripting. |
| 278 | def VecListTwoQHWordIndexAsmOperand : AsmOperandClass { |
| 279 | let Name = "VecListTwoQHWordIndexed"; |
| 280 | let ParserMethod = "parseVectorList"; |
| 281 | let RenderMethod = "addVecListIndexedOperands"; |
| 282 | } |
| 283 | def VecListTwoQHWordIndexed : Operand<i32> { |
| 284 | let ParserMatchClass = VecListTwoQHWordIndexAsmOperand; |
| 285 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 286 | } |
| 287 | // ...with word lane subscripting. |
| 288 | def VecListTwoQWordIndexAsmOperand : AsmOperandClass { |
| 289 | let Name = "VecListTwoQWordIndexed"; |
| 290 | let ParserMethod = "parseVectorList"; |
| 291 | let RenderMethod = "addVecListIndexedOperands"; |
| 292 | } |
| 293 | def VecListTwoQWordIndexed : Operand<i32> { |
| 294 | let ParserMatchClass = VecListTwoQWordIndexAsmOperand; |
| 295 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 296 | } |
Jim Grosbach | 7636bf6 | 2011-12-02 00:35:16 +0000 | [diff] [blame] | 297 | |
Jim Grosbach | 3a678af | 2012-01-23 21:53:26 +0000 | [diff] [blame] | 298 | |
| 299 | // Register list of three D registers with byte lane subscripting. |
| 300 | def VecListThreeDByteIndexAsmOperand : AsmOperandClass { |
| 301 | let Name = "VecListThreeDByteIndexed"; |
| 302 | let ParserMethod = "parseVectorList"; |
| 303 | let RenderMethod = "addVecListIndexedOperands"; |
| 304 | } |
| 305 | def VecListThreeDByteIndexed : Operand<i32> { |
| 306 | let ParserMatchClass = VecListThreeDByteIndexAsmOperand; |
| 307 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 308 | } |
| 309 | // ...with half-word lane subscripting. |
| 310 | def VecListThreeDHWordIndexAsmOperand : AsmOperandClass { |
| 311 | let Name = "VecListThreeDHWordIndexed"; |
| 312 | let ParserMethod = "parseVectorList"; |
| 313 | let RenderMethod = "addVecListIndexedOperands"; |
| 314 | } |
| 315 | def VecListThreeDHWordIndexed : Operand<i32> { |
| 316 | let ParserMatchClass = VecListThreeDHWordIndexAsmOperand; |
| 317 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 318 | } |
| 319 | // ...with word lane subscripting. |
| 320 | def VecListThreeDWordIndexAsmOperand : AsmOperandClass { |
| 321 | let Name = "VecListThreeDWordIndexed"; |
| 322 | let ParserMethod = "parseVectorList"; |
| 323 | let RenderMethod = "addVecListIndexedOperands"; |
| 324 | } |
| 325 | def VecListThreeDWordIndexed : Operand<i32> { |
| 326 | let ParserMatchClass = VecListThreeDWordIndexAsmOperand; |
| 327 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 328 | } |
| 329 | // Register list of three Q registers with half-word lane subscripting. |
| 330 | def VecListThreeQHWordIndexAsmOperand : AsmOperandClass { |
| 331 | let Name = "VecListThreeQHWordIndexed"; |
| 332 | let ParserMethod = "parseVectorList"; |
| 333 | let RenderMethod = "addVecListIndexedOperands"; |
| 334 | } |
| 335 | def VecListThreeQHWordIndexed : Operand<i32> { |
| 336 | let ParserMatchClass = VecListThreeQHWordIndexAsmOperand; |
| 337 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 338 | } |
| 339 | // ...with word lane subscripting. |
| 340 | def VecListThreeQWordIndexAsmOperand : AsmOperandClass { |
| 341 | let Name = "VecListThreeQWordIndexed"; |
| 342 | let ParserMethod = "parseVectorList"; |
| 343 | let RenderMethod = "addVecListIndexedOperands"; |
| 344 | } |
| 345 | def VecListThreeQWordIndexed : Operand<i32> { |
| 346 | let ParserMatchClass = VecListThreeQWordIndexAsmOperand; |
| 347 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 348 | } |
| 349 | |
Jim Grosbach | e983a13 | 2012-01-24 18:37:25 +0000 | [diff] [blame] | 350 | // Register list of four D registers with byte lane subscripting. |
| 351 | def VecListFourDByteIndexAsmOperand : AsmOperandClass { |
| 352 | let Name = "VecListFourDByteIndexed"; |
| 353 | let ParserMethod = "parseVectorList"; |
| 354 | let RenderMethod = "addVecListIndexedOperands"; |
| 355 | } |
| 356 | def VecListFourDByteIndexed : Operand<i32> { |
| 357 | let ParserMatchClass = VecListFourDByteIndexAsmOperand; |
| 358 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 359 | } |
| 360 | // ...with half-word lane subscripting. |
| 361 | def VecListFourDHWordIndexAsmOperand : AsmOperandClass { |
| 362 | let Name = "VecListFourDHWordIndexed"; |
| 363 | let ParserMethod = "parseVectorList"; |
| 364 | let RenderMethod = "addVecListIndexedOperands"; |
| 365 | } |
| 366 | def VecListFourDHWordIndexed : Operand<i32> { |
| 367 | let ParserMatchClass = VecListFourDHWordIndexAsmOperand; |
| 368 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 369 | } |
| 370 | // ...with word lane subscripting. |
| 371 | def VecListFourDWordIndexAsmOperand : AsmOperandClass { |
| 372 | let Name = "VecListFourDWordIndexed"; |
| 373 | let ParserMethod = "parseVectorList"; |
| 374 | let RenderMethod = "addVecListIndexedOperands"; |
| 375 | } |
| 376 | def VecListFourDWordIndexed : Operand<i32> { |
| 377 | let ParserMatchClass = VecListFourDWordIndexAsmOperand; |
| 378 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 379 | } |
| 380 | // Register list of four Q registers with half-word lane subscripting. |
| 381 | def VecListFourQHWordIndexAsmOperand : AsmOperandClass { |
| 382 | let Name = "VecListFourQHWordIndexed"; |
| 383 | let ParserMethod = "parseVectorList"; |
| 384 | let RenderMethod = "addVecListIndexedOperands"; |
| 385 | } |
| 386 | def VecListFourQHWordIndexed : Operand<i32> { |
| 387 | let ParserMatchClass = VecListFourQHWordIndexAsmOperand; |
| 388 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 389 | } |
| 390 | // ...with word lane subscripting. |
| 391 | def VecListFourQWordIndexAsmOperand : AsmOperandClass { |
| 392 | let Name = "VecListFourQWordIndexed"; |
| 393 | let ParserMethod = "parseVectorList"; |
| 394 | let RenderMethod = "addVecListIndexedOperands"; |
| 395 | } |
| 396 | def VecListFourQWordIndexed : Operand<i32> { |
| 397 | let ParserMatchClass = VecListFourQWordIndexAsmOperand; |
| 398 | let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); |
| 399 | } |
| 400 | |
Jim Grosbach | 3a678af | 2012-01-23 21:53:26 +0000 | [diff] [blame] | 401 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 402 | //===----------------------------------------------------------------------===// |
| 403 | // NEON-specific DAG Nodes. |
| 404 | //===----------------------------------------------------------------------===// |
| 405 | |
| 406 | def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 407 | def SDTARMVCMPZ : SDTypeProfile<1, 1, []>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 408 | |
| 409 | def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 410 | def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 411 | def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 412 | def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>; |
| 413 | def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 414 | def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; |
| 415 | def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 416 | def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>; |
| 417 | def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 418 | def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; |
| 419 | def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; |
| 420 | |
| 421 | // Types for vector shift by immediates. The "SHX" version is for long and |
| 422 | // narrow operations where the source and destination vectors have different |
| 423 | // types. The "SHINS" version is for shift and insert operations. |
| 424 | def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, |
| 425 | SDTCisVT<2, i32>]>; |
| 426 | def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, |
| 427 | SDTCisVT<2, i32>]>; |
| 428 | def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, |
| 429 | SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; |
| 430 | |
| 431 | def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; |
| 432 | def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; |
| 433 | def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; |
| 434 | def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; |
| 435 | def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; |
| 436 | def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; |
| 437 | def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; |
| 438 | |
| 439 | def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; |
| 440 | def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; |
| 441 | def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; |
| 442 | |
| 443 | def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; |
| 444 | def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; |
| 445 | def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; |
| 446 | def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; |
| 447 | def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; |
| 448 | def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; |
| 449 | |
| 450 | def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; |
| 451 | def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; |
| 452 | def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; |
| 453 | |
| 454 | def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; |
| 455 | def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; |
| 456 | |
| 457 | def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, |
| 458 | SDTCisVT<2, i32>]>; |
| 459 | def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; |
| 460 | def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; |
| 461 | |
Bob Wilson | 7e3f0d2 | 2010-07-14 06:31:50 +0000 | [diff] [blame] | 462 | def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; |
| 463 | def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; |
| 464 | def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; |
Evan Cheng | eaa192a | 2011-11-15 02:12:34 +0000 | [diff] [blame] | 465 | def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; |
Bob Wilson | 7e3f0d2 | 2010-07-14 06:31:50 +0000 | [diff] [blame] | 466 | |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 467 | def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, |
| 468 | SDTCisVT<2, i32>]>; |
| 469 | def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 470 | def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 471 | |
Cameron Zwarich | c0e6d78 | 2011-03-30 23:01:21 +0000 | [diff] [blame] | 472 | def NEONvbsl : SDNode<"ARMISD::VBSL", |
| 473 | SDTypeProfile<1, 3, [SDTCisVec<0>, |
| 474 | SDTCisSameAs<0, 1>, |
| 475 | SDTCisSameAs<0, 2>, |
| 476 | SDTCisSameAs<0, 3>]>>; |
| 477 | |
Bob Wilson | c1d287b | 2009-08-14 05:13:08 +0000 | [diff] [blame] | 478 | def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; |
| 479 | |
Bob Wilson | 0ce3710 | 2009-08-14 05:08:32 +0000 | [diff] [blame] | 480 | // VDUPLANE can produce a quad-register result from a double-register source, |
| 481 | // so the result is not constrained to match the source. |
| 482 | def NEONvduplane : SDNode<"ARMISD::VDUPLANE", |
| 483 | SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, |
| 484 | SDTCisVT<2, i32>]>>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 485 | |
Bob Wilson | de95c1b8 | 2009-08-19 17:03:43 +0000 | [diff] [blame] | 486 | def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, |
| 487 | SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; |
| 488 | def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>; |
| 489 | |
Bob Wilson | d8e1757 | 2009-08-12 22:31:50 +0000 | [diff] [blame] | 490 | def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; |
| 491 | def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; |
| 492 | def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; |
| 493 | def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; |
| 494 | |
Anton Korobeynikov | 62e84f1 | 2009-08-21 12:40:50 +0000 | [diff] [blame] | 495 | def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 496 | SDTCisSameAs<0, 2>, |
| 497 | SDTCisSameAs<0, 3>]>; |
Anton Korobeynikov | 051cfd6 | 2009-08-21 12:41:42 +0000 | [diff] [blame] | 498 | def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; |
| 499 | def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; |
| 500 | def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; |
Anton Korobeynikov | 62e84f1 | 2009-08-21 12:40:50 +0000 | [diff] [blame] | 501 | |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 502 | def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, |
| 503 | SDTCisSameAs<1, 2>]>; |
| 504 | def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; |
| 505 | def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; |
| 506 | |
Bob Wilson | 9f6c4c1 | 2010-02-18 06:05:53 +0000 | [diff] [blame] | 507 | def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>, |
| 508 | SDTCisSameAs<0, 2>]>; |
| 509 | def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>; |
| 510 | def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>; |
| 511 | |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 512 | def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{ |
| 513 | ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); |
Daniel Dunbar | 425f634 | 2010-07-31 21:08:54 +0000 | [diff] [blame] | 514 | unsigned EltBits = 0; |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 515 | uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); |
| 516 | return (EltBits == 32 && EltVal == 0); |
| 517 | }]>; |
| 518 | |
| 519 | def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{ |
| 520 | ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); |
Daniel Dunbar | 425f634 | 2010-07-31 21:08:54 +0000 | [diff] [blame] | 521 | unsigned EltBits = 0; |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 522 | uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); |
| 523 | return (EltBits == 8 && EltVal == 0xff); |
| 524 | }]>; |
| 525 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 526 | //===----------------------------------------------------------------------===// |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 527 | // NEON load / store instructions |
| 528 | //===----------------------------------------------------------------------===// |
| 529 | |
Bob Wilson | 9d4ebc0 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 530 | // Use VLDM to load a Q register as a D register pair. |
| 531 | // This is a pseudo instruction that is expanded to VLDMD after reg alloc. |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 532 | def VLDMQIA |
Jakob Stoklund Olesen | 5b2f913 | 2012-03-28 21:20:32 +0000 | [diff] [blame] | 533 | : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn), |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 534 | IIC_fpLoad_m, "", |
Jakob Stoklund Olesen | 5b2f913 | 2012-03-28 21:20:32 +0000 | [diff] [blame] | 535 | [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>; |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 536 | |
Bob Wilson | 9d4ebc0 | 2010-09-16 00:31:02 +0000 | [diff] [blame] | 537 | // Use VSTM to store a Q register as a D register pair. |
| 538 | // This is a pseudo instruction that is expanded to VSTMD after reg alloc. |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 539 | def VSTMQIA |
Jakob Stoklund Olesen | 5b2f913 | 2012-03-28 21:20:32 +0000 | [diff] [blame] | 540 | : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn), |
Bill Wendling | 73fe34a | 2010-11-16 01:16:36 +0000 | [diff] [blame] | 541 | IIC_fpStore_m, "", |
Jakob Stoklund Olesen | 5b2f913 | 2012-03-28 21:20:32 +0000 | [diff] [blame] | 542 | [(store (v2f64 DPair:$src), GPR:$Rn)]>; |
Evan Cheng | 69b9f98 | 2010-05-13 01:12:06 +0000 | [diff] [blame] | 543 | |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 544 | // Classes for VLD* pseudo-instructions with multi-register operands. |
| 545 | // These are expanded to real instructions after register allocation. |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 546 | class VLDQPseudo<InstrItinClass itin> |
| 547 | : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">; |
| 548 | class VLDQWBPseudo<InstrItinClass itin> |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 549 | : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 550 | (ins addrmode6:$addr, am6offset:$offset), itin, |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 551 | "$addr.addr = $wb">; |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 552 | class VLDQWBfixedPseudo<InstrItinClass itin> |
| 553 | : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), |
| 554 | (ins addrmode6:$addr), itin, |
| 555 | "$addr.addr = $wb">; |
| 556 | class VLDQWBregisterPseudo<InstrItinClass itin> |
| 557 | : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), |
| 558 | (ins addrmode6:$addr, rGPR:$offset), itin, |
| 559 | "$addr.addr = $wb">; |
Jim Grosbach | a4e3c7f | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 560 | |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 561 | class VLDQQPseudo<InstrItinClass itin> |
| 562 | : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">; |
| 563 | class VLDQQWBPseudo<InstrItinClass itin> |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 564 | : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 565 | (ins addrmode6:$addr, am6offset:$offset), itin, |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 566 | "$addr.addr = $wb">; |
Jim Grosbach | a4e3c7f | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 567 | class VLDQQWBfixedPseudo<InstrItinClass itin> |
| 568 | : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), |
| 569 | (ins addrmode6:$addr), itin, |
| 570 | "$addr.addr = $wb">; |
| 571 | class VLDQQWBregisterPseudo<InstrItinClass itin> |
| 572 | : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), |
| 573 | (ins addrmode6:$addr, rGPR:$offset), itin, |
| 574 | "$addr.addr = $wb">; |
| 575 | |
| 576 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 577 | class VLDQQQQPseudo<InstrItinClass itin> |
Bob Wilson | 9a45008 | 2011-08-05 07:24:09 +0000 | [diff] [blame] | 578 | : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin, |
| 579 | "$src = $dst">; |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 580 | class VLDQQQQWBPseudo<InstrItinClass itin> |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 581 | : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 582 | (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 583 | "$addr.addr = $wb, $src = $dst">; |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 584 | |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 585 | let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { |
| 586 | |
Bob Wilson | 205a5ca | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 587 | // VLD1 : Vector Load (multiple single elements) |
Bob Wilson | 621f195 | 2010-03-23 05:25:43 +0000 | [diff] [blame] | 588 | class VLD1D<bits<4> op7_4, string Dt> |
Jim Grosbach | 6b09c77 | 2011-10-20 15:04:25 +0000 | [diff] [blame] | 589 | : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 590 | (ins addrmode6:$Rn), IIC_VLD1, |
Jim Grosbach | 6b09c77 | 2011-10-20 15:04:25 +0000 | [diff] [blame] | 591 | "vld1", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 592 | let Rm = 0b1111; |
| 593 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 594 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | d9aa7d3 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 595 | } |
Bob Wilson | 621f195 | 2010-03-23 05:25:43 +0000 | [diff] [blame] | 596 | class VLD1Q<bits<4> op7_4, string Dt> |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 597 | : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 598 | (ins addrmode6:$Rn), IIC_VLD1x2, |
Jim Grosbach | 280dfad | 2011-10-21 18:54:25 +0000 | [diff] [blame] | 599 | "vld1", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 600 | let Rm = 0b1111; |
| 601 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 602 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | d9aa7d3 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 603 | } |
Bob Wilson | 205a5ca | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 604 | |
Owen Anderson | d9aa7d3 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 605 | def VLD1d8 : VLD1D<{0,0,0,?}, "8">; |
| 606 | def VLD1d16 : VLD1D<{0,1,0,?}, "16">; |
| 607 | def VLD1d32 : VLD1D<{1,0,0,?}, "32">; |
| 608 | def VLD1d64 : VLD1D<{1,1,0,?}, "64">; |
Bob Wilson | 205a5ca | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 609 | |
Owen Anderson | d9aa7d3 | 2010-11-02 00:05:05 +0000 | [diff] [blame] | 610 | def VLD1q8 : VLD1Q<{0,0,?,?}, "8">; |
| 611 | def VLD1q16 : VLD1Q<{0,1,?,?}, "16">; |
| 612 | def VLD1q32 : VLD1Q<{1,0,?,?}, "32">; |
| 613 | def VLD1q64 : VLD1Q<{1,1,?,?}, "64">; |
Bob Wilson | 99493b2 | 2010-03-20 17:59:03 +0000 | [diff] [blame] | 614 | |
| 615 | // ...with address register writeback: |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 616 | multiclass VLD1DWB<bits<4> op7_4, string Dt> { |
| 617 | def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), |
| 618 | (ins addrmode6:$Rn), IIC_VLD1u, |
| 619 | "vld1", Dt, "$Vd, $Rn!", |
| 620 | "$Rn.addr = $wb", []> { |
| 621 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 622 | let Inst{4} = Rn{4}; |
| 623 | let DecoderMethod = "DecodeVLDInstruction"; |
Jim Grosbach | 1243132 | 2011-10-24 22:16:58 +0000 | [diff] [blame] | 624 | let AsmMatchConverter = "cvtVLDwbFixed"; |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 625 | } |
| 626 | def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), |
| 627 | (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u, |
| 628 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 629 | "$Rn.addr = $wb", []> { |
| 630 | let Inst{4} = Rn{4}; |
| 631 | let DecoderMethod = "DecodeVLDInstruction"; |
Jim Grosbach | 1243132 | 2011-10-24 22:16:58 +0000 | [diff] [blame] | 632 | let AsmMatchConverter = "cvtVLDwbRegister"; |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 633 | } |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 634 | } |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 635 | multiclass VLD1QWB<bits<4> op7_4, string Dt> { |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 636 | def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb), |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 637 | (ins addrmode6:$Rn), IIC_VLD1x2u, |
| 638 | "vld1", Dt, "$Vd, $Rn!", |
| 639 | "$Rn.addr = $wb", []> { |
| 640 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 641 | let Inst{5-4} = Rn{5-4}; |
| 642 | let DecoderMethod = "DecodeVLDInstruction"; |
Jim Grosbach | 1243132 | 2011-10-24 22:16:58 +0000 | [diff] [blame] | 643 | let AsmMatchConverter = "cvtVLDwbFixed"; |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 644 | } |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 645 | def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb), |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 646 | (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, |
| 647 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 648 | "$Rn.addr = $wb", []> { |
| 649 | let Inst{5-4} = Rn{5-4}; |
| 650 | let DecoderMethod = "DecodeVLDInstruction"; |
Jim Grosbach | 1243132 | 2011-10-24 22:16:58 +0000 | [diff] [blame] | 651 | let AsmMatchConverter = "cvtVLDwbRegister"; |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 652 | } |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 653 | } |
Bob Wilson | 99493b2 | 2010-03-20 17:59:03 +0000 | [diff] [blame] | 654 | |
Jim Grosbach | 10b90a9 | 2011-10-24 21:45:13 +0000 | [diff] [blame] | 655 | defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">; |
| 656 | defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">; |
| 657 | defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">; |
| 658 | defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">; |
| 659 | defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">; |
| 660 | defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">; |
| 661 | defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">; |
| 662 | defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">; |
Bob Wilson | 99493b2 | 2010-03-20 17:59:03 +0000 | [diff] [blame] | 663 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 664 | // ...with 3 registers |
Bob Wilson | 9580832 | 2010-03-18 20:18:39 +0000 | [diff] [blame] | 665 | class VLD1D3<bits<4> op7_4, string Dt> |
Jim Grosbach | cdcfa28 | 2011-10-21 20:02:19 +0000 | [diff] [blame] | 666 | : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 667 | (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt, |
Jim Grosbach | cdcfa28 | 2011-10-21 20:02:19 +0000 | [diff] [blame] | 668 | "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 669 | let Rm = 0b1111; |
| 670 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 671 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 672 | } |
Jim Grosbach | 5921675 | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 673 | multiclass VLD1D3WB<bits<4> op7_4, string Dt> { |
| 674 | def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb), |
| 675 | (ins addrmode6:$Rn), IIC_VLD1x2u, |
| 676 | "vld1", Dt, "$Vd, $Rn!", |
| 677 | "$Rn.addr = $wb", []> { |
| 678 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
Owen Anderson | b3727fe | 2011-10-28 20:43:24 +0000 | [diff] [blame] | 679 | let Inst{4} = Rn{4}; |
Jim Grosbach | 5921675 | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 680 | let DecoderMethod = "DecodeVLDInstruction"; |
| 681 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 682 | } |
| 683 | def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb), |
| 684 | (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, |
| 685 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 686 | "$Rn.addr = $wb", []> { |
Owen Anderson | b3727fe | 2011-10-28 20:43:24 +0000 | [diff] [blame] | 687 | let Inst{4} = Rn{4}; |
Jim Grosbach | 5921675 | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 688 | let DecoderMethod = "DecodeVLDInstruction"; |
| 689 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 690 | } |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 691 | } |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 692 | |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 693 | def VLD1d8T : VLD1D3<{0,0,0,?}, "8">; |
| 694 | def VLD1d16T : VLD1D3<{0,1,0,?}, "16">; |
| 695 | def VLD1d32T : VLD1D3<{1,0,0,?}, "32">; |
| 696 | def VLD1d64T : VLD1D3<{1,1,0,?}, "64">; |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 697 | |
Jim Grosbach | 5921675 | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 698 | defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">; |
| 699 | defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">; |
| 700 | defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">; |
| 701 | defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">; |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 702 | |
Jim Grosbach | 5921675 | 2011-10-24 23:26:05 +0000 | [diff] [blame] | 703 | def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>; |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 704 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 705 | // ...with 4 registers |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 706 | class VLD1D4<bits<4> op7_4, string Dt> |
Jim Grosbach | b631031 | 2011-10-21 20:35:01 +0000 | [diff] [blame] | 707 | : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 708 | (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt, |
Jim Grosbach | b631031 | 2011-10-21 20:35:01 +0000 | [diff] [blame] | 709 | "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 710 | let Rm = 0b1111; |
| 711 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 712 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 713 | } |
Jim Grosbach | 399cdca | 2011-10-25 00:14:01 +0000 | [diff] [blame] | 714 | multiclass VLD1D4WB<bits<4> op7_4, string Dt> { |
| 715 | def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb), |
| 716 | (ins addrmode6:$Rn), IIC_VLD1x2u, |
| 717 | "vld1", Dt, "$Vd, $Rn!", |
| 718 | "$Rn.addr = $wb", []> { |
| 719 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 720 | let Inst{5-4} = Rn{5-4}; |
| 721 | let DecoderMethod = "DecodeVLDInstruction"; |
| 722 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 723 | } |
| 724 | def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb), |
| 725 | (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, |
| 726 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 727 | "$Rn.addr = $wb", []> { |
| 728 | let Inst{5-4} = Rn{5-4}; |
| 729 | let DecoderMethod = "DecodeVLDInstruction"; |
| 730 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 731 | } |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 732 | } |
Johnny Chen | d7283d9 | 2010-02-23 20:51:23 +0000 | [diff] [blame] | 733 | |
Owen Anderson | e85bd77 | 2010-11-02 00:24:52 +0000 | [diff] [blame] | 734 | def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">; |
| 735 | def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">; |
| 736 | def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">; |
| 737 | def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">; |
Bob Wilson | 99493b2 | 2010-03-20 17:59:03 +0000 | [diff] [blame] | 738 | |
Jim Grosbach | 399cdca | 2011-10-25 00:14:01 +0000 | [diff] [blame] | 739 | defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">; |
| 740 | defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">; |
| 741 | defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">; |
| 742 | defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">; |
Bob Wilson | 9f7d60f | 2009-08-12 17:04:56 +0000 | [diff] [blame] | 743 | |
Jim Grosbach | 399cdca | 2011-10-25 00:14:01 +0000 | [diff] [blame] | 744 | def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>; |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 745 | |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 746 | // VLD2 : Vector Load (multiple 2-element structures) |
Jim Grosbach | 2af50d9 | 2011-12-09 19:07:20 +0000 | [diff] [blame] | 747 | class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, |
| 748 | InstrItinClass itin> |
Jim Grosbach | 4661d4c | 2011-10-21 22:21:10 +0000 | [diff] [blame] | 749 | : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd), |
Jim Grosbach | 2af50d9 | 2011-12-09 19:07:20 +0000 | [diff] [blame] | 750 | (ins addrmode6:$Rn), itin, |
Jim Grosbach | 224180e | 2011-10-21 23:58:57 +0000 | [diff] [blame] | 751 | "vld2", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 752 | let Rm = 0b1111; |
| 753 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 754 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 755 | } |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 756 | |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 757 | def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>; |
| 758 | def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>; |
| 759 | def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>; |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 760 | |
Jim Grosbach | 2af50d9 | 2011-12-09 19:07:20 +0000 | [diff] [blame] | 761 | def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>; |
| 762 | def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>; |
| 763 | def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>; |
Bob Wilson | 3bf12ab | 2009-10-06 22:01:59 +0000 | [diff] [blame] | 764 | |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 765 | def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>; |
| 766 | def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>; |
| 767 | def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>; |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 768 | |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 769 | // ...with address register writeback: |
Jim Grosbach | a4e3c7f | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 770 | multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt, |
| 771 | RegisterOperand VdTy, InstrItinClass itin> { |
| 772 | def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), |
| 773 | (ins addrmode6:$Rn), itin, |
| 774 | "vld2", Dt, "$Vd, $Rn!", |
| 775 | "$Rn.addr = $wb", []> { |
| 776 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 777 | let Inst{5-4} = Rn{5-4}; |
| 778 | let DecoderMethod = "DecodeVLDInstruction"; |
| 779 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 780 | } |
| 781 | def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), |
| 782 | (ins addrmode6:$Rn, rGPR:$Rm), itin, |
| 783 | "vld2", Dt, "$Vd, $Rn, $Rm", |
| 784 | "$Rn.addr = $wb", []> { |
| 785 | let Inst{5-4} = Rn{5-4}; |
| 786 | let DecoderMethod = "DecodeVLDInstruction"; |
| 787 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 788 | } |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 789 | } |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 790 | |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 791 | defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>; |
| 792 | defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>; |
| 793 | defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>; |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 794 | |
Jim Grosbach | a4e3c7f | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 795 | defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>; |
| 796 | defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>; |
| 797 | defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>; |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 798 | |
Jim Grosbach | a4e3c7f | 2011-12-09 21:28:25 +0000 | [diff] [blame] | 799 | def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; |
| 800 | def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; |
| 801 | def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; |
| 802 | def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; |
| 803 | def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; |
| 804 | def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; |
Bob Wilson | ffde080 | 2010-09-02 16:00:54 +0000 | [diff] [blame] | 805 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 806 | // ...with double-spaced registers |
Jim Grosbach | c3384c9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 807 | def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>; |
| 808 | def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>; |
| 809 | def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>; |
| 810 | defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>; |
| 811 | defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>; |
| 812 | defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>; |
Johnny Chen | d7283d9 | 2010-02-23 20:51:23 +0000 | [diff] [blame] | 813 | |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 814 | // VLD3 : Vector Load (multiple 3-element structures) |
Bob Wilson | 00bf1d9 | 2010-03-20 18:14:26 +0000 | [diff] [blame] | 815 | class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 816 | : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 817 | (ins addrmode6:$Rn), IIC_VLD3, |
| 818 | "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { |
| 819 | let Rm = 0b1111; |
| 820 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 821 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 822 | } |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 823 | |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 824 | def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; |
| 825 | def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">; |
| 826 | def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">; |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 827 | |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 828 | def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>; |
| 829 | def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>; |
| 830 | def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 831 | |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 832 | // ...with address register writeback: |
| 833 | class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 834 | : NLdSt<0, 0b10, op11_8, op7_4, |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 835 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 836 | (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, |
| 837 | "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", |
| 838 | "$Rn.addr = $wb", []> { |
| 839 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 840 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 841 | } |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 842 | |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 843 | def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; |
| 844 | def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">; |
| 845 | def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">; |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 846 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 847 | def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; |
| 848 | def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; |
| 849 | def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 850 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 851 | // ...with double-spaced registers: |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 852 | def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">; |
| 853 | def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">; |
| 854 | def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">; |
| 855 | def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">; |
| 856 | def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">; |
| 857 | def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">; |
Bob Wilson | 00bf1d9 | 2010-03-20 18:14:26 +0000 | [diff] [blame] | 858 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 859 | def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
| 860 | def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
| 861 | def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 862 | |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 863 | // ...alternate versions to be allocated odd register numbers: |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 864 | def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>; |
| 865 | def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>; |
| 866 | def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>; |
| 867 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 868 | def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
| 869 | def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
| 870 | def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; |
Bob Wilson | ff8952e | 2009-10-07 17:24:55 +0000 | [diff] [blame] | 871 | |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 872 | // VLD4 : Vector Load (multiple 4-element structures) |
Bob Wilson | 00bf1d9 | 2010-03-20 18:14:26 +0000 | [diff] [blame] | 873 | class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 874 | : NLdSt<0, 0b10, op11_8, op7_4, |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 875 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 876 | (ins addrmode6:$Rn), IIC_VLD4, |
| 877 | "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { |
| 878 | let Rm = 0b1111; |
| 879 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 880 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 881 | } |
Bob Wilson | 4a3d35a | 2009-08-05 00:49:09 +0000 | [diff] [blame] | 882 | |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 883 | def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; |
| 884 | def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">; |
| 885 | def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">; |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 886 | |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 887 | def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>; |
| 888 | def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>; |
| 889 | def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 890 | |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 891 | // ...with address register writeback: |
| 892 | class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 893 | : NLdSt<0, 0b10, op11_8, op7_4, |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 894 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), |
Bob Wilson | 6eb08dd | 2011-02-07 17:43:12 +0000 | [diff] [blame] | 895 | (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 896 | "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", |
| 897 | "$Rn.addr = $wb", []> { |
| 898 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 899 | let DecoderMethod = "DecodeVLDInstruction"; |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 900 | } |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 901 | |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 902 | def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; |
| 903 | def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">; |
| 904 | def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">; |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 905 | |
Bob Wilson | 6eb08dd | 2011-02-07 17:43:12 +0000 | [diff] [blame] | 906 | def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; |
| 907 | def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; |
| 908 | def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 909 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 910 | // ...with double-spaced registers: |
Owen Anderson | cf667be | 2010-11-02 01:24:55 +0000 | [diff] [blame] | 911 | def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">; |
| 912 | def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">; |
| 913 | def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">; |
| 914 | def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">; |
| 915 | def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">; |
| 916 | def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">; |
Bob Wilson | 00bf1d9 | 2010-03-20 18:14:26 +0000 | [diff] [blame] | 917 | |
Bob Wilson | 6eb08dd | 2011-02-07 17:43:12 +0000 | [diff] [blame] | 918 | def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
| 919 | def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
| 920 | def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
Bob Wilson | f572191 | 2010-09-03 18:16:02 +0000 | [diff] [blame] | 921 | |
Bob Wilson | 92cb932 | 2010-03-20 20:10:51 +0000 | [diff] [blame] | 922 | // ...alternate versions to be allocated odd register numbers: |
Bob Wilson | 6eb08dd | 2011-02-07 17:43:12 +0000 | [diff] [blame] | 923 | def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>; |
| 924 | def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>; |
| 925 | def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>; |
| 926 | |
| 927 | def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
| 928 | def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
| 929 | def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 930 | |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 931 | } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 |
| 932 | |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 933 | // Classes for VLD*LN pseudo-instructions with multi-register operands. |
| 934 | // These are expanded to real instructions after register allocation. |
| 935 | class VLDQLNPseudo<InstrItinClass itin> |
| 936 | : PseudoNLdSt<(outs QPR:$dst), |
| 937 | (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), |
| 938 | itin, "$src = $dst">; |
| 939 | class VLDQLNWBPseudo<InstrItinClass itin> |
| 940 | : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), |
| 941 | (ins addrmode6:$addr, am6offset:$offset, QPR:$src, |
| 942 | nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; |
| 943 | class VLDQQLNPseudo<InstrItinClass itin> |
| 944 | : PseudoNLdSt<(outs QQPR:$dst), |
| 945 | (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), |
| 946 | itin, "$src = $dst">; |
| 947 | class VLDQQLNWBPseudo<InstrItinClass itin> |
| 948 | : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), |
| 949 | (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, |
| 950 | nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; |
| 951 | class VLDQQQQLNPseudo<InstrItinClass itin> |
| 952 | : PseudoNLdSt<(outs QQQQPR:$dst), |
| 953 | (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), |
| 954 | itin, "$src = $dst">; |
| 955 | class VLDQQQQLNWBPseudo<InstrItinClass itin> |
| 956 | : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), |
| 957 | (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, |
| 958 | nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; |
| 959 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 960 | // VLD1LN : Vector Load (single element to one lane) |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 961 | class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, |
| 962 | PatFrag LoadOp> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 963 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 964 | (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), |
| 965 | IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 966 | "$src = $Vd", |
| 967 | [(set DPR:$Vd, (vector_insert (Ty DPR:$src), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 968 | (i32 (LoadOp addrmode6:$Rn)), |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 969 | imm:$lane))]> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 970 | let Rm = 0b1111; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 971 | let DecoderMethod = "DecodeVLD1LN"; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 972 | } |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 973 | class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, |
| 974 | PatFrag LoadOp> |
| 975 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), |
| 976 | (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane), |
| 977 | IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", |
| 978 | "$src = $Vd", |
| 979 | [(set DPR:$Vd, (vector_insert (Ty DPR:$src), |
| 980 | (i32 (LoadOp addrmode6oneL32:$Rn)), |
| 981 | imm:$lane))]> { |
| 982 | let Rm = 0b1111; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 983 | let DecoderMethod = "DecodeVLD1LN"; |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 984 | } |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 985 | class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> { |
| 986 | let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), |
| 987 | (i32 (LoadOp addrmode6:$addr)), |
| 988 | imm:$lane))]; |
| 989 | } |
| 990 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 991 | def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> { |
| 992 | let Inst{7-5} = lane{2-0}; |
| 993 | } |
| 994 | def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { |
| 995 | let Inst{7-6} = lane{1-0}; |
Jim Grosbach | eeaf1c1 | 2011-12-19 18:31:43 +0000 | [diff] [blame] | 996 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 997 | } |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 998 | def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> { |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 999 | let Inst{7} = lane{0}; |
Jim Grosbach | eeaf1c1 | 2011-12-19 18:31:43 +0000 | [diff] [blame] | 1000 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1001 | } |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1002 | |
| 1003 | def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>; |
| 1004 | def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>; |
| 1005 | def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>; |
| 1006 | |
Bob Wilson | 746fa17 | 2010-12-10 22:13:32 +0000 | [diff] [blame] | 1007 | def : Pat<(vector_insert (v2f32 DPR:$src), |
| 1008 | (f32 (load addrmode6:$addr)), imm:$lane), |
| 1009 | (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; |
| 1010 | def : Pat<(vector_insert (v4f32 QPR:$src), |
| 1011 | (f32 (load addrmode6:$addr)), imm:$lane), |
| 1012 | (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; |
| 1013 | |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1014 | let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { |
| 1015 | |
| 1016 | // ...with address register writeback: |
| 1017 | class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1018 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1019 | (ins addrmode6:$Rn, am6offset:$Rm, |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1020 | DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1021 | "\\{$Vd[$lane]\\}, $Rn$Rm", |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1022 | "$src = $Vd, $Rn.addr = $wb", []> { |
| 1023 | let DecoderMethod = "DecodeVLD1LN"; |
| 1024 | } |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1025 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1026 | def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { |
| 1027 | let Inst{7-5} = lane{2-0}; |
| 1028 | } |
| 1029 | def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { |
| 1030 | let Inst{7-6} = lane{1-0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1031 | let Inst{4} = Rn{4}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1032 | } |
| 1033 | def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { |
| 1034 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1035 | let Inst{5} = Rn{4}; |
| 1036 | let Inst{4} = Rn{4}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1037 | } |
Bob Wilson | b796bbb | 2010-11-01 22:04:05 +0000 | [diff] [blame] | 1038 | |
| 1039 | def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; |
| 1040 | def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; |
| 1041 | def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; |
Bob Wilson | 7708c22 | 2009-10-07 18:09:32 +0000 | [diff] [blame] | 1042 | |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1043 | // VLD2LN : Vector Load (single 2-element structure to one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1044 | class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1045 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1046 | (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), |
| 1047 | IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1048 | "$src1 = $Vd, $src2 = $dst2", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1049 | let Rm = 0b1111; |
| 1050 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1051 | let DecoderMethod = "DecodeVLD2LN"; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1052 | } |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1053 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1054 | def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { |
| 1055 | let Inst{7-5} = lane{2-0}; |
| 1056 | } |
| 1057 | def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> { |
| 1058 | let Inst{7-6} = lane{1-0}; |
| 1059 | } |
| 1060 | def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> { |
| 1061 | let Inst{7} = lane{0}; |
| 1062 | } |
Bob Wilson | 30aea9d | 2009-10-08 18:56:10 +0000 | [diff] [blame] | 1063 | |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 1064 | def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>; |
| 1065 | def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>; |
| 1066 | def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1067 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 1068 | // ...with double-spaced registers: |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1069 | def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> { |
| 1070 | let Inst{7-6} = lane{1-0}; |
| 1071 | } |
| 1072 | def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> { |
| 1073 | let Inst{7} = lane{0}; |
| 1074 | } |
Bob Wilson | 30aea9d | 2009-10-08 18:56:10 +0000 | [diff] [blame] | 1075 | |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 1076 | def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; |
| 1077 | def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1078 | |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1079 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1080 | class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1081 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1082 | (ins addrmode6:$Rn, am6offset:$Rm, |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 1083 | DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1084 | "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", |
| 1085 | "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { |
| 1086 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1087 | let DecoderMethod = "DecodeVLD2LN"; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1088 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1089 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1090 | def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { |
| 1091 | let Inst{7-5} = lane{2-0}; |
| 1092 | } |
| 1093 | def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> { |
| 1094 | let Inst{7-6} = lane{1-0}; |
| 1095 | } |
| 1096 | def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> { |
| 1097 | let Inst{7} = lane{0}; |
| 1098 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1099 | |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 1100 | def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; |
| 1101 | def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; |
| 1102 | def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1103 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1104 | def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> { |
| 1105 | let Inst{7-6} = lane{1-0}; |
| 1106 | } |
| 1107 | def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> { |
| 1108 | let Inst{7} = lane{0}; |
| 1109 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1110 | |
Evan Cheng | d2ca813 | 2010-10-09 01:03:04 +0000 | [diff] [blame] | 1111 | def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; |
| 1112 | def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1113 | |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1114 | // VLD3LN : Vector Load (single 3-element structure to one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1115 | class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1116 | : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1117 | (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1118 | nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1119 | "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1120 | "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1121 | let Rm = 0b1111; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1122 | let DecoderMethod = "DecodeVLD3LN"; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1123 | } |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1124 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1125 | def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { |
| 1126 | let Inst{7-5} = lane{2-0}; |
| 1127 | } |
| 1128 | def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> { |
| 1129 | let Inst{7-6} = lane{1-0}; |
| 1130 | } |
| 1131 | def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> { |
| 1132 | let Inst{7} = lane{0}; |
| 1133 | } |
Bob Wilson | 0bf7d99 | 2009-10-08 22:27:33 +0000 | [diff] [blame] | 1134 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1135 | def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; |
| 1136 | def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; |
| 1137 | def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1138 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 1139 | // ...with double-spaced registers: |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1140 | def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> { |
| 1141 | let Inst{7-6} = lane{1-0}; |
| 1142 | } |
| 1143 | def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> { |
| 1144 | let Inst{7} = lane{0}; |
| 1145 | } |
Bob Wilson | 0bf7d99 | 2009-10-08 22:27:33 +0000 | [diff] [blame] | 1146 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1147 | def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>; |
| 1148 | def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>; |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1149 | |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1150 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1151 | class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1152 | : NLdStLn<1, 0b10, op11_8, op7_4, |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1153 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1154 | (ins addrmode6:$Rn, am6offset:$Rm, |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1155 | DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1156 | IIC_VLD3lnu, "vld3", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1157 | "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", |
| 1158 | "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1159 | []> { |
| 1160 | let DecoderMethod = "DecodeVLD3LN"; |
| 1161 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1162 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1163 | def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { |
| 1164 | let Inst{7-5} = lane{2-0}; |
| 1165 | } |
| 1166 | def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> { |
| 1167 | let Inst{7-6} = lane{1-0}; |
| 1168 | } |
| 1169 | def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1170 | let Inst{7} = lane{0}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1171 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1172 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1173 | def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; |
| 1174 | def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; |
| 1175 | def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1176 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1177 | def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> { |
| 1178 | let Inst{7-6} = lane{1-0}; |
| 1179 | } |
| 1180 | def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1181 | let Inst{7} = lane{0}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1182 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1183 | |
Evan Cheng | 84f69e8 | 2010-10-09 01:45:34 +0000 | [diff] [blame] | 1184 | def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>; |
| 1185 | def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1186 | |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1187 | // VLD4LN : Vector Load (single 4-element structure to one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1188 | class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1189 | : NLdStLn<1, 0b10, op11_8, op7_4, |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1190 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1191 | (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, |
Evan Cheng | 10dc63f | 2010-10-09 04:07:58 +0000 | [diff] [blame] | 1192 | nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1193 | "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1194 | "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1195 | let Rm = 0b1111; |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1196 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1197 | let DecoderMethod = "DecodeVLD4LN"; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1198 | } |
Bob Wilson | 243fcc5 | 2009-09-01 04:26:28 +0000 | [diff] [blame] | 1199 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1200 | def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { |
| 1201 | let Inst{7-5} = lane{2-0}; |
| 1202 | } |
| 1203 | def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> { |
| 1204 | let Inst{7-6} = lane{1-0}; |
| 1205 | } |
| 1206 | def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1207 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1208 | let Inst{5} = Rn{5}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1209 | } |
Bob Wilson | 62e053e | 2009-10-08 22:53:57 +0000 | [diff] [blame] | 1210 | |
Evan Cheng | 10dc63f | 2010-10-09 04:07:58 +0000 | [diff] [blame] | 1211 | def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; |
| 1212 | def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; |
| 1213 | def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1214 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 1215 | // ...with double-spaced registers: |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1216 | def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> { |
| 1217 | let Inst{7-6} = lane{1-0}; |
| 1218 | } |
| 1219 | def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1220 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1221 | let Inst{5} = Rn{5}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1222 | } |
Bob Wilson | 62e053e | 2009-10-08 22:53:57 +0000 | [diff] [blame] | 1223 | |
Evan Cheng | 10dc63f | 2010-10-09 04:07:58 +0000 | [diff] [blame] | 1224 | def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>; |
| 1225 | def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>; |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1226 | |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1227 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 1228 | class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | d138d70 | 2010-11-02 20:47:39 +0000 | [diff] [blame] | 1229 | : NLdStLn<1, 0b10, op11_8, op7_4, |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1230 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1231 | (ins addrmode6:$Rn, am6offset:$Rm, |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1232 | DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), |
Bob Wilson | 6eb08dd | 2011-02-07 17:43:12 +0000 | [diff] [blame] | 1233 | IIC_VLD4lnu, "vld4", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1234 | "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", |
| 1235 | "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1236 | []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1237 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1238 | let DecoderMethod = "DecodeVLD4LN" ; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1239 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1240 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1241 | def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { |
| 1242 | let Inst{7-5} = lane{2-0}; |
| 1243 | } |
| 1244 | def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> { |
| 1245 | let Inst{7-6} = lane{1-0}; |
| 1246 | } |
| 1247 | def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1248 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1249 | let Inst{5} = Rn{5}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1250 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1251 | |
Evan Cheng | 10dc63f | 2010-10-09 04:07:58 +0000 | [diff] [blame] | 1252 | def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; |
| 1253 | def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; |
| 1254 | def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1255 | |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1256 | def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> { |
| 1257 | let Inst{7-6} = lane{1-0}; |
| 1258 | } |
| 1259 | def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { |
Jim Grosbach | 3346dce | 2011-12-19 18:11:17 +0000 | [diff] [blame] | 1260 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1261 | let Inst{5} = Rn{5}; |
Owen Anderson | f0ea0f2 | 2010-11-02 20:40:59 +0000 | [diff] [blame] | 1262 | } |
Bob Wilson | a102364 | 2010-03-20 20:47:18 +0000 | [diff] [blame] | 1263 | |
Evan Cheng | 10dc63f | 2010-10-09 04:07:58 +0000 | [diff] [blame] | 1264 | def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>; |
| 1265 | def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1266 | |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1267 | } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 |
| 1268 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1269 | // VLD1DUP : Vector Load (single element to all lanes) |
Bob Wilson | f3d2f9d | 2010-11-28 06:51:15 +0000 | [diff] [blame] | 1270 | class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> |
Jim Grosbach | 98b05a5 | 2011-11-30 01:09:44 +0000 | [diff] [blame] | 1271 | : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd), |
| 1272 | (ins addrmode6dup:$Rn), |
| 1273 | IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "", |
| 1274 | [(set VecListOneDAllLanes:$Vd, |
| 1275 | (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> { |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1276 | let Rm = 0b1111; |
Bob Wilson | bce5577 | 2010-11-27 07:12:02 +0000 | [diff] [blame] | 1277 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1278 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1279 | } |
Bob Wilson | f3d2f9d | 2010-11-28 06:51:15 +0000 | [diff] [blame] | 1280 | def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>; |
| 1281 | def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>; |
| 1282 | def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1283 | |
Bob Wilson | 746fa17 | 2010-12-10 22:13:32 +0000 | [diff] [blame] | 1284 | def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), |
| 1285 | (VLD1DUPd32 addrmode6:$addr)>; |
Bob Wilson | 746fa17 | 2010-12-10 22:13:32 +0000 | [diff] [blame] | 1286 | |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1287 | class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> |
| 1288 | : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1289 | (ins addrmode6dup:$Rn), IIC_VLD1dup, |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1290 | "vld1", Dt, "$Vd, $Rn", "", |
| 1291 | [(set VecListDPairAllLanes:$Vd, |
| 1292 | (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> { |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1293 | let Rm = 0b1111; |
Bob Wilson | bce5577 | 2010-11-27 07:12:02 +0000 | [diff] [blame] | 1294 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1295 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1296 | } |
| 1297 | |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1298 | def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>; |
| 1299 | def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>; |
| 1300 | def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1301 | |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1302 | def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), |
| 1303 | (VLD1DUPq32 addrmode6:$addr)>; |
| 1304 | |
| 1305 | let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1306 | // ...with address register writeback: |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1307 | multiclass VLD1DUPWB<bits<4> op7_4, string Dt> { |
| 1308 | def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, |
| 1309 | (outs VecListOneDAllLanes:$Vd, GPR:$wb), |
| 1310 | (ins addrmode6dup:$Rn), IIC_VLD1dupu, |
| 1311 | "vld1", Dt, "$Vd, $Rn!", |
| 1312 | "$Rn.addr = $wb", []> { |
| 1313 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1314 | let Inst{4} = Rn{4}; |
| 1315 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
| 1316 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 1317 | } |
| 1318 | def _register : NLdSt<1, 0b10, 0b1100, op7_4, |
| 1319 | (outs VecListOneDAllLanes:$Vd, GPR:$wb), |
| 1320 | (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu, |
| 1321 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 1322 | "$Rn.addr = $wb", []> { |
| 1323 | let Inst{4} = Rn{4}; |
| 1324 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
| 1325 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 1326 | } |
Bob Wilson | bce5577 | 2010-11-27 07:12:02 +0000 | [diff] [blame] | 1327 | } |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1328 | multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> { |
| 1329 | def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1330 | (outs VecListDPairAllLanes:$Vd, GPR:$wb), |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1331 | (ins addrmode6dup:$Rn), IIC_VLD1dupu, |
| 1332 | "vld1", Dt, "$Vd, $Rn!", |
| 1333 | "$Rn.addr = $wb", []> { |
| 1334 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1335 | let Inst{4} = Rn{4}; |
| 1336 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
| 1337 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 1338 | } |
| 1339 | def _register : NLdSt<1, 0b10, 0b1100, op7_4, |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1340 | (outs VecListDPairAllLanes:$Vd, GPR:$wb), |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1341 | (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu, |
| 1342 | "vld1", Dt, "$Vd, $Rn, $Rm", |
| 1343 | "$Rn.addr = $wb", []> { |
| 1344 | let Inst{4} = Rn{4}; |
| 1345 | let DecoderMethod = "DecodeVLD1DupInstruction"; |
| 1346 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 1347 | } |
Bob Wilson | bce5577 | 2010-11-27 07:12:02 +0000 | [diff] [blame] | 1348 | } |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1349 | |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1350 | defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">; |
| 1351 | defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">; |
| 1352 | defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1353 | |
Jim Grosbach | 096334e | 2011-11-30 19:35:44 +0000 | [diff] [blame] | 1354 | defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">; |
| 1355 | defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">; |
| 1356 | defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">; |
Bob Wilson | 2a0e974 | 2010-11-27 06:35:16 +0000 | [diff] [blame] | 1357 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1358 | // VLD2DUP : Vector Load (single 2-element structure to all lanes) |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 1359 | class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy> |
| 1360 | : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1361 | (ins addrmode6dup:$Rn), IIC_VLD2dup, |
Jim Grosbach | 3471d4f | 2011-12-21 00:38:54 +0000 | [diff] [blame] | 1362 | "vld2", Dt, "$Vd, $Rn", "", []> { |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1363 | let Rm = 0b1111; |
| 1364 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1365 | let DecoderMethod = "DecodeVLD2DupInstruction"; |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1366 | } |
| 1367 | |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1368 | def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>; |
| 1369 | def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>; |
| 1370 | def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>; |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1371 | |
Jim Grosbach | 4d0983a | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 1372 | // ...with double-spaced registers |
| 1373 | def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>; |
| 1374 | def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>; |
| 1375 | def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>; |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1376 | |
| 1377 | // ...with address register writeback: |
Jim Grosbach | e6949b1 | 2011-12-21 19:40:55 +0000 | [diff] [blame] | 1378 | multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> { |
| 1379 | def _fixed : NLdSt<1, 0b10, 0b1101, op7_4, |
| 1380 | (outs VdTy:$Vd, GPR:$wb), |
| 1381 | (ins addrmode6dup:$Rn), IIC_VLD2dupu, |
| 1382 | "vld2", Dt, "$Vd, $Rn!", |
| 1383 | "$Rn.addr = $wb", []> { |
| 1384 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1385 | let Inst{4} = Rn{4}; |
| 1386 | let DecoderMethod = "DecodeVLD2DupInstruction"; |
| 1387 | let AsmMatchConverter = "cvtVLDwbFixed"; |
| 1388 | } |
| 1389 | def _register : NLdSt<1, 0b10, 0b1101, op7_4, |
| 1390 | (outs VdTy:$Vd, GPR:$wb), |
| 1391 | (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu, |
| 1392 | "vld2", Dt, "$Vd, $Rn, $Rm", |
| 1393 | "$Rn.addr = $wb", []> { |
| 1394 | let Inst{4} = Rn{4}; |
| 1395 | let DecoderMethod = "DecodeVLD2DupInstruction"; |
| 1396 | let AsmMatchConverter = "cvtVLDwbRegister"; |
| 1397 | } |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1398 | } |
| 1399 | |
Jim Grosbach | c0fc450 | 2012-03-06 22:01:44 +0000 | [diff] [blame] | 1400 | defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>; |
| 1401 | defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>; |
| 1402 | defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>; |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1403 | |
Jim Grosbach | 4d0983a | 2012-03-06 23:10:38 +0000 | [diff] [blame] | 1404 | defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>; |
| 1405 | defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>; |
| 1406 | defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>; |
Bob Wilson | b1dfa7a | 2010-11-28 06:51:26 +0000 | [diff] [blame] | 1407 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1408 | // VLD3DUP : Vector Load (single 3-element structure to all lanes) |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1409 | class VLD3DUP<bits<4> op7_4, string Dt> |
| 1410 | : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1411 | (ins addrmode6dup:$Rn), IIC_VLD3dup, |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1412 | "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> { |
| 1413 | let Rm = 0b1111; |
Owen Anderson | ef2865a | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 1414 | let Inst{4} = 0; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1415 | let DecoderMethod = "DecodeVLD3DupInstruction"; |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1416 | } |
| 1417 | |
| 1418 | def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">; |
| 1419 | def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">; |
| 1420 | def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">; |
| 1421 | |
| 1422 | def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>; |
| 1423 | def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>; |
| 1424 | def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>; |
| 1425 | |
| 1426 | // ...with double-spaced registers (not used for codegen): |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 1427 | def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">; |
| 1428 | def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">; |
| 1429 | def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">; |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1430 | |
| 1431 | // ...with address register writeback: |
| 1432 | class VLD3DUPWB<bits<4> op7_4, string Dt> |
| 1433 | : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1434 | (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu, |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1435 | "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm", |
| 1436 | "$Rn.addr = $wb", []> { |
Owen Anderson | ef2865a | 2011-08-15 23:38:54 +0000 | [diff] [blame] | 1437 | let Inst{4} = 0; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1438 | let DecoderMethod = "DecodeVLD3DupInstruction"; |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1439 | } |
| 1440 | |
| 1441 | def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">; |
| 1442 | def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">; |
| 1443 | def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">; |
| 1444 | |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 1445 | def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">; |
| 1446 | def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">; |
| 1447 | def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">; |
Bob Wilson | 86c6d80 | 2010-11-29 19:35:29 +0000 | [diff] [blame] | 1448 | |
| 1449 | def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; |
| 1450 | def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; |
| 1451 | def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; |
| 1452 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1453 | // VLD4DUP : Vector Load (single 4-element structure to all lanes) |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1454 | class VLD4DUP<bits<4> op7_4, string Dt> |
| 1455 | : NLdSt<1, 0b10, 0b1111, op7_4, |
| 1456 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1457 | (ins addrmode6dup:$Rn), IIC_VLD4dup, |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1458 | "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> { |
| 1459 | let Rm = 0b1111; |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1460 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1461 | let DecoderMethod = "DecodeVLD4DupInstruction"; |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1462 | } |
| 1463 | |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1464 | def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">; |
| 1465 | def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">; |
| 1466 | def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1467 | |
| 1468 | def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>; |
| 1469 | def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>; |
| 1470 | def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>; |
| 1471 | |
| 1472 | // ...with double-spaced registers (not used for codegen): |
Jim Grosbach | 6cd6a68 | 2012-01-24 23:47:07 +0000 | [diff] [blame] | 1473 | def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">; |
| 1474 | def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">; |
| 1475 | def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1476 | |
| 1477 | // ...with address register writeback: |
| 1478 | class VLD4DUPWB<bits<4> op7_4, string Dt> |
| 1479 | : NLdSt<1, 0b10, 0b1111, op7_4, |
| 1480 | (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1481 | (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu, |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1482 | "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm", |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1483 | "$Rn.addr = $wb", []> { |
| 1484 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1485 | let DecoderMethod = "DecodeVLD4DupInstruction"; |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1486 | } |
| 1487 | |
Bob Wilson | 8e0c7b5 | 2010-11-30 00:00:42 +0000 | [diff] [blame] | 1488 | def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">; |
| 1489 | def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">; |
| 1490 | def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } |
| 1491 | |
Jim Grosbach | 6cd6a68 | 2012-01-24 23:47:07 +0000 | [diff] [blame] | 1492 | def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">; |
| 1493 | def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">; |
| 1494 | def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } |
Bob Wilson | 6c4c982 | 2010-11-30 00:00:35 +0000 | [diff] [blame] | 1495 | |
| 1496 | def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; |
| 1497 | def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; |
| 1498 | def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; |
| 1499 | |
Evan Cheng | 5fd1c9b | 2010-05-19 06:07:03 +0000 | [diff] [blame] | 1500 | } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 |
Bob Wilson | dbd3c0e | 2009-08-12 00:49:01 +0000 | [diff] [blame] | 1501 | |
Evan Cheng | 5fd1c9b | 2010-05-19 06:07:03 +0000 | [diff] [blame] | 1502 | let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1503 | |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1504 | // Classes for VST* pseudo-instructions with multi-register operands. |
| 1505 | // These are expanded to real instructions after register allocation. |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 1506 | class VSTQPseudo<InstrItinClass itin> |
| 1507 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">; |
| 1508 | class VSTQWBPseudo<InstrItinClass itin> |
Bob Wilson | e5ce4f6 | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1509 | : PseudoNLdSt<(outs GPR:$wb), |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 1510 | (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin, |
Bob Wilson | e5ce4f6 | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1511 | "$addr.addr = $wb">; |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1512 | class VSTQWBfixedPseudo<InstrItinClass itin> |
| 1513 | : PseudoNLdSt<(outs GPR:$wb), |
| 1514 | (ins addrmode6:$addr, QPR:$src), itin, |
| 1515 | "$addr.addr = $wb">; |
| 1516 | class VSTQWBregisterPseudo<InstrItinClass itin> |
| 1517 | : PseudoNLdSt<(outs GPR:$wb), |
| 1518 | (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin, |
| 1519 | "$addr.addr = $wb">; |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 1520 | class VSTQQPseudo<InstrItinClass itin> |
| 1521 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">; |
| 1522 | class VSTQQWBPseudo<InstrItinClass itin> |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1523 | : PseudoNLdSt<(outs GPR:$wb), |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 1524 | (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin, |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1525 | "$addr.addr = $wb">; |
Jim Grosbach | 6d56730 | 2012-01-20 19:16:00 +0000 | [diff] [blame] | 1526 | class VSTQQWBfixedPseudo<InstrItinClass itin> |
| 1527 | : PseudoNLdSt<(outs GPR:$wb), |
| 1528 | (ins addrmode6:$addr, QQPR:$src), itin, |
| 1529 | "$addr.addr = $wb">; |
| 1530 | class VSTQQWBregisterPseudo<InstrItinClass itin> |
| 1531 | : PseudoNLdSt<(outs GPR:$wb), |
| 1532 | (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin, |
| 1533 | "$addr.addr = $wb">; |
| 1534 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1535 | class VSTQQQQPseudo<InstrItinClass itin> |
| 1536 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">; |
Bob Wilson | 9d84fb3 | 2010-09-14 20:59:49 +0000 | [diff] [blame] | 1537 | class VSTQQQQWBPseudo<InstrItinClass itin> |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1538 | : PseudoNLdSt<(outs GPR:$wb), |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1539 | (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1540 | "$addr.addr = $wb">; |
| 1541 | |
Bob Wilson | 11d9899 | 2010-03-23 06:20:33 +0000 | [diff] [blame] | 1542 | // VST1 : Vector Store (multiple single elements) |
| 1543 | class VST1D<bits<4> op7_4, string Dt> |
Jim Grosbach | 6b09c77 | 2011-10-20 15:04:25 +0000 | [diff] [blame] | 1544 | : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd), |
| 1545 | IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1546 | let Rm = 0b1111; |
| 1547 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1548 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1549 | } |
Bob Wilson | 11d9899 | 2010-03-23 06:20:33 +0000 | [diff] [blame] | 1550 | class VST1Q<bits<4> op7_4, string Dt> |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1551 | : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd), |
Jim Grosbach | 742c4ba | 2011-11-12 00:31:53 +0000 | [diff] [blame] | 1552 | IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1553 | let Rm = 0b1111; |
| 1554 | let Inst{5-4} = Rn{5-4}; |
Jim Grosbach | 4d06138 | 2011-11-11 23:51:31 +0000 | [diff] [blame] | 1555 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1556 | } |
Bob Wilson | 11d9899 | 2010-03-23 06:20:33 +0000 | [diff] [blame] | 1557 | |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1558 | def VST1d8 : VST1D<{0,0,0,?}, "8">; |
| 1559 | def VST1d16 : VST1D<{0,1,0,?}, "16">; |
| 1560 | def VST1d32 : VST1D<{1,0,0,?}, "32">; |
| 1561 | def VST1d64 : VST1D<{1,1,0,?}, "64">; |
Bob Wilson | 11d9899 | 2010-03-23 06:20:33 +0000 | [diff] [blame] | 1562 | |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1563 | def VST1q8 : VST1Q<{0,0,?,?}, "8">; |
| 1564 | def VST1q16 : VST1Q<{0,1,?,?}, "16">; |
| 1565 | def VST1q32 : VST1Q<{1,0,?,?}, "32">; |
| 1566 | def VST1q64 : VST1Q<{1,1,?,?}, "64">; |
Bob Wilson | 11d9899 | 2010-03-23 06:20:33 +0000 | [diff] [blame] | 1567 | |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1568 | // ...with address register writeback: |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1569 | multiclass VST1DWB<bits<4> op7_4, string Dt> { |
| 1570 | def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb), |
| 1571 | (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u, |
| 1572 | "vst1", Dt, "$Vd, $Rn!", |
| 1573 | "$Rn.addr = $wb", []> { |
| 1574 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1575 | let Inst{4} = Rn{4}; |
| 1576 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1577 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1578 | } |
| 1579 | def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb), |
| 1580 | (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd), |
| 1581 | IIC_VLD1u, |
| 1582 | "vst1", Dt, "$Vd, $Rn, $Rm", |
| 1583 | "$Rn.addr = $wb", []> { |
| 1584 | let Inst{4} = Rn{4}; |
| 1585 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1586 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1587 | } |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1588 | } |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1589 | multiclass VST1QWB<bits<4> op7_4, string Dt> { |
| 1590 | def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1591 | (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u, |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1592 | "vst1", Dt, "$Vd, $Rn!", |
| 1593 | "$Rn.addr = $wb", []> { |
| 1594 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1595 | let Inst{5-4} = Rn{5-4}; |
| 1596 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1597 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1598 | } |
| 1599 | def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1600 | (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd), |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1601 | IIC_VLD1x2u, |
| 1602 | "vst1", Dt, "$Vd, $Rn, $Rm", |
| 1603 | "$Rn.addr = $wb", []> { |
| 1604 | let Inst{5-4} = Rn{5-4}; |
| 1605 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1606 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1607 | } |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1608 | } |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1609 | |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1610 | defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">; |
| 1611 | defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">; |
| 1612 | defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">; |
| 1613 | defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">; |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1614 | |
Jim Grosbach | 4334e03 | 2011-10-31 21:50:31 +0000 | [diff] [blame] | 1615 | defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">; |
| 1616 | defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">; |
| 1617 | defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">; |
| 1618 | defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">; |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1619 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 1620 | // ...with 3 registers |
Bob Wilson | 9580832 | 2010-03-18 20:18:39 +0000 | [diff] [blame] | 1621 | class VST1D3<bits<4> op7_4, string Dt> |
Johnny Chen | f50e83f | 2010-02-24 02:57:20 +0000 | [diff] [blame] | 1622 | : NLdSt<0, 0b00, 0b0110, op7_4, (outs), |
Jim Grosbach | d5ca201 | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1623 | (ins addrmode6:$Rn, VecListThreeD:$Vd), |
| 1624 | IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1625 | let Rm = 0b1111; |
| 1626 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1627 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1628 | } |
Jim Grosbach | d5ca201 | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1629 | multiclass VST1D3WB<bits<4> op7_4, string Dt> { |
| 1630 | def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), |
| 1631 | (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u, |
| 1632 | "vst1", Dt, "$Vd, $Rn!", |
| 1633 | "$Rn.addr = $wb", []> { |
| 1634 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1635 | let Inst{5-4} = Rn{5-4}; |
| 1636 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1637 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1638 | } |
| 1639 | def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), |
| 1640 | (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd), |
| 1641 | IIC_VLD1x3u, |
| 1642 | "vst1", Dt, "$Vd, $Rn, $Rm", |
| 1643 | "$Rn.addr = $wb", []> { |
| 1644 | let Inst{5-4} = Rn{5-4}; |
| 1645 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1646 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1647 | } |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1648 | } |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 1649 | |
Jim Grosbach | d5ca201 | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1650 | def VST1d8T : VST1D3<{0,0,0,?}, "8">; |
| 1651 | def VST1d16T : VST1D3<{0,1,0,?}, "16">; |
| 1652 | def VST1d32T : VST1D3<{1,0,0,?}, "32">; |
| 1653 | def VST1d64T : VST1D3<{1,1,0,?}, "64">; |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 1654 | |
Jim Grosbach | d5ca201 | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1655 | defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">; |
| 1656 | defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">; |
| 1657 | defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">; |
| 1658 | defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">; |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 1659 | |
Jim Grosbach | d5ca201 | 2011-11-29 22:38:04 +0000 | [diff] [blame] | 1660 | def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>; |
| 1661 | def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>; |
| 1662 | def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>; |
Bob Wilson | 01ba461 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1663 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 1664 | // ...with 4 registers |
Bob Wilson | 052ba45 | 2010-03-22 18:22:06 +0000 | [diff] [blame] | 1665 | class VST1D4<bits<4> op7_4, string Dt> |
| 1666 | : NLdSt<0, 0b00, 0b0010, op7_4, (outs), |
Jim Grosbach | 4c7edb3 | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1667 | (ins addrmode6:$Rn, VecListFourD:$Vd), |
| 1668 | IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "", |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1669 | []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1670 | let Rm = 0b1111; |
| 1671 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1672 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1673 | } |
Jim Grosbach | 4c7edb3 | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1674 | multiclass VST1D4WB<bits<4> op7_4, string Dt> { |
| 1675 | def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), |
| 1676 | (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u, |
| 1677 | "vst1", Dt, "$Vd, $Rn!", |
| 1678 | "$Rn.addr = $wb", []> { |
| 1679 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
| 1680 | let Inst{5-4} = Rn{5-4}; |
| 1681 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1682 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1683 | } |
| 1684 | def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), |
| 1685 | (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), |
| 1686 | IIC_VLD1x4u, |
| 1687 | "vst1", Dt, "$Vd, $Rn, $Rm", |
| 1688 | "$Rn.addr = $wb", []> { |
| 1689 | let Inst{5-4} = Rn{5-4}; |
| 1690 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1691 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1692 | } |
Owen Anderson | cfebe3a | 2010-11-02 21:06:06 +0000 | [diff] [blame] | 1693 | } |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1694 | |
Jim Grosbach | 4c7edb3 | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1695 | def VST1d8Q : VST1D4<{0,0,?,?}, "8">; |
| 1696 | def VST1d16Q : VST1D4<{0,1,?,?}, "16">; |
| 1697 | def VST1d32Q : VST1D4<{1,0,?,?}, "32">; |
| 1698 | def VST1d64Q : VST1D4<{1,1,?,?}, "64">; |
Bob Wilson | 25eb501 | 2010-03-20 20:54:36 +0000 | [diff] [blame] | 1699 | |
Jim Grosbach | 4c7edb3 | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1700 | defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">; |
| 1701 | defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">; |
| 1702 | defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">; |
| 1703 | defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">; |
Bob Wilson | 9f7d60f | 2009-08-12 17:04:56 +0000 | [diff] [blame] | 1704 | |
Jim Grosbach | 4c7edb3 | 2011-11-29 22:58:48 +0000 | [diff] [blame] | 1705 | def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>; |
| 1706 | def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>; |
| 1707 | def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>; |
Bob Wilson | 70e48b2 | 2010-08-26 05:33:30 +0000 | [diff] [blame] | 1708 | |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1709 | // VST2 : Vector Store (multiple 2-element structures) |
Jim Grosbach | 20accfc | 2011-12-14 20:59:15 +0000 | [diff] [blame] | 1710 | class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, |
| 1711 | InstrItinClass itin> |
Jim Grosbach | e90ac9b | 2011-12-14 19:35:22 +0000 | [diff] [blame] | 1712 | : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd), |
Jim Grosbach | 20accfc | 2011-12-14 20:59:15 +0000 | [diff] [blame] | 1713 | itin, "vst2", Dt, "$Vd, $Rn", "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1714 | let Rm = 0b1111; |
| 1715 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1716 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | d2f3794 | 2010-11-02 21:16:58 +0000 | [diff] [blame] | 1717 | } |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1718 | |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1719 | def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>; |
| 1720 | def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>; |
| 1721 | def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>; |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1722 | |
Jim Grosbach | 20accfc | 2011-12-14 20:59:15 +0000 | [diff] [blame] | 1723 | def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>; |
| 1724 | def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>; |
| 1725 | def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>; |
Bob Wilson | d285575 | 2009-10-07 18:47:39 +0000 | [diff] [blame] | 1726 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1727 | def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>; |
| 1728 | def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>; |
| 1729 | def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>; |
Bob Wilson | e5ce4f6 | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1730 | |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1731 | // ...with address register writeback: |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1732 | multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, |
| 1733 | RegisterOperand VdTy> { |
| 1734 | def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), |
| 1735 | (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u, |
| 1736 | "vst2", Dt, "$Vd, $Rn!", |
| 1737 | "$Rn.addr = $wb", []> { |
| 1738 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
Jim Grosbach | ec04a3f | 2011-12-14 21:49:24 +0000 | [diff] [blame] | 1739 | let Inst{5-4} = Rn{5-4}; |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1740 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1741 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1742 | } |
| 1743 | def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), |
| 1744 | (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u, |
| 1745 | "vst2", Dt, "$Vd, $Rn, $Rm", |
| 1746 | "$Rn.addr = $wb", []> { |
Jim Grosbach | ec04a3f | 2011-12-14 21:49:24 +0000 | [diff] [blame] | 1747 | let Inst{5-4} = Rn{5-4}; |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1748 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1749 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1750 | } |
Owen Anderson | d2f3794 | 2010-11-02 21:16:58 +0000 | [diff] [blame] | 1751 | } |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1752 | multiclass VST2QWB<bits<4> op7_4, string Dt> { |
| 1753 | def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), |
| 1754 | (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u, |
| 1755 | "vst2", Dt, "$Vd, $Rn!", |
| 1756 | "$Rn.addr = $wb", []> { |
| 1757 | let Rm = 0b1101; // NLdSt will assign to the right encoding bits. |
Jim Grosbach | ec04a3f | 2011-12-14 21:49:24 +0000 | [diff] [blame] | 1758 | let Inst{5-4} = Rn{5-4}; |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1759 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1760 | let AsmMatchConverter = "cvtVSTwbFixed"; |
| 1761 | } |
| 1762 | def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), |
| 1763 | (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), |
| 1764 | IIC_VLD1u, |
| 1765 | "vst2", Dt, "$Vd, $Rn, $Rm", |
| 1766 | "$Rn.addr = $wb", []> { |
Jim Grosbach | ec04a3f | 2011-12-14 21:49:24 +0000 | [diff] [blame] | 1767 | let Inst{5-4} = Rn{5-4}; |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1768 | let DecoderMethod = "DecodeVSTInstruction"; |
| 1769 | let AsmMatchConverter = "cvtVSTwbRegister"; |
| 1770 | } |
Owen Anderson | d2f3794 | 2010-11-02 21:16:58 +0000 | [diff] [blame] | 1771 | } |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1772 | |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 1773 | defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>; |
| 1774 | defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>; |
| 1775 | defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>; |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1776 | |
Jim Grosbach | bb3a2e4 | 2011-12-14 21:32:11 +0000 | [diff] [blame] | 1777 | defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">; |
| 1778 | defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">; |
| 1779 | defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">; |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1780 | |
Jim Grosbach | 6d56730 | 2012-01-20 19:16:00 +0000 | [diff] [blame] | 1781 | def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; |
| 1782 | def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; |
| 1783 | def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; |
| 1784 | def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; |
| 1785 | def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; |
| 1786 | def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; |
Bob Wilson | e5ce4f6 | 2010-08-28 05:12:57 +0000 | [diff] [blame] | 1787 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 1788 | // ...with double-spaced registers |
Jim Grosbach | c3384c9 | 2012-03-05 21:43:40 +0000 | [diff] [blame] | 1789 | def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>; |
| 1790 | def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>; |
| 1791 | def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>; |
| 1792 | defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>; |
| 1793 | defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>; |
| 1794 | defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>; |
Johnny Chen | f50e83f | 2010-02-24 02:57:20 +0000 | [diff] [blame] | 1795 | |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1796 | // VST3 : Vector Store (multiple 3-element structures) |
Bob Wilson | 068b18b | 2010-03-20 21:15:48 +0000 | [diff] [blame] | 1797 | class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 1798 | : NLdSt<0, 0b00, op11_8, op7_4, (outs), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1799 | (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, |
| 1800 | "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { |
| 1801 | let Rm = 0b1111; |
| 1802 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1803 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1804 | } |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1805 | |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1806 | def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; |
| 1807 | def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">; |
| 1808 | def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">; |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1809 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1810 | def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>; |
| 1811 | def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>; |
| 1812 | def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>; |
Bob Wilson | 01ba461 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1813 | |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1814 | // ...with address register writeback: |
| 1815 | class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 1816 | : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1817 | (ins addrmode6:$Rn, am6offset:$Rm, |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1818 | DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1819 | "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", |
| 1820 | "$Rn.addr = $wb", []> { |
| 1821 | let Inst{4} = Rn{4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1822 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1823 | } |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1824 | |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1825 | def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; |
| 1826 | def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">; |
| 1827 | def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">; |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1828 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1829 | def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; |
| 1830 | def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; |
| 1831 | def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; |
Bob Wilson | 01ba461 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1832 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1833 | // ...with double-spaced registers: |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1834 | def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">; |
| 1835 | def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">; |
| 1836 | def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">; |
| 1837 | def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">; |
| 1838 | def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">; |
| 1839 | def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">; |
Bob Wilson | 068b18b | 2010-03-20 21:15:48 +0000 | [diff] [blame] | 1840 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1841 | def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
| 1842 | def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
| 1843 | def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
Bob Wilson | 01ba461 | 2010-08-26 18:51:29 +0000 | [diff] [blame] | 1844 | |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1845 | // ...alternate versions to be allocated odd register numbers: |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1846 | def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>; |
| 1847 | def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>; |
| 1848 | def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>; |
| 1849 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1850 | def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
| 1851 | def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
| 1852 | def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; |
Bob Wilson | 66a7063 | 2009-10-07 20:30:08 +0000 | [diff] [blame] | 1853 | |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1854 | // VST4 : Vector Store (multiple 4-element structures) |
Bob Wilson | 068b18b | 2010-03-20 21:15:48 +0000 | [diff] [blame] | 1855 | class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 1856 | : NLdSt<0, 0b00, op11_8, op7_4, (outs), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1857 | (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), |
| 1858 | IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1859 | "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1860 | let Rm = 0b1111; |
| 1861 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1862 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1863 | } |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 1864 | |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1865 | def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; |
| 1866 | def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">; |
| 1867 | def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">; |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 1868 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1869 | def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>; |
| 1870 | def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>; |
| 1871 | def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>; |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1872 | |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1873 | // ...with address register writeback: |
| 1874 | class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
| 1875 | : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1876 | (ins addrmode6:$Rn, am6offset:$Rm, |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1877 | DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1878 | "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", |
| 1879 | "$Rn.addr = $wb", []> { |
| 1880 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 1881 | let DecoderMethod = "DecodeVSTInstruction"; |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1882 | } |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1883 | |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1884 | def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; |
| 1885 | def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">; |
| 1886 | def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">; |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1887 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1888 | def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; |
| 1889 | def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; |
| 1890 | def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1891 | |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1892 | // ...with double-spaced registers: |
Owen Anderson | a1a45fd | 2010-11-02 21:47:03 +0000 | [diff] [blame] | 1893 | def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">; |
| 1894 | def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">; |
| 1895 | def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">; |
| 1896 | def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">; |
| 1897 | def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">; |
| 1898 | def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">; |
Bob Wilson | 068b18b | 2010-03-20 21:15:48 +0000 | [diff] [blame] | 1899 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1900 | def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
| 1901 | def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
| 1902 | def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
Bob Wilson | 709d592 | 2010-08-25 23:27:42 +0000 | [diff] [blame] | 1903 | |
Bob Wilson | 4f4f93f | 2010-03-20 21:45:18 +0000 | [diff] [blame] | 1904 | // ...alternate versions to be allocated odd register numbers: |
Bob Wilson | 7de6814 | 2011-02-07 17:43:15 +0000 | [diff] [blame] | 1905 | def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>; |
| 1906 | def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>; |
| 1907 | def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>; |
| 1908 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 1909 | def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
| 1910 | def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
| 1911 | def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1912 | |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1913 | } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 |
| 1914 | |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 1915 | // Classes for VST*LN pseudo-instructions with multi-register operands. |
| 1916 | // These are expanded to real instructions after register allocation. |
| 1917 | class VSTQLNPseudo<InstrItinClass itin> |
| 1918 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), |
| 1919 | itin, "">; |
| 1920 | class VSTQLNWBPseudo<InstrItinClass itin> |
| 1921 | : PseudoNLdSt<(outs GPR:$wb), |
| 1922 | (ins addrmode6:$addr, am6offset:$offset, QPR:$src, |
| 1923 | nohash_imm:$lane), itin, "$addr.addr = $wb">; |
| 1924 | class VSTQQLNPseudo<InstrItinClass itin> |
| 1925 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), |
| 1926 | itin, "">; |
| 1927 | class VSTQQLNWBPseudo<InstrItinClass itin> |
| 1928 | : PseudoNLdSt<(outs GPR:$wb), |
| 1929 | (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, |
| 1930 | nohash_imm:$lane), itin, "$addr.addr = $wb">; |
| 1931 | class VSTQQQQLNPseudo<InstrItinClass itin> |
| 1932 | : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), |
| 1933 | itin, "">; |
| 1934 | class VSTQQQQLNWBPseudo<InstrItinClass itin> |
| 1935 | : PseudoNLdSt<(outs GPR:$wb), |
| 1936 | (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, |
| 1937 | nohash_imm:$lane), itin, "$addr.addr = $wb">; |
| 1938 | |
Bob Wilson | b07c171 | 2009-10-07 21:53:04 +0000 | [diff] [blame] | 1939 | // VST1LN : Vector Store (single element from one lane) |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1940 | class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1941 | PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode> |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1942 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs), |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1943 | (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane), |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1944 | IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1945 | [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> { |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 1946 | let Rm = 0b1111; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1947 | let DecoderMethod = "DecodeVST1LN"; |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 1948 | } |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1949 | class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> |
| 1950 | : VSTQLNPseudo<IIC_VST1ln> { |
| 1951 | let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), |
| 1952 | addrmode6:$addr)]; |
| 1953 | } |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1954 | |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1955 | def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1956 | NEONvgetlaneu, addrmode6> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1957 | let Inst{7-5} = lane{2-0}; |
| 1958 | } |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1959 | def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1960 | NEONvgetlaneu, addrmode6> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1961 | let Inst{7-6} = lane{1-0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1962 | let Inst{4} = Rn{5}; |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1963 | } |
Mon P Wang | 183c627 | 2011-05-09 17:47:27 +0000 | [diff] [blame] | 1964 | |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 1965 | def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1966 | addrmode6oneL32> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1967 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1968 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1969 | } |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1970 | |
Bob Wilson | d168cef | 2010-11-03 16:24:53 +0000 | [diff] [blame] | 1971 | def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>; |
| 1972 | def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>; |
| 1973 | def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>; |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1974 | |
Bob Wilson | 746fa17 | 2010-12-10 22:13:32 +0000 | [diff] [blame] | 1975 | def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr), |
| 1976 | (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; |
| 1977 | def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr), |
| 1978 | (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; |
| 1979 | |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1980 | // ...with address register writeback: |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 1981 | class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1982 | PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode> |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1983 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1984 | (ins AdrMode:$Rn, am6offset:$Rm, |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 1985 | DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 1986 | "\\{$Vd[$lane]\\}, $Rn$Rm", |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 1987 | "$Rn.addr = $wb", |
| 1988 | [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1989 | AdrMode:$Rn, am6offset:$Rm))]> { |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 1990 | let DecoderMethod = "DecodeVST1LN"; |
| 1991 | } |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 1992 | class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> |
| 1993 | : VSTQLNWBPseudo<IIC_VST1lnu> { |
| 1994 | let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), |
| 1995 | addrmode6:$addr, am6offset:$offset))]; |
| 1996 | } |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 1997 | |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 1998 | def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 1999 | NEONvgetlaneu, addrmode6> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 2000 | let Inst{7-5} = lane{2-0}; |
| 2001 | } |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 2002 | def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 2003 | NEONvgetlaneu, addrmode6> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 2004 | let Inst{7-6} = lane{1-0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2005 | let Inst{4} = Rn{5}; |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 2006 | } |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 2007 | def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store, |
Richard Barton | 6e9d66c | 2012-03-28 10:18:11 +0000 | [diff] [blame] | 2008 | extractelt, addrmode6oneL32> { |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 2009 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2010 | let Inst{5-4} = Rn{5-4}; |
Owen Anderson | e95c946 | 2010-11-02 21:54:45 +0000 | [diff] [blame] | 2011 | } |
Bob Wilson | d0c6bc2 | 2010-11-02 21:18:25 +0000 | [diff] [blame] | 2012 | |
Bob Wilson | da52506 | 2011-02-25 06:42:42 +0000 | [diff] [blame] | 2013 | def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>; |
| 2014 | def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>; |
| 2015 | def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>; |
| 2016 | |
| 2017 | let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { |
Bob Wilson | 63c9063 | 2009-10-07 20:49:18 +0000 | [diff] [blame] | 2018 | |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2019 | // VST2LN : Vector Store (single 2-element structure from one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2020 | class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2021 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2022 | (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), |
| 2023 | IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2024 | "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2025 | let Rm = 0b1111; |
| 2026 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2027 | let DecoderMethod = "DecodeVST2LN"; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2028 | } |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2029 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2030 | def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { |
| 2031 | let Inst{7-5} = lane{2-0}; |
| 2032 | } |
| 2033 | def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> { |
| 2034 | let Inst{7-6} = lane{1-0}; |
| 2035 | } |
| 2036 | def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> { |
| 2037 | let Inst{7} = lane{0}; |
| 2038 | } |
Bob Wilson | c5c6edb | 2009-10-08 23:38:24 +0000 | [diff] [blame] | 2039 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2040 | def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>; |
| 2041 | def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>; |
| 2042 | def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2043 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 2044 | // ...with double-spaced registers: |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2045 | def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { |
| 2046 | let Inst{7-6} = lane{1-0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2047 | let Inst{4} = Rn{4}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2048 | } |
| 2049 | def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { |
| 2050 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2051 | let Inst{4} = Rn{4}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2052 | } |
Bob Wilson | c5c6edb | 2009-10-08 23:38:24 +0000 | [diff] [blame] | 2053 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2054 | def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>; |
| 2055 | def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>; |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2056 | |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2057 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2058 | class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2059 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 2060 | (ins addrmode6:$Rn, am6offset:$Rm, |
| 2061 | DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, |
| 2062 | "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm", |
| 2063 | "$Rn.addr = $wb", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2064 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2065 | let DecoderMethod = "DecodeVST2LN"; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2066 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2067 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2068 | def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { |
| 2069 | let Inst{7-5} = lane{2-0}; |
| 2070 | } |
| 2071 | def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> { |
| 2072 | let Inst{7-6} = lane{1-0}; |
| 2073 | } |
| 2074 | def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> { |
| 2075 | let Inst{7} = lane{0}; |
| 2076 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2077 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2078 | def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; |
| 2079 | def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; |
| 2080 | def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2081 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2082 | def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> { |
| 2083 | let Inst{7-6} = lane{1-0}; |
| 2084 | } |
| 2085 | def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> { |
| 2086 | let Inst{7} = lane{0}; |
| 2087 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2088 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2089 | def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>; |
| 2090 | def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2091 | |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2092 | // VST3LN : Vector Store (single 3-element structure from one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2093 | class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2094 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2095 | (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2096 | nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2097 | "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> { |
| 2098 | let Rm = 0b1111; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2099 | let DecoderMethod = "DecodeVST3LN"; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2100 | } |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2101 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2102 | def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { |
| 2103 | let Inst{7-5} = lane{2-0}; |
| 2104 | } |
| 2105 | def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> { |
| 2106 | let Inst{7-6} = lane{1-0}; |
| 2107 | } |
| 2108 | def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> { |
| 2109 | let Inst{7} = lane{0}; |
| 2110 | } |
Bob Wilson | 8cdb269 | 2009-10-08 23:51:31 +0000 | [diff] [blame] | 2111 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2112 | def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>; |
| 2113 | def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>; |
| 2114 | def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2115 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 2116 | // ...with double-spaced registers: |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2117 | def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> { |
| 2118 | let Inst{7-6} = lane{1-0}; |
| 2119 | } |
| 2120 | def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> { |
| 2121 | let Inst{7} = lane{0}; |
| 2122 | } |
Bob Wilson | 8cdb269 | 2009-10-08 23:51:31 +0000 | [diff] [blame] | 2123 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2124 | def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>; |
| 2125 | def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>; |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2126 | |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2127 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2128 | class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2129 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2130 | (ins addrmode6:$Rn, am6offset:$Rm, |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2131 | DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2132 | IIC_VST3lnu, "vst3", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2133 | "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2134 | "$Rn.addr = $wb", []> { |
| 2135 | let DecoderMethod = "DecodeVST3LN"; |
| 2136 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2137 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2138 | def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { |
| 2139 | let Inst{7-5} = lane{2-0}; |
| 2140 | } |
| 2141 | def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> { |
| 2142 | let Inst{7-6} = lane{1-0}; |
| 2143 | } |
| 2144 | def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> { |
| 2145 | let Inst{7} = lane{0}; |
| 2146 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2147 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2148 | def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; |
| 2149 | def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; |
| 2150 | def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2151 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2152 | def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> { |
| 2153 | let Inst{7-6} = lane{1-0}; |
| 2154 | } |
| 2155 | def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> { |
| 2156 | let Inst{7} = lane{0}; |
| 2157 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2158 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2159 | def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>; |
| 2160 | def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2161 | |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2162 | // VST4LN : Vector Store (single 4-element structure from one lane) |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2163 | class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2164 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2165 | (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2166 | nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2167 | "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2168 | "", []> { |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2169 | let Rm = 0b1111; |
| 2170 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2171 | let DecoderMethod = "DecodeVST4LN"; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2172 | } |
Bob Wilson | 8a3198b | 2009-09-01 18:51:56 +0000 | [diff] [blame] | 2173 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2174 | def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { |
| 2175 | let Inst{7-5} = lane{2-0}; |
| 2176 | } |
| 2177 | def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> { |
| 2178 | let Inst{7-6} = lane{1-0}; |
| 2179 | } |
| 2180 | def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { |
| 2181 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2182 | let Inst{5} = Rn{5}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2183 | } |
Bob Wilson | 5631139 | 2009-10-09 00:01:36 +0000 | [diff] [blame] | 2184 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2185 | def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>; |
| 2186 | def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>; |
| 2187 | def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2188 | |
Bob Wilson | 4131528 | 2010-03-20 20:39:53 +0000 | [diff] [blame] | 2189 | // ...with double-spaced registers: |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2190 | def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> { |
| 2191 | let Inst{7-6} = lane{1-0}; |
| 2192 | } |
| 2193 | def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { |
| 2194 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2195 | let Inst{5} = Rn{5}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2196 | } |
Bob Wilson | 5631139 | 2009-10-09 00:01:36 +0000 | [diff] [blame] | 2197 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2198 | def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>; |
| 2199 | def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>; |
Bob Wilson | 5631139 | 2009-10-09 00:01:36 +0000 | [diff] [blame] | 2200 | |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2201 | // ...with address register writeback: |
Bob Wilson | 3984255 | 2010-03-22 16:43:10 +0000 | [diff] [blame] | 2202 | class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2203 | : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2204 | (ins addrmode6:$Rn, am6offset:$Rm, |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2205 | DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2206 | IIC_VST4lnu, "vst4", Dt, |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2207 | "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", |
| 2208 | "$Rn.addr = $wb", []> { |
| 2209 | let Inst{4} = Rn{4}; |
Owen Anderson | 7a2e177 | 2011-08-15 18:44:44 +0000 | [diff] [blame] | 2210 | let DecoderMethod = "DecodeVST4LN"; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2211 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2212 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2213 | def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { |
| 2214 | let Inst{7-5} = lane{2-0}; |
| 2215 | } |
| 2216 | def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> { |
| 2217 | let Inst{7-6} = lane{1-0}; |
| 2218 | } |
| 2219 | def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { |
| 2220 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2221 | let Inst{5} = Rn{5}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2222 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2223 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2224 | def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; |
| 2225 | def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; |
| 2226 | def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2227 | |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2228 | def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> { |
| 2229 | let Inst{7-6} = lane{1-0}; |
| 2230 | } |
| 2231 | def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { |
| 2232 | let Inst{7} = lane{0}; |
Owen Anderson | f431eda | 2010-11-02 23:47:29 +0000 | [diff] [blame] | 2233 | let Inst{5} = Rn{5}; |
Owen Anderson | b20594f | 2010-11-02 22:18:18 +0000 | [diff] [blame] | 2234 | } |
Bob Wilson | d5fadaf | 2010-03-20 21:57:36 +0000 | [diff] [blame] | 2235 | |
Evan Cheng | 60ff879 | 2010-10-11 22:03:18 +0000 | [diff] [blame] | 2236 | def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>; |
| 2237 | def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>; |
Bob Wilson | 8466fa1 | 2010-09-13 23:01:35 +0000 | [diff] [blame] | 2238 | |
Evan Cheng | 5fd1c9b | 2010-05-19 06:07:03 +0000 | [diff] [blame] | 2239 | } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 |
Bob Wilson | b36ec86 | 2009-08-06 18:47:44 +0000 | [diff] [blame] | 2240 | |
Bob Wilson | 205a5ca | 2009-07-08 18:11:30 +0000 | [diff] [blame] | 2241 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2242 | //===----------------------------------------------------------------------===// |
| 2243 | // NEON pattern fragments |
| 2244 | //===----------------------------------------------------------------------===// |
| 2245 | |
| 2246 | // Extract D sub-registers of Q registers. |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2247 | def DSubReg_i8_reg : SDNodeXForm<imm, [{ |
Jakob Stoklund Olesen | 7bb31e3 | 2010-05-24 17:13:28 +0000 | [diff] [blame] | 2248 | assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); |
| 2249 | return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2250 | }]>; |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2251 | def DSubReg_i16_reg : SDNodeXForm<imm, [{ |
Jakob Stoklund Olesen | 7bb31e3 | 2010-05-24 17:13:28 +0000 | [diff] [blame] | 2252 | assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); |
| 2253 | return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2254 | }]>; |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2255 | def DSubReg_i32_reg : SDNodeXForm<imm, [{ |
Jakob Stoklund Olesen | 7bb31e3 | 2010-05-24 17:13:28 +0000 | [diff] [blame] | 2256 | assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); |
| 2257 | return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2258 | }]>; |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2259 | def DSubReg_f64_reg : SDNodeXForm<imm, [{ |
Jakob Stoklund Olesen | 7bb31e3 | 2010-05-24 17:13:28 +0000 | [diff] [blame] | 2260 | assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); |
| 2261 | return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2262 | }]>; |
| 2263 | |
Anton Korobeynikov | 2324bdc | 2009-08-28 23:41:26 +0000 | [diff] [blame] | 2264 | // Extract S sub-registers of Q/D registers. |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2265 | def SSubReg_f32_reg : SDNodeXForm<imm, [{ |
Jakob Stoklund Olesen | 7bb31e3 | 2010-05-24 17:13:28 +0000 | [diff] [blame] | 2266 | assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); |
| 2267 | return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32); |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 2268 | }]>; |
| 2269 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2270 | // Translate lane numbers from Q registers to D subregs. |
| 2271 | def SubReg_i8_lane : SDNodeXForm<imm, [{ |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 2272 | return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2273 | }]>; |
| 2274 | def SubReg_i16_lane : SDNodeXForm<imm, [{ |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 2275 | return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2276 | }]>; |
| 2277 | def SubReg_i32_lane : SDNodeXForm<imm, [{ |
Owen Anderson | 825b72b | 2009-08-11 20:47:22 +0000 | [diff] [blame] | 2278 | return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2279 | }]>; |
| 2280 | |
| 2281 | //===----------------------------------------------------------------------===// |
| 2282 | // Instruction Classes |
| 2283 | //===----------------------------------------------------------------------===// |
| 2284 | |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 2285 | // Basic 2-register operations: double- and quad-register. |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2286 | class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 2287 | bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, |
| 2288 | string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2289 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), |
| 2290 | (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "", |
| 2291 | [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2292 | class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 2293 | bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, |
| 2294 | string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2295 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), |
| 2296 | (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "", |
| 2297 | [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2298 | |
Bob Wilson | 69bfbd6 | 2010-02-17 22:42:54 +0000 | [diff] [blame] | 2299 | // Basic 2-register intrinsics, both double- and quad-register. |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2300 | class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Johnny Chen | fa80bec | 2010-03-25 20:39:04 +0000 | [diff] [blame] | 2301 | bits<2> op17_16, bits<5> op11_7, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2302 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2303 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2304 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), |
| 2305 | (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2306 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2307 | class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 2308 | bits<2> op17_16, bits<5> op11_7, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2309 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2310 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2311 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), |
| 2312 | (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2313 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2314 | |
Bob Wilson | 973a074 | 2010-08-30 20:02:30 +0000 | [diff] [blame] | 2315 | // Narrow 2-register operations. |
| 2316 | class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
| 2317 | bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, |
| 2318 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2319 | ValueType TyD, ValueType TyQ, SDNode OpNode> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2320 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), |
| 2321 | (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2322 | [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>; |
Bob Wilson | 973a074 | 2010-08-30 20:02:30 +0000 | [diff] [blame] | 2323 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2324 | // Narrow 2-register intrinsics. |
| 2325 | class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
| 2326 | bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2327 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2328 | ValueType TyD, ValueType TyQ, SDPatternOperator IntOp> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2329 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), |
| 2330 | (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2331 | [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2332 | |
Bob Wilson | b31a11b | 2010-08-20 04:54:02 +0000 | [diff] [blame] | 2333 | // Long 2-register operations (currently only used for VMOVL). |
| 2334 | class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
| 2335 | bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, |
| 2336 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2337 | ValueType TyQ, ValueType TyD, SDNode OpNode> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2338 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd), |
| 2339 | (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2340 | [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2341 | |
Bob Wilson | 0406356 | 2010-12-15 22:14:12 +0000 | [diff] [blame] | 2342 | // Long 2-register intrinsics. |
| 2343 | class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
| 2344 | bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, |
| 2345 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2346 | ValueType TyQ, ValueType TyD, SDPatternOperator IntOp> |
Bob Wilson | 0406356 | 2010-12-15 22:14:12 +0000 | [diff] [blame] | 2347 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd), |
| 2348 | (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2349 | [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>; |
| 2350 | |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 2351 | // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2352 | class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2353 | : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm), |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2354 | (ins DPR:$src1, DPR:$src2), IIC_VPERMD, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2355 | OpcodeStr, Dt, "$Vd, $Vm", |
| 2356 | "$src1 = $Vd, $src2 = $Vm", []>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 2357 | class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2358 | InstrItinClass itin, string OpcodeStr, string Dt> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2359 | : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm), |
| 2360 | (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm", |
| 2361 | "$src1 = $Vd, $src2 = $Vm", []>; |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 2362 | |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 2363 | // Basic 3-register operations: double- and quad-register. |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2364 | class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2365 | InstrItinClass itin, string OpcodeStr, string Dt, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2366 | ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2367 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | d451f88 | 2010-10-21 20:21:49 +0000 | [diff] [blame] | 2368 | (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2369 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2370 | [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2371 | // All of these have a two-operand InstAlias. |
| 2372 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2373 | let isCommutable = Commutable; |
| 2374 | } |
| 2375 | // Same as N3VD but no data type. |
| 2376 | class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2377 | InstrItinClass itin, string OpcodeStr, |
| 2378 | ValueType ResTy, ValueType OpTy, |
| 2379 | SDNode OpNode, bit Commutable> |
| 2380 | : N3VX<op24, op23, op21_20, op11_8, 0, op4, |
Jim Grosbach | efaeb41 | 2010-11-19 22:36:02 +0000 | [diff] [blame] | 2381 | (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2382 | OpcodeStr, "$Vd, $Vn, $Vm", "", |
| 2383 | [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{ |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2384 | // All of these have a two-operand InstAlias. |
| 2385 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2386 | let isCommutable = Commutable; |
| 2387 | } |
Johnny Chen | 897dd0c | 2010-03-27 01:03:13 +0000 | [diff] [blame] | 2388 | |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2389 | class N3VDSL<bits<2> op21_20, bits<4> op11_8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2390 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2391 | ValueType Ty, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2392 | : N3VLane32<0, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | 970f787 | 2011-10-18 18:01:52 +0000 | [diff] [blame] | 2393 | (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2394 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2395 | [(set (Ty DPR:$Vd), |
| 2396 | (Ty (ShOp (Ty DPR:$Vn), |
| 2397 | (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> { |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 2398 | // All of these have a two-operand InstAlias. |
| 2399 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2400 | let isCommutable = 0; |
| 2401 | } |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2402 | class N3VDSL16<bits<2> op21_20, bits<4> op11_8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2403 | string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2404 | : N3VLane16<0, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | 970f787 | 2011-10-18 18:01:52 +0000 | [diff] [blame] | 2405 | (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2406 | NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2407 | [(set (Ty DPR:$Vd), |
| 2408 | (Ty (ShOp (Ty DPR:$Vn), |
| 2409 | (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 2410 | // All of these have a two-operand InstAlias. |
| 2411 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2412 | let isCommutable = 0; |
| 2413 | } |
| 2414 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2415 | class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2416 | InstrItinClass itin, string OpcodeStr, string Dt, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2417 | ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2418 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2419 | (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin, |
| 2420 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2421 | [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> { |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2422 | // All of these have a two-operand InstAlias. |
| 2423 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2424 | let isCommutable = Commutable; |
| 2425 | } |
| 2426 | class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2427 | InstrItinClass itin, string OpcodeStr, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2428 | ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2429 | : N3VX<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2430 | (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin, |
| 2431 | OpcodeStr, "$Vd, $Vn, $Vm", "", |
| 2432 | [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{ |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2433 | // All of these have a two-operand InstAlias. |
| 2434 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2435 | let isCommutable = Commutable; |
| 2436 | } |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2437 | class N3VQSL<bits<2> op21_20, bits<4> op11_8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2438 | InstrItinClass itin, string OpcodeStr, string Dt, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2439 | ValueType ResTy, ValueType OpTy, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2440 | : N3VLane32<1, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2441 | (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2442 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2443 | [(set (ResTy QPR:$Vd), |
| 2444 | (ResTy (ShOp (ResTy QPR:$Vn), |
| 2445 | (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2446 | imm:$lane)))))]> { |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 2447 | // All of these have a two-operand InstAlias. |
| 2448 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2449 | let isCommutable = 0; |
| 2450 | } |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2451 | class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2452 | ValueType ResTy, ValueType OpTy, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2453 | : N3VLane16<1, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2454 | (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2455 | NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2456 | [(set (ResTy QPR:$Vd), |
| 2457 | (ResTy (ShOp (ResTy QPR:$Vn), |
| 2458 | (ResTy (NEONvduplane (OpTy DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2459 | imm:$lane)))))]> { |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 2460 | // All of these have a two-operand InstAlias. |
| 2461 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2462 | let isCommutable = 0; |
| 2463 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2464 | |
| 2465 | // Basic 3-register intrinsics, both double- and quad-register. |
| 2466 | class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 2467 | Format f, InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2468 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2469 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | d451f88 | 2010-10-21 20:21:49 +0000 | [diff] [blame] | 2470 | (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, |
| 2471 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2472 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2473 | // All of these have a two-operand InstAlias. |
| 2474 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2475 | let isCommutable = Commutable; |
| 2476 | } |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2477 | class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2478 | string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2479 | : N3VLane32<0, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | 0a03740 | 2011-10-18 18:12:09 +0000 | [diff] [blame] | 2480 | (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2481 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2482 | [(set (Ty DPR:$Vd), |
| 2483 | (Ty (IntOp (Ty DPR:$Vn), |
| 2484 | (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2485 | imm:$lane)))))]> { |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2486 | let isCommutable = 0; |
| 2487 | } |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2488 | class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2489 | string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2490 | : N3VLane16<0, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | 0a03740 | 2011-10-18 18:12:09 +0000 | [diff] [blame] | 2491 | (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2492 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2493 | [(set (Ty DPR:$Vd), |
| 2494 | (Ty (IntOp (Ty DPR:$Vn), |
| 2495 | (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2496 | let isCommutable = 0; |
| 2497 | } |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2498 | class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2499 | Format f, InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2500 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2501 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
| 2502 | (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin, |
| 2503 | OpcodeStr, Dt, "$Vd, $Vm, $Vn", "", |
| 2504 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> { |
Jim Grosbach | d83c9ea | 2012-04-20 23:30:14 +0000 | [diff] [blame] | 2505 | let TwoOperandAliasConstraint = "$Vm = $Vd"; |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 2506 | let isCommutable = 0; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2507 | } |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2508 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2509 | class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 2510 | Format f, InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2511 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable> |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2512 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | d451f88 | 2010-10-21 20:21:49 +0000 | [diff] [blame] | 2513 | (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, |
| 2514 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2515 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> { |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2516 | // All of these have a two-operand InstAlias. |
| 2517 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2518 | let isCommutable = Commutable; |
| 2519 | } |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 2520 | class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2521 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2522 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2523 | : N3VLane32<1, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2524 | (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2525 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2526 | [(set (ResTy QPR:$Vd), |
| 2527 | (ResTy (IntOp (ResTy QPR:$Vn), |
| 2528 | (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2529 | imm:$lane)))))]> { |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2530 | let isCommutable = 0; |
| 2531 | } |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2532 | class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2533 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2534 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2535 | : N3VLane16<1, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2536 | (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2537 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2538 | [(set (ResTy QPR:$Vd), |
| 2539 | (ResTy (IntOp (ResTy QPR:$Vn), |
| 2540 | (ResTy (NEONvduplane (OpTy DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2541 | imm:$lane)))))]> { |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2542 | let isCommutable = 0; |
| 2543 | } |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2544 | class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2545 | Format f, InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2546 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2547 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
| 2548 | (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin, |
| 2549 | OpcodeStr, Dt, "$Vd, $Vm, $Vn", "", |
| 2550 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> { |
Jim Grosbach | d83c9ea | 2012-04-20 23:30:14 +0000 | [diff] [blame] | 2551 | let TwoOperandAliasConstraint = "$Vm = $Vd"; |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 2552 | let isCommutable = 0; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 2553 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2554 | |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 2555 | // Multiply-Add/Sub operations: double- and quad-register. |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2556 | class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2557 | InstrItinClass itin, string OpcodeStr, string Dt, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 2558 | ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2559 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | 18341e9 | 2010-10-22 18:54:37 +0000 | [diff] [blame] | 2560 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2561 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2562 | [(set DPR:$Vd, (Ty (OpNode DPR:$src1, |
| 2563 | (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>; |
| 2564 | |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2565 | class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2566 | string OpcodeStr, string Dt, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 2567 | ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2568 | : N3VLane32<0, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2569 | (outs DPR:$Vd), |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2570 | (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2571 | NVMulSLFrm, itin, |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2572 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2573 | [(set (Ty DPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2574 | (Ty (ShOp (Ty DPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2575 | (Ty (MulOp DPR:$Vn, |
| 2576 | (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2577 | imm:$lane)))))))]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2578 | class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2579 | string OpcodeStr, string Dt, |
| 2580 | ValueType Ty, SDNode MulOp, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2581 | : N3VLane16<0, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | 18341e9 | 2010-10-22 18:54:37 +0000 | [diff] [blame] | 2582 | (outs DPR:$Vd), |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2583 | (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2584 | NVMulSLFrm, itin, |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2585 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | 18341e9 | 2010-10-22 18:54:37 +0000 | [diff] [blame] | 2586 | [(set (Ty DPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2587 | (Ty (ShOp (Ty DPR:$src1), |
Owen Anderson | 18341e9 | 2010-10-22 18:54:37 +0000 | [diff] [blame] | 2588 | (Ty (MulOp DPR:$Vn, |
| 2589 | (Ty (NEONvduplane (Ty DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2590 | imm:$lane)))))))]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2591 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2592 | class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2593 | InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 2594 | SDPatternOperator MulOp, SDPatternOperator OpNode> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2595 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | 18341e9 | 2010-10-22 18:54:37 +0000 | [diff] [blame] | 2596 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, |
| 2597 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2598 | [(set QPR:$Vd, (Ty (OpNode QPR:$src1, |
| 2599 | (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2600 | class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2601 | string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 2602 | SDPatternOperator MulOp, SDPatternOperator ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2603 | : N3VLane32<1, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2604 | (outs QPR:$Vd), |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2605 | (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2606 | NVMulSLFrm, itin, |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2607 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2608 | [(set (ResTy QPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2609 | (ResTy (ShOp (ResTy QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2610 | (ResTy (MulOp QPR:$Vn, |
| 2611 | (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2612 | imm:$lane)))))))]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2613 | class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2614 | string OpcodeStr, string Dt, |
| 2615 | ValueType ResTy, ValueType OpTy, |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2616 | SDNode MulOp, SDNode ShOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2617 | : N3VLane16<1, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2618 | (outs QPR:$Vd), |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2619 | (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2620 | NVMulSLFrm, itin, |
Jim Grosbach | 9120088 | 2011-10-18 18:27:07 +0000 | [diff] [blame] | 2621 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2622 | [(set (ResTy QPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2623 | (ResTy (ShOp (ResTy QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2624 | (ResTy (MulOp QPR:$Vn, |
| 2625 | (ResTy (NEONvduplane (OpTy DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2626 | imm:$lane)))))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2627 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2628 | // Neon Intrinsic-Op instructions (VABA): double- and quad-register. |
| 2629 | class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2630 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2631 | ValueType Ty, SDPatternOperator IntOp, SDNode OpNode> |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2632 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | 410aebc | 2010-10-25 20:52:57 +0000 | [diff] [blame] | 2633 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2634 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2635 | [(set DPR:$Vd, (Ty (OpNode DPR:$src1, |
| 2636 | (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>; |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2637 | class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2638 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2639 | ValueType Ty, SDPatternOperator IntOp, SDNode OpNode> |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2640 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | 410aebc | 2010-10-25 20:52:57 +0000 | [diff] [blame] | 2641 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, |
| 2642 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2643 | [(set QPR:$Vd, (Ty (OpNode QPR:$src1, |
| 2644 | (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>; |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2645 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2646 | // Neon 3-argument intrinsics, both double- and quad-register. |
| 2647 | // The destination register is also used as the first source operand register. |
| 2648 | class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2649 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2650 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2651 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2652 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2653 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2654 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1), |
| 2655 | (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2656 | class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2657 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2658 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2659 | : N3V<op24, op23, op21_20, op11_8, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2660 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, |
| 2661 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2662 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1), |
| 2663 | (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2664 | |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2665 | // Long Multiply-Add/Sub operations. |
| 2666 | class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2667 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2668 | ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> |
| 2669 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | 9220584 | 2010-10-22 19:05:25 +0000 | [diff] [blame] | 2670 | (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2671 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2672 | [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), |
| 2673 | (TyQ (MulOp (TyD DPR:$Vn), |
| 2674 | (TyD DPR:$Vm)))))]>; |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2675 | class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2676 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2677 | ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2678 | : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), |
Jim Grosbach | aead579 | 2011-10-18 20:14:56 +0000 | [diff] [blame] | 2679 | (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2680 | NVMulSLFrm, itin, |
Jim Grosbach | aead579 | 2011-10-18 20:14:56 +0000 | [diff] [blame] | 2681 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2682 | [(set QPR:$Vd, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2683 | (OpNode (TyQ QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2684 | (TyQ (MulOp (TyD DPR:$Vn), |
| 2685 | (TyD (NEONvduplane (TyD DPR_VFP2:$Vm), |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2686 | imm:$lane))))))]>; |
| 2687 | class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2688 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2689 | ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2690 | : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), |
Jim Grosbach | aead579 | 2011-10-18 20:14:56 +0000 | [diff] [blame] | 2691 | (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2692 | NVMulSLFrm, itin, |
Jim Grosbach | aead579 | 2011-10-18 20:14:56 +0000 | [diff] [blame] | 2693 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2694 | [(set QPR:$Vd, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2695 | (OpNode (TyQ QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2696 | (TyQ (MulOp (TyD DPR:$Vn), |
| 2697 | (TyD (NEONvduplane (TyD DPR_8:$Vm), |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2698 | imm:$lane))))))]>; |
| 2699 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2700 | // Long Intrinsic-Op vector operations with explicit extend (VABAL). |
| 2701 | class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2702 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2703 | ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2704 | SDNode OpNode> |
| 2705 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | 5258b61 | 2010-10-25 21:29:04 +0000 | [diff] [blame] | 2706 | (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2707 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2708 | [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), |
| 2709 | (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn), |
| 2710 | (TyD DPR:$Vm)))))))]>; |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2711 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2712 | // Neon Long 3-argument intrinsic. The destination register is |
| 2713 | // a quad-register and is also used as the first source operand register. |
| 2714 | class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2715 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2716 | ValueType TyQ, ValueType TyD, SDPatternOperator IntOp> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2717 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | 9b26497 | 2010-10-22 19:35:48 +0000 | [diff] [blame] | 2718 | (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2719 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", |
| 2720 | [(set QPR:$Vd, |
| 2721 | (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2722 | class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2723 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2724 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2725 | : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2726 | (outs QPR:$Vd), |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2727 | (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2728 | NVMulSLFrm, itin, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2729 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2730 | [(set (ResTy QPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2731 | (ResTy (IntOp (ResTy QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2732 | (OpTy DPR:$Vn), |
| 2733 | (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2734 | imm:$lane)))))]>; |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2735 | class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2736 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2737 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2738 | : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2739 | (outs QPR:$Vd), |
Jim Grosbach | e873d2a | 2011-10-18 17:16:30 +0000 | [diff] [blame] | 2740 | (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2741 | NVMulSLFrm, itin, |
Jim Grosbach | e873d2a | 2011-10-18 17:16:30 +0000 | [diff] [blame] | 2742 | OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2743 | [(set (ResTy QPR:$Vd), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2744 | (ResTy (IntOp (ResTy QPR:$src1), |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2745 | (OpTy DPR:$Vn), |
| 2746 | (OpTy (NEONvduplane (OpTy DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2747 | imm:$lane)))))]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 2748 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2749 | // Narrowing 3-register intrinsics. |
| 2750 | class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2751 | string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2752 | SDPatternOperator IntOp, bit Commutable> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2753 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2754 | (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D, |
| 2755 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2756 | [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2757 | let isCommutable = Commutable; |
| 2758 | } |
| 2759 | |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 2760 | // Long 3-register operations. |
| 2761 | class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2762 | InstrItinClass itin, string OpcodeStr, string Dt, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2763 | ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable> |
| 2764 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2765 | (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2766 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2767 | [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> { |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2768 | let isCommutable = Commutable; |
| 2769 | } |
| 2770 | class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2771 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2772 | ValueType TyQ, ValueType TyD, SDNode OpNode> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2773 | : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2774 | (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2775 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2776 | [(set QPR:$Vd, |
| 2777 | (TyQ (OpNode (TyD DPR:$Vn), |
| 2778 | (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>; |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2779 | class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2780 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2781 | ValueType TyQ, ValueType TyD, SDNode OpNode> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2782 | : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2783 | (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2784 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2785 | [(set QPR:$Vd, |
| 2786 | (TyQ (OpNode (TyD DPR:$Vn), |
| 2787 | (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>; |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 2788 | |
| 2789 | // Long 3-register operations with explicitly extended operands. |
| 2790 | class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2791 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 2792 | ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, |
| 2793 | bit Commutable> |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 2794 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2795 | (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2796 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2797 | [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))), |
| 2798 | (TyQ (ExtOp (TyD DPR:$Vm)))))]> { |
Owen Anderson | e0e6dc3 | 2010-10-21 18:09:17 +0000 | [diff] [blame] | 2799 | let isCommutable = Commutable; |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 2800 | } |
| 2801 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2802 | // Long 3-register intrinsics with explicit extend (VABDL). |
| 2803 | class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2804 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2805 | ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2806 | bit Commutable> |
| 2807 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2808 | (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2809 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2810 | [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn), |
| 2811 | (TyD DPR:$Vm))))))]> { |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 2812 | let isCommutable = Commutable; |
| 2813 | } |
| 2814 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2815 | // Long 3-register intrinsics. |
| 2816 | class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2817 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2818 | ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2819 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2820 | (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, |
| 2821 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2822 | [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2823 | let isCommutable = Commutable; |
| 2824 | } |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 2825 | class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2826 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2827 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2828 | : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2829 | (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), |
| 2830 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2831 | [(set (ResTy QPR:$Vd), |
| 2832 | (ResTy (IntOp (OpTy DPR:$Vn), |
| 2833 | (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2834 | imm:$lane)))))]>; |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 2835 | class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, |
| 2836 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2837 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | 6a7d36a | 2011-03-30 23:45:29 +0000 | [diff] [blame] | 2838 | : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, |
Jim Grosbach | a7d2e75 | 2011-10-18 20:21:17 +0000 | [diff] [blame] | 2839 | (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), |
| 2840 | NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2841 | [(set (ResTy QPR:$Vd), |
| 2842 | (ResTy (IntOp (OpTy DPR:$Vn), |
| 2843 | (OpTy (NEONvduplane (OpTy DPR_8:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 2844 | imm:$lane)))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2845 | |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 2846 | // Wide 3-register operations. |
| 2847 | class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, |
| 2848 | string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, |
| 2849 | SDNode OpNode, SDNode ExtOp, bit Commutable> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2850 | : N3V<op24, op23, op21_20, op11_8, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2851 | (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD, |
| 2852 | OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", |
| 2853 | [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn), |
| 2854 | (TyQ (ExtOp (TyD DPR:$Vm)))))]> { |
Jim Grosbach | d8b3ed8 | 2012-04-20 18:12:54 +0000 | [diff] [blame] | 2855 | // All of these have a two-operand InstAlias. |
| 2856 | let TwoOperandAliasConstraint = "$Vn = $Vd"; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2857 | let isCommutable = Commutable; |
| 2858 | } |
| 2859 | |
| 2860 | // Pairwise long 2-register intrinsics, both double- and quad-register. |
| 2861 | class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2862 | bits<2> op17_16, bits<5> op11_7, bit op4, |
| 2863 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2864 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2865 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), |
| 2866 | (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2867 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2868 | class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2869 | bits<2> op17_16, bits<5> op11_7, bit op4, |
| 2870 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2871 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2872 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), |
| 2873 | (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 2874 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2875 | |
| 2876 | // Pairwise long 2-register accumulate intrinsics, |
| 2877 | // both double- and quad-register. |
| 2878 | // The destination register is also used as the first source operand register. |
| 2879 | class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2880 | bits<2> op17_16, bits<5> op11_7, bit op4, |
| 2881 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2882 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2883 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, |
Owen Anderson | bc4118b | 2010-10-26 18:18:03 +0000 | [diff] [blame] | 2884 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD, |
| 2885 | OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd", |
| 2886 | [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2887 | class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2888 | bits<2> op17_16, bits<5> op11_7, bit op4, |
| 2889 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2890 | ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp> |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2891 | : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, |
Owen Anderson | bc4118b | 2010-10-26 18:18:03 +0000 | [diff] [blame] | 2892 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ, |
| 2893 | OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd", |
| 2894 | [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2895 | |
| 2896 | // Shift by immediate, |
| 2897 | // both double- and quad-register. |
Jim Grosbach | d83c9ea | 2012-04-20 23:30:14 +0000 | [diff] [blame] | 2898 | let TwoOperandAliasConstraint = "$Vm = $Vd" in { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2899 | class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 2900 | Format f, InstrItinClass itin, Operand ImmTy, |
| 2901 | string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2902 | : N2VImm<op24, op23, op11_8, op7, 0, op4, |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 2903 | (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2904 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2905 | [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2906 | class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 2907 | Format f, InstrItinClass itin, Operand ImmTy, |
| 2908 | string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2909 | : N2VImm<op24, op23, op11_8, op7, 1, op4, |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 2910 | (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2911 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2912 | [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>; |
Jim Grosbach | d83c9ea | 2012-04-20 23:30:14 +0000 | [diff] [blame] | 2913 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2914 | |
Johnny Chen | 6c8648b | 2010-03-17 23:26:50 +0000 | [diff] [blame] | 2915 | // Long shift by immediate. |
| 2916 | class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, |
| 2917 | string OpcodeStr, string Dt, |
Jim Grosbach | 4e41395 | 2011-12-07 00:02:17 +0000 | [diff] [blame] | 2918 | ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode> |
Johnny Chen | 6c8648b | 2010-03-17 23:26:50 +0000 | [diff] [blame] | 2919 | : N2VImm<op24, op23, op11_8, op7, op6, op4, |
Jim Grosbach | 4e41395 | 2011-12-07 00:02:17 +0000 | [diff] [blame] | 2920 | (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2921 | IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2922 | [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), |
Johnny Chen | 6c8648b | 2010-03-17 23:26:50 +0000 | [diff] [blame] | 2923 | (i32 imm:$SIMM))))]>; |
| 2924 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2925 | // Narrow shift by immediate. |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2926 | class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2927 | InstrItinClass itin, string OpcodeStr, string Dt, |
Bill Wendling | a656b63 | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 2928 | ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode> |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2929 | : N2VImm<op24, op23, op11_8, op7, op6, op4, |
Bill Wendling | a656b63 | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 2930 | (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 2931 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2932 | [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2933 | (i32 imm:$SIMM))))]>; |
| 2934 | |
| 2935 | // Shift right by immediate and accumulate, |
| 2936 | // both double- and quad-register. |
Jim Grosbach | e1d866e | 2012-04-23 21:00:49 +0000 | [diff] [blame] | 2937 | let TwoOperandAliasConstraint = "$Vm = $Vd" in { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2938 | class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 2939 | Operand ImmTy, string OpcodeStr, string Dt, |
| 2940 | ValueType Ty, SDNode ShOp> |
Owen Anderson | dd31ed6 | 2010-10-27 17:29:29 +0000 | [diff] [blame] | 2941 | : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd), |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 2942 | (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD, |
Owen Anderson | dd31ed6 | 2010-10-27 17:29:29 +0000 | [diff] [blame] | 2943 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", |
| 2944 | [(set DPR:$Vd, (Ty (add DPR:$src1, |
| 2945 | (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2946 | class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 2947 | Operand ImmTy, string OpcodeStr, string Dt, |
| 2948 | ValueType Ty, SDNode ShOp> |
Owen Anderson | dd31ed6 | 2010-10-27 17:29:29 +0000 | [diff] [blame] | 2949 | : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd), |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 2950 | (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD, |
Owen Anderson | dd31ed6 | 2010-10-27 17:29:29 +0000 | [diff] [blame] | 2951 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", |
| 2952 | [(set QPR:$Vd, (Ty (add QPR:$src1, |
| 2953 | (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>; |
Jim Grosbach | e1d866e | 2012-04-23 21:00:49 +0000 | [diff] [blame] | 2954 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2955 | |
| 2956 | // Shift by immediate and insert, |
| 2957 | // both double- and quad-register. |
Jim Grosbach | e1d866e | 2012-04-23 21:00:49 +0000 | [diff] [blame] | 2958 | let TwoOperandAliasConstraint = "$Vm = $Vd" in { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2959 | class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 2960 | Operand ImmTy, Format f, string OpcodeStr, string Dt, |
| 2961 | ValueType Ty,SDNode ShOp> |
Owen Anderson | 0745c38 | 2010-10-27 17:40:08 +0000 | [diff] [blame] | 2962 | : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd), |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 2963 | (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD, |
Owen Anderson | 0745c38 | 2010-10-27 17:40:08 +0000 | [diff] [blame] | 2964 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", |
| 2965 | [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2966 | class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 2967 | Operand ImmTy, Format f, string OpcodeStr, string Dt, |
| 2968 | ValueType Ty,SDNode ShOp> |
Owen Anderson | 0745c38 | 2010-10-27 17:40:08 +0000 | [diff] [blame] | 2969 | : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd), |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 2970 | (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ, |
Owen Anderson | 0745c38 | 2010-10-27 17:40:08 +0000 | [diff] [blame] | 2971 | OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", |
| 2972 | [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>; |
Jim Grosbach | e1d866e | 2012-04-23 21:00:49 +0000 | [diff] [blame] | 2973 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2974 | |
| 2975 | // Convert, with fractional bits immediate, |
| 2976 | // both double- and quad-register. |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2977 | class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2978 | string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2979 | SDPatternOperator IntOp> |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2980 | : N2VImm<op24, op23, op11_8, op7, 0, op4, |
Owen Anderson | 498ec20 | 2010-10-27 22:49:00 +0000 | [diff] [blame] | 2981 | (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm, |
| 2982 | IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2983 | [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2984 | class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 2985 | string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 2986 | SDPatternOperator IntOp> |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 2987 | : N2VImm<op24, op23, op11_8, op7, 1, op4, |
Owen Anderson | 498ec20 | 2010-10-27 22:49:00 +0000 | [diff] [blame] | 2988 | (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm, |
| 2989 | IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", |
| 2990 | [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 2991 | |
| 2992 | //===----------------------------------------------------------------------===// |
| 2993 | // Multiclasses |
| 2994 | //===----------------------------------------------------------------------===// |
| 2995 | |
Bob Wilson | 916ac5b | 2009-10-03 04:44:16 +0000 | [diff] [blame] | 2996 | // Abbreviations used in multiclass suffixes: |
| 2997 | // Q = quarter int (8 bit) elements |
| 2998 | // H = half int (16 bit) elements |
| 2999 | // S = single int (32 bit) elements |
| 3000 | // D = double int (64 bit) elements |
| 3001 | |
Bob Wilson | 094dd80 | 2010-12-18 00:42:58 +0000 | [diff] [blame] | 3002 | // Neon 2-register vector operations and intrinsics. |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3003 | |
Bob Wilson | 094dd80 | 2010-12-18 00:42:58 +0000 | [diff] [blame] | 3004 | // Neon 2-register comparisons. |
| 3005 | // source operand element sizes of 8, 16 and 32 bits: |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 3006 | multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3007 | bits<5> op11_7, bit op4, string opc, string Dt, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3008 | string asm, SDNode OpNode> { |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3009 | // 64-bit vector types. |
| 3010 | def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3011 | (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3012 | opc, !strconcat(Dt, "8"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3013 | [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3014 | def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3015 | (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3016 | opc, !strconcat(Dt, "16"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3017 | [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3018 | def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3019 | (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3020 | opc, !strconcat(Dt, "32"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3021 | [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3022 | def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3023 | (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3024 | opc, "f32", asm, "", |
Bob Wilson | 3deb451 | 2010-12-18 00:04:33 +0000 | [diff] [blame] | 3025 | [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> { |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3026 | let Inst{10} = 1; // overwrite F = 1 |
| 3027 | } |
| 3028 | |
| 3029 | // 128-bit vector types. |
| 3030 | def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3031 | (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3032 | opc, !strconcat(Dt, "8"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3033 | [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3034 | def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3035 | (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3036 | opc, !strconcat(Dt, "16"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3037 | [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3038 | def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3039 | (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3040 | opc, !strconcat(Dt, "32"), asm, "", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3041 | [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3042 | def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 3043 | (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 3044 | opc, "f32", asm, "", |
Bob Wilson | 3deb451 | 2010-12-18 00:04:33 +0000 | [diff] [blame] | 3045 | [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> { |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 3046 | let Inst{10} = 1; // overwrite F = 1 |
| 3047 | } |
| 3048 | } |
| 3049 | |
Bob Wilson | 094dd80 | 2010-12-18 00:42:58 +0000 | [diff] [blame] | 3050 | |
| 3051 | // Neon 2-register vector intrinsics, |
| 3052 | // element sizes of 8, 16 and 32 bits: |
| 3053 | multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3054 | bits<5> op11_7, bit op4, |
| 3055 | InstrItinClass itinD, InstrItinClass itinQ, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3056 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Bob Wilson | 094dd80 | 2010-12-18 00:42:58 +0000 | [diff] [blame] | 3057 | // 64-bit vector types. |
| 3058 | def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
| 3059 | itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>; |
| 3060 | def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
| 3061 | itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>; |
| 3062 | def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
| 3063 | itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>; |
| 3064 | |
| 3065 | // 128-bit vector types. |
| 3066 | def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
| 3067 | itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>; |
| 3068 | def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
| 3069 | itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>; |
| 3070 | def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
| 3071 | itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>; |
| 3072 | } |
| 3073 | |
| 3074 | |
| 3075 | // Neon Narrowing 2-register vector operations, |
| 3076 | // source operand element sizes of 16, 32 and 64 bits: |
| 3077 | multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3078 | bits<5> op11_7, bit op6, bit op4, |
| 3079 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 3080 | SDNode OpNode> { |
| 3081 | def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, |
| 3082 | itin, OpcodeStr, !strconcat(Dt, "16"), |
| 3083 | v8i8, v8i16, OpNode>; |
| 3084 | def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, |
| 3085 | itin, OpcodeStr, !strconcat(Dt, "32"), |
| 3086 | v4i16, v4i32, OpNode>; |
| 3087 | def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, |
| 3088 | itin, OpcodeStr, !strconcat(Dt, "64"), |
| 3089 | v2i32, v2i64, OpNode>; |
| 3090 | } |
| 3091 | |
| 3092 | // Neon Narrowing 2-register vector intrinsics, |
| 3093 | // source operand element sizes of 16, 32 and 64 bits: |
| 3094 | multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3095 | bits<5> op11_7, bit op6, bit op4, |
| 3096 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3097 | SDPatternOperator IntOp> { |
Bob Wilson | 094dd80 | 2010-12-18 00:42:58 +0000 | [diff] [blame] | 3098 | def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, |
| 3099 | itin, OpcodeStr, !strconcat(Dt, "16"), |
| 3100 | v8i8, v8i16, IntOp>; |
| 3101 | def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, |
| 3102 | itin, OpcodeStr, !strconcat(Dt, "32"), |
| 3103 | v4i16, v4i32, IntOp>; |
| 3104 | def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, |
| 3105 | itin, OpcodeStr, !strconcat(Dt, "64"), |
| 3106 | v2i32, v2i64, IntOp>; |
| 3107 | } |
| 3108 | |
| 3109 | |
| 3110 | // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). |
| 3111 | // source operand element sizes of 16, 32 and 64 bits: |
| 3112 | multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4, |
| 3113 | string OpcodeStr, string Dt, SDNode OpNode> { |
| 3114 | def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD, |
| 3115 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>; |
| 3116 | def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, |
| 3117 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>; |
| 3118 | def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, |
| 3119 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>; |
| 3120 | } |
| 3121 | |
| 3122 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3123 | // Neon 3-register vector operations. |
| 3124 | |
| 3125 | // First with only element sizes of 8, 16 and 32 bits: |
| 3126 | multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3127 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3128 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3129 | string OpcodeStr, string Dt, |
| 3130 | SDNode OpNode, bit Commutable = 0> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3131 | // 64-bit vector types. |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3132 | def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3133 | OpcodeStr, !strconcat(Dt, "8"), |
| 3134 | v8i8, v8i8, OpNode, Commutable>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3135 | def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3136 | OpcodeStr, !strconcat(Dt, "16"), |
| 3137 | v4i16, v4i16, OpNode, Commutable>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3138 | def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3139 | OpcodeStr, !strconcat(Dt, "32"), |
| 3140 | v2i32, v2i32, OpNode, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3141 | |
| 3142 | // 128-bit vector types. |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3143 | def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3144 | OpcodeStr, !strconcat(Dt, "8"), |
| 3145 | v16i8, v16i8, OpNode, Commutable>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3146 | def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3147 | OpcodeStr, !strconcat(Dt, "16"), |
| 3148 | v8i16, v8i16, OpNode, Commutable>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3149 | def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3150 | OpcodeStr, !strconcat(Dt, "32"), |
| 3151 | v4i32, v4i32, OpNode, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3152 | } |
| 3153 | |
Jim Grosbach | 45755a7 | 2011-12-05 20:09:44 +0000 | [diff] [blame] | 3154 | multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> { |
Jim Grosbach | 422faab | 2011-12-05 20:12:26 +0000 | [diff] [blame] | 3155 | def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>; |
| 3156 | def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>; |
Jim Grosbach | 45755a7 | 2011-12-05 20:09:44 +0000 | [diff] [blame] | 3157 | def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>; |
Jim Grosbach | 422faab | 2011-12-05 20:12:26 +0000 | [diff] [blame] | 3158 | def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3159 | v4i32, v2i32, ShOp>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3160 | } |
| 3161 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3162 | // ....then also with element size 64 bits: |
| 3163 | multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3164 | InstrItinClass itinD, InstrItinClass itinQ, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3165 | string OpcodeStr, string Dt, |
| 3166 | SDNode OpNode, bit Commutable = 0> |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3167 | : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3168 | OpcodeStr, Dt, OpNode, Commutable> { |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3169 | def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3170 | OpcodeStr, !strconcat(Dt, "64"), |
| 3171 | v1i64, v1i64, OpNode, Commutable>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 3172 | def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3173 | OpcodeStr, !strconcat(Dt, "64"), |
| 3174 | v2i64, v2i64, OpNode, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3175 | } |
| 3176 | |
| 3177 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3178 | // Neon 3-register vector intrinsics. |
| 3179 | |
| 3180 | // First with only element sizes of 16 and 32 bits: |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3181 | multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3182 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3183 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3184 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3185 | SDPatternOperator IntOp, bit Commutable = 0> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3186 | // 64-bit vector types. |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3187 | def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3188 | OpcodeStr, !strconcat(Dt, "16"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3189 | v4i16, v4i16, IntOp, Commutable>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3190 | def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3191 | OpcodeStr, !strconcat(Dt, "32"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3192 | v2i32, v2i32, IntOp, Commutable>; |
| 3193 | |
| 3194 | // 128-bit vector types. |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3195 | def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3196 | OpcodeStr, !strconcat(Dt, "16"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3197 | v8i16, v8i16, IntOp, Commutable>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3198 | def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3199 | OpcodeStr, !strconcat(Dt, "32"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3200 | v4i32, v4i32, IntOp, Commutable>; |
| 3201 | } |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3202 | multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
| 3203 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3204 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
| 3205 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3206 | SDPatternOperator IntOp> { |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3207 | // 64-bit vector types. |
| 3208 | def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16, |
| 3209 | OpcodeStr, !strconcat(Dt, "16"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3210 | v4i16, v4i16, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3211 | def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32, |
| 3212 | OpcodeStr, !strconcat(Dt, "32"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3213 | v2i32, v2i32, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3214 | |
| 3215 | // 128-bit vector types. |
| 3216 | def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16, |
| 3217 | OpcodeStr, !strconcat(Dt, "16"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3218 | v8i16, v8i16, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3219 | def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32, |
| 3220 | OpcodeStr, !strconcat(Dt, "32"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3221 | v4i32, v4i32, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3222 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3223 | |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3224 | multiclass N3VIntSL_HS<bits<4> op11_8, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3225 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3226 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3227 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3228 | def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3229 | OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>; |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3230 | def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3231 | OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>; |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3232 | def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3233 | OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>; |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3234 | def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3235 | OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3236 | } |
| 3237 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3238 | // ....then also with element size of 8 bits: |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3239 | multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3240 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3241 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3242 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3243 | SDPatternOperator IntOp, bit Commutable = 0> |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3244 | : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3245 | OpcodeStr, Dt, IntOp, Commutable> { |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3246 | def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3247 | OpcodeStr, !strconcat(Dt, "8"), |
| 3248 | v8i8, v8i8, IntOp, Commutable>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3249 | def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3250 | OpcodeStr, !strconcat(Dt, "8"), |
| 3251 | v16i8, v16i8, IntOp, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3252 | } |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3253 | multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
| 3254 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3255 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
| 3256 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3257 | SDPatternOperator IntOp> |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3258 | : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3259 | OpcodeStr, Dt, IntOp> { |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3260 | def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16, |
| 3261 | OpcodeStr, !strconcat(Dt, "8"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3262 | v8i8, v8i8, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3263 | def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16, |
| 3264 | OpcodeStr, !strconcat(Dt, "8"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3265 | v16i8, v16i8, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3266 | } |
| 3267 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3268 | |
| 3269 | // ....then also with element size of 64 bits: |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3270 | multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3271 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3272 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3273 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3274 | SDPatternOperator IntOp, bit Commutable = 0> |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3275 | : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3276 | OpcodeStr, Dt, IntOp, Commutable> { |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3277 | def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3278 | OpcodeStr, !strconcat(Dt, "64"), |
| 3279 | v1i64, v1i64, IntOp, Commutable>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3280 | def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3281 | OpcodeStr, !strconcat(Dt, "64"), |
| 3282 | v2i64, v2i64, IntOp, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3283 | } |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3284 | multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, |
| 3285 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3286 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
| 3287 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3288 | SDPatternOperator IntOp> |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3289 | : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3290 | OpcodeStr, Dt, IntOp> { |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3291 | def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32, |
| 3292 | OpcodeStr, !strconcat(Dt, "64"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3293 | v1i64, v1i64, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3294 | def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32, |
| 3295 | OpcodeStr, !strconcat(Dt, "64"), |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 3296 | v2i64, v2i64, IntOp>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 3297 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3298 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3299 | // Neon Narrowing 3-register vector intrinsics, |
| 3300 | // source operand element sizes of 16, 32 and 64 bits: |
| 3301 | multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3302 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3303 | SDPatternOperator IntOp, bit Commutable = 0> { |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3304 | def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, |
| 3305 | OpcodeStr, !strconcat(Dt, "16"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3306 | v8i8, v8i16, IntOp, Commutable>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3307 | def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, |
| 3308 | OpcodeStr, !strconcat(Dt, "32"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3309 | v4i16, v4i32, IntOp, Commutable>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3310 | def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, |
| 3311 | OpcodeStr, !strconcat(Dt, "64"), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3312 | v2i32, v2i64, IntOp, Commutable>; |
| 3313 | } |
| 3314 | |
| 3315 | |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 3316 | // Neon Long 3-register vector operations. |
| 3317 | |
| 3318 | multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3319 | InstrItinClass itin16, InstrItinClass itin32, |
| 3320 | string OpcodeStr, string Dt, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3321 | SDNode OpNode, bit Commutable = 0> { |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 3322 | def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16, |
| 3323 | OpcodeStr, !strconcat(Dt, "8"), |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3324 | v8i16, v8i8, OpNode, Commutable>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3325 | def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3326 | OpcodeStr, !strconcat(Dt, "16"), |
| 3327 | v4i32, v4i16, OpNode, Commutable>; |
| 3328 | def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32, |
| 3329 | OpcodeStr, !strconcat(Dt, "32"), |
| 3330 | v2i64, v2i32, OpNode, Commutable>; |
| 3331 | } |
| 3332 | |
| 3333 | multiclass N3VLSL_HS<bit op24, bits<4> op11_8, |
| 3334 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 3335 | SDNode OpNode> { |
| 3336 | def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr, |
| 3337 | !strconcat(Dt, "16"), v4i32, v4i16, OpNode>; |
| 3338 | def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr, |
| 3339 | !strconcat(Dt, "32"), v2i64, v2i32, OpNode>; |
| 3340 | } |
| 3341 | |
| 3342 | multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3343 | InstrItinClass itin16, InstrItinClass itin32, |
| 3344 | string OpcodeStr, string Dt, |
| 3345 | SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { |
| 3346 | def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16, |
| 3347 | OpcodeStr, !strconcat(Dt, "8"), |
| 3348 | v8i16, v8i8, OpNode, ExtOp, Commutable>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3349 | def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16, |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3350 | OpcodeStr, !strconcat(Dt, "16"), |
| 3351 | v4i32, v4i16, OpNode, ExtOp, Commutable>; |
| 3352 | def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32, |
| 3353 | OpcodeStr, !strconcat(Dt, "32"), |
| 3354 | v2i64, v2i32, OpNode, ExtOp, Commutable>; |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 3355 | } |
| 3356 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3357 | // Neon Long 3-register vector intrinsics. |
| 3358 | |
| 3359 | // First with only element sizes of 16 and 32 bits: |
| 3360 | multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3361 | InstrItinClass itin16, InstrItinClass itin32, |
| 3362 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3363 | SDPatternOperator IntOp, bit Commutable = 0> { |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3364 | def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3365 | OpcodeStr, !strconcat(Dt, "16"), |
| 3366 | v4i32, v4i16, IntOp, Commutable>; |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3367 | def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3368 | OpcodeStr, !strconcat(Dt, "32"), |
| 3369 | v2i64, v2i32, IntOp, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3370 | } |
| 3371 | |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3372 | multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3373 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3374 | SDPatternOperator IntOp> { |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3375 | def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3376 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3377 | def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3378 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3379 | } |
| 3380 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3381 | // ....then also with element size of 8 bits: |
| 3382 | multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3383 | InstrItinClass itin16, InstrItinClass itin32, |
| 3384 | string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3385 | SDPatternOperator IntOp, bit Commutable = 0> |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3386 | : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3387 | IntOp, Commutable> { |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3388 | def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3389 | OpcodeStr, !strconcat(Dt, "8"), |
| 3390 | v8i16, v8i8, IntOp, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3391 | } |
| 3392 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3393 | // ....with explicit extend (VABDL). |
| 3394 | multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3395 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3396 | SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> { |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3397 | def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin, |
| 3398 | OpcodeStr, !strconcat(Dt, "8"), |
| 3399 | v8i16, v8i8, IntOp, ExtOp, Commutable>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3400 | def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3401 | OpcodeStr, !strconcat(Dt, "16"), |
| 3402 | v4i32, v4i16, IntOp, ExtOp, Commutable>; |
| 3403 | def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin, |
| 3404 | OpcodeStr, !strconcat(Dt, "32"), |
| 3405 | v2i64, v2i32, IntOp, ExtOp, Commutable>; |
| 3406 | } |
| 3407 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3408 | |
| 3409 | // Neon Wide 3-register vector intrinsics, |
| 3410 | // source operand element sizes of 8, 16 and 32 bits: |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 3411 | multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3412 | string OpcodeStr, string Dt, |
| 3413 | SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { |
| 3414 | def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4, |
| 3415 | OpcodeStr, !strconcat(Dt, "8"), |
| 3416 | v8i16, v8i8, OpNode, ExtOp, Commutable>; |
| 3417 | def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4, |
| 3418 | OpcodeStr, !strconcat(Dt, "16"), |
| 3419 | v4i32, v4i16, OpNode, ExtOp, Commutable>; |
| 3420 | def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4, |
| 3421 | OpcodeStr, !strconcat(Dt, "32"), |
| 3422 | v2i64, v2i32, OpNode, ExtOp, Commutable>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3423 | } |
| 3424 | |
| 3425 | |
| 3426 | // Neon Multiply-Op vector operations, |
| 3427 | // element sizes of 8, 16 and 32 bits: |
| 3428 | multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3429 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3430 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3431 | string OpcodeStr, string Dt, SDNode OpNode> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3432 | // 64-bit vector types. |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3433 | def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3434 | OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3435 | def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3436 | OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3437 | def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3438 | OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3439 | |
| 3440 | // 128-bit vector types. |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3441 | def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3442 | OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3443 | def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3444 | OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3445 | def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3446 | OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3447 | } |
| 3448 | |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3449 | multiclass N3VMulOpSL_HS<bits<4> op11_8, |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3450 | InstrItinClass itinD16, InstrItinClass itinD32, |
| 3451 | InstrItinClass itinQ16, InstrItinClass itinQ32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3452 | string OpcodeStr, string Dt, SDNode ShOp> { |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3453 | def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3454 | OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3455 | def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3456 | OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3457 | def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3458 | OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, |
| 3459 | mul, ShOp>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3460 | def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3461 | OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, |
| 3462 | mul, ShOp>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3463 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3464 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3465 | // Neon Intrinsic-Op vector operations, |
| 3466 | // element sizes of 8, 16 and 32 bits: |
| 3467 | multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3468 | InstrItinClass itinD, InstrItinClass itinQ, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3469 | string OpcodeStr, string Dt, SDPatternOperator IntOp, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3470 | SDNode OpNode> { |
| 3471 | // 64-bit vector types. |
| 3472 | def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD, |
| 3473 | OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>; |
| 3474 | def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD, |
| 3475 | OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>; |
| 3476 | def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD, |
| 3477 | OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>; |
| 3478 | |
| 3479 | // 128-bit vector types. |
| 3480 | def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ, |
| 3481 | OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>; |
| 3482 | def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ, |
| 3483 | OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>; |
| 3484 | def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ, |
| 3485 | OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>; |
| 3486 | } |
| 3487 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3488 | // Neon 3-argument intrinsics, |
| 3489 | // element sizes of 8, 16 and 32 bits: |
| 3490 | multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3491 | InstrItinClass itinD, InstrItinClass itinQ, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3492 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3493 | // 64-bit vector types. |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3494 | def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3495 | OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>; |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3496 | def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3497 | OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>; |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3498 | def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3499 | OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3500 | |
| 3501 | // 128-bit vector types. |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3502 | def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3503 | OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>; |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3504 | def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3505 | OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>; |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 3506 | def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3507 | OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3508 | } |
| 3509 | |
| 3510 | |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3511 | // Neon Long Multiply-Op vector operations, |
| 3512 | // element sizes of 8, 16 and 32 bits: |
| 3513 | multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3514 | InstrItinClass itin16, InstrItinClass itin32, |
| 3515 | string OpcodeStr, string Dt, SDNode MulOp, |
| 3516 | SDNode OpNode> { |
| 3517 | def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr, |
| 3518 | !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>; |
| 3519 | def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr, |
| 3520 | !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>; |
| 3521 | def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr, |
| 3522 | !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>; |
| 3523 | } |
| 3524 | |
| 3525 | multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr, |
| 3526 | string Dt, SDNode MulOp, SDNode OpNode> { |
| 3527 | def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr, |
| 3528 | !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>; |
| 3529 | def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr, |
| 3530 | !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>; |
| 3531 | } |
| 3532 | |
| 3533 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3534 | // Neon Long 3-argument intrinsics. |
| 3535 | |
| 3536 | // First with only element sizes of 16 and 32 bits: |
| 3537 | multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4, |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 3538 | InstrItinClass itin16, InstrItinClass itin32, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3539 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 3540 | def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3541 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>; |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 3542 | def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3543 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3544 | } |
| 3545 | |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3546 | multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3547 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3548 | def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3549 | OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3550 | def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3551 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3552 | } |
| 3553 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3554 | // ....then also with element size of 8 bits: |
| 3555 | multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 3556 | InstrItinClass itin16, InstrItinClass itin32, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3557 | string OpcodeStr, string Dt, SDPatternOperator IntOp> |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 3558 | : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> { |
| 3559 | def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3560 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3561 | } |
| 3562 | |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3563 | // ....with explicit extend (VABAL). |
| 3564 | multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3565 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3566 | SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> { |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 3567 | def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin, |
| 3568 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, |
| 3569 | IntOp, ExtOp, OpNode>; |
| 3570 | def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin, |
| 3571 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, |
| 3572 | IntOp, ExtOp, OpNode>; |
| 3573 | def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin, |
| 3574 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, |
| 3575 | IntOp, ExtOp, OpNode>; |
| 3576 | } |
| 3577 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3578 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3579 | // Neon Pairwise long 2-register intrinsics, |
| 3580 | // element sizes of 8, 16 and 32 bits: |
| 3581 | multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3582 | bits<5> op11_7, bit op4, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3583 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3584 | // 64-bit vector types. |
| 3585 | def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3586 | OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3587 | def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3588 | OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3589 | def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3590 | OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3591 | |
| 3592 | // 128-bit vector types. |
| 3593 | def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3594 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3595 | def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3596 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3597 | def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3598 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3599 | } |
| 3600 | |
| 3601 | |
| 3602 | // Neon Pairwise long 2-register accumulate intrinsics, |
| 3603 | // element sizes of 8, 16 and 32 bits: |
| 3604 | multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, |
| 3605 | bits<5> op11_7, bit op4, |
Jim Grosbach | a4fba5e | 2012-07-10 00:51:13 +0000 | [diff] [blame] | 3606 | string OpcodeStr, string Dt, SDPatternOperator IntOp> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3607 | // 64-bit vector types. |
| 3608 | def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3609 | OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3610 | def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3611 | OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3612 | def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3613 | OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3614 | |
| 3615 | // 128-bit vector types. |
| 3616 | def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3617 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3618 | def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3619 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3620 | def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3621 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3622 | } |
| 3623 | |
| 3624 | |
| 3625 | // Neon 2-register vector shift by immediate, |
Johnny Chen | 0a3dc10 | 2010-03-26 01:07:59 +0000 | [diff] [blame] | 3626 | // with f of either N2RegVShLFrm or N2RegVShRFrm |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3627 | // element sizes of 8, 16, 32 and 64 bits: |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3628 | multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3629 | InstrItinClass itin, string OpcodeStr, string Dt, |
| 3630 | SDNode OpNode> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3631 | // 64-bit vector types. |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3632 | def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3633 | OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3634 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3635 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3636 | def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3637 | OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3638 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3639 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3640 | def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3641 | OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3642 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3643 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3644 | def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3645 | OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3646 | // imm6 = xxxxxx |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3647 | |
| 3648 | // 128-bit vector types. |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3649 | def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3650 | OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3651 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3652 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3653 | def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3654 | OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3655 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3656 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3657 | def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3658 | OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3659 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3660 | } |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3661 | def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm, |
| 3662 | OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>; |
| 3663 | // imm6 = xxxxxx |
| 3664 | } |
| 3665 | multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3666 | InstrItinClass itin, string OpcodeStr, string Dt, |
Jim Grosbach | 22378fd | 2012-04-05 07:23:53 +0000 | [diff] [blame] | 3667 | string baseOpc, SDNode OpNode> { |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 3668 | // 64-bit vector types. |
| 3669 | def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8, |
| 3670 | OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> { |
| 3671 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3672 | } |
| 3673 | def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16, |
| 3674 | OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> { |
| 3675 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3676 | } |
| 3677 | def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32, |
| 3678 | OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> { |
| 3679 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3680 | } |
| 3681 | def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64, |
| 3682 | OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>; |
| 3683 | // imm6 = xxxxxx |
| 3684 | |
| 3685 | // 128-bit vector types. |
| 3686 | def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8, |
| 3687 | OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> { |
| 3688 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3689 | } |
| 3690 | def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16, |
| 3691 | OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> { |
| 3692 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3693 | } |
| 3694 | def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32, |
| 3695 | OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> { |
| 3696 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3697 | } |
| 3698 | def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3699 | OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3700 | // imm6 = xxxxxx |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3701 | } |
| 3702 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3703 | // Neon Shift-Accumulate vector operations, |
| 3704 | // element sizes of 8, 16, 32 and 64 bits: |
| 3705 | multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3706 | string OpcodeStr, string Dt, SDNode ShOp> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3707 | // 64-bit vector types. |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3708 | def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3709 | OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3710 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3711 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3712 | def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3713 | OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3714 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3715 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3716 | def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3717 | OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3718 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3719 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3720 | def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3721 | OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3722 | // imm6 = xxxxxx |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3723 | |
| 3724 | // 128-bit vector types. |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3725 | def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3726 | OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3727 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3728 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3729 | def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3730 | OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3731 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3732 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3733 | def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3734 | OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3735 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3736 | } |
Bill Wendling | c04a9de | 2011-03-09 00:00:35 +0000 | [diff] [blame] | 3737 | def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3738 | OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3739 | // imm6 = xxxxxx |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3740 | } |
| 3741 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3742 | // Neon Shift-Insert vector operations, |
Johnny Chen | 0a3dc10 | 2010-03-26 01:07:59 +0000 | [diff] [blame] | 3743 | // with f of either N2RegVShLFrm or N2RegVShRFrm |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3744 | // element sizes of 8, 16, 32 and 64 bits: |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3745 | multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3746 | string OpcodeStr> { |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3747 | // 64-bit vector types. |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3748 | def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3749 | N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3750 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3751 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3752 | def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3753 | N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3754 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3755 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3756 | def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3757 | N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3758 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3759 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3760 | def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm, |
| 3761 | N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3762 | // imm6 = xxxxxx |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3763 | |
| 3764 | // 128-bit vector types. |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3765 | def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3766 | N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3767 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3768 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3769 | def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3770 | N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3771 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3772 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3773 | def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, |
| 3774 | N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3775 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3776 | } |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 3777 | def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm, |
| 3778 | N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>; |
| 3779 | // imm6 = xxxxxx |
| 3780 | } |
| 3781 | multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, |
| 3782 | string OpcodeStr> { |
| 3783 | // 64-bit vector types. |
| 3784 | def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8, |
| 3785 | N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> { |
| 3786 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3787 | } |
| 3788 | def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16, |
| 3789 | N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> { |
| 3790 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3791 | } |
| 3792 | def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32, |
| 3793 | N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> { |
| 3794 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3795 | } |
| 3796 | def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64, |
| 3797 | N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>; |
| 3798 | // imm6 = xxxxxx |
| 3799 | |
| 3800 | // 128-bit vector types. |
| 3801 | def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8, |
| 3802 | N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> { |
| 3803 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3804 | } |
| 3805 | def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16, |
| 3806 | N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> { |
| 3807 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3808 | } |
| 3809 | def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32, |
| 3810 | N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> { |
| 3811 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3812 | } |
| 3813 | def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64, |
| 3814 | N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3815 | // imm6 = xxxxxx |
| 3816 | } |
| 3817 | |
| 3818 | // Neon Shift Long operations, |
| 3819 | // element sizes of 8, 16, 32 bits: |
| 3820 | multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3821 | bit op4, string OpcodeStr, string Dt, SDNode OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3822 | def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4, |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 3823 | OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3824 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3825 | } |
| 3826 | def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4, |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 3827 | OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3828 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3829 | } |
| 3830 | def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4, |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 3831 | OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3832 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3833 | } |
| 3834 | } |
| 3835 | |
| 3836 | // Neon Shift Narrow operations, |
| 3837 | // element sizes of 16, 32, 64 bits: |
| 3838 | multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3839 | bit op4, InstrItinClass itin, string OpcodeStr, string Dt, |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3840 | SDNode OpNode> { |
| 3841 | def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, |
Bill Wendling | a656b63 | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 3842 | OpcodeStr, !strconcat(Dt, "16"), |
Bill Wendling | 3116dce | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 3843 | v8i8, v8i16, shr_imm8, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3844 | let Inst{21-19} = 0b001; // imm6 = 001xxx |
| 3845 | } |
| 3846 | def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, |
Bill Wendling | a656b63 | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 3847 | OpcodeStr, !strconcat(Dt, "32"), |
Bill Wendling | 3116dce | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 3848 | v4i16, v4i32, shr_imm16, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3849 | let Inst{21-20} = 0b01; // imm6 = 01xxxx |
| 3850 | } |
| 3851 | def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, |
Bill Wendling | a656b63 | 2011-03-01 01:00:59 +0000 | [diff] [blame] | 3852 | OpcodeStr, !strconcat(Dt, "64"), |
Bill Wendling | 3116dce | 2011-03-07 23:38:41 +0000 | [diff] [blame] | 3853 | v2i32, v2i64, shr_imm32, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 3854 | let Inst{21} = 0b1; // imm6 = 1xxxxx |
| 3855 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3856 | } |
| 3857 | |
| 3858 | //===----------------------------------------------------------------------===// |
| 3859 | // Instruction Definitions. |
| 3860 | //===----------------------------------------------------------------------===// |
| 3861 | |
| 3862 | // Vector Add Operations. |
| 3863 | |
| 3864 | // VADD : Vector Add (integer and floating-point) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3865 | defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3866 | add, 1>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3867 | def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3868 | v2f32, v2f32, fadd, 1>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3869 | def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3870 | v4f32, v4f32, fadd, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3871 | // VADDL : Vector Add Long (Q = D + D) |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3872 | defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, |
| 3873 | "vaddl", "s", add, sext, 1>; |
| 3874 | defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, |
| 3875 | "vaddl", "u", add, zext, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3876 | // VADDW : Vector Add Wide (Q = Q + D) |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 3877 | defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; |
| 3878 | defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3879 | // VHADD : Vector Halving Add |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3880 | defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm, |
| 3881 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3882 | "vhadd", "s", int_arm_neon_vhadds, 1>; |
| 3883 | defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm, |
| 3884 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3885 | "vhadd", "u", int_arm_neon_vhaddu, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3886 | // VRHADD : Vector Rounding Halving Add |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3887 | defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm, |
| 3888 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3889 | "vrhadd", "s", int_arm_neon_vrhadds, 1>; |
| 3890 | defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm, |
| 3891 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3892 | "vrhadd", "u", int_arm_neon_vrhaddu, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3893 | // VQADD : Vector Saturating Add |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3894 | defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm, |
| 3895 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3896 | "vqadd", "s", int_arm_neon_vqadds, 1>; |
| 3897 | defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm, |
| 3898 | IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, |
| 3899 | "vqadd", "u", int_arm_neon_vqaddu, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3900 | // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3901 | defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", |
| 3902 | int_arm_neon_vaddhn, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3903 | // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3904 | defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i", |
| 3905 | int_arm_neon_vraddhn, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3906 | |
| 3907 | // Vector Multiply Operations. |
| 3908 | |
| 3909 | // VMUL : Vector Multiply (integer, polynomial and floating-point) |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3910 | defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3911 | IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3912 | def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul", |
| 3913 | "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>; |
| 3914 | def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul", |
| 3915 | "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>; |
Evan Cheng | 08cec1e | 2010-10-11 23:41:41 +0000 | [diff] [blame] | 3916 | def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32", |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3917 | v2f32, v2f32, fmul, 1>; |
Evan Cheng | 08cec1e | 2010-10-11 23:41:41 +0000 | [diff] [blame] | 3918 | def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32", |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3919 | v4f32, v4f32, fmul, 1>; |
Jim Grosbach | 45755a7 | 2011-12-05 20:09:44 +0000 | [diff] [blame] | 3920 | defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>; |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3921 | def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>; |
| 3922 | def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, |
| 3923 | v2f32, fmul>; |
| 3924 | |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3925 | def : Pat<(v8i16 (mul (v8i16 QPR:$src1), |
| 3926 | (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), |
| 3927 | (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), |
| 3928 | (v4i16 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3929 | (DSubReg_i16_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3930 | (SubReg_i16_lane imm:$lane)))>; |
| 3931 | def : Pat<(v4i32 (mul (v4i32 QPR:$src1), |
| 3932 | (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), |
| 3933 | (v4i32 (VMULslv4i32 (v4i32 QPR:$src1), |
| 3934 | (v2i32 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3935 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3936 | (SubReg_i32_lane imm:$lane)))>; |
| 3937 | def : Pat<(v4f32 (fmul (v4f32 QPR:$src1), |
| 3938 | (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))), |
| 3939 | (v4f32 (VMULslfq (v4f32 QPR:$src1), |
| 3940 | (v2f32 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3941 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3942 | (SubReg_i32_lane imm:$lane)))>; |
| 3943 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3944 | // VQDMULH : Vector Saturating Doubling Multiply Returning High Half |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3945 | defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D, |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 3946 | IIC_VMULi16Q, IIC_VMULi32Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3947 | "vqdmulh", "s", int_arm_neon_vqdmulh, 1>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3948 | defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D, |
| 3949 | IIC_VMULi16Q, IIC_VMULi32Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3950 | "vqdmulh", "s", int_arm_neon_vqdmulh>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3951 | def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3952 | (v8i16 (NEONvduplane (v8i16 QPR:$src2), |
| 3953 | imm:$lane)))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3954 | (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), |
| 3955 | (v4i16 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3956 | (DSubReg_i16_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3957 | (SubReg_i16_lane imm:$lane)))>; |
| 3958 | def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3959 | (v4i32 (NEONvduplane (v4i32 QPR:$src2), |
| 3960 | imm:$lane)))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3961 | (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), |
| 3962 | (v2i32 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3963 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3964 | (SubReg_i32_lane imm:$lane)))>; |
| 3965 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3966 | // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 3967 | defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm, |
| 3968 | IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3969 | "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 3970 | defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D, |
| 3971 | IIC_VMULi16Q, IIC_VMULi32Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3972 | "vqrdmulh", "s", int_arm_neon_vqrdmulh>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3973 | def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3974 | (v8i16 (NEONvduplane (v8i16 QPR:$src2), |
| 3975 | imm:$lane)))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3976 | (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), |
| 3977 | (v4i16 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3978 | (DSubReg_i16_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3979 | (SubReg_i16_lane imm:$lane)))>; |
| 3980 | def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3981 | (v4i32 (NEONvduplane (v4i32 QPR:$src2), |
| 3982 | imm:$lane)))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3983 | (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), |
| 3984 | (v2i32 (EXTRACT_SUBREG QPR:$src2, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 3985 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3986 | (SubReg_i32_lane imm:$lane)))>; |
| 3987 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3988 | // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3989 | defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, |
| 3990 | "vmull", "s", NEONvmulls, 1>; |
| 3991 | defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, |
| 3992 | "vmull", "u", NEONvmullu, 1>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 3993 | def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 3994 | v8i16, v8i8, int_arm_neon_vmullp, 1>; |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 3995 | defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>; |
| 3996 | defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 3997 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 3998 | // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) |
Anton Korobeynikov | ecc6406 | 2010-04-07 18:21:10 +0000 | [diff] [blame] | 3999 | defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D, |
| 4000 | "vqdmull", "s", int_arm_neon_vqdmull, 1>; |
| 4001 | defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, |
| 4002 | "vqdmull", "s", int_arm_neon_vqdmull>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4003 | |
| 4004 | // Vector Multiply-Accumulate and Multiply-Subtract Operations. |
| 4005 | |
| 4006 | // VMLA : Vector Multiply Accumulate (integer and floating-point) |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 4007 | defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4008 | IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; |
| 4009 | def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4010 | v2f32, fmul_su, fadd_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4011 | Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4012 | def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4013 | v4f32, fmul_su, fadd_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4014 | Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 4015 | defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4016 | IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; |
| 4017 | def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4018 | v2f32, fmul_su, fadd_mlx>, |
| 4019 | Requires<[HasNEON, UseFPVMLx]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4020 | def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4021 | v4f32, v2f32, fmul_su, fadd_mlx>, |
| 4022 | Requires<[HasNEON, UseFPVMLx]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4023 | |
| 4024 | def : Pat<(v8i16 (add (v8i16 QPR:$src1), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4025 | (mul (v8i16 QPR:$src2), |
| 4026 | (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), |
| 4027 | (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4028 | (v4i16 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4029 | (DSubReg_i16_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4030 | (SubReg_i16_lane imm:$lane)))>; |
| 4031 | |
| 4032 | def : Pat<(v4i32 (add (v4i32 QPR:$src1), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4033 | (mul (v4i32 QPR:$src2), |
| 4034 | (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), |
| 4035 | (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4036 | (v2i32 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4037 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4038 | (SubReg_i32_lane imm:$lane)))>; |
| 4039 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4040 | def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1), |
| 4041 | (fmul_su (v4f32 QPR:$src2), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4042 | (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4043 | (v4f32 (VMLAslfq (v4f32 QPR:$src1), |
| 4044 | (v4f32 QPR:$src2), |
| 4045 | (v2f32 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4046 | (DSubReg_i32_reg imm:$lane))), |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4047 | (SubReg_i32_lane imm:$lane)))>, |
| 4048 | Requires<[HasNEON, UseFPVMLx]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4049 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4050 | // VMLAL : Vector Multiply Accumulate Long (Q += D * D) |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 4051 | defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, |
| 4052 | "vmlal", "s", NEONvmulls, add>; |
| 4053 | defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, |
| 4054 | "vmlal", "u", NEONvmullu, add>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4055 | |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 4056 | defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>; |
| 4057 | defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4058 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4059 | // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 4060 | defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 4061 | "vqdmlal", "s", int_arm_neon_vqdmlal>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4062 | defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4063 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4064 | // VMLS : Vector Multiply Subtract (integer and floating-point) |
Bob Wilson | 8f07b9e | 2009-10-03 04:41:21 +0000 | [diff] [blame] | 4065 | defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4066 | IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; |
| 4067 | def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4068 | v2f32, fmul_su, fsub_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4069 | Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4070 | def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4071 | v4f32, fmul_su, fsub_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4072 | Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>; |
David Goodwin | 658ea60 | 2009-09-25 18:38:29 +0000 | [diff] [blame] | 4073 | defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4074 | IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; |
| 4075 | def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4076 | v2f32, fmul_su, fsub_mlx>, |
| 4077 | Requires<[HasNEON, UseFPVMLx]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4078 | def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32", |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4079 | v4f32, v2f32, fmul_su, fsub_mlx>, |
| 4080 | Requires<[HasNEON, UseFPVMLx]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4081 | |
| 4082 | def : Pat<(v8i16 (sub (v8i16 QPR:$src1), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4083 | (mul (v8i16 QPR:$src2), |
| 4084 | (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), |
| 4085 | (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4086 | (v4i16 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4087 | (DSubReg_i16_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4088 | (SubReg_i16_lane imm:$lane)))>; |
| 4089 | |
| 4090 | def : Pat<(v4i32 (sub (v4i32 QPR:$src1), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4091 | (mul (v4i32 QPR:$src2), |
| 4092 | (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), |
| 4093 | (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4094 | (v2i32 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4095 | (DSubReg_i32_reg imm:$lane))), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4096 | (SubReg_i32_lane imm:$lane)))>; |
| 4097 | |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4098 | def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1), |
| 4099 | (fmul_su (v4f32 QPR:$src2), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4100 | (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), |
| 4101 | (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4102 | (v2f32 (EXTRACT_SUBREG QPR:$src3, |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4103 | (DSubReg_i32_reg imm:$lane))), |
Evan Cheng | 48575f6 | 2010-12-05 22:04:16 +0000 | [diff] [blame] | 4104 | (SubReg_i32_lane imm:$lane)))>, |
| 4105 | Requires<[HasNEON, UseFPVMLx]>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4106 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4107 | // VMLSL : Vector Multiply Subtract Long (Q -= D * D) |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 4108 | defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, |
| 4109 | "vmlsl", "s", NEONvmulls, sub>; |
| 4110 | defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, |
| 4111 | "vmlsl", "u", NEONvmullu, sub>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4112 | |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 4113 | defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>; |
| 4114 | defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; |
Anton Korobeynikov | 6ca0b9e | 2009-09-08 15:22:32 +0000 | [diff] [blame] | 4115 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4116 | // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) |
Anton Korobeynikov | 9510207 | 2010-04-07 18:21:04 +0000 | [diff] [blame] | 4117 | defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, |
Anton Korobeynikov | 0a3e2b5 | 2010-04-07 18:20:42 +0000 | [diff] [blame] | 4118 | "vqdmlsl", "s", int_arm_neon_vqdmlsl>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4119 | defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4120 | |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 4121 | // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations. |
| 4122 | def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32", |
| 4123 | v2f32, fmul_su, fadd_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4124 | Requires<[HasVFP4,UseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 4125 | |
| 4126 | def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32", |
| 4127 | v4f32, fmul_su, fadd_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4128 | Requires<[HasVFP4,UseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 4129 | |
| 4130 | // Fused Vector Multiply Subtract (floating-point) |
| 4131 | def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32", |
| 4132 | v2f32, fmul_su, fsub_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4133 | Requires<[HasVFP4,UseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 4134 | def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32", |
| 4135 | v4f32, fmul_su, fsub_mlx>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4136 | Requires<[HasVFP4,UseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 4137 | |
Evan Cheng | 3aef2ff | 2012-04-10 21:40:28 +0000 | [diff] [blame] | 4138 | // Match @llvm.fma.* intrinsics |
Lang Hames | 7787800 | 2012-04-27 18:51:24 +0000 | [diff] [blame] | 4139 | def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)), |
Evan Cheng | 3aef2ff | 2012-04-10 21:40:28 +0000 | [diff] [blame] | 4140 | (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4141 | Requires<[HasVFP4]>; |
Lang Hames | 7787800 | 2012-04-27 18:51:24 +0000 | [diff] [blame] | 4142 | def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)), |
Evan Cheng | 3aef2ff | 2012-04-10 21:40:28 +0000 | [diff] [blame] | 4143 | (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 4144 | Requires<[HasVFP4]>; |
Lang Hames | 7787800 | 2012-04-27 18:51:24 +0000 | [diff] [blame] | 4145 | def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)), |
Evan Cheng | 14b4c03 | 2012-04-11 06:59:47 +0000 | [diff] [blame] | 4146 | (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>, |
| 4147 | Requires<[HasVFP4]>; |
Lang Hames | 7787800 | 2012-04-27 18:51:24 +0000 | [diff] [blame] | 4148 | def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)), |
Evan Cheng | 14b4c03 | 2012-04-11 06:59:47 +0000 | [diff] [blame] | 4149 | (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>, |
| 4150 | Requires<[HasVFP4]>; |
Evan Cheng | 3aef2ff | 2012-04-10 21:40:28 +0000 | [diff] [blame] | 4151 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4152 | // Vector Subtract Operations. |
| 4153 | |
| 4154 | // VSUB : Vector Subtract (integer and floating-point) |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4155 | defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4156 | "vsub", "i", sub, 0>; |
| 4157 | def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4158 | v2f32, v2f32, fsub, 0>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4159 | def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4160 | v4f32, v4f32, fsub, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4161 | // VSUBL : Vector Subtract Long (Q = D - D) |
Bob Wilson | d0b69cf | 2010-09-01 23:50:19 +0000 | [diff] [blame] | 4162 | defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, |
| 4163 | "vsubl", "s", sub, sext, 0>; |
| 4164 | defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, |
| 4165 | "vsubl", "u", sub, zext, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4166 | // VSUBW : Vector Subtract Wide (Q = Q - D) |
Bob Wilson | 04d6c28 | 2010-08-29 05:57:34 +0000 | [diff] [blame] | 4167 | defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; |
| 4168 | defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4169 | // VHSUB : Vector Halving Subtract |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4170 | defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm, |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4171 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4172 | "vhsub", "s", int_arm_neon_vhsubs, 0>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4173 | defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm, |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4174 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4175 | "vhsub", "u", int_arm_neon_vhsubu, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4176 | // VQSUB : Vector Saturing Subtract |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4177 | defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm, |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4178 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4179 | "vqsub", "s", int_arm_neon_vqsubs, 0>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4180 | defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm, |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4181 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4182 | "vqsub", "u", int_arm_neon_vqsubu, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4183 | // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4184 | defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", |
| 4185 | int_arm_neon_vsubhn, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4186 | // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4187 | defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i", |
| 4188 | int_arm_neon_vrsubhn, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4189 | |
| 4190 | // Vector Comparisons. |
| 4191 | |
| 4192 | // VCEQ : Vector Compare Equal |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4193 | defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, |
| 4194 | IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4195 | def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4196 | NEONvceq, 1>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4197 | def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4198 | NEONvceq, 1>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 4199 | |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4200 | defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4201 | "$Vd, $Vm, #0", NEONvceqz>; |
Johnny Chen | ec5a4cd | 2010-02-23 00:33:12 +0000 | [diff] [blame] | 4202 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4203 | // VCGE : Vector Compare Greater Than or Equal |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4204 | defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, |
| 4205 | IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4206 | defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4207 | IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>; |
Johnny Chen | 69631b1 | 2010-03-24 21:25:07 +0000 | [diff] [blame] | 4208 | def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, |
| 4209 | NEONvcge, 0>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4210 | def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32, |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4211 | NEONvcge, 0>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 4212 | |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4213 | defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4214 | "$Vd, $Vm, #0", NEONvcgez>; |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4215 | defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4216 | "$Vd, $Vm, #0", NEONvclez>; |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4217 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4218 | // VCGT : Vector Compare Greater Than |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4219 | defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, |
| 4220 | IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>; |
| 4221 | defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, |
| 4222 | IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4223 | def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32, |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4224 | NEONvcgt, 0>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4225 | def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32, |
Evan Cheng | ac0869d | 2009-11-21 06:21:52 +0000 | [diff] [blame] | 4226 | NEONvcgt, 0>; |
Owen Anderson | c24cb35 | 2010-11-08 23:21:22 +0000 | [diff] [blame] | 4227 | |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4228 | defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4229 | "$Vd, $Vm, #0", NEONvcgtz>; |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4230 | defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4231 | "$Vd, $Vm, #0", NEONvcltz>; |
Johnny Chen | 363ac58 | 2010-02-23 01:42:58 +0000 | [diff] [blame] | 4232 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4233 | // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4234 | def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", |
| 4235 | "f32", v2i32, v2f32, int_arm_neon_vacged, 0>; |
| 4236 | def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge", |
| 4237 | "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4238 | // VACGT : Vector Absolute Compare Greater Than (aka VCAGT) |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4239 | def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt", |
| 4240 | "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>; |
| 4241 | def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", |
| 4242 | "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4243 | // VTST : Vector Test Bits |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4244 | defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, |
Bob Wilson | 3a4a832 | 2010-01-17 06:35:17 +0000 | [diff] [blame] | 4245 | IIC_VBINi4Q, "vtst", "", NEONvtst, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4246 | |
| 4247 | // Vector Bitwise Operations. |
| 4248 | |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 4249 | def vnotd : PatFrag<(ops node:$in), |
| 4250 | (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>; |
| 4251 | def vnotq : PatFrag<(ops node:$in), |
| 4252 | (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>; |
Chris Lattner | b26fdcb | 2010-03-28 08:08:07 +0000 | [diff] [blame] | 4253 | |
| 4254 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4255 | // VAND : Vector Bitwise AND |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4256 | def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", |
| 4257 | v2i32, v2i32, and, 1>; |
| 4258 | def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", |
| 4259 | v4i32, v4i32, and, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4260 | |
| 4261 | // VEOR : Vector Bitwise Exclusive OR |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4262 | def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", |
| 4263 | v2i32, v2i32, xor, 1>; |
| 4264 | def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", |
| 4265 | v4i32, v4i32, xor, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4266 | |
| 4267 | // VORR : Vector Bitwise OR |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4268 | def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", |
| 4269 | v2i32, v2i32, or, 1>; |
| 4270 | def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", |
| 4271 | v4i32, v4i32, or, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4272 | |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4273 | def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1, |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4274 | (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4275 | IIC_VMOVImm, |
| 4276 | "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", |
| 4277 | [(set DPR:$Vd, |
| 4278 | (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { |
| 4279 | let Inst{9} = SIMM{9}; |
| 4280 | } |
| 4281 | |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4282 | def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4283 | (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4284 | IIC_VMOVImm, |
| 4285 | "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", |
| 4286 | [(set DPR:$Vd, |
| 4287 | (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4288 | let Inst{10-9} = SIMM{10-9}; |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4289 | } |
| 4290 | |
| 4291 | def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4292 | (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4293 | IIC_VMOVImm, |
| 4294 | "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", |
| 4295 | [(set QPR:$Vd, |
| 4296 | (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { |
| 4297 | let Inst{9} = SIMM{9}; |
| 4298 | } |
| 4299 | |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4300 | def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4301 | (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4302 | IIC_VMOVImm, |
| 4303 | "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", |
| 4304 | [(set QPR:$Vd, |
| 4305 | (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4306 | let Inst{10-9} = SIMM{10-9}; |
Owen Anderson | d966817 | 2010-11-03 22:44:51 +0000 | [diff] [blame] | 4307 | } |
| 4308 | |
| 4309 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4310 | // VBIC : Vector Bitwise Bit Clear (AND NOT) |
Jim Grosbach | 2727930 | 2012-05-02 21:11:56 +0000 | [diff] [blame] | 4311 | let TwoOperandAliasConstraint = "$Vn = $Vd" in { |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4312 | def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), |
| 4313 | (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, |
| 4314 | "vbic", "$Vd, $Vn, $Vm", "", |
| 4315 | [(set DPR:$Vd, (v2i32 (and DPR:$Vn, |
| 4316 | (vnotd DPR:$Vm))))]>; |
| 4317 | def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), |
| 4318 | (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, |
| 4319 | "vbic", "$Vd, $Vn, $Vm", "", |
| 4320 | [(set QPR:$Vd, (v4i32 (and QPR:$Vn, |
| 4321 | (vnotq QPR:$Vm))))]>; |
Jim Grosbach | 2727930 | 2012-05-02 21:11:56 +0000 | [diff] [blame] | 4322 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4323 | |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4324 | def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4325 | (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4326 | IIC_VMOVImm, |
| 4327 | "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", |
| 4328 | [(set DPR:$Vd, |
| 4329 | (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { |
| 4330 | let Inst{9} = SIMM{9}; |
| 4331 | } |
| 4332 | |
| 4333 | def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4334 | (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4335 | IIC_VMOVImm, |
| 4336 | "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", |
| 4337 | [(set DPR:$Vd, |
| 4338 | (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { |
| 4339 | let Inst{10-9} = SIMM{10-9}; |
| 4340 | } |
| 4341 | |
| 4342 | def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4343 | (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4344 | IIC_VMOVImm, |
| 4345 | "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", |
| 4346 | [(set QPR:$Vd, |
| 4347 | (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { |
| 4348 | let Inst{9} = SIMM{9}; |
| 4349 | } |
| 4350 | |
| 4351 | def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4352 | (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), |
Owen Anderson | 080c092 | 2010-11-05 19:27:46 +0000 | [diff] [blame] | 4353 | IIC_VMOVImm, |
| 4354 | "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", |
| 4355 | [(set QPR:$Vd, |
| 4356 | (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { |
| 4357 | let Inst{10-9} = SIMM{10-9}; |
| 4358 | } |
| 4359 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4360 | // VORN : Vector Bitwise OR NOT |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4361 | def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd), |
| 4362 | (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, |
| 4363 | "vorn", "$Vd, $Vn, $Vm", "", |
| 4364 | [(set DPR:$Vd, (v2i32 (or DPR:$Vn, |
| 4365 | (vnotd DPR:$Vm))))]>; |
| 4366 | def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd), |
| 4367 | (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, |
| 4368 | "vorn", "$Vd, $Vn, $Vm", "", |
| 4369 | [(set QPR:$Vd, (v4i32 (or QPR:$Vn, |
| 4370 | (vnotq QPR:$Vm))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4371 | |
Bob Wilson | 7e3f0d2 | 2010-07-14 06:31:50 +0000 | [diff] [blame] | 4372 | // VMVN : Vector Bitwise NOT (Immediate) |
| 4373 | |
| 4374 | let isReMaterializable = 1 in { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4375 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4376 | def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd), |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4377 | (ins nImmSplatI16:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4378 | "vmvn", "i16", "$Vd, $SIMM", "", |
| 4379 | [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4380 | let Inst{9} = SIMM{9}; |
| 4381 | } |
| 4382 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4383 | def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd), |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4384 | (ins nImmSplatI16:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4385 | "vmvn", "i16", "$Vd, $SIMM", "", |
| 4386 | [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4387 | let Inst{9} = SIMM{9}; |
| 4388 | } |
| 4389 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4390 | def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd), |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4391 | (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4392 | "vmvn", "i32", "$Vd, $SIMM", "", |
| 4393 | [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4394 | let Inst{11-8} = SIMM{11-8}; |
| 4395 | } |
| 4396 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4397 | def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd), |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4398 | (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4399 | "vmvn", "i32", "$Vd, $SIMM", "", |
| 4400 | [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4401 | let Inst{11-8} = SIMM{11-8}; |
| 4402 | } |
Bob Wilson | 7e3f0d2 | 2010-07-14 06:31:50 +0000 | [diff] [blame] | 4403 | } |
| 4404 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4405 | // VMVN : Vector Bitwise NOT |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4406 | def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4407 | (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD, |
| 4408 | "vmvn", "$Vd, $Vm", "", |
| 4409 | [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4410 | def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4411 | (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD, |
| 4412 | "vmvn", "$Vd, $Vm", "", |
| 4413 | [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>; |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 4414 | def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>; |
| 4415 | def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4416 | |
| 4417 | // VBSL : Vector Bitwise Select |
Owen Anderson | 4110b43 | 2010-10-25 20:13:13 +0000 | [diff] [blame] | 4418 | def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), |
| 4419 | (ins DPR:$src1, DPR:$Vn, DPR:$Vm), |
Bob Wilson | 2cd1a12 | 2010-03-27 04:01:23 +0000 | [diff] [blame] | 4420 | N3RegFrm, IIC_VCNTiD, |
Owen Anderson | 4110b43 | 2010-10-25 20:13:13 +0000 | [diff] [blame] | 4421 | "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 4422 | [(set DPR:$Vd, |
| 4423 | (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>; |
Cameron Zwarich | c0e6d78 | 2011-03-30 23:01:21 +0000 | [diff] [blame] | 4424 | |
| 4425 | def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd), |
| 4426 | (and DPR:$Vm, (vnotd DPR:$Vd)))), |
| 4427 | (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>; |
| 4428 | |
Owen Anderson | 4110b43 | 2010-10-25 20:13:13 +0000 | [diff] [blame] | 4429 | def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), |
| 4430 | (ins QPR:$src1, QPR:$Vn, QPR:$Vm), |
Bob Wilson | 2cd1a12 | 2010-03-27 04:01:23 +0000 | [diff] [blame] | 4431 | N3RegFrm, IIC_VCNTiQ, |
Owen Anderson | 4110b43 | 2010-10-25 20:13:13 +0000 | [diff] [blame] | 4432 | "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | f921c0fe | 2011-06-13 22:54:22 +0000 | [diff] [blame] | 4433 | [(set QPR:$Vd, |
| 4434 | (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>; |
Cameron Zwarich | c0e6d78 | 2011-03-30 23:01:21 +0000 | [diff] [blame] | 4435 | |
| 4436 | def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd), |
| 4437 | (and QPR:$Vm, (vnotq QPR:$Vd)))), |
| 4438 | (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4439 | |
| 4440 | // VBIF : Vector Bitwise Insert if False |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4441 | // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst", |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4442 | // FIXME: This instruction's encoding MAY NOT BE correct. |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4443 | def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4444 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 4445 | N3RegFrm, IIC_VBINiD, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4446 | "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 4447 | []>; |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4448 | def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4449 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 4450 | N3RegFrm, IIC_VBINiQ, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4451 | "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 4452 | []>; |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4453 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4454 | // VBIT : Vector Bitwise Insert if True |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4455 | // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst", |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4456 | // FIXME: This instruction's encoding MAY NOT BE correct. |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4457 | def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4458 | (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 4459 | N3RegFrm, IIC_VBINiD, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4460 | "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 4461 | []>; |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4462 | def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4463 | (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), |
Bob Wilson | 10bc69c | 2010-03-27 03:56:52 +0000 | [diff] [blame] | 4464 | N3RegFrm, IIC_VBINiQ, |
Owen Anderson | 31e6ed8 | 2010-10-25 20:17:22 +0000 | [diff] [blame] | 4465 | "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 4466 | []>; |
Johnny Chen | 4814e71 | 2010-02-09 23:05:23 +0000 | [diff] [blame] | 4467 | |
| 4468 | // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4469 | // for equivalent operations with different register constraints; it just |
| 4470 | // inserts copies. |
| 4471 | |
| 4472 | // Vector Absolute Differences. |
| 4473 | |
| 4474 | // VABD : Vector Absolute Difference |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4475 | defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm, |
Anton Korobeynikov | 4ac0af8 | 2010-04-07 18:20:18 +0000 | [diff] [blame] | 4476 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4477 | "vabd", "s", int_arm_neon_vabds, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4478 | defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm, |
Anton Korobeynikov | 4ac0af8 | 2010-04-07 18:20:18 +0000 | [diff] [blame] | 4479 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4480 | "vabd", "u", int_arm_neon_vabdu, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4481 | def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4482 | "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4483 | def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ, |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4484 | "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4485 | |
| 4486 | // VABDL : Vector Absolute Difference Long (Q = | D - D |) |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4487 | defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, |
| 4488 | "vabdl", "s", int_arm_neon_vabds, zext, 1>; |
| 4489 | defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, |
| 4490 | "vabdl", "u", int_arm_neon_vabdu, zext, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4491 | |
| 4492 | // VABA : Vector Absolute Difference and Accumulate |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4493 | defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ, |
| 4494 | "vaba", "s", int_arm_neon_vabds, add>; |
| 4495 | defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ, |
| 4496 | "vaba", "u", int_arm_neon_vabdu, add>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4497 | |
| 4498 | // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) |
Bob Wilson | eb0c3d3 | 2010-09-03 01:35:08 +0000 | [diff] [blame] | 4499 | defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD, |
| 4500 | "vabal", "s", int_arm_neon_vabds, zext, add>; |
| 4501 | defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD, |
| 4502 | "vabal", "u", int_arm_neon_vabdu, zext, add>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4503 | |
| 4504 | // Vector Maximum and Minimum. |
| 4505 | |
| 4506 | // VMAX : Vector Maximum |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4507 | defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm, |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4508 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4509 | "vmax", "s", int_arm_neon_vmaxs, 1>; |
| 4510 | defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm, |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4511 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4512 | "vmax", "u", int_arm_neon_vmaxu, 1>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4513 | def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND, |
| 4514 | "vmax", "f32", |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4515 | v2f32, v2f32, int_arm_neon_vmaxs, 1>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4516 | def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ, |
| 4517 | "vmax", "f32", |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4518 | v4f32, v4f32, int_arm_neon_vmaxs, 1>; |
| 4519 | |
| 4520 | // VMIN : Vector Minimum |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4521 | defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm, |
| 4522 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
| 4523 | "vmin", "s", int_arm_neon_vmins, 1>; |
| 4524 | defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm, |
| 4525 | IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, |
| 4526 | "vmin", "u", int_arm_neon_vminu, 1>; |
| 4527 | def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, |
| 4528 | "vmin", "f32", |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4529 | v2f32, v2f32, int_arm_neon_vmins, 1>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4530 | def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, |
| 4531 | "vmin", "f32", |
Anton Korobeynikov | f8b5c63 | 2010-04-07 18:20:13 +0000 | [diff] [blame] | 4532 | v4f32, v4f32, int_arm_neon_vmins, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4533 | |
| 4534 | // Vector Pairwise Operations. |
| 4535 | |
| 4536 | // VPADD : Vector Pairwise Add |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4537 | def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD, |
| 4538 | "vpadd", "i8", |
| 4539 | v8i8, v8i8, int_arm_neon_vpadd, 0>; |
| 4540 | def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD, |
| 4541 | "vpadd", "i16", |
| 4542 | v4i16, v4i16, int_arm_neon_vpadd, 0>; |
| 4543 | def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD, |
| 4544 | "vpadd", "i32", |
| 4545 | v2i32, v2i32, int_arm_neon_vpadd, 0>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4546 | def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm, |
Evan Cheng | 08cec1e | 2010-10-11 23:41:41 +0000 | [diff] [blame] | 4547 | IIC_VPBIND, "vpadd", "f32", |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4548 | v2f32, v2f32, int_arm_neon_vpadd, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4549 | |
| 4550 | // VPADDL : Vector Pairwise Add Long |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4551 | defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4552 | int_arm_neon_vpaddls>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4553 | defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4554 | int_arm_neon_vpaddlu>; |
| 4555 | |
| 4556 | // VPADAL : Vector Pairwise Add and Accumulate Long |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4557 | defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4558 | int_arm_neon_vpadals>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4559 | defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4560 | int_arm_neon_vpadalu>; |
| 4561 | |
| 4562 | // VPMAX : Vector Pairwise Maximum |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4563 | def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4564 | "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4565 | def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4566 | "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4567 | def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4568 | "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4569 | def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4570 | "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4571 | def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4572 | "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4573 | def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4574 | "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>; |
Evan Cheng | 08cec1e | 2010-10-11 23:41:41 +0000 | [diff] [blame] | 4575 | def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4576 | "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4577 | |
| 4578 | // VPMIN : Vector Pairwise Minimum |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4579 | def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4580 | "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4581 | def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4582 | "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4583 | def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4584 | "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4585 | def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4586 | "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4587 | def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4588 | "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>; |
Anton Korobeynikov | 1c03f24 | 2010-04-07 18:20:24 +0000 | [diff] [blame] | 4589 | def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4590 | "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>; |
Evan Cheng | 08cec1e | 2010-10-11 23:41:41 +0000 | [diff] [blame] | 4591 | def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin", |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4592 | "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4593 | |
| 4594 | // Vector Reciprocal and Reciprocal Square Root Estimate and Step. |
| 4595 | |
| 4596 | // VRECPE : Vector Reciprocal Estimate |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4597 | def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4598 | IIC_VUNAD, "vrecpe", "u32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4599 | v2i32, v2i32, int_arm_neon_vrecpe>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4600 | def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4601 | IIC_VUNAQ, "vrecpe", "u32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4602 | v4i32, v4i32, int_arm_neon_vrecpe>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4603 | def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4604 | IIC_VUNAD, "vrecpe", "f32", |
Bob Wilson | b0abb4d | 2009-08-11 05:39:44 +0000 | [diff] [blame] | 4605 | v2f32, v2f32, int_arm_neon_vrecpe>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4606 | def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4607 | IIC_VUNAQ, "vrecpe", "f32", |
Bob Wilson | b0abb4d | 2009-08-11 05:39:44 +0000 | [diff] [blame] | 4608 | v4f32, v4f32, int_arm_neon_vrecpe>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4609 | |
| 4610 | // VRECPS : Vector Reciprocal Step |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4611 | def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4612 | IIC_VRECSD, "vrecps", "f32", |
| 4613 | v2f32, v2f32, int_arm_neon_vrecps, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4614 | def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4615 | IIC_VRECSQ, "vrecps", "f32", |
| 4616 | v4f32, v4f32, int_arm_neon_vrecps, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4617 | |
| 4618 | // VRSQRTE : Vector Reciprocal Square Root Estimate |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4619 | def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4620 | IIC_VUNAD, "vrsqrte", "u32", |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4621 | v2i32, v2i32, int_arm_neon_vrsqrte>; |
| 4622 | def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4623 | IIC_VUNAQ, "vrsqrte", "u32", |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4624 | v4i32, v4i32, int_arm_neon_vrsqrte>; |
| 4625 | def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4626 | IIC_VUNAD, "vrsqrte", "f32", |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4627 | v2f32, v2f32, int_arm_neon_vrsqrte>; |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4628 | def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4629 | IIC_VUNAQ, "vrsqrte", "f32", |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4630 | v4f32, v4f32, int_arm_neon_vrsqrte>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4631 | |
| 4632 | // VRSQRTS : Vector Reciprocal Square Root Step |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4633 | def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4634 | IIC_VRECSD, "vrsqrts", "f32", |
| 4635 | v2f32, v2f32, int_arm_neon_vrsqrts, 1>; |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4636 | def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4637 | IIC_VRECSQ, "vrsqrts", "f32", |
| 4638 | v4f32, v4f32, int_arm_neon_vrsqrts, 1>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4639 | |
| 4640 | // Vector Shifts. |
| 4641 | |
| 4642 | // VSHL : Vector Shift |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 4643 | defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4644 | IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 4645 | "vshl", "s", int_arm_neon_vshifts>; |
Owen Anderson | 3557d00 | 2010-10-26 20:56:57 +0000 | [diff] [blame] | 4646 | defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4647 | IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, |
Owen Anderson | ac92262 | 2010-10-26 21:13:59 +0000 | [diff] [blame] | 4648 | "vshl", "u", int_arm_neon_vshiftu>; |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 4649 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4650 | // VSHL : Vector Shift Left (Immediate) |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 4651 | defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>; |
| 4652 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4653 | // VSHR : Vector Shift Right (Immediate) |
Jim Grosbach | 22378fd | 2012-04-05 07:23:53 +0000 | [diff] [blame] | 4654 | defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs", |
| 4655 | NEONvshrs>; |
| 4656 | defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu", |
| 4657 | NEONvshru>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4658 | |
| 4659 | // VSHLL : Vector Shift Left Long |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4660 | defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>; |
| 4661 | defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4662 | |
| 4663 | // VSHLL : Vector Shift Left Long (with maximum shift count) |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4664 | class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4665 | bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy, |
Jim Grosbach | 4e41395 | 2011-12-07 00:02:17 +0000 | [diff] [blame] | 4666 | ValueType OpTy, Operand ImmTy, SDNode OpNode> |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4667 | : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt, |
Jim Grosbach | 4e41395 | 2011-12-07 00:02:17 +0000 | [diff] [blame] | 4668 | ResTy, OpTy, ImmTy, OpNode> { |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4669 | let Inst{21-16} = op21_16; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 4670 | let DecoderMethod = "DecodeVSHLMaxInstruction"; |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4671 | } |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4672 | def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8", |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 4673 | v8i16, v8i8, imm8, NEONvshlli>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4674 | def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16", |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 4675 | v4i32, v4i16, imm16, NEONvshlli>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4676 | def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32", |
Jim Grosbach | 3b8991c | 2011-12-07 01:07:24 +0000 | [diff] [blame] | 4677 | v2i64, v2i32, imm32, NEONvshlli>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4678 | |
| 4679 | // VSHRN : Vector Shift Right and Narrow |
Evan Cheng | ef0ccad | 2010-10-01 21:48:06 +0000 | [diff] [blame] | 4680 | defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4681 | NEONvshrn>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4682 | |
| 4683 | // VRSHL : Vector Rounding Shift |
Owen Anderson | 632c235 | 2010-10-26 21:58:41 +0000 | [diff] [blame] | 4684 | defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4685 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 632c235 | 2010-10-26 21:58:41 +0000 | [diff] [blame] | 4686 | "vrshl", "s", int_arm_neon_vrshifts>; |
| 4687 | defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4688 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 632c235 | 2010-10-26 21:58:41 +0000 | [diff] [blame] | 4689 | "vrshl", "u", int_arm_neon_vrshiftu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4690 | // VRSHR : Vector Rounding Shift Right |
Jim Grosbach | 22378fd | 2012-04-05 07:23:53 +0000 | [diff] [blame] | 4691 | defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs", |
| 4692 | NEONvrshrs>; |
| 4693 | defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu", |
| 4694 | NEONvrshru>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4695 | |
| 4696 | // VRSHRN : Vector Rounding Shift Right and Narrow |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4697 | defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4698 | NEONvrshrn>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4699 | |
| 4700 | // VQSHL : Vector Saturating Shift |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4701 | defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4702 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4703 | "vqshl", "s", int_arm_neon_vqshifts>; |
| 4704 | defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4705 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4706 | "vqshl", "u", int_arm_neon_vqshiftu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4707 | // VQSHL : Vector Saturating Shift Left (Immediate) |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 4708 | defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>; |
| 4709 | defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>; |
| 4710 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4711 | // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) |
Bill Wendling | 7c6b608 | 2011-03-08 23:48:09 +0000 | [diff] [blame] | 4712 | defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4713 | |
| 4714 | // VQSHRN : Vector Saturating Shift Right and Narrow |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4715 | defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4716 | NEONvqshrns>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4717 | defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4718 | NEONvqshrnu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4719 | |
| 4720 | // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4721 | defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4722 | NEONvqshrnsu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4723 | |
| 4724 | // VQRSHL : Vector Saturating Rounding Shift |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4725 | defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4726 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4727 | "vqrshl", "s", int_arm_neon_vqrshifts>; |
| 4728 | defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm, |
Johnny Chen | 9ee9d7d | 2010-03-26 23:49:07 +0000 | [diff] [blame] | 4729 | IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, |
Owen Anderson | 86ed232 | 2010-10-26 22:50:46 +0000 | [diff] [blame] | 4730 | "vqrshl", "u", int_arm_neon_vqrshiftu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4731 | |
| 4732 | // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4733 | defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4734 | NEONvqrshrns>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4735 | defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4736 | NEONvqrshrnu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4737 | |
| 4738 | // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4739 | defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s", |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 4740 | NEONvqrshrnsu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4741 | |
| 4742 | // VSRA : Vector Shift Right and Accumulate |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4743 | defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>; |
| 4744 | defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4745 | // VRSRA : Vector Rounding Shift Right and Accumulate |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4746 | defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>; |
| 4747 | defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4748 | |
| 4749 | // VSLI : Vector Shift Left and Insert |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 4750 | defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">; |
| 4751 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4752 | // VSRI : Vector Shift Right and Insert |
Bill Wendling | 620d0cc | 2011-03-09 00:33:17 +0000 | [diff] [blame] | 4753 | defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4754 | |
| 4755 | // Vector Absolute and Saturating Absolute. |
| 4756 | |
| 4757 | // VABS : Vector Absolute Value |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4758 | defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4759 | IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4760 | int_arm_neon_vabs>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4761 | def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4762 | IIC_VUNAD, "vabs", "f32", |
Bob Wilson | b0abb4d | 2009-08-11 05:39:44 +0000 | [diff] [blame] | 4763 | v2f32, v2f32, int_arm_neon_vabs>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4764 | def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4765 | IIC_VUNAQ, "vabs", "f32", |
Bob Wilson | b0abb4d | 2009-08-11 05:39:44 +0000 | [diff] [blame] | 4766 | v4f32, v4f32, int_arm_neon_vabs>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4767 | |
| 4768 | // VQABS : Vector Saturating Absolute Value |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4769 | defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4770 | IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4771 | int_arm_neon_vqabs>; |
| 4772 | |
| 4773 | // Vector Negate. |
| 4774 | |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 4775 | def vnegd : PatFrag<(ops node:$in), |
| 4776 | (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>; |
| 4777 | def vnegq : PatFrag<(ops node:$in), |
| 4778 | (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4779 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4780 | class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4781 | : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), |
| 4782 | IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 4783 | [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4784 | class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4785 | : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), |
| 4786 | IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "", |
| 4787 | [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4788 | |
Chris Lattner | 0a00ed9 | 2010-03-28 08:39:10 +0000 | [diff] [blame] | 4789 | // VNEG : Vector Negate (integer) |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4790 | def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>; |
| 4791 | def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>; |
| 4792 | def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>; |
| 4793 | def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>; |
| 4794 | def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>; |
| 4795 | def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4796 | |
| 4797 | // VNEG : Vector Negate (floating-point) |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 4798 | def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4799 | (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD, |
| 4800 | "vneg", "f32", "$Vd, $Vm", "", |
| 4801 | [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4802 | def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4803 | (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ, |
| 4804 | "vneg", "f32", "$Vd, $Vm", "", |
| 4805 | [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4806 | |
Bob Wilson | cba270d | 2010-07-13 21:16:48 +0000 | [diff] [blame] | 4807 | def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>; |
| 4808 | def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>; |
| 4809 | def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>; |
| 4810 | def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>; |
| 4811 | def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>; |
| 4812 | def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4813 | |
| 4814 | // VQNEG : Vector Saturating Negate |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4815 | defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4816 | IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4817 | int_arm_neon_vqneg>; |
| 4818 | |
| 4819 | // Vector Bit Counting Operations. |
| 4820 | |
| 4821 | // VCLS : Vector Count Leading Sign Bits |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4822 | defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4823 | IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4824 | int_arm_neon_vcls>; |
| 4825 | // VCLZ : Vector Count Leading Zeros |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4826 | defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4827 | IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i", |
Joel Jones | 06a6a30 | 2012-07-13 23:25:25 +0000 | [diff] [blame] | 4828 | ctlz>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4829 | // VCNT : Vector Count One Bits |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4830 | def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4831 | IIC_VCNTiD, "vcnt", "8", |
Joel Jones | 7c82e6a | 2012-07-18 00:02:16 +0000 | [diff] [blame] | 4832 | v8i8, v8i8, ctpop>; |
David Goodwin | 127221f | 2009-09-23 21:38:08 +0000 | [diff] [blame] | 4833 | def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 4834 | IIC_VCNTiQ, "vcnt", "8", |
Joel Jones | 7c82e6a | 2012-07-18 00:02:16 +0000 | [diff] [blame] | 4835 | v16i8, v16i8, ctpop>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4836 | |
Jim Grosbach | fe7b499 | 2011-10-21 16:14:12 +0000 | [diff] [blame] | 4837 | // Vector Swap |
Johnny Chen | d883604 | 2010-02-24 20:06:07 +0000 | [diff] [blame] | 4838 | def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0, |
Jim Grosbach | a45e374 | 2012-03-30 18:53:01 +0000 | [diff] [blame] | 4839 | (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2), |
| 4840 | NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", |
Lang Hames | 2cc494b | 2012-02-13 23:37:19 +0000 | [diff] [blame] | 4841 | []>; |
Johnny Chen | d883604 | 2010-02-24 20:06:07 +0000 | [diff] [blame] | 4842 | def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0, |
Jim Grosbach | a45e374 | 2012-03-30 18:53:01 +0000 | [diff] [blame] | 4843 | (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2), |
| 4844 | NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", |
Lang Hames | 2cc494b | 2012-02-13 23:37:19 +0000 | [diff] [blame] | 4845 | []>; |
Johnny Chen | d883604 | 2010-02-24 20:06:07 +0000 | [diff] [blame] | 4846 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4847 | // Vector Move Operations. |
| 4848 | |
| 4849 | // VMOV : Vector Move (Register) |
Owen Anderson | 43967a9 | 2011-07-15 18:46:47 +0000 | [diff] [blame] | 4850 | def : InstAlias<"vmov${p} $Vd, $Vm", |
| 4851 | (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; |
| 4852 | def : InstAlias<"vmov${p} $Vd, $Vm", |
| 4853 | (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4854 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4855 | // VMOV : Vector Move (Immediate) |
| 4856 | |
Evan Cheng | 47006be | 2010-05-17 21:54:50 +0000 | [diff] [blame] | 4857 | let isReMaterializable = 1 in { |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4858 | def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd), |
Jim Grosbach | 0e387b2 | 2011-10-17 22:26:03 +0000 | [diff] [blame] | 4859 | (ins nImmSplatI8:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4860 | "vmov", "i8", "$Vd, $SIMM", "", |
| 4861 | [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>; |
| 4862 | def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd), |
Jim Grosbach | 0e387b2 | 2011-10-17 22:26:03 +0000 | [diff] [blame] | 4863 | (ins nImmSplatI8:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4864 | "vmov", "i8", "$Vd, $SIMM", "", |
| 4865 | [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4866 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4867 | def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd), |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4868 | (ins nImmSplatI16:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4869 | "vmov", "i16", "$Vd, $SIMM", "", |
| 4870 | [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> { |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 4871 | let Inst{9} = SIMM{9}; |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4872 | } |
| 4873 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4874 | def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd), |
Jim Grosbach | ea46110 | 2011-10-17 23:09:09 +0000 | [diff] [blame] | 4875 | (ins nImmSplatI16:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4876 | "vmov", "i16", "$Vd, $SIMM", "", |
| 4877 | [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4878 | let Inst{9} = SIMM{9}; |
| 4879 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4880 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4881 | def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd), |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4882 | (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4883 | "vmov", "i32", "$Vd, $SIMM", "", |
| 4884 | [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4885 | let Inst{11-8} = SIMM{11-8}; |
| 4886 | } |
| 4887 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4888 | def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd), |
Jim Grosbach | 6248a54 | 2011-10-18 00:22:00 +0000 | [diff] [blame] | 4889 | (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4890 | "vmov", "i32", "$Vd, $SIMM", "", |
| 4891 | [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> { |
Owen Anderson | a88ea03 | 2010-10-26 17:40:54 +0000 | [diff] [blame] | 4892 | let Inst{11-8} = SIMM{11-8}; |
| 4893 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4894 | |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4895 | def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd), |
Jim Grosbach | f2f5bc6 | 2011-10-18 16:18:11 +0000 | [diff] [blame] | 4896 | (ins nImmSplatI64:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4897 | "vmov", "i64", "$Vd, $SIMM", "", |
| 4898 | [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>; |
| 4899 | def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd), |
Jim Grosbach | f2f5bc6 | 2011-10-18 16:18:11 +0000 | [diff] [blame] | 4900 | (ins nImmSplatI64:$SIMM), IIC_VMOVImm, |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 4901 | "vmov", "i64", "$Vd, $SIMM", "", |
| 4902 | [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>; |
Evan Cheng | eaa192a | 2011-11-15 02:12:34 +0000 | [diff] [blame] | 4903 | |
| 4904 | def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd), |
| 4905 | (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, |
| 4906 | "vmov", "f32", "$Vd, $SIMM", "", |
| 4907 | [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>; |
| 4908 | def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd), |
| 4909 | (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, |
| 4910 | "vmov", "f32", "$Vd, $SIMM", "", |
| 4911 | [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>; |
Evan Cheng | 47006be | 2010-05-17 21:54:50 +0000 | [diff] [blame] | 4912 | } // isReMaterializable |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4913 | |
| 4914 | // VMOV : Vector Get Lane (move scalar to ARM core register) |
| 4915 | |
Johnny Chen | 131c4a5 | 2009-11-23 17:48:17 +0000 | [diff] [blame] | 4916 | def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?}, |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4917 | (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), |
| 4918 | IIC_VMOVSI, "vmov", "s8", "$R, $V$lane", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4919 | [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V), |
| 4920 | imm:$lane))]> { |
| 4921 | let Inst{21} = lane{2}; |
| 4922 | let Inst{6-5} = lane{1-0}; |
| 4923 | } |
Johnny Chen | 131c4a5 | 2009-11-23 17:48:17 +0000 | [diff] [blame] | 4924 | def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1}, |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4925 | (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), |
| 4926 | IIC_VMOVSI, "vmov", "s16", "$R, $V$lane", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4927 | [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V), |
| 4928 | imm:$lane))]> { |
| 4929 | let Inst{21} = lane{1}; |
| 4930 | let Inst{6} = lane{0}; |
| 4931 | } |
Johnny Chen | 131c4a5 | 2009-11-23 17:48:17 +0000 | [diff] [blame] | 4932 | def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?}, |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4933 | (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), |
| 4934 | IIC_VMOVSI, "vmov", "u8", "$R, $V$lane", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4935 | [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V), |
| 4936 | imm:$lane))]> { |
| 4937 | let Inst{21} = lane{2}; |
| 4938 | let Inst{6-5} = lane{1-0}; |
| 4939 | } |
Johnny Chen | 131c4a5 | 2009-11-23 17:48:17 +0000 | [diff] [blame] | 4940 | def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1}, |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4941 | (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), |
| 4942 | IIC_VMOVSI, "vmov", "u16", "$R, $V$lane", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4943 | [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V), |
| 4944 | imm:$lane))]> { |
| 4945 | let Inst{21} = lane{1}; |
| 4946 | let Inst{6} = lane{0}; |
| 4947 | } |
Johnny Chen | 131c4a5 | 2009-11-23 17:48:17 +0000 | [diff] [blame] | 4948 | def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4949 | (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane), |
| 4950 | IIC_VMOVSI, "vmov", "32", "$R, $V$lane", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4951 | [(set GPR:$R, (extractelt (v2i32 DPR:$V), |
| 4952 | imm:$lane))]> { |
| 4953 | let Inst{21} = lane{0}; |
| 4954 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4955 | // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td |
| 4956 | def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), |
| 4957 | (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4958 | (DSubReg_i8_reg imm:$lane))), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4959 | (SubReg_i8_lane imm:$lane))>; |
| 4960 | def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), |
| 4961 | (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4962 | (DSubReg_i16_reg imm:$lane))), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4963 | (SubReg_i16_lane imm:$lane))>; |
| 4964 | def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), |
| 4965 | (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4966 | (DSubReg_i8_reg imm:$lane))), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4967 | (SubReg_i8_lane imm:$lane))>; |
| 4968 | def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), |
| 4969 | (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4970 | (DSubReg_i16_reg imm:$lane))), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4971 | (SubReg_i16_lane imm:$lane))>; |
| 4972 | def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), |
| 4973 | (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4974 | (DSubReg_i32_reg imm:$lane))), |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4975 | (SubReg_i32_lane imm:$lane))>; |
Anton Korobeynikov | 2324bdc | 2009-08-28 23:41:26 +0000 | [diff] [blame] | 4976 | def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4977 | (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)), |
Anton Korobeynikov | e56f908 | 2009-09-12 22:21:08 +0000 | [diff] [blame] | 4978 | (SSubReg_f32_reg imm:$src2))>; |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4979 | def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2), |
Bob Wilson | 9abe19d | 2010-02-17 00:31:29 +0000 | [diff] [blame] | 4980 | (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)), |
Anton Korobeynikov | e56f908 | 2009-09-12 22:21:08 +0000 | [diff] [blame] | 4981 | (SSubReg_f32_reg imm:$src2))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4982 | //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4983 | // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4984 | def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 4985 | (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 4986 | |
| 4987 | |
| 4988 | // VMOV : Vector Set Lane (move ARM core register to scalar) |
| 4989 | |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4990 | let Constraints = "$src1 = $V" in { |
| 4991 | def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V), |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 4992 | (ins DPR:$src1, GPR:$R, VectorIndex8:$lane), |
| 4993 | IIC_VMOVISL, "vmov", "8", "$V$lane, $R", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 4994 | [(set DPR:$V, (vector_insert (v8i8 DPR:$src1), |
| 4995 | GPR:$R, imm:$lane))]> { |
| 4996 | let Inst{21} = lane{2}; |
| 4997 | let Inst{6-5} = lane{1-0}; |
| 4998 | } |
| 4999 | def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V), |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 5000 | (ins DPR:$src1, GPR:$R, VectorIndex16:$lane), |
| 5001 | IIC_VMOVISL, "vmov", "16", "$V$lane, $R", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 5002 | [(set DPR:$V, (vector_insert (v4i16 DPR:$src1), |
| 5003 | GPR:$R, imm:$lane))]> { |
| 5004 | let Inst{21} = lane{1}; |
| 5005 | let Inst{6} = lane{0}; |
| 5006 | } |
| 5007 | def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), |
Jim Grosbach | 687656c | 2011-10-18 20:10:47 +0000 | [diff] [blame] | 5008 | (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), |
| 5009 | IIC_VMOVISL, "vmov", "32", "$V$lane, $R", |
Owen Anderson | d2fbdb7 | 2010-10-27 21:28:09 +0000 | [diff] [blame] | 5010 | [(set DPR:$V, (insertelt (v2i32 DPR:$src1), |
| 5011 | GPR:$R, imm:$lane))]> { |
| 5012 | let Inst{21} = lane{0}; |
| 5013 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5014 | } |
| 5015 | def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 5016 | (v16i8 (INSERT_SUBREG QPR:$src1, |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5017 | (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5018 | (DSubReg_i8_reg imm:$lane))), |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5019 | GPR:$src2, (SubReg_i8_lane imm:$lane))), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5020 | (DSubReg_i8_reg imm:$lane)))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5021 | def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 5022 | (v8i16 (INSERT_SUBREG QPR:$src1, |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5023 | (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5024 | (DSubReg_i16_reg imm:$lane))), |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5025 | GPR:$src2, (SubReg_i16_lane imm:$lane))), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5026 | (DSubReg_i16_reg imm:$lane)))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5027 | def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), |
Jim Grosbach | 1251e1a | 2010-11-18 01:39:50 +0000 | [diff] [blame] | 5028 | (v4i32 (INSERT_SUBREG QPR:$src1, |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5029 | (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5030 | (DSubReg_i32_reg imm:$lane))), |
Chris Lattner | d10a53d | 2010-03-08 18:51:21 +0000 | [diff] [blame] | 5031 | GPR:$src2, (SubReg_i32_lane imm:$lane))), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5032 | (DSubReg_i32_reg imm:$lane)))>; |
| 5033 | |
Anton Korobeynikov | d91aafd | 2009-08-30 19:06:39 +0000 | [diff] [blame] | 5034 | def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 5035 | (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)), |
| 5036 | SPR:$src2, (SSubReg_f32_reg imm:$src3))>; |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5037 | def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), |
Anton Korobeynikov | 3a639a0 | 2009-11-02 00:11:39 +0000 | [diff] [blame] | 5038 | (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)), |
| 5039 | SPR:$src2, (SSubReg_f32_reg imm:$src3))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5040 | |
| 5041 | //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5042 | // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5043 | def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), |
Anton Korobeynikov | 06af2ba | 2009-08-08 14:06:07 +0000 | [diff] [blame] | 5044 | (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5045 | |
Anton Korobeynikov | fdf189a | 2009-08-27 14:38:44 +0000 | [diff] [blame] | 5046 | def : Pat<(v2f32 (scalar_to_vector SPR:$src)), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5047 | (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; |
Chris Lattner | 77144e7 | 2010-03-15 00:52:43 +0000 | [diff] [blame] | 5048 | def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5049 | (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; |
Anton Korobeynikov | fdf189a | 2009-08-27 14:38:44 +0000 | [diff] [blame] | 5050 | def : Pat<(v4f32 (scalar_to_vector SPR:$src)), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5051 | (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; |
Anton Korobeynikov | fdf189a | 2009-08-27 14:38:44 +0000 | [diff] [blame] | 5052 | |
Anton Korobeynikov | b5cdf87 | 2009-08-27 16:10:17 +0000 | [diff] [blame] | 5053 | def : Pat<(v8i8 (scalar_to_vector GPR:$src)), |
| 5054 | (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; |
| 5055 | def : Pat<(v4i16 (scalar_to_vector GPR:$src)), |
| 5056 | (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; |
| 5057 | def : Pat<(v2i32 (scalar_to_vector GPR:$src)), |
| 5058 | (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; |
| 5059 | |
| 5060 | def : Pat<(v16i8 (scalar_to_vector GPR:$src)), |
| 5061 | (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), |
| 5062 | (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5063 | dsub_0)>; |
Anton Korobeynikov | b5cdf87 | 2009-08-27 16:10:17 +0000 | [diff] [blame] | 5064 | def : Pat<(v8i16 (scalar_to_vector GPR:$src)), |
| 5065 | (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), |
| 5066 | (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5067 | dsub_0)>; |
Anton Korobeynikov | b5cdf87 | 2009-08-27 16:10:17 +0000 | [diff] [blame] | 5068 | def : Pat<(v4i32 (scalar_to_vector GPR:$src)), |
| 5069 | (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), |
| 5070 | (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)), |
Jakob Stoklund Olesen | 558661d | 2010-05-24 16:54:32 +0000 | [diff] [blame] | 5071 | dsub_0)>; |
Anton Korobeynikov | b5cdf87 | 2009-08-27 16:10:17 +0000 | [diff] [blame] | 5072 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5073 | // VDUP : Vector Duplicate (from ARM core register to all elements) |
| 5074 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5075 | class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 5076 | : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R), |
| 5077 | IIC_VMOVIS, "vdup", Dt, "$V, $R", |
| 5078 | [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5079 | class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty> |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 5080 | : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R), |
| 5081 | IIC_VMOVIS, "vdup", Dt, "$V, $R", |
| 5082 | [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5083 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5084 | def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>; |
| 5085 | def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>; |
| 5086 | def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>; |
| 5087 | def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>; |
| 5088 | def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>; |
| 5089 | def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5090 | |
Jim Grosbach | 958108a | 2011-03-11 20:44:08 +0000 | [diff] [blame] | 5091 | def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>; |
| 5092 | def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5093 | |
| 5094 | // VDUP : Vector Duplicate Lane (from scalar to all elements) |
| 5095 | |
Johnny Chen | e4614f7 | 2010-03-25 17:01:27 +0000 | [diff] [blame] | 5096 | class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt, |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5097 | ValueType Ty, Operand IdxTy> |
| 5098 | : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane), |
| 5099 | IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 5100 | [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5101 | |
Johnny Chen | e4614f7 | 2010-03-25 17:01:27 +0000 | [diff] [blame] | 5102 | class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt, |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5103 | ValueType ResTy, ValueType OpTy, Operand IdxTy> |
| 5104 | : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane), |
| 5105 | IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane", |
Owen Anderson | ca6945e | 2010-12-01 00:28:25 +0000 | [diff] [blame] | 5106 | [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm), |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5107 | VectorIndex32:$lane)))]>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5108 | |
Bob Wilson | 507df40 | 2009-10-21 02:15:46 +0000 | [diff] [blame] | 5109 | // Inst{19-16} is partially specified depending on the element size. |
| 5110 | |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5111 | def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> { |
| 5112 | bits<3> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5113 | let Inst{19-17} = lane{2-0}; |
| 5114 | } |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5115 | def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> { |
| 5116 | bits<2> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5117 | let Inst{19-18} = lane{1-0}; |
| 5118 | } |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5119 | def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> { |
| 5120 | bits<1> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5121 | let Inst{19} = lane{0}; |
| 5122 | } |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5123 | def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> { |
| 5124 | bits<3> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5125 | let Inst{19-17} = lane{2-0}; |
| 5126 | } |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5127 | def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> { |
| 5128 | bits<2> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5129 | let Inst{19-18} = lane{1-0}; |
| 5130 | } |
Jim Grosbach | 460a905 | 2011-10-07 23:56:00 +0000 | [diff] [blame] | 5131 | def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> { |
| 5132 | bits<1> lane; |
Owen Anderson | f587a93 | 2010-10-27 19:25:54 +0000 | [diff] [blame] | 5133 | let Inst{19} = lane{0}; |
| 5134 | } |
Jim Grosbach | 8b8515c | 2011-03-11 20:31:17 +0000 | [diff] [blame] | 5135 | |
| 5136 | def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), |
| 5137 | (VDUPLN32d DPR:$Vm, imm:$lane)>; |
| 5138 | |
| 5139 | def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), |
| 5140 | (VDUPLN32q DPR:$Vm, imm:$lane)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5141 | |
Bob Wilson | 0ce3710 | 2009-08-14 05:08:32 +0000 | [diff] [blame] | 5142 | def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)), |
| 5143 | (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, |
| 5144 | (DSubReg_i8_reg imm:$lane))), |
| 5145 | (SubReg_i8_lane imm:$lane)))>; |
| 5146 | def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)), |
| 5147 | (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src, |
| 5148 | (DSubReg_i16_reg imm:$lane))), |
| 5149 | (SubReg_i16_lane imm:$lane)))>; |
| 5150 | def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)), |
| 5151 | (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src, |
| 5152 | (DSubReg_i32_reg imm:$lane))), |
| 5153 | (SubReg_i32_lane imm:$lane)))>; |
| 5154 | def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), |
Jim Grosbach | 8b8515c | 2011-03-11 20:31:17 +0000 | [diff] [blame] | 5155 | (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src, |
Bob Wilson | 0ce3710 | 2009-08-14 05:08:32 +0000 | [diff] [blame] | 5156 | (DSubReg_i32_reg imm:$lane))), |
| 5157 | (SubReg_i32_lane imm:$lane)))>; |
| 5158 | |
Jim Grosbach | 65dc303 | 2010-10-06 21:16:16 +0000 | [diff] [blame] | 5159 | def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "", |
Johnny Chen | da1aea4 | 2009-11-23 21:00:43 +0000 | [diff] [blame] | 5160 | [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>; |
Jim Grosbach | 65dc303 | 2010-10-06 21:16:16 +0000 | [diff] [blame] | 5161 | def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "", |
Johnny Chen | da1aea4 | 2009-11-23 21:00:43 +0000 | [diff] [blame] | 5162 | [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>; |
Anton Korobeynikov | 32a1b25 | 2009-08-07 22:36:50 +0000 | [diff] [blame] | 5163 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5164 | // VMOVN : Vector Narrowing Move |
Evan Cheng | cae6a12 | 2010-10-01 20:50:58 +0000 | [diff] [blame] | 5165 | defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN, |
Bob Wilson | 973a074 | 2010-08-30 20:02:30 +0000 | [diff] [blame] | 5166 | "vmovn", "i", trunc>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5167 | // VQMOVN : Vector Saturating Narrowing Move |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5168 | defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, |
| 5169 | "vqmovn", "s", int_arm_neon_vqmovns>; |
| 5170 | defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, |
| 5171 | "vqmovn", "u", int_arm_neon_vqmovnu>; |
| 5172 | defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, |
| 5173 | "vqmovun", "s", int_arm_neon_vqmovnsu>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5174 | // VMOVL : Vector Lengthening Move |
Bob Wilson | b31a11b | 2010-08-20 04:54:02 +0000 | [diff] [blame] | 5175 | defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>; |
| 5176 | defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>; |
Bob Wilson | 1e9ccd6 | 2012-01-20 20:59:56 +0000 | [diff] [blame] | 5177 | def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>; |
| 5178 | def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>; |
| 5179 | def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5180 | |
| 5181 | // Vector Conversions. |
| 5182 | |
Johnny Chen | 9e08876 | 2010-03-17 17:52:21 +0000 | [diff] [blame] | 5183 | // VCVT : Vector Convert Between Floating-Point and Integers |
Johnny Chen | 6c8648b | 2010-03-17 23:26:50 +0000 | [diff] [blame] | 5184 | def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", |
| 5185 | v2i32, v2f32, fp_to_sint>; |
| 5186 | def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", |
| 5187 | v2i32, v2f32, fp_to_uint>; |
| 5188 | def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", |
| 5189 | v2f32, v2i32, sint_to_fp>; |
| 5190 | def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", |
| 5191 | v2f32, v2i32, uint_to_fp>; |
Johnny Chen | 9e08876 | 2010-03-17 17:52:21 +0000 | [diff] [blame] | 5192 | |
Johnny Chen | 6c8648b | 2010-03-17 23:26:50 +0000 | [diff] [blame] | 5193 | def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", |
| 5194 | v4i32, v4f32, fp_to_sint>; |
| 5195 | def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", |
| 5196 | v4i32, v4f32, fp_to_uint>; |
| 5197 | def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", |
| 5198 | v4f32, v4i32, sint_to_fp>; |
| 5199 | def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", |
| 5200 | v4f32, v4i32, uint_to_fp>; |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5201 | |
| 5202 | // VCVT : Vector Convert Between Floating-Point and Fixed-Point. |
Owen Anderson | b589be9 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5203 | let DecoderMethod = "DecodeVCVTD" in { |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5204 | def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5205 | v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5206 | def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5207 | v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5208 | def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5209 | v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5210 | def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5211 | v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; |
Owen Anderson | b589be9 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5212 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5213 | |
Owen Anderson | b589be9 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5214 | let DecoderMethod = "DecodeVCVTQ" in { |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5215 | def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5216 | v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5217 | def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5218 | v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5219 | def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5220 | v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5221 | def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5222 | v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; |
Owen Anderson | b589be9 | 2011-11-15 19:55:00 +0000 | [diff] [blame] | 5223 | } |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5224 | |
Bob Wilson | 0406356 | 2010-12-15 22:14:12 +0000 | [diff] [blame] | 5225 | // VCVT : Vector Convert Between Half-Precision and Single-Precision. |
| 5226 | def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0, |
| 5227 | IIC_VUNAQ, "vcvt", "f16.f32", |
| 5228 | v4i16, v4f32, int_arm_neon_vcvtfp2hf>, |
| 5229 | Requires<[HasNEON, HasFP16]>; |
| 5230 | def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0, |
| 5231 | IIC_VUNAQ, "vcvt", "f32.f16", |
| 5232 | v4f32, v4i16, int_arm_neon_vcvthf2fp>, |
| 5233 | Requires<[HasNEON, HasFP16]>; |
| 5234 | |
Bob Wilson | d8e1757 | 2009-08-12 22:31:50 +0000 | [diff] [blame] | 5235 | // Vector Reverse. |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5236 | |
| 5237 | // VREV64 : Vector Reverse elements within 64-bit doublewords |
| 5238 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5239 | class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5240 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd), |
| 5241 | (ins DPR:$Vm), IIC_VMOVD, |
| 5242 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5243 | [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5244 | class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5245 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd), |
| 5246 | (ins QPR:$Vm), IIC_VMOVQ, |
| 5247 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5248 | [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5249 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5250 | def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>; |
| 5251 | def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>; |
| 5252 | def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>; |
Jim Grosbach | 1558df7 | 2011-03-11 20:18:05 +0000 | [diff] [blame] | 5253 | def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5254 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5255 | def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>; |
| 5256 | def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; |
| 5257 | def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; |
Jim Grosbach | 1558df7 | 2011-03-11 20:18:05 +0000 | [diff] [blame] | 5258 | def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5259 | |
| 5260 | // VREV32 : Vector Reverse elements within 32-bit words |
| 5261 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5262 | class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5263 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd), |
| 5264 | (ins DPR:$Vm), IIC_VMOVD, |
| 5265 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5266 | [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5267 | class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5268 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd), |
| 5269 | (ins QPR:$Vm), IIC_VMOVQ, |
| 5270 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5271 | [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5272 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5273 | def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>; |
| 5274 | def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5275 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5276 | def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>; |
| 5277 | def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5278 | |
| 5279 | // VREV16 : Vector Reverse elements within 16-bit halfwords |
| 5280 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5281 | class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5282 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd), |
| 5283 | (ins DPR:$Vm), IIC_VMOVD, |
| 5284 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5285 | [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>; |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5286 | class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5287 | : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd), |
| 5288 | (ins QPR:$Vm), IIC_VMOVQ, |
| 5289 | OpcodeStr, Dt, "$Vd, $Vm", "", |
| 5290 | [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5291 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5292 | def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>; |
| 5293 | def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>; |
Bob Wilson | 8bb9e48 | 2009-07-26 00:39:34 +0000 | [diff] [blame] | 5294 | |
Bob Wilson | de95c1b8 | 2009-08-19 17:03:43 +0000 | [diff] [blame] | 5295 | // Other Vector Shuffles. |
| 5296 | |
Bob Wilson | 5e8b833 | 2011-01-07 04:59:04 +0000 | [diff] [blame] | 5297 | // Aligned extractions: really just dropping registers |
| 5298 | |
| 5299 | class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT> |
| 5300 | : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))), |
| 5301 | (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>; |
| 5302 | |
| 5303 | def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>; |
| 5304 | |
| 5305 | def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>; |
| 5306 | |
| 5307 | def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>; |
| 5308 | |
| 5309 | def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>; |
| 5310 | |
| 5311 | def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>; |
| 5312 | |
| 5313 | |
Bob Wilson | de95c1b8 | 2009-08-19 17:03:43 +0000 | [diff] [blame] | 5314 | // VEXT : Vector Extract |
| 5315 | |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 5316 | |
| 5317 | // All of these have a two-operand InstAlias. |
| 5318 | let TwoOperandAliasConstraint = "$Vn = $Vd" in { |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5319 | class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5320 | : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd), |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5321 | (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm, |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5322 | IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", |
| 5323 | [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn), |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5324 | (Ty DPR:$Vm), imm:$index)))]> { |
Owen Anderson | 3eff4af | 2010-10-27 23:56:39 +0000 | [diff] [blame] | 5325 | bits<4> index; |
| 5326 | let Inst{11-8} = index{3-0}; |
| 5327 | } |
Anton Korobeynikov | 5da894f | 2009-08-21 12:40:21 +0000 | [diff] [blame] | 5328 | |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5329 | class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5330 | : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd), |
Jim Grosbach | e40ab24 | 2011-12-02 22:57:57 +0000 | [diff] [blame] | 5331 | (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm, |
Owen Anderson | aa54524 | 2010-11-21 06:47:06 +0000 | [diff] [blame] | 5332 | IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", |
| 5333 | [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn), |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5334 | (Ty QPR:$Vm), imm:$index)))]> { |
Owen Anderson | 3eff4af | 2010-10-27 23:56:39 +0000 | [diff] [blame] | 5335 | bits<4> index; |
| 5336 | let Inst{11-8} = index{3-0}; |
| 5337 | } |
Jim Grosbach | 8e3c17a | 2012-04-20 23:46:33 +0000 | [diff] [blame] | 5338 | } |
Anton Korobeynikov | 5da894f | 2009-08-21 12:40:21 +0000 | [diff] [blame] | 5339 | |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5340 | def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5341 | let Inst{11-8} = index{3-0}; |
| 5342 | } |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5343 | def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5344 | let Inst{11-9} = index{2-0}; |
| 5345 | let Inst{8} = 0b0; |
| 5346 | } |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5347 | def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5348 | let Inst{11-10} = index{1-0}; |
| 5349 | let Inst{9-8} = 0b00; |
| 5350 | } |
Owen Anderson | 167eb1f | 2011-07-15 17:48:05 +0000 | [diff] [blame] | 5351 | def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn), |
| 5352 | (v2f32 DPR:$Vm), |
| 5353 | (i32 imm:$index))), |
| 5354 | (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>; |
Anton Korobeynikov | 5da894f | 2009-08-21 12:40:21 +0000 | [diff] [blame] | 5355 | |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5356 | def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5357 | let Inst{11-8} = index{3-0}; |
| 5358 | } |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5359 | def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5360 | let Inst{11-9} = index{2-0}; |
| 5361 | let Inst{8} = 0b0; |
| 5362 | } |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5363 | def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> { |
Owen Anderson | 7a25825 | 2010-11-03 18:16:27 +0000 | [diff] [blame] | 5364 | let Inst{11-10} = index{1-0}; |
| 5365 | let Inst{9-8} = 0b00; |
| 5366 | } |
Jim Grosbach | 8759c3f | 2011-12-08 22:19:04 +0000 | [diff] [blame] | 5367 | def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> { |
Jim Grosbach | 587f506 | 2011-12-02 23:34:39 +0000 | [diff] [blame] | 5368 | let Inst{11} = index{0}; |
| 5369 | let Inst{10-8} = 0b000; |
| 5370 | } |
Owen Anderson | 167eb1f | 2011-07-15 17:48:05 +0000 | [diff] [blame] | 5371 | def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn), |
| 5372 | (v4f32 QPR:$Vm), |
| 5373 | (i32 imm:$index))), |
| 5374 | (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>; |
Bob Wilson | de95c1b8 | 2009-08-19 17:03:43 +0000 | [diff] [blame] | 5375 | |
Bob Wilson | 64efd90 | 2009-08-08 05:53:00 +0000 | [diff] [blame] | 5376 | // VTRN : Vector Transpose |
| 5377 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5378 | def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">; |
| 5379 | def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">; |
| 5380 | def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">; |
Bob Wilson | 64efd90 | 2009-08-08 05:53:00 +0000 | [diff] [blame] | 5381 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5382 | def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">; |
| 5383 | def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">; |
| 5384 | def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">; |
Bob Wilson | 64efd90 | 2009-08-08 05:53:00 +0000 | [diff] [blame] | 5385 | |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 5386 | // VUZP : Vector Unzip (Deinterleave) |
| 5387 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5388 | def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">; |
| 5389 | def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">; |
Jim Grosbach | 1835547 | 2012-04-11 17:40:18 +0000 | [diff] [blame] | 5390 | // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. |
| 5391 | def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm", |
| 5392 | (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>; |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 5393 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5394 | def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">; |
| 5395 | def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">; |
| 5396 | def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">; |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 5397 | |
| 5398 | // VZIP : Vector Zip (Interleave) |
| 5399 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5400 | def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">; |
| 5401 | def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">; |
Jim Grosbach | 6073b30 | 2012-04-11 16:53:25 +0000 | [diff] [blame] | 5402 | // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm. |
| 5403 | def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm", |
| 5404 | (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>; |
Bob Wilson | b6ab51e | 2009-08-08 06:13:25 +0000 | [diff] [blame] | 5405 | |
Evan Cheng | f81bf15 | 2009-11-23 21:57:23 +0000 | [diff] [blame] | 5406 | def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">; |
| 5407 | def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">; |
| 5408 | def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">; |
Bob Wilson | 64efd90 | 2009-08-08 05:53:00 +0000 | [diff] [blame] | 5409 | |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5410 | // Vector Table Lookup and Table Extension. |
| 5411 | |
| 5412 | // VTBL : Vector Table Lookup |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 5413 | let DecoderMethod = "DecodeTBLInstruction" in { |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5414 | def VTBL1 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5415 | : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd), |
Jim Grosbach | 862019c | 2011-10-18 23:02:30 +0000 | [diff] [blame] | 5416 | (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1, |
| 5417 | "vtbl", "8", "$Vd, $Vn, $Vm", "", |
| 5418 | [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>; |
Evan Cheng | 0d92f5f | 2009-10-01 08:22:27 +0000 | [diff] [blame] | 5419 | let hasExtraSrcRegAllocReq = 1 in { |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5420 | def VTBL2 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5421 | : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd), |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 5422 | (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2, |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5423 | "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5424 | def VTBL3 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5425 | : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd), |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5426 | (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3, |
| 5427 | "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5428 | def VTBL4 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5429 | : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd), |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5430 | (ins VecListFourD:$Vn, DPR:$Vm), |
Johnny Chen | 79c4d82 | 2010-03-29 01:14:22 +0000 | [diff] [blame] | 5431 | NVTBLFrm, IIC_VTB4, |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5432 | "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; |
Evan Cheng | 0d92f5f | 2009-10-01 08:22:27 +0000 | [diff] [blame] | 5433 | } // hasExtraSrcRegAllocReq = 1 |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5434 | |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5435 | def VTBL3Pseudo |
Jim Grosbach | 7cd2729 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 5436 | : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>; |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5437 | def VTBL4Pseudo |
Jim Grosbach | 7cd2729 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 5438 | : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>; |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5439 | |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5440 | // VTBX : Vector Table Extension |
| 5441 | def VTBX1 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5442 | : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd), |
Jim Grosbach | d0b6147 | 2011-10-20 14:48:50 +0000 | [diff] [blame] | 5443 | (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1, |
| 5444 | "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5445 | [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1 |
Jim Grosbach | d0b6147 | 2011-10-20 14:48:50 +0000 | [diff] [blame] | 5446 | DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>; |
Evan Cheng | 0d92f5f | 2009-10-01 08:22:27 +0000 | [diff] [blame] | 5447 | let hasExtraSrcRegAllocReq = 1 in { |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5448 | def VTBX2 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5449 | : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd), |
Jim Grosbach | 28f08c9 | 2012-03-05 19:33:30 +0000 | [diff] [blame] | 5450 | (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2, |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5451 | "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>; |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5452 | def VTBX3 |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5453 | : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd), |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5454 | (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm), |
Johnny Chen | 79c4d82 | 2010-03-29 01:14:22 +0000 | [diff] [blame] | 5455 | NVTBLFrm, IIC_VTBX3, |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5456 | "vtbx", "8", "$Vd, $Vn, $Vm", |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5457 | "$orig = $Vd", []>; |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5458 | def VTBX4 |
Jim Grosbach | 60d99a5 | 2011-12-15 22:27:11 +0000 | [diff] [blame] | 5459 | : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), |
| 5460 | (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4, |
| 5461 | "vtbx", "8", "$Vd, $Vn, $Vm", |
Owen Anderson | cfd0e1f | 2010-10-28 00:18:46 +0000 | [diff] [blame] | 5462 | "$orig = $Vd", []>; |
Evan Cheng | 0d92f5f | 2009-10-01 08:22:27 +0000 | [diff] [blame] | 5463 | } // hasExtraSrcRegAllocReq = 1 |
Bob Wilson | 114a266 | 2009-08-12 20:51:55 +0000 | [diff] [blame] | 5464 | |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5465 | def VTBX3Pseudo |
| 5466 | : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), |
Jim Grosbach | 7cd2729 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 5467 | IIC_VTBX3, "$orig = $dst", []>; |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5468 | def VTBX4Pseudo |
| 5469 | : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), |
Jim Grosbach | 7cd2729 | 2010-10-06 20:36:55 +0000 | [diff] [blame] | 5470 | IIC_VTBX4, "$orig = $dst", []>; |
Owen Anderson | 8d7d2e1 | 2011-08-09 20:55:18 +0000 | [diff] [blame] | 5471 | } // DecoderMethod = "DecodeTBLInstruction" |
Bob Wilson | bd916c5 | 2010-09-13 23:55:10 +0000 | [diff] [blame] | 5472 | |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5473 | //===----------------------------------------------------------------------===// |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 5474 | // NEON instructions for single-precision FP math |
| 5475 | //===----------------------------------------------------------------------===// |
| 5476 | |
Bob Wilson | 0e6d540 | 2010-12-13 23:02:31 +0000 | [diff] [blame] | 5477 | class N2VSPat<SDNode OpNode, NeonI Inst> |
| 5478 | : NEONFPPat<(f32 (OpNode SPR:$a)), |
Bob Wilson | 1e6f596 | 2010-12-13 21:58:05 +0000 | [diff] [blame] | 5479 | (EXTRACT_SUBREG |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5480 | (v2f32 (COPY_TO_REGCLASS (Inst |
| 5481 | (INSERT_SUBREG |
Bob Wilson | 0e6d540 | 2010-12-13 23:02:31 +0000 | [diff] [blame] | 5482 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5483 | SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>; |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 5484 | |
| 5485 | class N3VSPat<SDNode OpNode, NeonI Inst> |
| 5486 | : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5487 | (EXTRACT_SUBREG |
| 5488 | (v2f32 (COPY_TO_REGCLASS (Inst |
| 5489 | (INSERT_SUBREG |
| 5490 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5491 | SPR:$a, ssub_0), |
| 5492 | (INSERT_SUBREG |
| 5493 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5494 | SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 5495 | |
| 5496 | class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst> |
| 5497 | : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5498 | (EXTRACT_SUBREG |
| 5499 | (v2f32 (COPY_TO_REGCLASS (Inst |
| 5500 | (INSERT_SUBREG |
| 5501 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5502 | SPR:$acc, ssub_0), |
| 5503 | (INSERT_SUBREG |
| 5504 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5505 | SPR:$a, ssub_0), |
| 5506 | (INSERT_SUBREG |
| 5507 | (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), |
| 5508 | SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; |
Bob Wilson | 3c0f96e | 2010-02-17 22:23:11 +0000 | [diff] [blame] | 5509 | |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5510 | def : N3VSPat<fadd, VADDfd>; |
| 5511 | def : N3VSPat<fsub, VSUBfd>; |
| 5512 | def : N3VSPat<fmul, VMULfd>; |
| 5513 | def : N3VSMulOpPat<fmul, fadd, VMLAfd>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 5514 | Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>; |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5515 | def : N3VSMulOpPat<fmul, fsub, VMLSfd>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 5516 | Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 5517 | def : N3VSMulOpPat<fmul, fadd, VFMAfd>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 5518 | Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; |
Anton Korobeynikov | 4b4e622 | 2012-01-22 12:07:33 +0000 | [diff] [blame] | 5519 | def : N3VSMulOpPat<fmul, fsub, VFMSfd>, |
Evan Cheng | bee78fe | 2012-04-11 05:33:07 +0000 | [diff] [blame] | 5520 | Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>; |
Bob Wilson | 0e6d540 | 2010-12-13 23:02:31 +0000 | [diff] [blame] | 5521 | def : N2VSPat<fabs, VABSfd>; |
Bob Wilson | 0e6d540 | 2010-12-13 23:02:31 +0000 | [diff] [blame] | 5522 | def : N2VSPat<fneg, VNEGfd>; |
Bob Wilson | 4711d5c | 2010-12-13 23:02:37 +0000 | [diff] [blame] | 5523 | def : N3VSPat<NEONfmax, VMAXfd>; |
| 5524 | def : N3VSPat<NEONfmin, VMINfd>; |
Bob Wilson | 0e6d540 | 2010-12-13 23:02:31 +0000 | [diff] [blame] | 5525 | def : N2VSPat<arm_ftosi, VCVTf2sd>; |
| 5526 | def : N2VSPat<arm_ftoui, VCVTf2ud>; |
| 5527 | def : N2VSPat<arm_sitof, VCVTs2fd>; |
| 5528 | def : N2VSPat<arm_uitof, VCVTu2fd>; |
David Goodwin | 338268c | 2009-08-10 22:17:39 +0000 | [diff] [blame] | 5529 | |
Evan Cheng | 1d2426c | 2009-08-07 19:30:41 +0000 | [diff] [blame] | 5530 | //===----------------------------------------------------------------------===// |
Bob Wilson | 5bafff3 | 2009-06-22 23:27:02 +0000 | [diff] [blame] | 5531 | // Non-Instruction Patterns |
| 5532 | //===----------------------------------------------------------------------===// |
| 5533 | |
| 5534 | // bit_convert |
| 5535 | def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; |
| 5536 | def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; |
| 5537 | def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; |
| 5538 | def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; |
| 5539 | def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; |
| 5540 | def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; |
| 5541 | def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; |
| 5542 | def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; |
| 5543 | def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; |
| 5544 | def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; |
| 5545 | def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; |
| 5546 | def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; |
| 5547 | def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; |
| 5548 | def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; |
| 5549 | def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; |
| 5550 | def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; |
| 5551 | def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; |
| 5552 | def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; |
| 5553 | def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; |
| 5554 | def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; |
| 5555 | def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; |
| 5556 | def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; |
| 5557 | def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; |
| 5558 | def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; |
| 5559 | def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; |
| 5560 | def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; |
| 5561 | def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; |
| 5562 | def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; |
| 5563 | def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; |
| 5564 | def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; |
| 5565 | |
| 5566 | def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; |
| 5567 | def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; |
| 5568 | def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; |
| 5569 | def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; |
| 5570 | def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; |
| 5571 | def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; |
| 5572 | def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; |
| 5573 | def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; |
| 5574 | def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; |
| 5575 | def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; |
| 5576 | def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; |
| 5577 | def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; |
| 5578 | def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; |
| 5579 | def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; |
| 5580 | def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; |
| 5581 | def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; |
| 5582 | def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; |
| 5583 | def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; |
| 5584 | def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; |
| 5585 | def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; |
| 5586 | def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; |
| 5587 | def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; |
| 5588 | def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; |
| 5589 | def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; |
| 5590 | def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; |
| 5591 | def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; |
| 5592 | def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; |
| 5593 | def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; |
| 5594 | def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; |
| 5595 | def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5596 | |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5597 | // Vector lengthening move with load, matching extending loads. |
| 5598 | |
| 5599 | // extload, zextload and sextload for a standard lengthening load. Example: |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5600 | // Lengthen_Single<"8", "i16", "i8"> = |
| 5601 | // Pat<(v8i16 (extloadvi8 addrmode6oneL32:$addr)) |
| 5602 | // (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, |
| 5603 | // (f64 (IMPLICIT_DEF)), (i32 0)))>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5604 | multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> { |
| 5605 | def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5606 | (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5607 | (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5608 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5609 | (f64 (IMPLICIT_DEF)), (i32 0)))>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5610 | def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5611 | (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5612 | (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5613 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5614 | (f64 (IMPLICIT_DEF)), (i32 0)))>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5615 | def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5616 | (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5617 | (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5618 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5619 | (f64 (IMPLICIT_DEF)), (i32 0)))>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5620 | } |
| 5621 | |
| 5622 | // extload, zextload and sextload for a lengthening load which only uses |
| 5623 | // half the lanes available. Example: |
| 5624 | // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> = |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5625 | // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)), |
| 5626 | // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, |
| 5627 | // (f64 (IMPLICIT_DEF)), (i32 0))), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5628 | // dsub_0)>; |
| 5629 | multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy, |
| 5630 | string InsnLanes, string InsnTy> { |
| 5631 | def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5632 | (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5633 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5634 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5635 | dsub_0)>; |
| 5636 | def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5637 | (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5638 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5639 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5640 | dsub_0)>; |
| 5641 | def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5642 | (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5643 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5644 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5645 | dsub_0)>; |
| 5646 | } |
| 5647 | |
| 5648 | // extload, zextload and sextload for a lengthening load followed by another |
| 5649 | // lengthening load, to quadruple the initial length. |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5650 | // |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5651 | // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> = |
| 5652 | // Pat<(v4i32 (extloadvi8 addrmode5:$addr)) |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5653 | // (EXTRACT_SUBREG (VMOVLuv4i32 |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5654 | // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, |
| 5655 | // (f64 (IMPLICIT_DEF)), |
| 5656 | // (i32 0))), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5657 | // dsub_0)), |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5658 | // dsub_0)>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5659 | multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy, |
| 5660 | string Insn1Lanes, string Insn1Ty, string Insn2Lanes, |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5661 | string Insn2Ty> { |
| 5662 | def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5663 | (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5664 | (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) |
| 5665 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5666 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5667 | dsub_0))>; |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5668 | def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5669 | (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5670 | (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) |
| 5671 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5672 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5673 | dsub_0))>; |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5674 | def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5675 | (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5676 | (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty) |
| 5677 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5678 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5679 | dsub_0))>; |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5680 | } |
| 5681 | |
| 5682 | // extload, zextload and sextload for a lengthening load followed by another |
| 5683 | // lengthening load, to quadruple the initial length, but which ends up only |
| 5684 | // requiring half the available lanes (a 64-bit outcome instead of a 128-bit). |
| 5685 | // |
| 5686 | // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> = |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5687 | // Pat<(v4i32 (extloadvi8 addrmode5:$addr)) |
| 5688 | // (EXTRACT_SUBREG (VMOVLuv4i32 |
| 5689 | // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr, |
| 5690 | // (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5691 | // dsub_0)), |
| 5692 | // dsub_0)>; |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5693 | multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy, |
| 5694 | string Insn1Lanes, string Insn1Ty, string Insn2Lanes, |
| 5695 | string Insn2Ty> { |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5696 | def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5697 | (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5698 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) |
| 5699 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5700 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5701 | dsub_0)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5702 | dsub_0)>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5703 | def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5704 | (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5705 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) |
| 5706 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5707 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5708 | dsub_0)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5709 | dsub_0)>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5710 | def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5711 | (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5712 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty) |
| 5713 | (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty) |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5714 | (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))), |
| 5715 | dsub_0)), |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5716 | dsub_0)>; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5717 | } |
| 5718 | |
| 5719 | defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16 |
| 5720 | defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32 |
| 5721 | defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64 |
| 5722 | |
| 5723 | defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16 |
| 5724 | defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16 |
| 5725 | defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32 |
| 5726 | |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5727 | // Double lengthening - v4i8 -> v4i16 -> v4i32 |
| 5728 | defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5729 | // v2i8 -> v2i16 -> v2i32 |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5730 | defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5731 | // v2i16 -> v2i32 -> v2i64 |
James Molloy | 72aadc0 | 2012-04-17 08:18:00 +0000 | [diff] [blame] | 5732 | defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">; |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5733 | |
| 5734 | // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64 |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5735 | def : Pat<(v2i64 (extloadvi8 addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5736 | (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5737 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5738 | (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; |
| 5739 | def : Pat<(v2i64 (zextloadvi8 addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5740 | (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5741 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5742 | (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; |
| 5743 | def : Pat<(v2i64 (sextloadvi8 addrmode6oneL32:$addr)), |
James Molloy | 873fd5f | 2012-02-20 09:24:05 +0000 | [diff] [blame] | 5744 | (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 |
Tim Northover | 37abe8d | 2012-04-26 08:46:29 +0000 | [diff] [blame] | 5745 | (VLD1LNd32 addrmode6oneL32:$addr, |
| 5746 | (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>; |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5747 | |
| 5748 | //===----------------------------------------------------------------------===// |
| 5749 | // Assembler aliases |
| 5750 | // |
Jim Grosbach | 485d8bf | 2011-12-13 20:08:32 +0000 | [diff] [blame] | 5751 | |
Jim Grosbach | 21d7fb8 | 2011-12-09 23:34:09 +0000 | [diff] [blame] | 5752 | def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn", |
| 5753 | (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>; |
| 5754 | def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn", |
| 5755 | (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>; |
| 5756 | |
Jim Grosbach | 4332983 | 2011-12-09 21:46:04 +0000 | [diff] [blame] | 5757 | // VAND/VBIC/VEOR/VORR accept but do not require a type suffix. |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5758 | defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5759 | (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5760 | defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5761 | (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5762 | defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | 4332983 | 2011-12-09 21:46:04 +0000 | [diff] [blame] | 5763 | (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5764 | defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | 4332983 | 2011-12-09 21:46:04 +0000 | [diff] [blame] | 5765 | (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5766 | defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5767 | (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5768 | defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5769 | (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5770 | defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5771 | (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5772 | defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", |
Jim Grosbach | ef44876 | 2011-11-14 23:11:19 +0000 | [diff] [blame] | 5773 | (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5774 | // ... two-operand aliases |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5775 | defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5776 | (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5777 | defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5778 | (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5779 | defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5780 | (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5781 | defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5782 | (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5783 | defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5784 | (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 5785 | defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", |
Jim Grosbach | 9fa0a74 | 2011-12-07 23:08:12 +0000 | [diff] [blame] | 5786 | (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; |
Jim Grosbach | e052b9a | 2011-11-14 23:32:59 +0000 | [diff] [blame] | 5787 | |
Jim Grosbach | 872eedb | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 5788 | // VLD1 single-lane pseudo-instructions. These need special handling for |
| 5789 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5790 | def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5791 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5792 | def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5793 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5794 | def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5795 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 872eedb | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 5796 | |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5797 | def VLD1LNdWB_fixed_Asm_8 : |
| 5798 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5799 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5800 | def VLD1LNdWB_fixed_Asm_16 : |
| 5801 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5802 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5803 | def VLD1LNdWB_fixed_Asm_32 : |
| 5804 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5805 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5806 | def VLD1LNdWB_register_Asm_8 : |
| 5807 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm", |
Jim Grosbach | 872eedb | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 5808 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, |
| 5809 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5810 | def VLD1LNdWB_register_Asm_16 : |
| 5811 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5812 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 872eedb | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 5813 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5814 | def VLD1LNdWB_register_Asm_32 : |
| 5815 | NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5816 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 872eedb | 2011-12-02 22:01:52 +0000 | [diff] [blame] | 5817 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 84defb5 | 2011-12-02 22:34:51 +0000 | [diff] [blame] | 5818 | |
| 5819 | |
| 5820 | // VST1 single-lane pseudo-instructions. These need special handling for |
| 5821 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5822 | def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5823 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5824 | def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5825 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5826 | def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5827 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 84defb5 | 2011-12-02 22:34:51 +0000 | [diff] [blame] | 5828 | |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5829 | def VST1LNdWB_fixed_Asm_8 : |
| 5830 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5831 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5832 | def VST1LNdWB_fixed_Asm_16 : |
| 5833 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5834 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5835 | def VST1LNdWB_fixed_Asm_32 : |
| 5836 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5837 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5838 | def VST1LNdWB_register_Asm_8 : |
| 5839 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm", |
Jim Grosbach | 84defb5 | 2011-12-02 22:34:51 +0000 | [diff] [blame] | 5840 | (ins VecListOneDByteIndexed:$list, addrmode6:$addr, |
| 5841 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5842 | def VST1LNdWB_register_Asm_16 : |
| 5843 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5844 | (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 84defb5 | 2011-12-02 22:34:51 +0000 | [diff] [blame] | 5845 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5846 | def VST1LNdWB_register_Asm_32 : |
| 5847 | NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5848 | (ins VecListOneDWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 84defb5 | 2011-12-02 22:34:51 +0000 | [diff] [blame] | 5849 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 1ceef1a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 5850 | |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5851 | // VLD2 single-lane pseudo-instructions. These need special handling for |
| 5852 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5853 | def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5854 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5855 | def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5856 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5857 | def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5858 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5859 | def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5860 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5861 | def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5862 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5863 | |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5864 | def VLD2LNdWB_fixed_Asm_8 : |
| 5865 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5866 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5867 | def VLD2LNdWB_fixed_Asm_16 : |
| 5868 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5869 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5870 | def VLD2LNdWB_fixed_Asm_32 : |
| 5871 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5872 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5873 | def VLD2LNqWB_fixed_Asm_16 : |
| 5874 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5875 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5876 | def VLD2LNqWB_fixed_Asm_32 : |
| 5877 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5878 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5879 | def VLD2LNdWB_register_Asm_8 : |
| 5880 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm", |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5881 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, |
| 5882 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5883 | def VLD2LNdWB_register_Asm_16 : |
| 5884 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5885 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5886 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5887 | def VLD2LNdWB_register_Asm_32 : |
| 5888 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5889 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5890 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5891 | def VLD2LNqWB_register_Asm_16 : |
| 5892 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5893 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, |
| 5894 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5895 | def VLD2LNqWB_register_Asm_32 : |
| 5896 | NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 95fad1c | 2011-12-20 19:21:26 +0000 | [diff] [blame] | 5897 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, |
| 5898 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5899 | |
| 5900 | |
| 5901 | // VST2 single-lane pseudo-instructions. These need special handling for |
| 5902 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5903 | def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5904 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5905 | def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5906 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5907 | def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5908 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5909 | def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5910 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5911 | def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5912 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5913 | |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5914 | def VST2LNdWB_fixed_Asm_8 : |
| 5915 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5916 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5917 | def VST2LNdWB_fixed_Asm_16 : |
| 5918 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5919 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5920 | def VST2LNdWB_fixed_Asm_32 : |
| 5921 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5922 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5923 | def VST2LNqWB_fixed_Asm_16 : |
| 5924 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5925 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5926 | def VST2LNqWB_fixed_Asm_32 : |
| 5927 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5928 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5929 | def VST2LNdWB_register_Asm_8 : |
| 5930 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm", |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5931 | (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, |
| 5932 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5933 | def VST2LNdWB_register_Asm_16 : |
| 5934 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5935 | (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5936 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5937 | def VST2LNdWB_register_Asm_32 : |
| 5938 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 799ca9d | 2011-12-14 23:35:06 +0000 | [diff] [blame] | 5939 | (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5940 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5941 | def VST2LNqWB_register_Asm_16 : |
| 5942 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5943 | (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, |
| 5944 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 5945 | def VST2LNqWB_register_Asm_32 : |
| 5946 | NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", |
Jim Grosbach | 5b48431 | 2011-12-20 20:46:29 +0000 | [diff] [blame] | 5947 | (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, |
| 5948 | rGPR:$Rm, pred:$p)>; |
Jim Grosbach | 9b1b390 | 2011-12-14 23:25:46 +0000 | [diff] [blame] | 5949 | |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5950 | // VLD3 all-lanes pseudo-instructions. These need special handling for |
| 5951 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5952 | def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5953 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5954 | def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5955 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5956 | def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5957 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5958 | def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5959 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5960 | def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5961 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 5962 | def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
Jim Grosbach | 5e59f7e | 2012-01-24 23:47:04 +0000 | [diff] [blame] | 5963 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5964 | |
| 5965 | def VLD3DUPdWB_fixed_Asm_8 : |
| 5966 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", |
| 5967 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5968 | def VLD3DUPdWB_fixed_Asm_16 : |
| 5969 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 5970 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5971 | def VLD3DUPdWB_fixed_Asm_32 : |
| 5972 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 5973 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5974 | def VLD3DUPqWB_fixed_Asm_8 : |
| 5975 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", |
| 5976 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5977 | def VLD3DUPqWB_fixed_Asm_16 : |
| 5978 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 5979 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5980 | def VLD3DUPqWB_fixed_Asm_32 : |
| 5981 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 5982 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 5983 | def VLD3DUPdWB_register_Asm_8 : |
| 5984 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", |
| 5985 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, |
| 5986 | rGPR:$Rm, pred:$p)>; |
| 5987 | def VLD3DUPdWB_register_Asm_16 : |
| 5988 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 5989 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, |
| 5990 | rGPR:$Rm, pred:$p)>; |
| 5991 | def VLD3DUPdWB_register_Asm_32 : |
| 5992 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 5993 | (ins VecListThreeDAllLanes:$list, addrmode6:$addr, |
| 5994 | rGPR:$Rm, pred:$p)>; |
| 5995 | def VLD3DUPqWB_register_Asm_8 : |
| 5996 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", |
| 5997 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, |
| 5998 | rGPR:$Rm, pred:$p)>; |
| 5999 | def VLD3DUPqWB_register_Asm_16 : |
| 6000 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 6001 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, |
| 6002 | rGPR:$Rm, pred:$p)>; |
| 6003 | def VLD3DUPqWB_register_Asm_32 : |
| 6004 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 6005 | (ins VecListThreeQAllLanes:$list, addrmode6:$addr, |
| 6006 | rGPR:$Rm, pred:$p)>; |
| 6007 | |
Jim Grosbach | 8b31f95 | 2012-01-23 19:39:08 +0000 | [diff] [blame] | 6008 | |
Jim Grosbach | 3a678af | 2012-01-23 21:53:26 +0000 | [diff] [blame] | 6009 | // VLD3 single-lane pseudo-instructions. These need special handling for |
| 6010 | // the lane index that an InstAlias can't handle, so we use these instead. |
| 6011 | def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", |
| 6012 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6013 | def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
| 6014 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6015 | def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
| 6016 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6017 | def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
| 6018 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6019 | def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
| 6020 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6021 | |
| 6022 | def VLD3LNdWB_fixed_Asm_8 : |
| 6023 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", |
| 6024 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6025 | def VLD3LNdWB_fixed_Asm_16 : |
| 6026 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 6027 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6028 | def VLD3LNdWB_fixed_Asm_32 : |
| 6029 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 6030 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6031 | def VLD3LNqWB_fixed_Asm_16 : |
| 6032 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 6033 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6034 | def VLD3LNqWB_fixed_Asm_32 : |
| 6035 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 6036 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6037 | def VLD3LNdWB_register_Asm_8 : |
| 6038 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", |
| 6039 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, |
| 6040 | rGPR:$Rm, pred:$p)>; |
| 6041 | def VLD3LNdWB_register_Asm_16 : |
| 6042 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 6043 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, |
| 6044 | rGPR:$Rm, pred:$p)>; |
| 6045 | def VLD3LNdWB_register_Asm_32 : |
| 6046 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 6047 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, |
| 6048 | rGPR:$Rm, pred:$p)>; |
| 6049 | def VLD3LNqWB_register_Asm_16 : |
| 6050 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 6051 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, |
| 6052 | rGPR:$Rm, pred:$p)>; |
| 6053 | def VLD3LNqWB_register_Asm_32 : |
| 6054 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 6055 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, |
| 6056 | rGPR:$Rm, pred:$p)>; |
| 6057 | |
Jim Grosbach | 7b426ce | 2012-01-24 00:12:39 +0000 | [diff] [blame] | 6058 | // VLD3 multiple structure pseudo-instructions. These need special handling for |
Jim Grosbach | c387fc6 | 2012-01-23 23:20:46 +0000 | [diff] [blame] | 6059 | // the vector operands that the normal instructions don't yet model. |
| 6060 | // FIXME: Remove these when the register classes and instructions are updated. |
| 6061 | def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", |
| 6062 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6063 | def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
| 6064 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6065 | def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
| 6066 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6067 | def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", |
| 6068 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6069 | def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", |
| 6070 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6071 | def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", |
| 6072 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6073 | |
| 6074 | def VLD3dWB_fixed_Asm_8 : |
| 6075 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", |
| 6076 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6077 | def VLD3dWB_fixed_Asm_16 : |
| 6078 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 6079 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6080 | def VLD3dWB_fixed_Asm_32 : |
| 6081 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 6082 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6083 | def VLD3qWB_fixed_Asm_8 : |
| 6084 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", |
| 6085 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6086 | def VLD3qWB_fixed_Asm_16 : |
| 6087 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", |
| 6088 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6089 | def VLD3qWB_fixed_Asm_32 : |
| 6090 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", |
| 6091 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6092 | def VLD3dWB_register_Asm_8 : |
| 6093 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", |
| 6094 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6095 | rGPR:$Rm, pred:$p)>; |
| 6096 | def VLD3dWB_register_Asm_16 : |
| 6097 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 6098 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6099 | rGPR:$Rm, pred:$p)>; |
| 6100 | def VLD3dWB_register_Asm_32 : |
| 6101 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 6102 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6103 | rGPR:$Rm, pred:$p)>; |
| 6104 | def VLD3qWB_register_Asm_8 : |
| 6105 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", |
| 6106 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6107 | rGPR:$Rm, pred:$p)>; |
| 6108 | def VLD3qWB_register_Asm_16 : |
| 6109 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", |
| 6110 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6111 | rGPR:$Rm, pred:$p)>; |
| 6112 | def VLD3qWB_register_Asm_32 : |
| 6113 | NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", |
| 6114 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6115 | rGPR:$Rm, pred:$p)>; |
| 6116 | |
Jim Grosbach | 4adb182 | 2012-01-24 00:07:41 +0000 | [diff] [blame] | 6117 | // VST3 single-lane pseudo-instructions. These need special handling for |
| 6118 | // the lane index that an InstAlias can't handle, so we use these instead. |
| 6119 | def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", |
| 6120 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6121 | def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", |
| 6122 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6123 | def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", |
| 6124 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6125 | def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", |
| 6126 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6127 | def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", |
| 6128 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6129 | |
| 6130 | def VST3LNdWB_fixed_Asm_8 : |
| 6131 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", |
| 6132 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6133 | def VST3LNdWB_fixed_Asm_16 : |
| 6134 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", |
| 6135 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6136 | def VST3LNdWB_fixed_Asm_32 : |
| 6137 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", |
| 6138 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6139 | def VST3LNqWB_fixed_Asm_16 : |
| 6140 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", |
| 6141 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6142 | def VST3LNqWB_fixed_Asm_32 : |
| 6143 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", |
| 6144 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6145 | def VST3LNdWB_register_Asm_8 : |
| 6146 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", |
| 6147 | (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, |
| 6148 | rGPR:$Rm, pred:$p)>; |
| 6149 | def VST3LNdWB_register_Asm_16 : |
| 6150 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", |
| 6151 | (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, |
| 6152 | rGPR:$Rm, pred:$p)>; |
| 6153 | def VST3LNdWB_register_Asm_32 : |
| 6154 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", |
| 6155 | (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, |
| 6156 | rGPR:$Rm, pred:$p)>; |
| 6157 | def VST3LNqWB_register_Asm_16 : |
| 6158 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", |
| 6159 | (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, |
| 6160 | rGPR:$Rm, pred:$p)>; |
| 6161 | def VST3LNqWB_register_Asm_32 : |
| 6162 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", |
| 6163 | (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, |
| 6164 | rGPR:$Rm, pred:$p)>; |
| 6165 | |
| 6166 | |
Jim Grosbach | 7b426ce | 2012-01-24 00:12:39 +0000 | [diff] [blame] | 6167 | // VST3 multiple structure pseudo-instructions. These need special handling for |
Jim Grosbach | d7433e2 | 2012-01-23 23:45:44 +0000 | [diff] [blame] | 6168 | // the vector operands that the normal instructions don't yet model. |
| 6169 | // FIXME: Remove these when the register classes and instructions are updated. |
| 6170 | def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", |
| 6171 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6172 | def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", |
| 6173 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6174 | def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", |
| 6175 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6176 | def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", |
| 6177 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6178 | def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", |
| 6179 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6180 | def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", |
| 6181 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6182 | |
| 6183 | def VST3dWB_fixed_Asm_8 : |
| 6184 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", |
| 6185 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6186 | def VST3dWB_fixed_Asm_16 : |
| 6187 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", |
| 6188 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6189 | def VST3dWB_fixed_Asm_32 : |
| 6190 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", |
| 6191 | (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; |
| 6192 | def VST3qWB_fixed_Asm_8 : |
| 6193 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", |
| 6194 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6195 | def VST3qWB_fixed_Asm_16 : |
| 6196 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", |
| 6197 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6198 | def VST3qWB_fixed_Asm_32 : |
| 6199 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", |
| 6200 | (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; |
| 6201 | def VST3dWB_register_Asm_8 : |
| 6202 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", |
| 6203 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6204 | rGPR:$Rm, pred:$p)>; |
| 6205 | def VST3dWB_register_Asm_16 : |
| 6206 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", |
| 6207 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6208 | rGPR:$Rm, pred:$p)>; |
| 6209 | def VST3dWB_register_Asm_32 : |
| 6210 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", |
| 6211 | (ins VecListThreeD:$list, addrmode6:$addr, |
| 6212 | rGPR:$Rm, pred:$p)>; |
| 6213 | def VST3qWB_register_Asm_8 : |
| 6214 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", |
| 6215 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6216 | rGPR:$Rm, pred:$p)>; |
| 6217 | def VST3qWB_register_Asm_16 : |
| 6218 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", |
| 6219 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6220 | rGPR:$Rm, pred:$p)>; |
| 6221 | def VST3qWB_register_Asm_32 : |
| 6222 | NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", |
| 6223 | (ins VecListThreeQ:$list, addrmode6:$addr, |
| 6224 | rGPR:$Rm, pred:$p)>; |
| 6225 | |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6226 | // VLD4 all-lanes pseudo-instructions. These need special handling for |
| 6227 | // the lane index that an InstAlias can't handle, so we use these instead. |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6228 | def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6229 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6230 | def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6231 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6232 | def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6233 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6234 | def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6235 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6236 | def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6237 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
Jim Grosbach | c92ba4e | 2012-04-23 22:04:10 +0000 | [diff] [blame] | 6238 | def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
Jim Grosbach | a57a36a | 2012-01-25 00:01:08 +0000 | [diff] [blame] | 6239 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6240 | |
| 6241 | def VLD4DUPdWB_fixed_Asm_8 : |
| 6242 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", |
| 6243 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6244 | def VLD4DUPdWB_fixed_Asm_16 : |
| 6245 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6246 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6247 | def VLD4DUPdWB_fixed_Asm_32 : |
| 6248 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6249 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6250 | def VLD4DUPqWB_fixed_Asm_8 : |
| 6251 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", |
| 6252 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6253 | def VLD4DUPqWB_fixed_Asm_16 : |
| 6254 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6255 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6256 | def VLD4DUPqWB_fixed_Asm_32 : |
| 6257 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6258 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; |
| 6259 | def VLD4DUPdWB_register_Asm_8 : |
| 6260 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", |
| 6261 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, |
| 6262 | rGPR:$Rm, pred:$p)>; |
| 6263 | def VLD4DUPdWB_register_Asm_16 : |
| 6264 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6265 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, |
| 6266 | rGPR:$Rm, pred:$p)>; |
| 6267 | def VLD4DUPdWB_register_Asm_32 : |
| 6268 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6269 | (ins VecListFourDAllLanes:$list, addrmode6:$addr, |
| 6270 | rGPR:$Rm, pred:$p)>; |
| 6271 | def VLD4DUPqWB_register_Asm_8 : |
| 6272 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", |
| 6273 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, |
| 6274 | rGPR:$Rm, pred:$p)>; |
| 6275 | def VLD4DUPqWB_register_Asm_16 : |
| 6276 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6277 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, |
| 6278 | rGPR:$Rm, pred:$p)>; |
| 6279 | def VLD4DUPqWB_register_Asm_32 : |
| 6280 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6281 | (ins VecListFourQAllLanes:$list, addrmode6:$addr, |
| 6282 | rGPR:$Rm, pred:$p)>; |
| 6283 | |
| 6284 | |
Jim Grosbach | e983a13 | 2012-01-24 18:37:25 +0000 | [diff] [blame] | 6285 | // VLD4 single-lane pseudo-instructions. These need special handling for |
| 6286 | // the lane index that an InstAlias can't handle, so we use these instead. |
| 6287 | def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", |
| 6288 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6289 | def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
| 6290 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6291 | def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
| 6292 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6293 | def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
| 6294 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6295 | def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
| 6296 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6297 | |
| 6298 | def VLD4LNdWB_fixed_Asm_8 : |
| 6299 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", |
| 6300 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6301 | def VLD4LNdWB_fixed_Asm_16 : |
| 6302 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6303 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6304 | def VLD4LNdWB_fixed_Asm_32 : |
| 6305 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6306 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6307 | def VLD4LNqWB_fixed_Asm_16 : |
| 6308 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6309 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6310 | def VLD4LNqWB_fixed_Asm_32 : |
| 6311 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6312 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6313 | def VLD4LNdWB_register_Asm_8 : |
| 6314 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", |
| 6315 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, |
| 6316 | rGPR:$Rm, pred:$p)>; |
| 6317 | def VLD4LNdWB_register_Asm_16 : |
| 6318 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6319 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, |
| 6320 | rGPR:$Rm, pred:$p)>; |
| 6321 | def VLD4LNdWB_register_Asm_32 : |
| 6322 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6323 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, |
| 6324 | rGPR:$Rm, pred:$p)>; |
| 6325 | def VLD4LNqWB_register_Asm_16 : |
| 6326 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6327 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, |
| 6328 | rGPR:$Rm, pred:$p)>; |
| 6329 | def VLD4LNqWB_register_Asm_32 : |
| 6330 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6331 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, |
| 6332 | rGPR:$Rm, pred:$p)>; |
| 6333 | |
Jim Grosbach | c387fc6 | 2012-01-23 23:20:46 +0000 | [diff] [blame] | 6334 | |
| 6335 | |
Jim Grosbach | 8abe7e3 | 2012-01-24 00:43:17 +0000 | [diff] [blame] | 6336 | // VLD4 multiple structure pseudo-instructions. These need special handling for |
| 6337 | // the vector operands that the normal instructions don't yet model. |
| 6338 | // FIXME: Remove these when the register classes and instructions are updated. |
| 6339 | def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", |
| 6340 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6341 | def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
| 6342 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6343 | def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
| 6344 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6345 | def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", |
| 6346 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6347 | def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", |
| 6348 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6349 | def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", |
| 6350 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6351 | |
| 6352 | def VLD4dWB_fixed_Asm_8 : |
| 6353 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", |
| 6354 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6355 | def VLD4dWB_fixed_Asm_16 : |
| 6356 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6357 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6358 | def VLD4dWB_fixed_Asm_32 : |
| 6359 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6360 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6361 | def VLD4qWB_fixed_Asm_8 : |
| 6362 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", |
| 6363 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6364 | def VLD4qWB_fixed_Asm_16 : |
| 6365 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", |
| 6366 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6367 | def VLD4qWB_fixed_Asm_32 : |
| 6368 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", |
| 6369 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6370 | def VLD4dWB_register_Asm_8 : |
| 6371 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", |
| 6372 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6373 | rGPR:$Rm, pred:$p)>; |
| 6374 | def VLD4dWB_register_Asm_16 : |
| 6375 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6376 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6377 | rGPR:$Rm, pred:$p)>; |
| 6378 | def VLD4dWB_register_Asm_32 : |
| 6379 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6380 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6381 | rGPR:$Rm, pred:$p)>; |
| 6382 | def VLD4qWB_register_Asm_8 : |
| 6383 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", |
| 6384 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6385 | rGPR:$Rm, pred:$p)>; |
| 6386 | def VLD4qWB_register_Asm_16 : |
| 6387 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", |
| 6388 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6389 | rGPR:$Rm, pred:$p)>; |
| 6390 | def VLD4qWB_register_Asm_32 : |
| 6391 | NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", |
| 6392 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6393 | rGPR:$Rm, pred:$p)>; |
| 6394 | |
Jim Grosbach | 88a54de | 2012-01-24 18:53:13 +0000 | [diff] [blame] | 6395 | // VST4 single-lane pseudo-instructions. These need special handling for |
| 6396 | // the lane index that an InstAlias can't handle, so we use these instead. |
| 6397 | def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", |
| 6398 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6399 | def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", |
| 6400 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6401 | def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", |
| 6402 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6403 | def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", |
| 6404 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6405 | def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", |
| 6406 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6407 | |
| 6408 | def VST4LNdWB_fixed_Asm_8 : |
| 6409 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", |
| 6410 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6411 | def VST4LNdWB_fixed_Asm_16 : |
| 6412 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", |
| 6413 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6414 | def VST4LNdWB_fixed_Asm_32 : |
| 6415 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", |
| 6416 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6417 | def VST4LNqWB_fixed_Asm_16 : |
| 6418 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", |
| 6419 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6420 | def VST4LNqWB_fixed_Asm_32 : |
| 6421 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", |
| 6422 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; |
| 6423 | def VST4LNdWB_register_Asm_8 : |
| 6424 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", |
| 6425 | (ins VecListFourDByteIndexed:$list, addrmode6:$addr, |
| 6426 | rGPR:$Rm, pred:$p)>; |
| 6427 | def VST4LNdWB_register_Asm_16 : |
| 6428 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", |
| 6429 | (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, |
| 6430 | rGPR:$Rm, pred:$p)>; |
| 6431 | def VST4LNdWB_register_Asm_32 : |
| 6432 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", |
| 6433 | (ins VecListFourDWordIndexed:$list, addrmode6:$addr, |
| 6434 | rGPR:$Rm, pred:$p)>; |
| 6435 | def VST4LNqWB_register_Asm_16 : |
| 6436 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", |
| 6437 | (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, |
| 6438 | rGPR:$Rm, pred:$p)>; |
| 6439 | def VST4LNqWB_register_Asm_32 : |
| 6440 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", |
| 6441 | (ins VecListFourQWordIndexed:$list, addrmode6:$addr, |
| 6442 | rGPR:$Rm, pred:$p)>; |
| 6443 | |
Jim Grosbach | 539aab7 | 2012-01-24 00:58:13 +0000 | [diff] [blame] | 6444 | |
| 6445 | // VST4 multiple structure pseudo-instructions. These need special handling for |
| 6446 | // the vector operands that the normal instructions don't yet model. |
| 6447 | // FIXME: Remove these when the register classes and instructions are updated. |
| 6448 | def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", |
| 6449 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6450 | def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", |
| 6451 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6452 | def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", |
| 6453 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6454 | def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", |
| 6455 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6456 | def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", |
| 6457 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6458 | def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", |
| 6459 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6460 | |
| 6461 | def VST4dWB_fixed_Asm_8 : |
| 6462 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", |
| 6463 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6464 | def VST4dWB_fixed_Asm_16 : |
| 6465 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", |
| 6466 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6467 | def VST4dWB_fixed_Asm_32 : |
| 6468 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", |
| 6469 | (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; |
| 6470 | def VST4qWB_fixed_Asm_8 : |
| 6471 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", |
| 6472 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6473 | def VST4qWB_fixed_Asm_16 : |
| 6474 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", |
| 6475 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6476 | def VST4qWB_fixed_Asm_32 : |
| 6477 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", |
| 6478 | (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; |
| 6479 | def VST4dWB_register_Asm_8 : |
| 6480 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", |
| 6481 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6482 | rGPR:$Rm, pred:$p)>; |
| 6483 | def VST4dWB_register_Asm_16 : |
| 6484 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", |
| 6485 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6486 | rGPR:$Rm, pred:$p)>; |
| 6487 | def VST4dWB_register_Asm_32 : |
| 6488 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", |
| 6489 | (ins VecListFourD:$list, addrmode6:$addr, |
| 6490 | rGPR:$Rm, pred:$p)>; |
| 6491 | def VST4qWB_register_Asm_8 : |
| 6492 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", |
| 6493 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6494 | rGPR:$Rm, pred:$p)>; |
| 6495 | def VST4qWB_register_Asm_16 : |
| 6496 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", |
| 6497 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6498 | rGPR:$Rm, pred:$p)>; |
| 6499 | def VST4qWB_register_Asm_32 : |
| 6500 | NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", |
| 6501 | (ins VecListFourQ:$list, addrmode6:$addr, |
| 6502 | rGPR:$Rm, pred:$p)>; |
| 6503 | |
Jim Grosbach | 1ceef1a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 6504 | // VMOV takes an optional datatype suffix |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 6505 | defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", |
Jim Grosbach | 1ceef1a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 6506 | (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 6507 | defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", |
Jim Grosbach | 1ceef1a | 2011-12-07 01:50:36 +0000 | [diff] [blame] | 6508 | (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; |
| 6509 | |
Jim Grosbach | 470855b | 2011-12-07 17:51:15 +0000 | [diff] [blame] | 6510 | // VCLT (register) is an assembler alias for VCGT w/ the operands reversed. |
| 6511 | // D-register versions. |
Jim Grosbach | a738da7 | 2011-12-15 22:56:33 +0000 | [diff] [blame] | 6512 | def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm", |
| 6513 | (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6514 | def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm", |
| 6515 | (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6516 | def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm", |
| 6517 | (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6518 | def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm", |
| 6519 | (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6520 | def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm", |
| 6521 | (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6522 | def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm", |
| 6523 | (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6524 | def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm", |
| 6525 | (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6526 | // Q-register versions. |
| 6527 | def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm", |
| 6528 | (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6529 | def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm", |
| 6530 | (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6531 | def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm", |
| 6532 | (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6533 | def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm", |
| 6534 | (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6535 | def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm", |
| 6536 | (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6537 | def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm", |
| 6538 | (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6539 | def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm", |
| 6540 | (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6541 | |
| 6542 | // VCLT (register) is an assembler alias for VCGT w/ the operands reversed. |
| 6543 | // D-register versions. |
Jim Grosbach | 470855b | 2011-12-07 17:51:15 +0000 | [diff] [blame] | 6544 | def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm", |
| 6545 | (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6546 | def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm", |
| 6547 | (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6548 | def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm", |
| 6549 | (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6550 | def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm", |
| 6551 | (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6552 | def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm", |
| 6553 | (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6554 | def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm", |
| 6555 | (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6556 | def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm", |
| 6557 | (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; |
| 6558 | // Q-register versions. |
| 6559 | def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm", |
| 6560 | (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6561 | def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm", |
| 6562 | (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6563 | def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm", |
| 6564 | (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6565 | def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm", |
| 6566 | (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6567 | def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm", |
| 6568 | (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6569 | def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm", |
| 6570 | (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
| 6571 | def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm", |
| 6572 | (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; |
Jim Grosbach | a44f2c4 | 2011-12-08 00:43:47 +0000 | [diff] [blame] | 6573 | |
Jim Grosbach | 5f669fa | 2011-12-21 23:09:28 +0000 | [diff] [blame] | 6574 | // VSWP allows, but does not require, a type suffix. |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 6575 | defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", |
Jim Grosbach | 5f669fa | 2011-12-21 23:09:28 +0000 | [diff] [blame] | 6576 | (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>; |
Jim Grosbach | 78d13e1 | 2012-01-24 17:23:29 +0000 | [diff] [blame] | 6577 | defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", |
Jim Grosbach | 5f669fa | 2011-12-21 23:09:28 +0000 | [diff] [blame] | 6578 | (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>; |
| 6579 | |
Jim Grosbach | c94206e | 2012-02-28 19:11:07 +0000 | [diff] [blame] | 6580 | // VBIF, VBIT, and VBSL allow, but do not require, a type suffix. |
| 6581 | defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", |
| 6582 | (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
| 6583 | defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", |
| 6584 | (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
| 6585 | defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", |
| 6586 | (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; |
| 6587 | defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", |
| 6588 | (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
| 6589 | defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", |
| 6590 | (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
| 6591 | defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", |
| 6592 | (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; |
| 6593 | |
Jim Grosbach | 9b08785 | 2011-12-19 23:51:07 +0000 | [diff] [blame] | 6594 | // "vmov Rd, #-imm" can be handled via "vmvn". |
| 6595 | def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", |
| 6596 | (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; |
| 6597 | def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", |
| 6598 | (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; |
| 6599 | def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", |
| 6600 | (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; |
| 6601 | def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", |
| 6602 | (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; |
| 6603 | |
Jim Grosbach | 485d8bf | 2011-12-13 20:08:32 +0000 | [diff] [blame] | 6604 | // 'gas' compatibility aliases for quad-word instructions. Strictly speaking, |
| 6605 | // these should restrict to just the Q register variants, but the register |
| 6606 | // classes are enough to match correctly regardless, so we keep it simple |
| 6607 | // and just use MnemonicAlias. |
| 6608 | def : NEONMnemonicAlias<"vbicq", "vbic">; |
| 6609 | def : NEONMnemonicAlias<"vandq", "vand">; |
| 6610 | def : NEONMnemonicAlias<"veorq", "veor">; |
| 6611 | def : NEONMnemonicAlias<"vorrq", "vorr">; |
| 6612 | |
| 6613 | def : NEONMnemonicAlias<"vmovq", "vmov">; |
| 6614 | def : NEONMnemonicAlias<"vmvnq", "vmvn">; |
Jim Grosbach | ddecfe5 | 2011-12-16 00:12:22 +0000 | [diff] [blame] | 6615 | // Explicit versions for floating point so that the FPImm variants get |
| 6616 | // handled early. The parser gets confused otherwise. |
| 6617 | def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">; |
| 6618 | def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">; |
Jim Grosbach | 485d8bf | 2011-12-13 20:08:32 +0000 | [diff] [blame] | 6619 | |
| 6620 | def : NEONMnemonicAlias<"vaddq", "vadd">; |
| 6621 | def : NEONMnemonicAlias<"vsubq", "vsub">; |
| 6622 | |
| 6623 | def : NEONMnemonicAlias<"vminq", "vmin">; |
| 6624 | def : NEONMnemonicAlias<"vmaxq", "vmax">; |
| 6625 | |
| 6626 | def : NEONMnemonicAlias<"vmulq", "vmul">; |
| 6627 | |
| 6628 | def : NEONMnemonicAlias<"vabsq", "vabs">; |
| 6629 | |
| 6630 | def : NEONMnemonicAlias<"vshlq", "vshl">; |
| 6631 | def : NEONMnemonicAlias<"vshrq", "vshr">; |
| 6632 | |
| 6633 | def : NEONMnemonicAlias<"vcvtq", "vcvt">; |
| 6634 | |
| 6635 | def : NEONMnemonicAlias<"vcleq", "vcle">; |
| 6636 | def : NEONMnemonicAlias<"vceqq", "vceq">; |
Jim Grosbach | 4553fa3 | 2011-12-21 23:04:33 +0000 | [diff] [blame] | 6637 | |
| 6638 | def : NEONMnemonicAlias<"vzipq", "vzip">; |
| 6639 | def : NEONMnemonicAlias<"vswpq", "vswp">; |
Jim Grosbach | f7c66fa | 2011-12-21 23:52:37 +0000 | [diff] [blame] | 6640 | |
| 6641 | def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">; |
| 6642 | def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">; |
Jim Grosbach | 51222d1 | 2012-01-20 18:09:51 +0000 | [diff] [blame] | 6643 | |
| 6644 | |
| 6645 | // Alias for loading floating point immediates that aren't representable |
| 6646 | // using the vmov.f32 encoding but the bitpattern is representable using |
| 6647 | // the .i32 encoding. |
| 6648 | def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", |
| 6649 | (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; |
| 6650 | def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", |
| 6651 | (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; |