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Evan Chengc6fe3332010-03-02 02:38:24 +00001//===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass performs global common subexpression elimination on machine
Evan Chengc5bbba12010-03-02 19:02:27 +000011// instructions using a scoped hash table based value numbering scheme. It
Evan Chengc6fe3332010-03-02 02:38:24 +000012// must be run while the machine function is still in SSA form.
13//
14//===----------------------------------------------------------------------===//
15
16#define DEBUG_TYPE "machine-cse"
17#include "llvm/CodeGen/Passes.h"
18#include "llvm/CodeGen/MachineDominators.h"
19#include "llvm/CodeGen/MachineInstr.h"
Evan Cheng6ba95542010-03-03 02:48:20 +000020#include "llvm/CodeGen/MachineRegisterInfo.h"
Evan Chenga5f32cb2010-03-04 21:18:08 +000021#include "llvm/Analysis/AliasAnalysis.h"
Evan Cheng6ba95542010-03-03 02:48:20 +000022#include "llvm/Target/TargetInstrInfo.h"
Evan Cheng31156982010-04-21 00:21:07 +000023#include "llvm/ADT/DenseMap.h"
Evan Chengc6fe3332010-03-02 02:38:24 +000024#include "llvm/ADT/ScopedHashTable.h"
Evan Cheng189c1ec2010-10-29 23:36:03 +000025#include "llvm/ADT/SmallSet.h"
Evan Chengc6fe3332010-03-02 02:38:24 +000026#include "llvm/ADT/Statistic.h"
27#include "llvm/Support/Debug.h"
Cameron Zwarich53eeba52011-01-03 04:07:46 +000028#include "llvm/Support/RecyclingAllocator.h"
Evan Chengc6fe3332010-03-02 02:38:24 +000029using namespace llvm;
30
Evan Cheng16b48b82010-03-03 21:20:05 +000031STATISTIC(NumCoalesces, "Number of copies coalesced");
32STATISTIC(NumCSEs, "Number of common subexpression eliminated");
Evan Cheng189c1ec2010-10-29 23:36:03 +000033STATISTIC(NumPhysCSEs,
34 "Number of physreg referencing common subexpr eliminated");
Evan Cheng97b5beb2012-01-10 02:02:58 +000035STATISTIC(NumCrossBBCSEs,
36 "Number of cross-MBB physreg referencing CS eliminated");
Evan Chenga63cde22010-12-15 22:16:21 +000037STATISTIC(NumCommutes, "Number of copies coalesced after commuting");
Bob Wilson38441732010-06-03 18:28:31 +000038
Evan Chengc6fe3332010-03-02 02:38:24 +000039namespace {
40 class MachineCSE : public MachineFunctionPass {
Evan Cheng6ba95542010-03-03 02:48:20 +000041 const TargetInstrInfo *TII;
Evan Chengb3958e82010-03-04 01:33:55 +000042 const TargetRegisterInfo *TRI;
Evan Chenga5f32cb2010-03-04 21:18:08 +000043 AliasAnalysis *AA;
Evan Cheng31f94c72010-03-09 03:21:12 +000044 MachineDominatorTree *DT;
45 MachineRegisterInfo *MRI;
Evan Chengc6fe3332010-03-02 02:38:24 +000046 public:
47 static char ID; // Pass identification
Owen Anderson081c34b2010-10-19 17:21:58 +000048 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) {
49 initializeMachineCSEPass(*PassRegistry::getPassRegistry());
50 }
Evan Chengc6fe3332010-03-02 02:38:24 +000051
52 virtual bool runOnMachineFunction(MachineFunction &MF);
Andrew Trick1df91b02012-02-08 21:22:43 +000053
Evan Chengc6fe3332010-03-02 02:38:24 +000054 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
55 AU.setPreservesCFG();
56 MachineFunctionPass::getAnalysisUsage(AU);
Evan Chenga5f32cb2010-03-04 21:18:08 +000057 AU.addRequired<AliasAnalysis>();
Evan Cheng65424162010-08-17 20:57:42 +000058 AU.addPreservedID(MachineLoopInfoID);
Evan Chengc6fe3332010-03-02 02:38:24 +000059 AU.addRequired<MachineDominatorTree>();
60 AU.addPreserved<MachineDominatorTree>();
61 }
62
Evan Chengc2b768f2010-09-17 21:59:42 +000063 virtual void releaseMemory() {
64 ScopeMap.clear();
65 Exps.clear();
Lang Hamesc2e08db2012-02-17 00:27:16 +000066 AllocatableRegs.clear();
67 ReservedRegs.clear();
Evan Chengc2b768f2010-09-17 21:59:42 +000068 }
69
Evan Chengc6fe3332010-03-02 02:38:24 +000070 private:
Evan Cheng835810b2010-05-21 21:22:19 +000071 const unsigned LookAheadLimit;
Cameron Zwarich53eeba52011-01-03 04:07:46 +000072 typedef RecyclingAllocator<BumpPtrAllocator,
73 ScopedHashTableVal<MachineInstr*, unsigned> > AllocatorTy;
74 typedef ScopedHashTable<MachineInstr*, unsigned,
75 MachineInstrExpressionTrait, AllocatorTy> ScopedHTType;
76 typedef ScopedHTType::ScopeTy ScopeType;
Evan Cheng31156982010-04-21 00:21:07 +000077 DenseMap<MachineBasicBlock*, ScopeType*> ScopeMap;
Cameron Zwarich53eeba52011-01-03 04:07:46 +000078 ScopedHTType VNT;
Evan Cheng16b48b82010-03-03 21:20:05 +000079 SmallVector<MachineInstr*, 64> Exps;
Evan Cheng31156982010-04-21 00:21:07 +000080 unsigned CurrVN;
Lang Hamesc2e08db2012-02-17 00:27:16 +000081 BitVector AllocatableRegs;
82 BitVector ReservedRegs;
Evan Cheng16b48b82010-03-03 21:20:05 +000083
Evan Chenga5f32cb2010-03-04 21:18:08 +000084 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
Evan Chengb3958e82010-03-04 01:33:55 +000085 bool isPhysDefTriviallyDead(unsigned Reg,
86 MachineBasicBlock::const_iterator I,
Evan Cheng835810b2010-05-21 21:22:19 +000087 MachineBasicBlock::const_iterator E) const ;
Evan Cheng189c1ec2010-10-29 23:36:03 +000088 bool hasLivePhysRegDefUses(const MachineInstr *MI,
89 const MachineBasicBlock *MBB,
Evan Cheng97b5beb2012-01-10 02:02:58 +000090 SmallSet<unsigned,8> &PhysRefs,
91 SmallVector<unsigned,2> &PhysDefs) const;
Evan Cheng189c1ec2010-10-29 23:36:03 +000092 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
Evan Cheng97b5beb2012-01-10 02:02:58 +000093 SmallSet<unsigned,8> &PhysRefs,
Evan Chengf96703e2012-01-11 00:38:11 +000094 SmallVector<unsigned,2> &PhysDefs,
Evan Cheng97b5beb2012-01-10 02:02:58 +000095 bool &NonLocal) const;
Evan Chenga5f32cb2010-03-04 21:18:08 +000096 bool isCSECandidate(MachineInstr *MI);
Evan Cheng2938a002010-03-10 02:12:03 +000097 bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
98 MachineInstr *CSMI, MachineInstr *MI);
Evan Cheng31156982010-04-21 00:21:07 +000099 void EnterScope(MachineBasicBlock *MBB);
100 void ExitScope(MachineBasicBlock *MBB);
101 bool ProcessBlock(MachineBasicBlock *MBB);
102 void ExitScopeIfDone(MachineDomTreeNode *Node,
103 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
104 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap);
105 bool PerformCSE(MachineDomTreeNode *Node);
Evan Chengc6fe3332010-03-02 02:38:24 +0000106 };
107} // end anonymous namespace
108
109char MachineCSE::ID = 0;
Andrew Trick1dd8c852012-02-08 21:23:13 +0000110char &llvm::MachineCSEID = MachineCSE::ID;
Owen Anderson2ab36d32010-10-12 19:48:12 +0000111INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
112 "Machine Common Subexpression Elimination", false, false)
113INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
114INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
115INITIALIZE_PASS_END(MachineCSE, "machine-cse",
Owen Andersonce665bd2010-10-07 22:25:06 +0000116 "Machine Common Subexpression Elimination", false, false)
Evan Chengc6fe3332010-03-02 02:38:24 +0000117
Evan Cheng6ba95542010-03-03 02:48:20 +0000118bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
119 MachineBasicBlock *MBB) {
120 bool Changed = false;
121 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MI->getOperand(i);
Evan Cheng16b48b82010-03-03 21:20:05 +0000123 if (!MO.isReg() || !MO.isUse())
124 continue;
125 unsigned Reg = MO.getReg();
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +0000126 if (!TargetRegisterInfo::isVirtualRegister(Reg))
Evan Cheng16b48b82010-03-03 21:20:05 +0000127 continue;
Evan Chengf437f732010-09-17 21:56:26 +0000128 if (!MRI->hasOneNonDBGUse(Reg))
Evan Cheng16b48b82010-03-03 21:20:05 +0000129 // Only coalesce single use copies. This ensure the copy will be
130 // deleted.
131 continue;
132 MachineInstr *DefMI = MRI->getVRegDef(Reg);
133 if (DefMI->getParent() != MBB)
134 continue;
Jakob Stoklund Olesen0bc25f42010-07-08 16:40:22 +0000135 if (!DefMI->isCopy())
136 continue;
Jakob Stoklund Olesen04c528a2010-07-16 04:45:42 +0000137 unsigned SrcReg = DefMI->getOperand(1).getReg();
Jakob Stoklund Olesen0bc25f42010-07-08 16:40:22 +0000138 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
139 continue;
140 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
141 continue;
Jakob Stoklund Olesenbf4699c2010-10-06 23:54:39 +0000142 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
Jakob Stoklund Olesen0bc25f42010-07-08 16:40:22 +0000143 continue;
144 DEBUG(dbgs() << "Coalescing: " << *DefMI);
Jakob Stoklund Olesenbf4699c2010-10-06 23:54:39 +0000145 DEBUG(dbgs() << "*** to: " << *MI);
Jakob Stoklund Olesen0bc25f42010-07-08 16:40:22 +0000146 MO.setReg(SrcReg);
147 MRI->clearKillFlags(SrcReg);
Jakob Stoklund Olesen0bc25f42010-07-08 16:40:22 +0000148 DefMI->eraseFromParent();
149 ++NumCoalesces;
150 Changed = true;
Evan Cheng6ba95542010-03-03 02:48:20 +0000151 }
152
153 return Changed;
154}
155
Evan Cheng835810b2010-05-21 21:22:19 +0000156bool
157MachineCSE::isPhysDefTriviallyDead(unsigned Reg,
158 MachineBasicBlock::const_iterator I,
159 MachineBasicBlock::const_iterator E) const {
Eric Christophere81d0102010-05-21 23:40:03 +0000160 unsigned LookAheadLeft = LookAheadLimit;
Evan Cheng112e5e72010-03-23 20:33:48 +0000161 while (LookAheadLeft) {
Evan Cheng22504252010-03-24 01:50:28 +0000162 // Skip over dbg_value's.
163 while (I != E && I->isDebugValue())
164 ++I;
165
Evan Chengb3958e82010-03-04 01:33:55 +0000166 if (I == E)
167 // Reached end of block, register is obviously dead.
168 return true;
169
Evan Chengb3958e82010-03-04 01:33:55 +0000170 bool SeenDef = false;
171 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
172 const MachineOperand &MO = I->getOperand(i);
173 if (!MO.isReg() || !MO.getReg())
174 continue;
175 if (!TRI->regsOverlap(MO.getReg(), Reg))
176 continue;
177 if (MO.isUse())
Evan Cheng835810b2010-05-21 21:22:19 +0000178 // Found a use!
Evan Chengb3958e82010-03-04 01:33:55 +0000179 return false;
180 SeenDef = true;
181 }
182 if (SeenDef)
Andrew Trick1df91b02012-02-08 21:22:43 +0000183 // See a def of Reg (or an alias) before encountering any use, it's
Evan Chengb3958e82010-03-04 01:33:55 +0000184 // trivially dead.
185 return true;
Evan Cheng112e5e72010-03-23 20:33:48 +0000186
187 --LookAheadLeft;
Evan Chengb3958e82010-03-04 01:33:55 +0000188 ++I;
189 }
190 return false;
191}
192
Evan Cheng189c1ec2010-10-29 23:36:03 +0000193/// hasLivePhysRegDefUses - Return true if the specified instruction read/write
Evan Cheng835810b2010-05-21 21:22:19 +0000194/// physical registers (except for dead defs of physical registers). It also
Evan Cheng2b4e7272010-06-04 23:28:13 +0000195/// returns the physical register def by reference if it's the only one and the
196/// instruction does not uses a physical register.
Evan Cheng189c1ec2010-10-29 23:36:03 +0000197bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI,
198 const MachineBasicBlock *MBB,
Evan Cheng97b5beb2012-01-10 02:02:58 +0000199 SmallSet<unsigned,8> &PhysRefs,
200 SmallVector<unsigned,2> &PhysDefs) const{
Evan Cheng189c1ec2010-10-29 23:36:03 +0000201 MachineBasicBlock::const_iterator I = MI; I = llvm::next(I);
Evan Cheng6ba95542010-03-03 02:48:20 +0000202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
Evan Cheng835810b2010-05-21 21:22:19 +0000203 const MachineOperand &MO = MI->getOperand(i);
Evan Cheng6ba95542010-03-03 02:48:20 +0000204 if (!MO.isReg())
205 continue;
206 unsigned Reg = MO.getReg();
207 if (!Reg)
208 continue;
Evan Cheng835810b2010-05-21 21:22:19 +0000209 if (TargetRegisterInfo::isVirtualRegister(Reg))
210 continue;
Evan Cheng189c1ec2010-10-29 23:36:03 +0000211 // If the def is dead, it's ok. But the def may not marked "dead". That's
Evan Cheng835810b2010-05-21 21:22:19 +0000212 // common since this pass is run before livevariables. We can scan
213 // forward a few instructions and check if it is obviously dead.
Evan Cheng189c1ec2010-10-29 23:36:03 +0000214 if (MO.isDef() &&
215 (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
216 continue;
217 PhysRefs.insert(Reg);
Evan Cheng97b5beb2012-01-10 02:02:58 +0000218 if (MO.isDef())
219 PhysDefs.push_back(Reg);
Evan Cheng189c1ec2010-10-29 23:36:03 +0000220 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
221 PhysRefs.insert(*Alias);
Evan Chengb3958e82010-03-04 01:33:55 +0000222 }
223
Evan Cheng189c1ec2010-10-29 23:36:03 +0000224 return !PhysRefs.empty();
Evan Chengc6fe3332010-03-02 02:38:24 +0000225}
226
Evan Cheng189c1ec2010-10-29 23:36:03 +0000227bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI,
Evan Cheng97b5beb2012-01-10 02:02:58 +0000228 SmallSet<unsigned,8> &PhysRefs,
Evan Chengf96703e2012-01-11 00:38:11 +0000229 SmallVector<unsigned,2> &PhysDefs,
Evan Cheng97b5beb2012-01-10 02:02:58 +0000230 bool &NonLocal) const {
Eli Friedman5e926ac2011-05-06 05:23:07 +0000231 // For now conservatively returns false if the common subexpression is
Evan Cheng97b5beb2012-01-10 02:02:58 +0000232 // not in the same basic block as the given instruction. The only exception
233 // is if the common subexpression is in the sole predecessor block.
234 const MachineBasicBlock *MBB = MI->getParent();
235 const MachineBasicBlock *CSMBB = CSMI->getParent();
236
237 bool CrossMBB = false;
238 if (CSMBB != MBB) {
Evan Chengf96703e2012-01-11 00:38:11 +0000239 if (MBB->pred_size() != 1 || *MBB->pred_begin() != CSMBB)
Evan Cheng97b5beb2012-01-10 02:02:58 +0000240 return false;
Evan Chengf96703e2012-01-11 00:38:11 +0000241
242 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
Lang Hamesc2e08db2012-02-17 00:27:16 +0000243 if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
244 // Avoid extending live range of physical registers if they are
245 //allocatable or reserved.
Evan Chengf96703e2012-01-11 00:38:11 +0000246 return false;
247 }
248 CrossMBB = true;
Evan Cheng97b5beb2012-01-10 02:02:58 +0000249 }
Eli Friedman5e926ac2011-05-06 05:23:07 +0000250 MachineBasicBlock::const_iterator I = CSMI; I = llvm::next(I);
251 MachineBasicBlock::const_iterator E = MI;
Evan Cheng97b5beb2012-01-10 02:02:58 +0000252 MachineBasicBlock::const_iterator EE = CSMBB->end();
Evan Cheng835810b2010-05-21 21:22:19 +0000253 unsigned LookAheadLeft = LookAheadLimit;
254 while (LookAheadLeft) {
Eli Friedman5e926ac2011-05-06 05:23:07 +0000255 // Skip over dbg_value's.
Evan Cheng97b5beb2012-01-10 02:02:58 +0000256 while (I != E && I != EE && I->isDebugValue())
Evan Cheng835810b2010-05-21 21:22:19 +0000257 ++I;
Eli Friedman5e926ac2011-05-06 05:23:07 +0000258
Evan Cheng97b5beb2012-01-10 02:02:58 +0000259 if (I == EE) {
260 assert(CrossMBB && "Reaching end-of-MBB without finding MI?");
Duncan Sands5b8a1db2012-02-05 14:20:11 +0000261 (void)CrossMBB;
Evan Cheng97b5beb2012-01-10 02:02:58 +0000262 CrossMBB = false;
263 NonLocal = true;
264 I = MBB->begin();
265 EE = MBB->end();
266 continue;
267 }
268
Eli Friedman5e926ac2011-05-06 05:23:07 +0000269 if (I == E)
270 return true;
271
272 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
273 const MachineOperand &MO = I->getOperand(i);
274 if (!MO.isReg() || !MO.isDef())
275 continue;
276 unsigned MOReg = MO.getReg();
277 if (TargetRegisterInfo::isVirtualRegister(MOReg))
278 continue;
279 if (PhysRefs.count(MOReg))
280 return false;
Evan Cheng189c1ec2010-10-29 23:36:03 +0000281 }
Eli Friedman5e926ac2011-05-06 05:23:07 +0000282
283 --LookAheadLeft;
284 ++I;
Evan Cheng835810b2010-05-21 21:22:19 +0000285 }
286
287 return false;
288}
289
Evan Chenga5f32cb2010-03-04 21:18:08 +0000290bool MachineCSE::isCSECandidate(MachineInstr *MI) {
Evan Cheng51960182010-03-08 23:49:12 +0000291 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
Dale Johannesene68ea062010-03-11 02:10:24 +0000292 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
Evan Cheng51960182010-03-08 23:49:12 +0000293 return false;
294
Evan Cheng2938a002010-03-10 02:12:03 +0000295 // Ignore copies.
Jakob Stoklund Olesen04c528a2010-07-16 04:45:42 +0000296 if (MI->isCopyLike())
Evan Chenga5f32cb2010-03-04 21:18:08 +0000297 return false;
298
299 // Ignore stuff that we obviously can't move.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000300 if (MI->mayStore() || MI->isCall() || MI->isTerminator() ||
Evan Chengc36b7062011-01-07 23:50:32 +0000301 MI->hasUnmodeledSideEffects())
Evan Chenga5f32cb2010-03-04 21:18:08 +0000302 return false;
303
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000304 if (MI->mayLoad()) {
Evan Chenga5f32cb2010-03-04 21:18:08 +0000305 // Okay, this instruction does a load. As a refinement, we allow the target
306 // to decide whether the loaded value is actually a constant. If so, we can
307 // actually use it as a load.
308 if (!MI->isInvariantLoad(AA))
309 // FIXME: we should be able to hoist loads with no other side effects if
310 // there are no other instructions which can change memory in this loop.
311 // This is a trivial form of alias analysis.
312 return false;
313 }
314 return true;
315}
316
Evan Cheng31f94c72010-03-09 03:21:12 +0000317/// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
318/// common expression that defines Reg.
Evan Cheng2938a002010-03-10 02:12:03 +0000319bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
320 MachineInstr *CSMI, MachineInstr *MI) {
321 // FIXME: Heuristics that works around the lack the live range splitting.
322
Chris Lattner622a11b2011-01-10 07:51:31 +0000323 // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in
324 // an immediate predecessor. We don't want to increase register pressure and
325 // end up causing other computation to be spilled.
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000326 if (MI->isAsCheapAsAMove()) {
Evan Cheng2938a002010-03-10 02:12:03 +0000327 MachineBasicBlock *CSBB = CSMI->getParent();
328 MachineBasicBlock *BB = MI->getParent();
Chris Lattner622a11b2011-01-10 07:51:31 +0000329 if (CSBB != BB && !CSBB->isSuccessor(BB))
Evan Cheng2938a002010-03-10 02:12:03 +0000330 return false;
331 }
332
333 // Heuristics #2: If the expression doesn't not use a vr and the only use
334 // of the redundant computation are copies, do not cse.
335 bool HasVRegUse = false;
336 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
337 const MachineOperand &MO = MI->getOperand(i);
Jakob Stoklund Olesenc9df0252011-01-10 02:58:51 +0000338 if (MO.isReg() && MO.isUse() &&
Evan Cheng2938a002010-03-10 02:12:03 +0000339 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
340 HasVRegUse = true;
341 break;
342 }
343 }
344 if (!HasVRegUse) {
345 bool HasNonCopyUse = false;
346 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(Reg),
347 E = MRI->use_nodbg_end(); I != E; ++I) {
348 MachineInstr *Use = &*I;
349 // Ignore copies.
Jakob Stoklund Olesen04c528a2010-07-16 04:45:42 +0000350 if (!Use->isCopyLike()) {
Evan Cheng2938a002010-03-10 02:12:03 +0000351 HasNonCopyUse = true;
352 break;
353 }
354 }
355 if (!HasNonCopyUse)
356 return false;
357 }
358
359 // Heuristics #3: If the common subexpression is used by PHIs, do not reuse
360 // it unless the defined value is already used in the BB of the new use.
Evan Cheng31f94c72010-03-09 03:21:12 +0000361 bool HasPHI = false;
362 SmallPtrSet<MachineBasicBlock*, 4> CSBBs;
Evan Cheng2938a002010-03-10 02:12:03 +0000363 for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(CSReg),
Evan Cheng31f94c72010-03-09 03:21:12 +0000364 E = MRI->use_nodbg_end(); I != E; ++I) {
365 MachineInstr *Use = &*I;
366 HasPHI |= Use->isPHI();
367 CSBBs.insert(Use->getParent());
368 }
369
370 if (!HasPHI)
371 return true;
372 return CSBBs.count(MI->getParent());
373}
374
Evan Cheng31156982010-04-21 00:21:07 +0000375void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
376 DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
377 ScopeType *Scope = new ScopeType(VNT);
378 ScopeMap[MBB] = Scope;
379}
380
381void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
382 DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
383 DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
384 assert(SI != ScopeMap.end());
385 ScopeMap.erase(SI);
386 delete SI->second;
387}
388
389bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
Evan Cheng6ba95542010-03-03 02:48:20 +0000390 bool Changed = false;
391
Evan Cheng31f94c72010-03-09 03:21:12 +0000392 SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
Evan Cheng16b48b82010-03-03 21:20:05 +0000393 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
Evan Cheng6ba95542010-03-03 02:48:20 +0000394 MachineInstr *MI = &*I;
Evan Cheng16b48b82010-03-03 21:20:05 +0000395 ++I;
Evan Chenga5f32cb2010-03-04 21:18:08 +0000396
397 if (!isCSECandidate(MI))
Evan Cheng6ba95542010-03-03 02:48:20 +0000398 continue;
Evan Cheng6ba95542010-03-03 02:48:20 +0000399
400 bool FoundCSE = VNT.count(MI);
401 if (!FoundCSE) {
402 // Look for trivial copy coalescing opportunities.
Evan Chengdb8771a2010-04-02 02:21:24 +0000403 if (PerformTrivialCoalescing(MI, MBB)) {
Evan Chengcfea9852011-04-11 18:47:20 +0000404 Changed = true;
405
Evan Chengdb8771a2010-04-02 02:21:24 +0000406 // After coalescing MI itself may become a copy.
Jakob Stoklund Olesen04c528a2010-07-16 04:45:42 +0000407 if (MI->isCopyLike())
Evan Chengdb8771a2010-04-02 02:21:24 +0000408 continue;
Evan Cheng6ba95542010-03-03 02:48:20 +0000409 FoundCSE = VNT.count(MI);
Evan Chengdb8771a2010-04-02 02:21:24 +0000410 }
Evan Cheng6ba95542010-03-03 02:48:20 +0000411 }
Evan Chenga63cde22010-12-15 22:16:21 +0000412
413 // Commute commutable instructions.
414 bool Commuted = false;
Evan Cheng5a96b3d2011-12-07 07:15:52 +0000415 if (!FoundCSE && MI->isCommutable()) {
Evan Chenga63cde22010-12-15 22:16:21 +0000416 MachineInstr *NewMI = TII->commuteInstruction(MI);
417 if (NewMI) {
418 Commuted = true;
419 FoundCSE = VNT.count(NewMI);
Evan Chengcfea9852011-04-11 18:47:20 +0000420 if (NewMI != MI) {
Evan Chenga63cde22010-12-15 22:16:21 +0000421 // New instruction. It doesn't need to be kept.
422 NewMI->eraseFromParent();
Evan Chengcfea9852011-04-11 18:47:20 +0000423 Changed = true;
424 } else if (!FoundCSE)
Evan Chenga63cde22010-12-15 22:16:21 +0000425 // MI was changed but it didn't help, commute it back!
426 (void)TII->commuteInstruction(MI);
427 }
428 }
Evan Cheng6ba95542010-03-03 02:48:20 +0000429
Evan Cheng189c1ec2010-10-29 23:36:03 +0000430 // If the instruction defines physical registers and the values *may* be
Evan Cheng67bda722010-03-03 23:59:08 +0000431 // used, then it's not safe to replace it with a common subexpression.
Evan Cheng189c1ec2010-10-29 23:36:03 +0000432 // It's also not safe if the instruction uses physical registers.
Evan Cheng97b5beb2012-01-10 02:02:58 +0000433 bool CrossMBBPhysDef = false;
Evan Cheng189c1ec2010-10-29 23:36:03 +0000434 SmallSet<unsigned,8> PhysRefs;
Evan Cheng97b5beb2012-01-10 02:02:58 +0000435 SmallVector<unsigned, 2> PhysDefs;
436 if (FoundCSE && hasLivePhysRegDefUses(MI, MBB, PhysRefs, PhysDefs)) {
Evan Cheng67bda722010-03-03 23:59:08 +0000437 FoundCSE = false;
438
Evan Cheng97b5beb2012-01-10 02:02:58 +0000439 // ... Unless the CS is local or is in the sole predecessor block
440 // and it also defines the physical register which is not clobbered
441 // in between and the physical register uses were not clobbered.
Evan Cheng189c1ec2010-10-29 23:36:03 +0000442 unsigned CSVN = VNT.lookup(MI);
443 MachineInstr *CSMI = Exps[CSVN];
Evan Chengf96703e2012-01-11 00:38:11 +0000444 if (PhysRegDefsReach(CSMI, MI, PhysRefs, PhysDefs, CrossMBBPhysDef))
Evan Cheng189c1ec2010-10-29 23:36:03 +0000445 FoundCSE = true;
Evan Cheng835810b2010-05-21 21:22:19 +0000446 }
447
Evan Cheng16b48b82010-03-03 21:20:05 +0000448 if (!FoundCSE) {
449 VNT.insert(MI, CurrVN++);
450 Exps.push_back(MI);
451 continue;
452 }
453
454 // Found a common subexpression, eliminate it.
455 unsigned CSVN = VNT.lookup(MI);
456 MachineInstr *CSMI = Exps[CSVN];
457 DEBUG(dbgs() << "Examining: " << *MI);
458 DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
Evan Cheng31f94c72010-03-09 03:21:12 +0000459
460 // Check if it's profitable to perform this CSE.
461 bool DoCSE = true;
Evan Cheng16b48b82010-03-03 21:20:05 +0000462 unsigned NumDefs = MI->getDesc().getNumDefs();
463 for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
464 MachineOperand &MO = MI->getOperand(i);
465 if (!MO.isReg() || !MO.isDef())
466 continue;
467 unsigned OldReg = MO.getReg();
468 unsigned NewReg = CSMI->getOperand(i).getReg();
Evan Cheng6cc1aea2010-03-06 01:14:19 +0000469 if (OldReg == NewReg)
470 continue;
Bill Wendlingf6fb7ed2011-10-12 23:03:40 +0000471
Evan Cheng6cc1aea2010-03-06 01:14:19 +0000472 assert(TargetRegisterInfo::isVirtualRegister(OldReg) &&
Evan Cheng16b48b82010-03-03 21:20:05 +0000473 TargetRegisterInfo::isVirtualRegister(NewReg) &&
474 "Do not CSE physical register defs!");
Bill Wendlingf6fb7ed2011-10-12 23:03:40 +0000475
Evan Cheng2938a002010-03-10 02:12:03 +0000476 if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
Evan Cheng31f94c72010-03-09 03:21:12 +0000477 DoCSE = false;
478 break;
479 }
Bill Wendlingf6fb7ed2011-10-12 23:03:40 +0000480
481 // Don't perform CSE if the result of the old instruction cannot exist
482 // within the register class of the new instruction.
483 const TargetRegisterClass *OldRC = MRI->getRegClass(OldReg);
484 if (!MRI->constrainRegClass(NewReg, OldRC)) {
485 DoCSE = false;
486 break;
487 }
488
Evan Cheng31f94c72010-03-09 03:21:12 +0000489 CSEPairs.push_back(std::make_pair(OldReg, NewReg));
Evan Cheng16b48b82010-03-03 21:20:05 +0000490 --NumDefs;
491 }
Evan Cheng31f94c72010-03-09 03:21:12 +0000492
493 // Actually perform the elimination.
494 if (DoCSE) {
Dan Gohman49b45892010-05-13 19:24:00 +0000495 for (unsigned i = 0, e = CSEPairs.size(); i != e; ++i) {
Evan Cheng31f94c72010-03-09 03:21:12 +0000496 MRI->replaceRegWith(CSEPairs[i].first, CSEPairs[i].second);
Dan Gohman49b45892010-05-13 19:24:00 +0000497 MRI->clearKillFlags(CSEPairs[i].second);
498 }
Evan Cheng97b5beb2012-01-10 02:02:58 +0000499
500 if (CrossMBBPhysDef) {
501 // Add physical register defs now coming in from a predecessor to MBB
502 // livein list.
503 while (!PhysDefs.empty()) {
504 unsigned LiveIn = PhysDefs.pop_back_val();
505 if (!MBB->isLiveIn(LiveIn))
506 MBB->addLiveIn(LiveIn);
507 }
508 ++NumCrossBBCSEs;
509 }
510
Evan Cheng31f94c72010-03-09 03:21:12 +0000511 MI->eraseFromParent();
512 ++NumCSEs;
Evan Cheng189c1ec2010-10-29 23:36:03 +0000513 if (!PhysRefs.empty())
Evan Cheng2b4e7272010-06-04 23:28:13 +0000514 ++NumPhysCSEs;
Evan Chenga63cde22010-12-15 22:16:21 +0000515 if (Commuted)
516 ++NumCommutes;
Evan Chengcfea9852011-04-11 18:47:20 +0000517 Changed = true;
Evan Cheng31f94c72010-03-09 03:21:12 +0000518 } else {
519 DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
520 VNT.insert(MI, CurrVN++);
521 Exps.push_back(MI);
522 }
523 CSEPairs.clear();
Evan Cheng6ba95542010-03-03 02:48:20 +0000524 }
525
Evan Cheng31156982010-04-21 00:21:07 +0000526 return Changed;
527}
528
529/// ExitScopeIfDone - Destroy scope for the MBB that corresponds to the given
530/// dominator tree node if its a leaf or all of its children are done. Walk
531/// up the dominator tree to destroy ancestors which are now done.
532void
533MachineCSE::ExitScopeIfDone(MachineDomTreeNode *Node,
534 DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren,
535 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> &ParentMap) {
536 if (OpenChildren[Node])
537 return;
538
539 // Pop scope.
540 ExitScope(Node->getBlock());
541
542 // Now traverse upwards to pop ancestors whose offsprings are all done.
543 while (MachineDomTreeNode *Parent = ParentMap[Node]) {
544 unsigned Left = --OpenChildren[Parent];
545 if (Left != 0)
546 break;
547 ExitScope(Parent->getBlock());
548 Node = Parent;
549 }
550}
551
552bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
553 SmallVector<MachineDomTreeNode*, 32> Scopes;
554 SmallVector<MachineDomTreeNode*, 8> WorkList;
555 DenseMap<MachineDomTreeNode*, MachineDomTreeNode*> ParentMap;
556 DenseMap<MachineDomTreeNode*, unsigned> OpenChildren;
557
Evan Chengc2b768f2010-09-17 21:59:42 +0000558 CurrVN = 0;
559
Evan Cheng31156982010-04-21 00:21:07 +0000560 // Perform a DFS walk to determine the order of visit.
561 WorkList.push_back(Node);
562 do {
563 Node = WorkList.pop_back_val();
564 Scopes.push_back(Node);
565 const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
566 unsigned NumChildren = Children.size();
567 OpenChildren[Node] = NumChildren;
568 for (unsigned i = 0; i != NumChildren; ++i) {
569 MachineDomTreeNode *Child = Children[i];
570 ParentMap[Child] = Node;
571 WorkList.push_back(Child);
572 }
573 } while (!WorkList.empty());
574
575 // Now perform CSE.
576 bool Changed = false;
577 for (unsigned i = 0, e = Scopes.size(); i != e; ++i) {
578 MachineDomTreeNode *Node = Scopes[i];
579 MachineBasicBlock *MBB = Node->getBlock();
580 EnterScope(MBB);
581 Changed |= ProcessBlock(MBB);
582 // If it's a leaf node, it's done. Traverse upwards to pop ancestors.
583 ExitScopeIfDone(Node, OpenChildren, ParentMap);
584 }
Evan Cheng6ba95542010-03-03 02:48:20 +0000585
586 return Changed;
587}
588
Evan Chengc6fe3332010-03-02 02:38:24 +0000589bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
Evan Cheng6ba95542010-03-03 02:48:20 +0000590 TII = MF.getTarget().getInstrInfo();
Evan Chengb3958e82010-03-04 01:33:55 +0000591 TRI = MF.getTarget().getRegisterInfo();
Evan Cheng6ba95542010-03-03 02:48:20 +0000592 MRI = &MF.getRegInfo();
Evan Chenga5f32cb2010-03-04 21:18:08 +0000593 AA = &getAnalysis<AliasAnalysis>();
Evan Cheng31f94c72010-03-09 03:21:12 +0000594 DT = &getAnalysis<MachineDominatorTree>();
Lang Hamesc2e08db2012-02-17 00:27:16 +0000595 AllocatableRegs = TRI->getAllocatableSet(MF);
596 ReservedRegs = TRI->getReservedRegs(MF);
Evan Cheng31156982010-04-21 00:21:07 +0000597 return PerformCSE(DT->getRootNode());
Evan Chengc6fe3332010-03-02 02:38:24 +0000598}