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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c20048d05ce27118c5a50fefc8829ccf12be8e38 / . / lib / Target / ARM / ARMInstrThumb.td
blob: 58cef041886fcf953c9b88037d9c3f7f79025285 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Thumb specific DAG Nodes.
16//
17
18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
20
21// TI - Thumb instruction.
22
23// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
26}
27
28class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
30}
31
32class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, ops, asm, cstr> {
36 let Pattern = pattern;
37 list<Predicate> Predicates = [IsThumb];
38}
39
40class TI<dag ops, string asm, list<dag> pattern>
41 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
42class TI1<dag ops, string asm, list<dag> pattern>
43 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
44class TI2<dag ops, string asm, list<dag> pattern>
45 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
46class TI4<dag ops, string asm, list<dag> pattern>
47 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
48class TIs<dag ops, string asm, list<dag> pattern>
49 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
50
51// Two-address instructions
52class TIt<dag ops, string asm, list<dag> pattern>
53 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
54
55// BL, BLX(1) are translated by assembler into two instructions
56class TIx2<dag ops, string asm, list<dag> pattern>
57 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
58
59def imm_neg_XFORM : SDNodeXForm<imm, [{
60 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
61}]>;
62def imm_comp_XFORM : SDNodeXForm<imm, [{
63 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
64}]>;
65
66
67/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
68def imm0_7 : PatLeaf<(i32 imm), [{
69 return (uint32_t)N->getValue() < 8;
70}]>;
71def imm0_7_neg : PatLeaf<(i32 imm), [{
72 return (uint32_t)-N->getValue() < 8;
73}], imm_neg_XFORM>;
74
75def imm0_255 : PatLeaf<(i32 imm), [{
76 return (uint32_t)N->getValue() < 256;
77}]>;
78def imm0_255_comp : PatLeaf<(i32 imm), [{
79 return ~((uint32_t)N->getValue()) < 256;
80}]>;
81
82def imm8_255 : PatLeaf<(i32 imm), [{
83 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
84}]>;
85def imm8_255_neg : PatLeaf<(i32 imm), [{
86 unsigned Val = -N->getValue();
87 return Val >= 8 && Val < 256;
88}], imm_neg_XFORM>;
89
90// Break imm's up into two pieces: an immediate + a left shift.
91// This uses thumb_immshifted to match and thumb_immshifted_val and
92// thumb_immshifted_shamt to get the val/shift pieces.
93def thumb_immshifted : PatLeaf<(imm), [{
94 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
95}]>;
96
97def thumb_immshifted_val : SDNodeXForm<imm, [{
98 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
99 return CurDAG->getTargetConstant(V, MVT::i32);
100}]>;
101
102def thumb_immshifted_shamt : SDNodeXForm<imm, [{
103 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
104 return CurDAG->getTargetConstant(V, MVT::i32);
105}]>;
106
107// Define Thumb specific addressing modes.
108
109// t_addrmode_rr := reg + reg
110//
111def t_addrmode_rr : Operand<i32>,
112 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
113 let PrintMethod = "printThumbAddrModeRROperand";
114 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
115}
116
117// t_addrmode_ri5_{1|2|4} := reg + imm5 * {1|2|4}
118//
119def t_addrmode_ri5_1 : Operand<i32>,
120 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_1", []> {
121 let PrintMethod = "printThumbAddrModeRI5_1Operand";
122 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
123}
124def t_addrmode_ri5_2 : Operand<i32>,
125 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_2", []> {
126 let PrintMethod = "printThumbAddrModeRI5_2Operand";
127 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
128}
129def t_addrmode_ri5_4 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5_4", []> {
131 let PrintMethod = "printThumbAddrModeRI5_4Operand";
132 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
133}
134
135// t_addrmode_sp := sp + imm8 * 4
136//
137def t_addrmode_sp : Operand<i32>,
138 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
139 let PrintMethod = "printThumbAddrModeSPOperand";
140 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141}
142
143//===----------------------------------------------------------------------===//
144// Miscellaneous Instructions.
145//
146
147def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
148 "\n$cp:\n\tadd $dst, pc",
149 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
150
151//===----------------------------------------------------------------------===//
152// Control Flow Instructions.
153//
154
155let isReturn = 1, isTerminator = 1 in
156 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
157
158// FIXME: remove when we have a way to marking a MI with these properties.
159let isLoad = 1, isReturn = 1, isTerminator = 1 in
160def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
161 "pop $dst1", []>;
162
163let isCall = 1, noResults = 1,
164 Defs = [R0, R1, R2, R3, LR,
165 D0, D1, D2, D3, D4, D5, D6, D7] in {
166 def tBL : TIx2<(ops i32imm:$func, variable_ops),
167 "bl ${func:call}",
168 [(ARMtcall tglobaladdr:$func)]>;
169 // ARMv5T and above
170 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
171 "blx ${func:call}",
172 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
173 def tBLXr : TI<(ops GPR:$dst, variable_ops),
174 "blx $dst",
175 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
176 // ARMv4T
177 def tBX : TIx2<(ops GPR:$dst, variable_ops),
178 "cpy lr, pc\n\tbx $dst",
179 [(ARMcall_nolink GPR:$dst)]>;
180}
181
182let isBranch = 1, isTerminator = 1, isBarrier = 1 in
183 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
184
185let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
186 def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
187 [(ARMbrcond bb:$dst, imm:$cc)]>;
188
189//===----------------------------------------------------------------------===//
190// Load Store Instructions.
191//
192
193let isLoad = 1 in {
194def tLDRri : TI4<(ops GPR:$dst, t_addrmode_ri5_4:$addr),
195 "ldr $dst, $addr",
196 [(set GPR:$dst, (load t_addrmode_ri5_4:$addr))]>;
197
198def tLDRrr : TI<(ops GPR:$dst, t_addrmode_rr:$addr),
199 "ldr $dst, $addr",
200 [(set GPR:$dst, (load t_addrmode_rr:$addr))]>;
201// def tLDRpci
202def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
203 "ldr $dst, $addr",
204 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
205
206def tLDRBri : TI1<(ops GPR:$dst, t_addrmode_ri5_1:$addr),
207 "ldrb $dst, $addr",
208 [(set GPR:$dst, (zextloadi8 t_addrmode_ri5_1:$addr))]>;
209
210def tLDRBrr : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
211 "ldrb $dst, $addr",
212 [(set GPR:$dst, (zextloadi8 t_addrmode_rr:$addr))]>;
213
214def tLDRHri : TI2<(ops GPR:$dst, t_addrmode_ri5_2:$addr),
215 "ldrh $dst, $addr",
216 [(set GPR:$dst, (zextloadi16 t_addrmode_ri5_2:$addr))]>;
217
218def tLDRHrr : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
219 "ldrh $dst, $addr",
220 [(set GPR:$dst, (zextloadi16 t_addrmode_rr:$addr))]>;
221
222def tLDRSBrr : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
223 "ldrsb $dst, $addr",
224 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
225
226def tLDRSHrr : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
227 "ldrsh $dst, $addr",
228 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
229} // isLoad
230
231let isStore = 1 in {
232def tSTRri : TI4<(ops GPR:$src, t_addrmode_ri5_4:$addr),
233 "str $src, $addr",
234 [(store GPR:$src, t_addrmode_ri5_4:$addr)]>;
235
236def tSTRrr : TI<(ops GPR:$src, t_addrmode_rr:$addr),
237 "str $src, $addr",
238 [(store GPR:$src, t_addrmode_rr:$addr)]>;
239
240def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
241 "str $src, $addr",
242 [(store GPR:$src, t_addrmode_sp:$addr)]>;
243
244def tSTRBri : TI1<(ops GPR:$src, t_addrmode_ri5_1:$addr),
245 "strb $src, $addr",
246 [(truncstorei8 GPR:$src, t_addrmode_ri5_1:$addr)]>;
247
248def tSTRBrr : TI1<(ops GPR:$src, t_addrmode_rr:$addr),
249 "strb $src, $addr",
250 [(truncstorei8 GPR:$src, t_addrmode_rr:$addr)]>;
251
252def tSTRHri : TI2<(ops GPR:$src, t_addrmode_ri5_2:$addr),
253 "strh $src, $addr",
254 [(truncstorei16 GPR:$src, t_addrmode_ri5_1:$addr)]>;
255
256def tSTRHrr : TI2<(ops GPR:$src, t_addrmode_rr:$addr),
257 "strh $src, $addr",
258 [(truncstorei16 GPR:$src, t_addrmode_rr:$addr)]>;
259}
260
261//===----------------------------------------------------------------------===//
262// Load / store multiple Instructions.
263//
264
265// TODO: A7-44: LDMIA - load multiple
266
267let isLoad = 1 in
268def tPOP : TI<(ops reglist:$dst1, variable_ops),
269 "pop $dst1", []>;
270
271let isStore = 1 in
272def tPUSH : TI<(ops reglist:$src1, variable_ops),
273 "push $src1", []>;
274
275//===----------------------------------------------------------------------===//
276// Arithmetic Instructions.
277//
278
279def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
280 "add $dst, $lhs, $rhs",
281 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
282
283def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
284 "add $dst, $rhs",
285 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
286
287def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
288 "add $dst, $lhs, $rhs",
289 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
290
291def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
292 "add $dst, $rhs", []>;
293
294def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
295 "add $dst, pc, $rhs * 4", []>;
296def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
297 "add $dst, $sp, $rhs * 4", []>;
298def tADDspi : TI<(ops GPR:$sp, i32imm:$rhs),
299 "add $sp, $rhs * 4", []>;
300
301
302def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
303 "and $dst, $rhs",
304 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
305
306def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
307 "asr $dst, $lhs, $rhs",
308 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
309
310def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
311 "asr $dst, $rhs",
312 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
313
314def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
315 "bic $dst, $rhs",
316 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
317
318
319def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
320 "cmn $lhs, $rhs",
321 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
322
323def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
324 "cmp $lhs, $rhs",
325 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
326
327def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
328 "cmp $lhs, $rhs",
329 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
330
331// TODO: A7-37: CMP(3) - cmp hi regs
332
333def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
334 "eor $dst, $rhs",
335 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
336
337def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
338 "lsl $dst, $lhs, $rhs",
339 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
340
341def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
342 "lsl $dst, $rhs",
343 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
344
345def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
346 "lsr $dst, $lhs, $rhs",
347 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
348
349def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
350 "lsr $dst, $rhs",
351 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
352
353def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
354 "mov $dst, $src",
355 [(set GPR:$dst, imm0_255:$src)]>;
356
357// TODO: A7-73: MOV(2) - mov setting flag.
358
359
360// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
361// which is MOV(3). This also supports high registers.
362def tMOVrr : TI<(ops GPR:$dst, GPR:$src),
363 "cpy $dst, $src", []>;
364
365def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
366 "mul $dst, $rhs",
367 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
368
369def tMVN : TI<(ops GPR:$dst, GPR:$src),
370 "mvn $dst, $src",
371 [(set GPR:$dst, (not GPR:$src))]>;
372
373def tNEG : TI<(ops GPR:$dst, GPR:$src),
374 "neg $dst, $src",
375 [(set GPR:$dst, (ineg GPR:$src))]>;
376
377def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
378 "orr $dst, $rhs",
379 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
380
381
382def tREV : TI<(ops GPR:$dst, GPR:$src),
383 "rev $dst, $src",
384 [(set GPR:$dst, (bswap GPR:$src))]>,
385 Requires<[IsThumb, HasV6]>;
386
387def tREV16 : TI<(ops GPR:$dst, GPR:$src),
388 "rev16 $dst, $src",
389 [(set GPR:$dst,
390 (or (and (srl GPR:$src, 8), 0xFF),
391 (or (and (shl GPR:$src, 8), 0xFF00),
392 (or (and (srl GPR:$src, 8), 0xFF0000),
393 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
394 Requires<[IsThumb, HasV6]>;
395
396def tREVSH : TI<(ops GPR:$dst, GPR:$src),
397 "revsh $dst, $src",
398 [(set GPR:$dst,
399 (sext_inreg
400 (or (srl (and GPR:$src, 0xFFFF), 8),
401 (shl GPR:$src, 8)), i16))]>,
402 Requires<[IsThumb, HasV6]>;
403
404def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
405 "ror $dst, $rhs",
406 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
407
408def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
409 "sbc $dst, $rhs",
410 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
411
412// TODO: A7-96: STMIA - store multiple.
413
414def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
415 "sub $dst, $lhs, $rhs",
416 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
417
418def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
419 "sub $dst, $rhs",
420 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
421
422def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
423 "sub $dst, $lhs, $rhs",
424 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
425
426def tSUBspi : TI<(ops GPR:$sp, i32imm:$rhs),
427 "sub $sp, $rhs * 4", []>;
428
429def tSXTB : TI<(ops GPR:$dst, GPR:$src),
430 "sxtb $dst, $src",
431 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
432 Requires<[IsThumb, HasV6]>;
433def tSXTH : TI<(ops GPR:$dst, GPR:$src),
434 "sxth $dst, $src",
435 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
436 Requires<[IsThumb, HasV6]>;
437
438// TODO: A7-122: TST - test.
439
440def tUXTB : TI<(ops GPR:$dst, GPR:$src),
441 "uxtb $dst, $src",
442 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
443 Requires<[IsThumb, HasV6]>;
444def tUXTH : TI<(ops GPR:$dst, GPR:$src),
445 "uxth $dst, $src",
446 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
447 Requires<[IsThumb, HasV6]>;
448
449
450// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
451// Expanded by the scheduler into a branch sequence.
452let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
453 def tMOVCCr :
454 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
455 "@ tMOVCCr $cc",
456 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
457
458// tLEApcrel - Load a pc-relative address into a register without offending the
459// assembler.
460def tLEApcrel : TI<(ops GPR:$dst, i32imm:$label),
461 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
462 "${:private}PCRELL${:uid}+4))\n"),
463 !strconcat("${:private}PCRELL${:uid}:\n\t",
464 "add $dst, pc, #PCRELV${:uid}")),
465 []>;
466
467def tLEApcrelCall : TI<(ops GPR:$dst, i32imm:$label),
468 !strconcat(!strconcat(".set PCRELV${:uid}, (${label:call}-(",
469 "${:private}PCRELL${:uid}+4))\n"),
470 !strconcat("${:private}PCRELL${:uid}:\n\t",
471 "add $dst, pc, #PCRELV${:uid}")),
472 []>;
473
474//===----------------------------------------------------------------------===//
475// Non-Instruction Patterns
476//
477
478// ConstantPool, GlobalAddress
479def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
480def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
481def : ThumbPat<(ARMWrapperCall tglobaladdr :$dst),
482 (tLEApcrelCall tglobaladdr :$dst)>;
483def : ThumbPat<(ARMWrapperCall texternalsym:$dst),
484 (tLEApcrelCall texternalsym:$dst)>;
485
486// Direct calls
487def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
488def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
489
490// Indirect calls to ARM routines
491def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
492
493// zextload i1 -> zextload i8
494def : ThumbPat<(zextloadi1 t_addrmode_ri5_1:$addr),
495 (tLDRBri t_addrmode_ri5_1:$addr)>;
496def : ThumbPat<(zextloadi1 t_addrmode_rr:$addr),
497 (tLDRBri t_addrmode_rr:$addr)>;
498
499// truncstore i1 -> truncstore i8
500def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_ri5_1:$dst),
501 (tSTRBri GPR:$src, t_addrmode_ri5_1:$dst)>;
502def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_rr:$dst),
503 (tSTRBrr GPR:$src, t_addrmode_rr:$dst)>;
504
505// Large immediate handling.
506
507// Two piece imms.
508def : ThumbPat<(i32 thumb_immshifted:$src),
509 (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)),
510 (thumb_immshifted_shamt imm:$src))>;
511
512def : ThumbPat<(i32 imm0_255_comp:$src),
513 (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>;