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5 <title>Writing an LLVM backend</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8
9<body>
10
11<div class="doc_title">
12 Writing an LLVM backend
13</div>
14
15<ol>
16 <li><a href="#intro">Introduction</a>
17 <li><a href="#backends">Writing a backend</a>
18 <ol>
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]19 <li><a href="#machine">Machine backends</a>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]20 <ol>
21 <li><a href="#machineTOC">Outline</a></li>
22 <li><a href="#machineDetails">Implementation details</a></li>
23 </ol></li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]24 <li><a href="#lang">Language backends</a></li>
25 </ol></li>
26 <li><a href="#related">Related reading material</a>
27</ol>
28
29<div class="doc_author">
30 <p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p>
31</div>
32
33<!-- *********************************************************************** -->
34<div class="doc_section">
35 <a name="intro">Introduction</a>
36</div>
37<!-- *********************************************************************** -->
38
39<div class="doc_text">
40
41<p>This document describes techniques for writing backends for LLVM which
42convert the LLVM representation to machine assembly code or other languages.</p>
43
44</div>
45
46<!-- *********************************************************************** -->
47<div class="doc_section">
48 <a name="backends">Writing a backend</a>
49</div>
50<!-- *********************************************************************** -->
51
52<!-- ======================================================================= -->
53<div class="doc_subsection">
54 <a name="machine">Machine backends</a>
55</div>
56
57<!-- _______________________________________________________________________ -->
58<div class="doc_subsubsection">
59 <a name="machineTOC">Outline</a>
60</div>
61
62<div class="doc_text">
63
64<p>In general, you want to follow the format of X86 or PowerPC (in
65<tt>lib/Target</tt>).</p>
66
67<p>To create a static compiler (one that emits text assembly), you need to
68implement the following:</p>
69
70<ul>
71<li>Describe the register set
72 <ul>
73 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
74 the register set and register classes</li>
75 <li>Implement a subclass of <tt><a
76 href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
77 </ul></li>
78<li>Describe the instruction set
79 <ul>
80 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
81 the instruction set</li>
82 <li>Implement a subclass of <tt><a
83 href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
84 </ul></li>
85<li>Describe the target machine
86 <ul>
87 <li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
88 the target that describes the pointer size and references the instruction
89 set</li>
90 <li>Implement a subclass of <tt><a
91 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which
92 configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt>
93 correctly</li>
Misha Brukman93d416f2004-12-27 19:05:16 +0000[diff] [blame]94 <li>Register your new target using the <tt>RegisterTarget</tt>
95 template:<br><br>
96<div class="doc_code"><pre>
97RegisterTarget&lt;<em>MyTargetMachine</em>&gt; M("short_name", " Target name");
98</pre></div>
99 <br>Here, <em>MyTargetMachine</em> is the name of your implemented
100 subclass of <tt><a
101 href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>,
102 <em>short_name</em> is the option that will be active following
103 <tt>-march=</tt> to select a target in llc and lli, and the last string
104 is the description of your target to appear in <tt>-help</tt>
105 listing.</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]106 </ul></li>
107<li>Implement the assembly printer for the architecture. Usually, if you have
108described the instruction set with the assembly printer generator in mind, that
109step can be almost automated.</li>
110</ul>
111
Misha Brukman4937c9d2005-05-17 02:27:30 +0000[diff] [blame]112<p>You also need to write an instruction selector for your platform. The
Misha Brukmand985a1c2005-05-17 02:33:03 +0000[diff] [blame]113recommended method is the <a
114href="CodeGenerator.html#instselect">pattern-matching instruction selector</a>,
115examples of which you can see in other targets:
116<tt>lib/Target/*/*ISelPattern.cpp</tt>. The former method for writing
117instruction selectors (<b>not</b> recommended for new targets) is evident in
118<tt>lib/Target/*/*ISelSimple.cpp</tt>, which are <tt>InstVisitor</tt>-based
119translators, generating code for an LLVM instruction at a time. Creating an
120instruction selector is perhaps the most time-consuming part of creating a
121back-end.</p>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]122
123<p>To create a JIT for your platform:</p>
124
125<ul>
126<li>Create a subclass of <tt><a
127 href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
128<li>Create a machine code emitter that will be used to emit binary code
129 directly into memory, given <tt>MachineInstr</tt>s</li>
130</ul>
131
132<p>Note that <tt>lib/target/Skeleton</tt> is a clean skeleton for a new target,
133so you might want to start with that and adapt it for your target, and if you
134are wondering how things are done, peek in the X86 or PowerPC target.</p>
135
136<p>The Skeleton target is non-functional but provides the basic building blocks
137you will need for your endeavor.</p>
138
139</div>
140
141<!-- _______________________________________________________________________ -->
142<div class="doc_subsubsection">
143 <a name="machineDetails">Implementation details</a>
144</div>
145
146<div class="doc_text">
147
148<ul>
149
150<li><p><b>TableGen register info description</b> - describe a class which
151will store the register's number in the binary encoding of the instruction
152(e.g., for JIT purposes).</p>
153
154<p>You also need to define register classes to contain these registers, such as
155the integer register class and floating-point register class, so that you can
156allocate virtual registers to instructions from these sets, and let the
157target-independent register allocator automatically choose the actual
158architected registers.</p>
159
160<div class="doc_code">
161<pre>
162// class Register is defined in Target.td
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]163<b>class</b> <em>Target</em>Reg&lt;string name&gt; : Register&lt;name&gt; {
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]164 <b>let</b> Namespace = "<em>Target</em>";
165}
166
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]167<b>class</b> IntReg&lt;<b>bits</b>&lt;5&gt; num, string name&gt; : <em>Target</em>Reg&lt;name&gt; {
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]168 <b>field</b> <b>bits</b>&lt;5&gt; Num = num;
169}
170
Chris Lattner7a2fd892004-09-18 06:28:07 +0000[diff] [blame]171<b>def</b> R0 : IntReg&lt;0, "%R0"&gt;;
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]172...
173
174// class RegisterClass is defined in Target.td
175<b>def</b> IReg : RegisterClass&lt;i64, 64, [R0, ... ]&gt;;
176</pre>
177</div>
178</li>
179
180<li><p><b>TableGen instruction info description</b> - break up instructions into
181classes, usually that's already done by the manufacturer (see instruction
182manual). Define a class for each instruction category. Define each opcode as a
183subclass of the category, with appropriate parameters such as the fixed binary
184encoding of opcodes and extended opcodes, and map the register bits to the bits
185of the instruction which they are encoded in (for the JIT). Also specify how
186the instruction should be printed so it can use the automatic assembly printer,
187e.g.:</p>
188
189<div class="doc_code">
190<pre>
191// class Instruction is defined in Target.td
192<b>class</b> Form&lt;<b>bits</b>&lt;6&gt; opcode, <b>dag</b> OL, <b>string</b> asmstr&gt; : Instruction {
193 <b>field</b> <b>bits</b>&lt;42&gt; Inst;
194
195 <b>let</b> Namespace = "<em>Target</em>";
196 <b>let</b> Inst{0-6} = opcode;
197 <b>let</b> OperandList = OL;
198 <b>let</b> AsmString = asmstr;
199}
200
201<b>def</b> ADD : Form&lt;42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB"&gt;;
202</pre>
203</div>
204</li>
205
206</ul>
207
208</div>
209
210<!-- ======================================================================= -->
211<div class="doc_subsection">
212 <a name="lang">Language backends</a>
213</div>
214
215<div class="doc_text">
216
217<p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of
218how the C backend is written.</p>
219
220</div>
221
222<!-- *********************************************************************** -->
223<div class="doc_section">
224 <a name="related">Related reading material</a>
225</div>
226<!-- *********************************************************************** -->
227
228<div class="doc_text">
229
230<ul>
231<li><a href="CodeGenerator.html">Code generator</a> -
232 describes some of the classes in code generation at a high level, but
Misha Brukmana3bfc6f2005-05-17 02:12:32 +0000[diff] [blame]233 it is not (yet) complete</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]234<li><a href="TableGenFundamentals.html">TableGen fundamentals</a> -
Misha Brukmana3bfc6f2005-05-17 02:12:32 +0000[diff] [blame]235 describes how to use TableGen to describe your target information
236 succinctly</li>
237<li><a href="HowToSubmitABug.html#codegen">Debugging code generation with
238 bugpoint</a> - shows bugpoint usage scenarios to simplify backend
239 development</li>
Misha Brukman8eb67192004-09-06 22:58:13 +0000[diff] [blame]240</ul>
241
242</div>
243
244<!-- *********************************************************************** -->
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