Chris Lattner | 1e60a91 | 2003-12-20 01:22:19 +0000 | [diff] [blame] | 1 | //===- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*- ===// |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 2 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 7 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 9 | // |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 10 | // This file contains the X86 implementation of the TargetInstrInfo class. |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | #ifndef X86INSTRUCTIONINFO_H |
| 15 | #define X86INSTRUCTIONINFO_H |
| 16 | |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 17 | #include "llvm/Target/TargetInstrInfo.h" |
Nicolas Geoffray | 52e724a | 2008-04-16 20:10:13 +0000 | [diff] [blame] | 18 | #include "X86.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 19 | #include "X86RegisterInfo.h" |
Bill Wendling | 6259d51 | 2007-12-30 03:18:58 +0000 | [diff] [blame] | 20 | #include "llvm/ADT/IndexedMap.h" |
Dan Gohman | 6f0d024 | 2008-02-10 18:45:23 +0000 | [diff] [blame] | 21 | #include "llvm/Target/TargetRegisterInfo.h" |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 22 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 23 | namespace llvm { |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 24 | class X86RegisterInfo; |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 25 | class X86TargetMachine; |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 26 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 27 | namespace X86 { |
| 28 | // X86 specific condition code. These correspond to X86_*_COND in |
| 29 | // X86InstrInfo.td. They must be kept in synch. |
| 30 | enum CondCode { |
| 31 | COND_A = 0, |
| 32 | COND_AE = 1, |
| 33 | COND_B = 2, |
| 34 | COND_BE = 3, |
| 35 | COND_E = 4, |
| 36 | COND_G = 5, |
| 37 | COND_GE = 6, |
| 38 | COND_L = 7, |
| 39 | COND_LE = 8, |
| 40 | COND_NE = 9, |
| 41 | COND_NO = 10, |
| 42 | COND_NP = 11, |
| 43 | COND_NS = 12, |
Bill Wendling | 3fafd93 | 2008-11-26 22:37:40 +0000 | [diff] [blame] | 44 | COND_NC = 13, |
| 45 | COND_O = 14, |
| 46 | COND_P = 15, |
| 47 | COND_S = 16, |
| 48 | COND_C = 17, |
Dan Gohman | 279c22e | 2008-10-21 03:29:32 +0000 | [diff] [blame] | 49 | |
| 50 | // Artificial condition codes. These are used by AnalyzeBranch |
| 51 | // to indicate a block terminated with two conditional branches to |
| 52 | // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, |
| 53 | // which can't be represented on x86 with a single condition. These |
| 54 | // are never used in MachineInstrs. |
| 55 | COND_NE_OR_P, |
| 56 | COND_NP_OR_E, |
| 57 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 58 | COND_INVALID |
| 59 | }; |
Christopher Lamb | 6634e26 | 2008-03-13 05:47:01 +0000 | [diff] [blame] | 60 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 61 | // Turn condition code into conditional branch opcode. |
| 62 | unsigned GetCondBranchFromCond(CondCode CC); |
Chris Lattner | 9cd6875 | 2006-10-21 05:52:40 +0000 | [diff] [blame] | 63 | |
| 64 | /// GetOppositeBranchCondition - Return the inverse of the specified cond, |
| 65 | /// e.g. turning COND_E to COND_NE. |
| 66 | CondCode GetOppositeBranchCondition(X86::CondCode CC); |
| 67 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 68 | } |
| 69 | |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 70 | /// X86II - This namespace holds all of the target specific flags that |
| 71 | /// instruction info tracks. |
| 72 | /// |
| 73 | namespace X86II { |
| 74 | enum { |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 75 | //===------------------------------------------------------------------===// |
| 76 | // Instruction types. These are the standard/most common forms for X86 |
| 77 | // instructions. |
| 78 | // |
| 79 | |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 80 | // PseudoFrm - This represents an instruction that is a pseudo instruction |
| 81 | // or one that has not been implemented yet. It is illegal to code generate |
| 82 | // it, but tolerated for intermediate implementation stages. |
| 83 | Pseudo = 0, |
| 84 | |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 85 | /// Raw - This form is for instructions that don't have any operands, so |
| 86 | /// they are just a fixed opcode value, like 'leave'. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 87 | RawFrm = 1, |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 88 | |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 89 | /// AddRegFrm - This form is used for instructions like 'push r32' that have |
| 90 | /// their one register operand added to their opcode. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 91 | AddRegFrm = 2, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 92 | |
| 93 | /// MRMDestReg - This form is used for instructions that use the Mod/RM byte |
| 94 | /// to specify a destination, which in this case is a register. |
| 95 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 96 | MRMDestReg = 3, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 97 | |
| 98 | /// MRMDestMem - This form is used for instructions that use the Mod/RM byte |
| 99 | /// to specify a destination, which in this case is memory. |
| 100 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 101 | MRMDestMem = 4, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 102 | |
| 103 | /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte |
| 104 | /// to specify a source, which in this case is a register. |
| 105 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 106 | MRMSrcReg = 5, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 107 | |
| 108 | /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte |
| 109 | /// to specify a source, which in this case is memory. |
| 110 | /// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 111 | MRMSrcMem = 6, |
Misha Brukman | 0e0a7a45 | 2005-04-21 23:38:14 +0000 | [diff] [blame] | 112 | |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 113 | /// MRM[0-7][rm] - These forms are used to represent instructions that use |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 114 | /// a Mod/RM byte, and use the middle field to hold extended opcode |
| 115 | /// information. In the intel manual these are represented as /0, /1, ... |
| 116 | /// |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 117 | |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 118 | // First, instructions that operate on a register r/m operand... |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 119 | MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 |
| 120 | MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 121 | |
| 122 | // Next, instructions that operate on a memory r/m operand... |
Alkis Evlogimenos | 169584e | 2004-02-27 18:55:12 +0000 | [diff] [blame] | 123 | MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, // Format /0 /1 /2 /3 |
| 124 | MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 |
Chris Lattner | 85b39f2 | 2002-11-21 17:08:49 +0000 | [diff] [blame] | 125 | |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 126 | // MRMInitReg - This form is used for instructions whose source and |
| 127 | // destinations are the same register. |
| 128 | MRMInitReg = 32, |
| 129 | |
| 130 | FormMask = 63, |
Chris Lattner | 6aab9cf | 2002-11-18 05:37:11 +0000 | [diff] [blame] | 131 | |
| 132 | //===------------------------------------------------------------------===// |
| 133 | // Actual flags... |
| 134 | |
Chris Lattner | 11e53e3 | 2002-11-21 01:32:55 +0000 | [diff] [blame] | 135 | // OpSize - Set if this instruction requires an operand size prefix (0x66), |
| 136 | // which most often indicates that the instruction operates on 16 bit data |
| 137 | // instead of 32 bit data. |
Evan Cheng | 3c55c54 | 2006-02-01 06:13:50 +0000 | [diff] [blame] | 138 | OpSize = 1 << 6, |
Brian Gaeke | 86764d7 | 2002-12-05 08:30:40 +0000 | [diff] [blame] | 139 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 140 | // AsSize - Set if this instruction requires an operand size prefix (0x67), |
| 141 | // which most often indicates that the instruction address 16 bit address |
| 142 | // instead of 32 bit address (or 32 bit address in 64 bit mode). |
| 143 | AdSize = 1 << 7, |
| 144 | |
| 145 | //===------------------------------------------------------------------===// |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 146 | // Op0Mask - There are several prefix bytes that are used to form two byte |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 147 | // opcodes. These are currently 0x0F, 0xF3, and 0xD8-0xDF. This mask is |
| 148 | // used to obtain the setting of this field. If no bits in this field is |
| 149 | // set, there is no prefix byte for obtaining a multibyte opcode. |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 150 | // |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 151 | Op0Shift = 8, |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 152 | Op0Mask = 0xF << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 153 | |
| 154 | // TB - TwoByte - Set if this instruction has a two byte opcode, which |
| 155 | // starts with a 0x0F byte before the real opcode. |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 156 | TB = 1 << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 157 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 158 | // REP - The 0xF3 prefix byte indicating repetition of the following |
| 159 | // instruction. |
| 160 | REP = 2 << Op0Shift, |
| 161 | |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 162 | // D8-DF - These escape opcodes are used by the floating point unit. These |
| 163 | // values must remain sequential. |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 164 | D8 = 3 << Op0Shift, D9 = 4 << Op0Shift, |
| 165 | DA = 5 << Op0Shift, DB = 6 << Op0Shift, |
| 166 | DC = 7 << Op0Shift, DD = 8 << Op0Shift, |
| 167 | DE = 9 << Op0Shift, DF = 10 << Op0Shift, |
Jeff Cohen | 9eb59ec | 2005-07-27 05:53:44 +0000 | [diff] [blame] | 168 | |
Nate Begeman | f63be7d | 2005-07-06 18:59:04 +0000 | [diff] [blame] | 169 | // XS, XD - These prefix codes are for single and double precision scalar |
| 170 | // floating point operations performed in the SSE registers. |
Bill Wendling | bb1ee05 | 2007-04-10 22:10:25 +0000 | [diff] [blame] | 171 | XD = 11 << Op0Shift, XS = 12 << Op0Shift, |
| 172 | |
| 173 | // T8, TA - Prefix after the 0x0F prefix. |
| 174 | T8 = 13 << Op0Shift, TA = 14 << Op0Shift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 175 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 176 | //===------------------------------------------------------------------===// |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 177 | // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. |
| 178 | // They are used to specify GPRs and SSE registers, 64-bit operand size, |
| 179 | // etc. We only cares about REX.W and REX.R bits and only the former is |
| 180 | // statically determined. |
| 181 | // |
| 182 | REXShift = 12, |
| 183 | REX_W = 1 << REXShift, |
| 184 | |
| 185 | //===------------------------------------------------------------------===// |
| 186 | // This three-bit field describes the size of an immediate operand. Zero is |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 187 | // unused so that we can tell if we forgot to set a value. |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 188 | ImmShift = 13, |
| 189 | ImmMask = 7 << ImmShift, |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 190 | Imm8 = 1 << ImmShift, |
| 191 | Imm16 = 2 << ImmShift, |
| 192 | Imm32 = 3 << ImmShift, |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 193 | Imm64 = 4 << ImmShift, |
Chris Lattner | 4c299f5 | 2002-12-25 05:09:59 +0000 | [diff] [blame] | 194 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 195 | //===------------------------------------------------------------------===// |
| 196 | // FP Instruction Classification... Zero is non-fp instruction. |
| 197 | |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 198 | // FPTypeMask - Mask for all of the FP types... |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 199 | FPTypeShift = 16, |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 200 | FPTypeMask = 7 << FPTypeShift, |
| 201 | |
Chris Lattner | 79b1373 | 2004-01-30 22:24:18 +0000 | [diff] [blame] | 202 | // NotFP - The default, set for instructions that do not use FP registers. |
| 203 | NotFP = 0 << FPTypeShift, |
| 204 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 205 | // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 206 | ZeroArgFP = 1 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 207 | |
| 208 | // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 209 | OneArgFP = 2 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 210 | |
| 211 | // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a |
| 212 | // result back to ST(0). For example, fcos, fsqrt, etc. |
| 213 | // |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 214 | OneArgFPRW = 3 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 215 | |
| 216 | // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an |
| 217 | // explicit argument, storing the result to either ST(0) or the implicit |
| 218 | // argument. For example: fadd, fsub, fmul, etc... |
Chris Lattner | 2959b6e | 2003-08-06 15:32:20 +0000 | [diff] [blame] | 219 | TwoArgFP = 4 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 220 | |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 221 | // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an |
| 222 | // explicit argument, but have no destination. Example: fucom, fucomi, ... |
| 223 | CompareFP = 5 << FPTypeShift, |
| 224 | |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 225 | // CondMovFP - "2 operand" floating point conditional move instructions. |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 226 | CondMovFP = 6 << FPTypeShift, |
Chris Lattner | 1c54a85 | 2004-03-31 22:02:13 +0000 | [diff] [blame] | 227 | |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 228 | // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. |
Chris Lattner | ab8decc | 2004-06-11 04:41:24 +0000 | [diff] [blame] | 229 | SpecialFP = 7 << FPTypeShift, |
Chris Lattner | 0c514f4 | 2003-01-13 00:49:24 +0000 | [diff] [blame] | 230 | |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 231 | // Lock prefix |
| 232 | LOCKShift = 19, |
| 233 | LOCK = 1 << LOCKShift, |
| 234 | |
Anton Korobeynikov | ef93cec | 2008-10-11 19:09:15 +0000 | [diff] [blame] | 235 | // Segment override prefixes. Currently we just need ability to address |
| 236 | // stuff in gs and fs segments. |
| 237 | SegOvrShift = 20, |
| 238 | SegOvrMask = 3 << SegOvrShift, |
| 239 | FS = 1 << SegOvrShift, |
| 240 | GS = 2 << SegOvrShift, |
| 241 | |
| 242 | // Bits 22 -> 23 are unused |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 243 | OpcodeShift = 24, |
Chris Lattner | d74ea2b | 2006-05-24 17:04:05 +0000 | [diff] [blame] | 244 | OpcodeMask = 0xFF << OpcodeShift |
Chris Lattner | 9d17740 | 2002-10-30 01:09:34 +0000 | [diff] [blame] | 245 | }; |
| 246 | } |
| 247 | |
Anton Korobeynikov | 1c4b5ea | 2008-06-28 11:07:54 +0000 | [diff] [blame] | 248 | inline static bool isScale(const MachineOperand &MO) { |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 249 | return MO.isImm() && |
Anton Korobeynikov | 1c4b5ea | 2008-06-28 11:07:54 +0000 | [diff] [blame] | 250 | (MO.getImm() == 1 || MO.getImm() == 2 || |
| 251 | MO.getImm() == 4 || MO.getImm() == 8); |
| 252 | } |
| 253 | |
| 254 | inline static bool isMem(const MachineInstr *MI, unsigned Op) { |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 255 | if (MI->getOperand(Op).isFI()) return true; |
Anton Korobeynikov | 1c4b5ea | 2008-06-28 11:07:54 +0000 | [diff] [blame] | 256 | return Op+4 <= MI->getNumOperands() && |
Dan Gohman | d735b80 | 2008-10-03 15:45:36 +0000 | [diff] [blame] | 257 | MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && |
| 258 | MI->getOperand(Op+2).isReg() && |
| 259 | (MI->getOperand(Op+3).isImm() || |
| 260 | MI->getOperand(Op+3).isGlobal() || |
| 261 | MI->getOperand(Op+3).isCPI() || |
| 262 | MI->getOperand(Op+3).isJTI()); |
Anton Korobeynikov | 1c4b5ea | 2008-06-28 11:07:54 +0000 | [diff] [blame] | 263 | } |
| 264 | |
Chris Lattner | 6410552 | 2008-01-01 01:03:04 +0000 | [diff] [blame] | 265 | class X86InstrInfo : public TargetInstrInfoImpl { |
Evan Cheng | aa3c141 | 2006-05-30 21:45:53 +0000 | [diff] [blame] | 266 | X86TargetMachine &TM; |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 267 | const X86RegisterInfo RI; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 268 | |
| 269 | /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, |
| 270 | /// RegOp2MemOpTable2 - Load / store folding opcode maps. |
| 271 | /// |
| 272 | DenseMap<unsigned*, unsigned> RegOp2MemOpTable2Addr; |
| 273 | DenseMap<unsigned*, unsigned> RegOp2MemOpTable0; |
| 274 | DenseMap<unsigned*, unsigned> RegOp2MemOpTable1; |
| 275 | DenseMap<unsigned*, unsigned> RegOp2MemOpTable2; |
| 276 | |
| 277 | /// MemOp2RegOpTable - Load / store unfolding opcode map. |
| 278 | /// |
| 279 | DenseMap<unsigned*, std::pair<unsigned, unsigned> > MemOp2RegOpTable; |
| 280 | |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 281 | public: |
Dan Gohman | 950a4c4 | 2008-03-25 22:06:05 +0000 | [diff] [blame] | 282 | explicit X86InstrInfo(X86TargetMachine &tm); |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 283 | |
Chris Lattner | 3501fea | 2003-01-14 22:00:31 +0000 | [diff] [blame] | 284 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 285 | /// such, whenever a client has an instance of instruction info, it should |
| 286 | /// always be able to get register info as well (through this method). |
| 287 | /// |
Dan Gohman | c9f5f3f | 2008-05-14 01:58:56 +0000 | [diff] [blame] | 288 | virtual const X86RegisterInfo &getRegisterInfo() const { return RI; } |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 289 | |
Alkis Evlogimenos | 5e30002 | 2003-12-28 17:35:08 +0000 | [diff] [blame] | 290 | // Return true if the instruction is a register to register move and |
| 291 | // leave the source and dest operands in the passed parameters. |
| 292 | // |
Chris Lattner | 4083960 | 2006-02-02 20:12:32 +0000 | [diff] [blame] | 293 | bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, |
| 294 | unsigned& destReg) const; |
Dan Gohman | cbad42c | 2008-11-18 19:49:32 +0000 | [diff] [blame] | 295 | unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; |
| 296 | unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; |
Evan Cheng | ca1267c | 2008-03-31 20:40:39 +0000 | [diff] [blame] | 297 | |
Bill Wendling | 9f8fea3 | 2008-05-12 20:54:26 +0000 | [diff] [blame] | 298 | bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; |
Evan Cheng | ca1267c | 2008-03-31 20:40:39 +0000 | [diff] [blame] | 299 | void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, |
| 300 | unsigned DestReg, const MachineInstr *Orig) const; |
| 301 | |
Dan Gohman | cbad42c | 2008-11-18 19:49:32 +0000 | [diff] [blame] | 302 | bool isInvariantLoad(const MachineInstr *MI) const; |
Bill Wendling | 627c00b | 2007-12-17 23:07:56 +0000 | [diff] [blame] | 303 | |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 304 | /// convertToThreeAddress - This method must be implemented by targets that |
| 305 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
| 306 | /// may be able to convert a two-address instruction into a true |
| 307 | /// three-address instruction on demand. This allows the X86 target (for |
| 308 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
| 309 | /// would require register copies due to two-addressness. |
| 310 | /// |
| 311 | /// This method returns a null pointer if the transformation cannot be |
| 312 | /// performed, otherwise it returns the new instruction. |
| 313 | /// |
Evan Cheng | ba59a1e | 2006-12-01 21:52:58 +0000 | [diff] [blame] | 314 | virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, |
| 315 | MachineBasicBlock::iterator &MBBI, |
Owen Anderson | f660c17 | 2008-07-02 23:41:07 +0000 | [diff] [blame] | 316 | LiveVariables *LV) const; |
Chris Lattner | bcea4d6 | 2005-01-02 02:37:07 +0000 | [diff] [blame] | 317 | |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 318 | /// commuteInstruction - We have a few instructions that must be hacked on to |
| 319 | /// commute them. |
| 320 | /// |
Evan Cheng | 58dcb0e | 2008-06-16 07:33:11 +0000 | [diff] [blame] | 321 | virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 322 | |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 323 | // Branch analysis. |
Dale Johannesen | 318093b | 2007-06-14 22:03:45 +0000 | [diff] [blame] | 324 | virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const; |
Chris Lattner | 7fbe972 | 2006-10-20 17:42:20 +0000 | [diff] [blame] | 325 | virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
| 326 | MachineBasicBlock *&FBB, |
Owen Anderson | 44eb65c | 2008-08-14 22:49:33 +0000 | [diff] [blame] | 327 | SmallVectorImpl<MachineOperand> &Cond) const; |
Evan Cheng | 6ae3626 | 2007-05-18 00:18:17 +0000 | [diff] [blame] | 328 | virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; |
| 329 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
| 330 | MachineBasicBlock *FBB, |
Owen Anderson | 44eb65c | 2008-08-14 22:49:33 +0000 | [diff] [blame] | 331 | const SmallVectorImpl<MachineOperand> &Cond) const; |
Owen Anderson | 940f83e | 2008-08-26 18:03:31 +0000 | [diff] [blame] | 332 | virtual bool copyRegToReg(MachineBasicBlock &MBB, |
Owen Anderson | d10fd97 | 2007-12-31 06:32:00 +0000 | [diff] [blame] | 333 | MachineBasicBlock::iterator MI, |
| 334 | unsigned DestReg, unsigned SrcReg, |
| 335 | const TargetRegisterClass *DestRC, |
| 336 | const TargetRegisterClass *SrcRC) const; |
Owen Anderson | f6372aa | 2008-01-01 21:11:32 +0000 | [diff] [blame] | 337 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
| 338 | MachineBasicBlock::iterator MI, |
| 339 | unsigned SrcReg, bool isKill, int FrameIndex, |
| 340 | const TargetRegisterClass *RC) const; |
| 341 | |
| 342 | virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, |
| 343 | SmallVectorImpl<MachineOperand> &Addr, |
| 344 | const TargetRegisterClass *RC, |
| 345 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
| 346 | |
| 347 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
| 348 | MachineBasicBlock::iterator MI, |
| 349 | unsigned DestReg, int FrameIndex, |
| 350 | const TargetRegisterClass *RC) const; |
| 351 | |
| 352 | virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, |
| 353 | SmallVectorImpl<MachineOperand> &Addr, |
| 354 | const TargetRegisterClass *RC, |
| 355 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
Owen Anderson | d94b6a1 | 2008-01-04 23:57:37 +0000 | [diff] [blame] | 356 | |
| 357 | virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 358 | MachineBasicBlock::iterator MI, |
| 359 | const std::vector<CalleeSavedInfo> &CSI) const; |
| 360 | |
| 361 | virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, |
| 362 | MachineBasicBlock::iterator MI, |
| 363 | const std::vector<CalleeSavedInfo> &CSI) const; |
| 364 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 365 | /// foldMemoryOperand - If this target supports it, fold a load or store of |
| 366 | /// the specified stack slot into the specified machine instruction for the |
| 367 | /// specified operand(s). If this is possible, the target should perform the |
| 368 | /// folding and return true, otherwise it should return false. If it folds |
| 369 | /// the instruction, it is likely that the MachineInstruction the iterator |
| 370 | /// references has been changed. |
Dan Gohman | c54baa2 | 2008-12-03 18:43:12 +0000 | [diff] [blame^] | 371 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 372 | MachineInstr* MI, |
| 373 | const SmallVectorImpl<unsigned> &Ops, |
| 374 | int FrameIndex) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 375 | |
| 376 | /// foldMemoryOperand - Same as the previous version except it allows folding |
| 377 | /// of any load and store from / to any address, not just from a specific |
| 378 | /// stack slot. |
Dan Gohman | c54baa2 | 2008-12-03 18:43:12 +0000 | [diff] [blame^] | 379 | virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 380 | MachineInstr* MI, |
| 381 | const SmallVectorImpl<unsigned> &Ops, |
| 382 | MachineInstr* LoadMI) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 383 | |
| 384 | /// canFoldMemoryOperand - Returns true if the specified load / store is |
| 385 | /// folding is possible. |
Dan Gohman | 8e8b8a2 | 2008-10-16 01:49:15 +0000 | [diff] [blame] | 386 | virtual bool canFoldMemoryOperand(const MachineInstr*, |
| 387 | const SmallVectorImpl<unsigned> &) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 388 | |
| 389 | /// unfoldMemoryOperand - Separate a single instruction which folded a load or |
| 390 | /// a store or a load and a store into two or more instruction. If this is |
| 391 | /// possible, returns true as well as the new instructions by reference. |
| 392 | virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, |
| 393 | unsigned Reg, bool UnfoldLoad, bool UnfoldStore, |
| 394 | SmallVectorImpl<MachineInstr*> &NewMIs) const; |
| 395 | |
| 396 | virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
| 397 | SmallVectorImpl<SDNode*> &NewNodes) const; |
| 398 | |
| 399 | /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new |
| 400 | /// instruction after load / store are unfolded from an instruction of the |
| 401 | /// specified opcode. It returns zero if the specified unfolding is not |
| 402 | /// possible. |
| 403 | virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, |
| 404 | bool UnfoldLoad, bool UnfoldStore) const; |
| 405 | |
Dan Gohman | 8e8b8a2 | 2008-10-16 01:49:15 +0000 | [diff] [blame] | 406 | virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const; |
Owen Anderson | 44eb65c | 2008-08-14 22:49:33 +0000 | [diff] [blame] | 407 | virtual |
| 408 | bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; |
Chris Lattner | 41e431b | 2005-01-19 07:11:01 +0000 | [diff] [blame] | 409 | |
Evan Cheng | 2306628 | 2008-10-27 07:14:50 +0000 | [diff] [blame] | 410 | /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation |
| 411 | /// live interval splitting pass should ignore barriers of the specified |
| 412 | /// register class. |
| 413 | bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const; |
| 414 | |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 415 | const TargetRegisterClass *getPointerRegClass() const; |
| 416 | |
Chris Lattner | f21dfcd | 2002-11-18 06:56:24 +0000 | [diff] [blame] | 417 | // getBaseOpcodeFor - This function returns the "base" X86 opcode for the |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 418 | // specified machine instruction. |
Chris Lattner | f21dfcd | 2002-11-18 06:56:24 +0000 | [diff] [blame] | 419 | // |
Chris Lattner | 749c6f6 | 2008-01-07 07:27:27 +0000 | [diff] [blame] | 420 | unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const { |
Evan Cheng | 19f2ffc | 2006-12-05 04:01:03 +0000 | [diff] [blame] | 421 | return TID->TSFlags >> X86II::OpcodeShift; |
Chris Lattner | 4d18d5c | 2003-08-03 21:56:22 +0000 | [diff] [blame] | 422 | } |
Chris Lattner | cc8cd0c | 2008-01-07 02:48:55 +0000 | [diff] [blame] | 423 | unsigned char getBaseOpcodeFor(unsigned Opcode) const { |
Duncan Sands | ee46574 | 2007-08-29 19:01:20 +0000 | [diff] [blame] | 424 | return getBaseOpcodeFor(&get(Opcode)); |
| 425 | } |
Nicolas Geoffray | 52e724a | 2008-04-16 20:10:13 +0000 | [diff] [blame] | 426 | |
| 427 | static bool isX86_64NonExtLowByteReg(unsigned reg) { |
| 428 | return (reg == X86::SPL || reg == X86::BPL || |
| 429 | reg == X86::SIL || reg == X86::DIL); |
| 430 | } |
| 431 | |
| 432 | static unsigned sizeOfImm(const TargetInstrDesc *Desc); |
Nicolas Geoffray | 52e724a | 2008-04-16 20:10:13 +0000 | [diff] [blame] | 433 | static bool isX86_64ExtendedReg(const MachineOperand &MO); |
| 434 | static unsigned determineREX(const MachineInstr &MI); |
| 435 | |
| 436 | /// GetInstSize - Returns the size of the specified MachineInstr. |
| 437 | /// |
| 438 | virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const; |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 439 | |
Dan Gohman | 57c3dac | 2008-09-30 00:58:23 +0000 | [diff] [blame] | 440 | /// getGlobalBaseReg - Return a virtual register initialized with the |
| 441 | /// the global base register value. Output instructions required to |
| 442 | /// initialize the register in the function entry block, if necessary. |
Dan Gohman | 8b74696 | 2008-09-23 18:22:58 +0000 | [diff] [blame] | 443 | /// |
Dan Gohman | 57c3dac | 2008-09-30 00:58:23 +0000 | [diff] [blame] | 444 | unsigned getGlobalBaseReg(MachineFunction *MF) const; |
Dan Gohman | 8b74696 | 2008-09-23 18:22:58 +0000 | [diff] [blame] | 445 | |
Owen Anderson | 43dbe05 | 2008-01-07 01:35:02 +0000 | [diff] [blame] | 446 | private: |
Dan Gohman | c54baa2 | 2008-12-03 18:43:12 +0000 | [diff] [blame^] | 447 | MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, |
| 448 | MachineInstr* MI, |
| 449 | unsigned OpNum, |
| 450 | const SmallVector<MachineOperand,4> &MOs) const; |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 451 | }; |
| 452 | |
Brian Gaeke | d0fde30 | 2003-11-11 22:41:34 +0000 | [diff] [blame] | 453 | } // End llvm namespace |
| 454 | |
Chris Lattner | 7261408 | 2002-10-25 22:55:53 +0000 | [diff] [blame] | 455 | #endif |