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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 / . / lib / Target / PowerPC / PPC.td
blob: 367f9ccd27caf9d773e5ddd6be76ab5eb27c81a2 [file] [log] [blame]
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]1//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This is the top level entry point for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing.
15//
Evan Cheng027fdbe2008-11-24 07:34:46 +0000[diff] [blame]16include "llvm/Target/Target.td"
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]17
18//===----------------------------------------------------------------------===//
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]19// PowerPC Subtarget features.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]20//
21
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]22//===----------------------------------------------------------------------===//
23// CPU Directives //
24//===----------------------------------------------------------------------===//
25
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame^]26def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]27def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
28def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
29def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
30def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
31def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
32def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
33def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
34def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
35def Directive32 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
36def Directive64 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
37
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]38def Feature64Bit : SubtargetFeature<"64bit","Has64BitSupport", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]39 "Enable 64-bit instructions">;
Chris Lattnera7a58542006-06-16 17:34:12 +0000[diff] [blame]40def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
41 "Enable 64-bit registers usage for ppc32 [beta]">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]42def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]43 "Enable Altivec instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]44def FeatureGPUL : SubtargetFeature<"gpul","IsGigaProcessor", "true",
Chris Lattner2e1f8232005-10-23 05:28:51 +0000[diff] [blame]45 "Enable GPUL instructions">;
Evan Cheng19c95502006-01-27 08:09:42 +0000[diff] [blame]46def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]47 "Enable the fsqrt instruction">;
Chris Lattnerbf751e22006-02-28 07:08:22 +0000[diff] [blame]48def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
Hal Finkel8ee53e22011-10-14 18:54:13 +0000[diff] [blame]49 "Enable the stfiwx instruction">;
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame^]50def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
51 "Enable Book E instructions">;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]52
53//===----------------------------------------------------------------------===//
Chris Lattnerc8d28892005-10-23 22:08:13 +0000[diff] [blame]54// Register File Description
55//===----------------------------------------------------------------------===//
56
57include "PPCRegisterInfo.td"
58include "PPCSchedule.td"
59include "PPCInstrInfo.td"
60
61//===----------------------------------------------------------------------===//
62// PowerPC processors supported.
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]63//
64
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]65def : Processor<"generic", G3Itineraries, [Directive32]>;
Hal Finkelc6d08f12011-10-17 04:03:49 +0000[diff] [blame^]66def : Processor<"440", PPC440Itineraries, [Directive440, FeatureBookE]>;
67def : Processor<"450", PPC440Itineraries, [Directive440, FeatureBookE]>;
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]68def : Processor<"601", G3Itineraries, [Directive601]>;
69def : Processor<"602", G3Itineraries, [Directive602]>;
70def : Processor<"603", G3Itineraries, [Directive603]>;
71def : Processor<"603e", G3Itineraries, [Directive603]>;
72def : Processor<"603ev", G3Itineraries, [Directive603]>;
73def : Processor<"604", G3Itineraries, [Directive604]>;
74def : Processor<"604e", G3Itineraries, [Directive604]>;
75def : Processor<"620", G3Itineraries, [Directive620]>;
76def : Processor<"g3", G3Itineraries, [Directive7400]>;
77def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
78def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
79def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
80def : Processor<"g4+", G4PlusItineraries, [Directive750, FeatureAltivec]>;
81def : Processor<"750", G4Itineraries, [Directive750, FeatureAltivec]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]82def : Processor<"970", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]83 [Directive970, FeatureAltivec,
84 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]85 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]86def : Processor<"g5", G5Itineraries,
Jim Laskeyc35010d2006-12-12 20:57:08 +0000[diff] [blame]87 [Directive970, FeatureAltivec,
88 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
89 Feature64Bit /*, Feature64BitRegs */]>;
90def : Processor<"ppc", G3Itineraries, [Directive32]>;
91def : Processor<"ppc64", G5Itineraries,
92 [Directive64, FeatureAltivec,
93 FeatureGPUL, FeatureFSqrt, FeatureSTFIWX,
Jim Laskey5476b9b2005-10-22 08:04:24 +0000[diff] [blame]94 Feature64Bit /*, Feature64BitRegs */]>;
Jim Laskey53842142005-10-19 19:51:16 +0000[diff] [blame]95
96
Chris Lattnerb9a7bea2007-03-06 00:59:59 +0000[diff] [blame]97//===----------------------------------------------------------------------===//
98// Calling Conventions
99//===----------------------------------------------------------------------===//
100
101include "PPCCallingConv.td"
102
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]103def PPCInstrInfo : InstrInfo {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]104 let isLittleEndianEncoding = 1;
105}
106
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]107def PPCAsmWriter : AsmWriter {
108 string AsmWriterClassName = "InstPrinter";
109 bit isMCAsmWriter = 1;
110}
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]111
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]112def PPC : Target {
Chris Lattner88d211f2006-03-12 09:13:49 +0000[diff] [blame]113 // Information about the instructions.
114 let InstructionSet = PPCInstrInfo;
Chris Lattner84a04ad2010-11-15 03:53:53 +0000[diff] [blame]115
116 let AssemblyWriters = [PPCAsmWriter];
Chris Lattner4c7b43b2005-10-14 23:37:35 +0000[diff] [blame]117}