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Chris Lattner64105522008-01-01 01:03:04 +00001//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TargetInstrInfoImpl class, it just provides default
11// implementations of various methods.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/Target/TargetInstrInfo.h"
Evan Cheng86050dc2010-06-18 23:09:54 +000016#include "llvm/Target/TargetLowering.h"
Dan Gohmana70dca12009-10-09 23:27:56 +000017#include "llvm/Target/TargetMachine.h"
18#include "llvm/Target/TargetRegisterInfo.h"
Owen Anderson44eb65c2008-08-14 22:49:33 +000019#include "llvm/ADT/SmallVector.h"
Dan Gohmanc54baa22008-12-03 18:43:12 +000020#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner64105522008-01-01 01:03:04 +000021#include "llvm/CodeGen/MachineInstr.h"
Evan Cheng58dcb0e2008-06-16 07:33:11 +000022#include "llvm/CodeGen/MachineInstrBuilder.h"
Dan Gohmanc76909a2009-09-25 20:36:54 +000023#include "llvm/CodeGen/MachineMemOperand.h"
Dan Gohmana70dca12009-10-09 23:27:56 +000024#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick6b120722010-12-08 20:04:29 +000025#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
Dan Gohmanc54baa22008-12-03 18:43:12 +000026#include "llvm/CodeGen/PseudoSourceValue.h"
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +000027#include "llvm/Support/Debug.h"
Evan Cheng34c75092009-07-10 23:26:12 +000028#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/raw_ostream.h"
Chris Lattner64105522008-01-01 01:03:04 +000030using namespace llvm;
31
Evan Cheng4d54e5b2010-06-22 01:18:16 +000032/// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
33/// after it, replacing it with an unconditional branch to NewDest.
Evan Cheng86050dc2010-06-18 23:09:54 +000034void
35TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
36 MachineBasicBlock *NewDest) const {
37 MachineBasicBlock *MBB = Tail->getParent();
38
39 // Remove all the old successors of MBB from the CFG.
40 while (!MBB->succ_empty())
41 MBB->removeSuccessor(MBB->succ_begin());
42
43 // Remove all the dead instructions from the end of MBB.
44 MBB->erase(Tail, MBB->end());
45
46 // If MBB isn't immediately before MBB, insert a branch to it.
47 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
48 InsertBranch(*MBB, NewDest, 0, SmallVector<MachineOperand, 0>(),
49 Tail->getDebugLoc());
50 MBB->addSuccessor(NewDest);
51}
52
Chris Lattner64105522008-01-01 01:03:04 +000053// commuteInstruction - The default implementation of this method just exchanges
Evan Cheng34c75092009-07-10 23:26:12 +000054// the two operands returned by findCommutedOpIndices.
Evan Cheng58dcb0e2008-06-16 07:33:11 +000055MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
56 bool NewMI) const {
Evan Cheng498c2902009-07-01 08:29:08 +000057 const TargetInstrDesc &TID = MI->getDesc();
58 bool HasDef = TID.getNumDefs();
Evan Cheng34c75092009-07-10 23:26:12 +000059 if (HasDef && !MI->getOperand(0).isReg())
60 // No idea how to commute this instruction. Target should implement its own.
61 return 0;
62 unsigned Idx1, Idx2;
63 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
64 std::string msg;
65 raw_string_ostream Msg(msg);
66 Msg << "Don't know how to commute: " << *MI;
Chris Lattner75361b62010-04-07 22:58:41 +000067 report_fatal_error(Msg.str());
Evan Cheng34c75092009-07-10 23:26:12 +000068 }
Evan Cheng498c2902009-07-01 08:29:08 +000069
70 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
Chris Lattner64105522008-01-01 01:03:04 +000071 "This only knows how to commute register operands so far");
Evan Cheng498c2902009-07-01 08:29:08 +000072 unsigned Reg1 = MI->getOperand(Idx1).getReg();
73 unsigned Reg2 = MI->getOperand(Idx2).getReg();
74 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
75 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
Evan Cheng58dcb0e2008-06-16 07:33:11 +000076 bool ChangeReg0 = false;
Evan Cheng498c2902009-07-01 08:29:08 +000077 if (HasDef && MI->getOperand(0).getReg() == Reg1) {
Evan Chenga4d16a12008-02-13 02:46:49 +000078 // Must be two address instruction!
79 assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
80 "Expecting a two-address instruction!");
81 Reg2IsKill = false;
Evan Cheng58dcb0e2008-06-16 07:33:11 +000082 ChangeReg0 = true;
Evan Chenga4d16a12008-02-13 02:46:49 +000083 }
Evan Cheng58dcb0e2008-06-16 07:33:11 +000084
85 if (NewMI) {
86 // Create a new instruction.
Evan Cheng498c2902009-07-01 08:29:08 +000087 unsigned Reg0 = HasDef
88 ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
89 bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
Dan Gohman8e5f2c62008-07-07 23:14:23 +000090 MachineFunction &MF = *MI->getParent()->getParent();
Evan Cheng498c2902009-07-01 08:29:08 +000091 if (HasDef)
92 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
93 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
94 .addReg(Reg2, getKillRegState(Reg2IsKill))
95 .addReg(Reg1, getKillRegState(Reg2IsKill));
96 else
97 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
98 .addReg(Reg2, getKillRegState(Reg2IsKill))
99 .addReg(Reg1, getKillRegState(Reg2IsKill));
Evan Cheng58dcb0e2008-06-16 07:33:11 +0000100 }
101
102 if (ChangeReg0)
103 MI->getOperand(0).setReg(Reg2);
Evan Cheng498c2902009-07-01 08:29:08 +0000104 MI->getOperand(Idx2).setReg(Reg1);
105 MI->getOperand(Idx1).setReg(Reg2);
106 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
107 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
Chris Lattner64105522008-01-01 01:03:04 +0000108 return MI;
109}
110
Evan Cheng261ce1d2009-07-10 19:15:51 +0000111/// findCommutedOpIndices - If specified MI is commutable, return the two
112/// operand indices that would swap value. Return true if the instruction
113/// is not in a form which this routine understands.
114bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
115 unsigned &SrcOpIdx1,
116 unsigned &SrcOpIdx2) const {
Evan Cheng498c2902009-07-01 08:29:08 +0000117 const TargetInstrDesc &TID = MI->getDesc();
Evan Cheng261ce1d2009-07-10 19:15:51 +0000118 if (!TID.isCommutable())
Evan Cheng498c2902009-07-01 08:29:08 +0000119 return false;
Evan Cheng261ce1d2009-07-10 19:15:51 +0000120 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
121 // is not true, then the target must implement this.
122 SrcOpIdx1 = TID.getNumDefs();
123 SrcOpIdx2 = SrcOpIdx1 + 1;
124 if (!MI->getOperand(SrcOpIdx1).isReg() ||
125 !MI->getOperand(SrcOpIdx2).isReg())
126 // No idea.
127 return false;
128 return true;
Evan Chengf20db152008-02-15 18:21:33 +0000129}
130
131
Chris Lattner64105522008-01-01 01:03:04 +0000132bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
Owen Anderson44eb65c2008-08-14 22:49:33 +0000133 const SmallVectorImpl<MachineOperand> &Pred) const {
Chris Lattner64105522008-01-01 01:03:04 +0000134 bool MadeChange = false;
Chris Lattner749c6f62008-01-07 07:27:27 +0000135 const TargetInstrDesc &TID = MI->getDesc();
136 if (!TID.isPredicable())
137 return false;
Andrew Trick6b120722010-12-08 20:04:29 +0000138
Chris Lattner749c6f62008-01-07 07:27:27 +0000139 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
140 if (TID.OpInfo[i].isPredicate()) {
141 MachineOperand &MO = MI->getOperand(i);
Dan Gohmand735b802008-10-03 15:45:36 +0000142 if (MO.isReg()) {
Chris Lattner749c6f62008-01-07 07:27:27 +0000143 MO.setReg(Pred[j].getReg());
144 MadeChange = true;
Dan Gohmand735b802008-10-03 15:45:36 +0000145 } else if (MO.isImm()) {
Chris Lattner749c6f62008-01-07 07:27:27 +0000146 MO.setImm(Pred[j].getImm());
147 MadeChange = true;
Dan Gohmand735b802008-10-03 15:45:36 +0000148 } else if (MO.isMBB()) {
Chris Lattner749c6f62008-01-07 07:27:27 +0000149 MO.setMBB(Pred[j].getMBB());
150 MadeChange = true;
Chris Lattner64105522008-01-01 01:03:04 +0000151 }
Chris Lattner749c6f62008-01-07 07:27:27 +0000152 ++j;
Chris Lattner64105522008-01-01 01:03:04 +0000153 }
154 }
155 return MadeChange;
156}
Evan Chengca1267c2008-03-31 20:40:39 +0000157
158void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
159 MachineBasicBlock::iterator I,
160 unsigned DestReg,
Evan Cheng37844532009-07-16 09:20:10 +0000161 unsigned SubIdx,
Evan Chengd57cdd52009-11-14 02:55:43 +0000162 const MachineInstr *Orig,
Jakob Stoklund Olesen9edf7de2010-06-02 22:47:25 +0000163 const TargetRegisterInfo &TRI) const {
Dan Gohman8e5f2c62008-07-07 23:14:23 +0000164 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Jakob Stoklund Olesen9edf7de2010-06-02 22:47:25 +0000165 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chengca1267c2008-03-31 20:40:39 +0000166 MBB.insert(I, MI);
167}
168
Evan Cheng9fe20092011-01-20 08:34:58 +0000169bool
170TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
171 const MachineInstr *MI1,
172 const MachineRegisterInfo *MRI) const {
Evan Cheng506049f2010-03-03 01:44:33 +0000173 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
174}
175
Jakob Stoklund Olesen30ac0462010-01-06 23:47:07 +0000176MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
177 MachineFunction &MF) const {
178 assert(!Orig->getDesc().isNotDuplicable() &&
179 "Instruction cannot be duplicated");
180 return MF.CloneMachineInstr(Orig);
181}
182
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000183// If the COPY instruction in MI can be folded to a stack operation, return
184// the register class to use.
185static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
186 unsigned FoldIdx) {
187 assert(MI->isCopy() && "MI must be a COPY instruction");
188 if (MI->getNumOperands() != 2)
189 return 0;
190 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
191
192 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
193 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
194
195 if (FoldOp.getSubReg() || LiveOp.getSubReg())
196 return 0;
197
198 unsigned FoldReg = FoldOp.getReg();
199 unsigned LiveReg = LiveOp.getReg();
200
201 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
202 "Cannot fold physregs");
203
204 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
205 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
206
207 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
208 return RC->contains(LiveOp.getReg()) ? RC : 0;
209
210 const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg);
211 if (RC == LiveRC || RC->hasSubClass(LiveRC))
212 return RC;
213
214 // FIXME: Allow folding when register classes are memory compatible.
215 return 0;
216}
217
218bool TargetInstrInfoImpl::
219canFoldMemoryOperand(const MachineInstr *MI,
220 const SmallVectorImpl<unsigned> &Ops) const {
221 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
222}
223
Dan Gohmanc54baa22008-12-03 18:43:12 +0000224/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
225/// slot into the specified machine instruction for the specified operand(s).
226/// If this is possible, a new instruction is returned with the specified
227/// operand folded, otherwise NULL is returned. The client is responsible for
228/// removing the old instruction and adding the new one in the instruction
229/// stream.
230MachineInstr*
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000231TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
Dan Gohmanc54baa22008-12-03 18:43:12 +0000232 const SmallVectorImpl<unsigned> &Ops,
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000233 int FI) const {
Dan Gohmanc54baa22008-12-03 18:43:12 +0000234 unsigned Flags = 0;
235 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
236 if (MI->getOperand(Ops[i]).isDef())
237 Flags |= MachineMemOperand::MOStore;
238 else
239 Flags |= MachineMemOperand::MOLoad;
240
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000241 MachineBasicBlock *MBB = MI->getParent();
242 assert(MBB && "foldMemoryOperand needs an inserted instruction");
243 MachineFunction &MF = *MBB->getParent();
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000244
Dan Gohmanc54baa22008-12-03 18:43:12 +0000245 // Ask the target to do the actual folding.
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000246 if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
247 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
248 assert((!(Flags & MachineMemOperand::MOStore) ||
249 NewMI->getDesc().mayStore()) &&
250 "Folded a def to a non-store!");
251 assert((!(Flags & MachineMemOperand::MOLoad) ||
252 NewMI->getDesc().mayLoad()) &&
253 "Folded a use to a non-load!");
254 const MachineFrameInfo &MFI = *MF.getFrameInfo();
255 assert(MFI.getObjectOffset(FI) != -1);
256 MachineMemOperand *MMO =
Chris Lattner93a95ae2010-09-21 04:46:39 +0000257 MF.getMachineMemOperand(
258 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
259 Flags, MFI.getObjectSize(FI),
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000260 MFI.getObjectAlignment(FI));
261 NewMI->addMemOperand(MF, MMO);
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000262
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000263 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000264 return MBB->insert(MI, NewMI);
Jakob Stoklund Olesen1f323402010-07-09 20:43:13 +0000265 }
266
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000267 // Straight COPY may fold as load/store.
268 if (!MI->isCopy() || Ops.size() != 1)
269 return 0;
Dan Gohmanc54baa22008-12-03 18:43:12 +0000270
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000271 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
272 if (!RC)
273 return 0;
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000274
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000275 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
276 MachineBasicBlock::iterator Pos = MI;
277 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
Dan Gohmanc54baa22008-12-03 18:43:12 +0000278
Jakob Stoklund Olesen9fac4152010-07-13 00:23:30 +0000279 if (Flags == MachineMemOperand::MOStore)
280 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
281 else
282 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
283 return --Pos;
Dan Gohmanc54baa22008-12-03 18:43:12 +0000284}
285
286/// foldMemoryOperand - Same as the previous version except it allows folding
287/// of any load and store from / to any address, not just from a specific
288/// stack slot.
289MachineInstr*
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000290TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
Dan Gohmanc54baa22008-12-03 18:43:12 +0000291 const SmallVectorImpl<unsigned> &Ops,
292 MachineInstr* LoadMI) const {
293 assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
294#ifndef NDEBUG
295 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
296 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
297#endif
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000298 MachineBasicBlock &MBB = *MI->getParent();
299 MachineFunction &MF = *MBB.getParent();
Dan Gohmanc54baa22008-12-03 18:43:12 +0000300
301 // Ask the target to do the actual folding.
302 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
303 if (!NewMI) return 0;
304
Jakob Stoklund Olesene05442d2010-07-09 17:29:08 +0000305 NewMI = MBB.insert(MI, NewMI);
306
Dan Gohmanc54baa22008-12-03 18:43:12 +0000307 // Copy the memoperands from the load to the folded instruction.
Dan Gohmanc76909a2009-09-25 20:36:54 +0000308 NewMI->setMemRefs(LoadMI->memoperands_begin(),
309 LoadMI->memoperands_end());
Dan Gohmanc54baa22008-12-03 18:43:12 +0000310
311 return NewMI;
312}
Dan Gohmana70dca12009-10-09 23:27:56 +0000313
Evan Cheng44acc242010-06-12 00:11:53 +0000314bool TargetInstrInfo::
315isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
316 AliasAnalysis *AA) const {
Dan Gohmana70dca12009-10-09 23:27:56 +0000317 const MachineFunction &MF = *MI->getParent()->getParent();
318 const MachineRegisterInfo &MRI = MF.getRegInfo();
319 const TargetMachine &TM = MF.getTarget();
320 const TargetInstrInfo &TII = *TM.getInstrInfo();
321 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
322
323 // A load from a fixed stack slot can be rematerialized. This may be
324 // redundant with subsequent checks, but it's target-independent,
325 // simple, and a common case.
326 int FrameIdx = 0;
327 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
328 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
329 return true;
330
331 const TargetInstrDesc &TID = MI->getDesc();
332
333 // Avoid instructions obviously unsafe for remat.
Evan Chengc36b7062011-01-07 23:50:32 +0000334 if (TID.isNotDuplicable() || TID.mayStore() ||
335 MI->hasUnmodeledSideEffects())
336 return false;
337
338 // Don't remat inline asm. We have no idea how expensive it is
339 // even if it's side effect free.
340 if (MI->isInlineAsm())
Dan Gohmana70dca12009-10-09 23:27:56 +0000341 return false;
342
343 // Avoid instructions which load from potentially varying memory.
344 if (TID.mayLoad() && !MI->isInvariantLoad(AA))
345 return false;
346
347 // If any of the registers accessed are non-constant, conservatively assume
348 // the instruction is not rematerializable.
349 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
350 const MachineOperand &MO = MI->getOperand(i);
351 if (!MO.isReg()) continue;
352 unsigned Reg = MO.getReg();
353 if (Reg == 0)
354 continue;
355
356 // Check for a well-behaved physical register.
357 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
358 if (MO.isUse()) {
359 // If the physreg has no defs anywhere, it's just an ambient register
360 // and we can freely move its uses. Alternatively, if it's allocatable,
361 // it could get allocated to something with a def during allocation.
362 if (!MRI.def_empty(Reg))
363 return false;
364 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
365 if (AllocatableRegs.test(Reg))
366 return false;
367 // Check for a def among the register's aliases too.
368 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
369 unsigned AliasReg = *Alias;
370 if (!MRI.def_empty(AliasReg))
371 return false;
372 if (AllocatableRegs.test(AliasReg))
373 return false;
374 }
375 } else {
376 // A physreg def. We can't remat it.
377 return false;
378 }
379 continue;
380 }
381
382 // Only allow one virtual-register def, and that in the first operand.
383 if (MO.isDef() != (i == 0))
384 return false;
385
386 // For the def, it should be the only def of that register.
Chris Lattner7896c9f2009-12-03 00:50:42 +0000387 if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
Dan Gohmana70dca12009-10-09 23:27:56 +0000388 MRI.isLiveIn(Reg)))
389 return false;
390
391 // Don't allow any virtual-register uses. Rematting an instruction with
392 // virtual register uses would length the live ranges of the uses, which
393 // is not necessarily a good idea, certainly not "trivial".
394 if (MO.isUse())
395 return false;
396 }
397
398 // Everything checked out.
399 return true;
400}
Evan Cheng774bc882010-06-14 21:06:53 +0000401
Evan Cheng86050dc2010-06-18 23:09:54 +0000402/// isSchedulingBoundary - Test if the given instruction should be
403/// considered a scheduling boundary. This primarily includes labels
404/// and terminators.
405bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
406 const MachineBasicBlock *MBB,
407 const MachineFunction &MF) const{
408 // Terminators and labels can't be scheduled around.
409 if (MI->getDesc().isTerminator() || MI->isLabel())
410 return true;
411
412 // Don't attempt to schedule around any instruction that defines
413 // a stack-oriented pointer, as it's unlikely to be profitable. This
414 // saves compile time, because it doesn't require every single
415 // stack slot reference to depend on the instruction that does the
416 // modification.
417 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
418 if (MI->definesRegister(TLI.getStackPointerRegisterToSaveRestore()))
419 return true;
420
421 return false;
422}
423
Andrew Trick2da8bc82010-12-24 05:03:26 +0000424// Default implementation of CreateTargetPreRAHazardRecognizer.
425ScheduleHazardRecognizer *TargetInstrInfoImpl::
426CreateTargetHazardRecognizer(const TargetMachine *TM,
427 const ScheduleDAG *DAG) const {
428 // Dummy hazard recognizer allows all instructions to issue.
429 return new ScheduleHazardRecognizer();
430}
431
Evan Cheng774bc882010-06-14 21:06:53 +0000432// Default implementation of CreateTargetPostRAHazardRecognizer.
433ScheduleHazardRecognizer *TargetInstrInfoImpl::
Andrew Trick2da8bc82010-12-24 05:03:26 +0000434CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
435 const ScheduleDAG *DAG) const {
436 return (ScheduleHazardRecognizer *)
437 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
Evan Cheng774bc882010-06-14 21:06:53 +0000438}