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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Evan Cheng957840b2007-02-21 02:22:03 +000030#include "llvm/ADT/BitVector.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000031#include "llvm/ADT/Statistic.h"
32#include "llvm/ADT/STLExtras.h"
Chris Lattner08a4d5a2007-01-23 00:59:48 +000033#include "llvm/ADT/SmallSet.h"
Chris Lattner27f29162004-10-26 15:35:58 +000034#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000035using namespace llvm;
36
Chris Lattnercd3245a2006-12-19 22:41:21 +000037STATISTIC(NumSpills, "Number of register spills");
Evan Cheng2638e1a2007-03-20 08:13:50 +000038STATISTIC(NumReMats, "Number of re-materialization");
Chris Lattnercd3245a2006-12-19 22:41:21 +000039STATISTIC(NumStores, "Number of stores added");
40STATISTIC(NumLoads , "Number of loads added");
41STATISTIC(NumReused, "Number of values reused");
42STATISTIC(NumDSE , "Number of dead stores elided");
43STATISTIC(NumDCE , "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000044
Chris Lattnercd3245a2006-12-19 22:41:21 +000045namespace {
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000047
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000048 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000050 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000051 cl::Prefix,
52 cl::values(clEnumVal(simple, " simple spiller"),
53 clEnumVal(local, " local spiller"),
54 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000055 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000056}
57
Chris Lattner8c4d88d2004-09-30 01:54:45 +000058//===----------------------------------------------------------------------===//
59// VirtRegMap implementation
60//===----------------------------------------------------------------------===//
61
Chris Lattner29268692006-09-05 02:12:02 +000062VirtRegMap::VirtRegMap(MachineFunction &mf)
63 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
Evan Cheng2638e1a2007-03-20 08:13:50 +000064 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
Evan Cheng549f27d32007-08-13 23:45:17 +000065 Virt2ReMatIdMap(NO_STACK_SLOT), ReMatMap(NULL),
Evan Cheng2638e1a2007-03-20 08:13:50 +000066 ReMatId(MAX_STACK_SLOT+1) {
Chris Lattner29268692006-09-05 02:12:02 +000067 grow();
68}
69
Chris Lattner8c4d88d2004-09-30 01:54:45 +000070void VirtRegMap::grow() {
Evan Cheng549f27d32007-08-13 23:45:17 +000071 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
72 Virt2PhysMap.grow(LastVirtReg);
73 Virt2StackSlotMap.grow(LastVirtReg);
74 Virt2ReMatIdMap.grow(LastVirtReg);
75 ReMatMap.grow(LastVirtReg);
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000076}
77
Chris Lattner8c4d88d2004-09-30 01:54:45 +000078int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
79 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000080 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000081 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000082 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
83 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
84 RC->getAlignment());
85 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000086 ++NumSpills;
87 return frameIndex;
88}
89
90void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
91 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000092 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000093 "attempt to assign stack slot to already spilled register");
Evan Cheng91935142007-04-04 07:40:01 +000094 assert((frameIndex >= 0 ||
95 (frameIndex >= MF.getFrameInfo()->getObjectIndexBegin())) &&
96 "illegal fixed frame index");
Chris Lattner7f690e62004-09-30 02:15:18 +000097 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000098}
99
Evan Cheng2638e1a2007-03-20 08:13:50 +0000100int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
101 assert(MRegisterInfo::isVirtualRegister(virtReg));
Evan Cheng549f27d32007-08-13 23:45:17 +0000102 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
Evan Cheng2638e1a2007-03-20 08:13:50 +0000103 "attempt to assign re-mat id to already spilled register");
Evan Cheng549f27d32007-08-13 23:45:17 +0000104 Virt2ReMatIdMap[virtReg] = ReMatId;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000105 return ReMatId++;
106}
107
Evan Cheng549f27d32007-08-13 23:45:17 +0000108void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
109 assert(MRegisterInfo::isVirtualRegister(virtReg));
110 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
111 "attempt to assign re-mat id to already spilled register");
112 Virt2ReMatIdMap[virtReg] = id;
113}
114
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000115void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +0000116 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000117 // Move previous memory references folded to new instruction.
118 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000119 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000120 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
121 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +0000122 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000123 }
Chris Lattnerdbea9732004-09-30 16:35:08 +0000124
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000125 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000126 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
127 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000128 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000129 // Folded a two-address operand.
130 MRInfo = isModRef;
131 } else if (OldMI->getOperand(OpNo).isDef()) {
132 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000133 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000134 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000135 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000136
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000137 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000138 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000139}
140
Chris Lattner7f690e62004-09-30 02:15:18 +0000141void VirtRegMap::print(std::ostream &OS) const {
142 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000143
Chris Lattner7f690e62004-09-30 02:15:18 +0000144 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000145 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000146 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
147 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
148 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000149
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000150 }
151
152 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000153 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
154 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
155 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
156 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000157}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000158
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000159void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000160 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000161}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000162
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000163
164//===----------------------------------------------------------------------===//
165// Simple Spiller Implementation
166//===----------------------------------------------------------------------===//
167
168Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000169
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000170namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000171 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000172 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000173 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000174}
175
Chris Lattner35f27052006-05-01 21:16:03 +0000176bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000177 DOUT << "********** REWRITE MACHINE CODE **********\n";
178 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000179 const TargetMachine &TM = MF.getTarget();
180 const MRegisterInfo &MRI = *TM.getRegisterInfo();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000181
Chris Lattner4ea1b822004-09-30 02:33:48 +0000182 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
183 // each vreg once (in the case where a spilled vreg is used by multiple
184 // operands). This is always smaller than the number of operands to the
185 // current machine instr, so it should be small.
186 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000187
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000188 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
189 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000190 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000191 MachineBasicBlock &MBB = *MBBI;
192 for (MachineBasicBlock::iterator MII = MBB.begin(),
193 E = MBB.end(); MII != E; ++MII) {
194 MachineInstr &MI = *MII;
195 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000196 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000197 if (MO.isRegister() && MO.getReg())
198 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
199 unsigned VirtReg = MO.getReg();
200 unsigned PhysReg = VRM.getPhys(VirtReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000201 if (!VRM.isAssignedReg(VirtReg)) {
Chris Lattner886dd912005-04-04 21:35:34 +0000202 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000203 const TargetRegisterClass* RC =
204 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000205
Chris Lattner886dd912005-04-04 21:35:34 +0000206 if (MO.isUse() &&
207 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
208 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000209 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000210 LoadedRegs.push_back(VirtReg);
211 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000212 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000213 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000214
Chris Lattner886dd912005-04-04 21:35:34 +0000215 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000216 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000217 ++NumStores;
218 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000219 }
Evan Cheng6c087e52007-04-25 22:13:27 +0000220 MF.setPhysRegUsed(PhysReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000221 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000222 } else {
Evan Cheng6c087e52007-04-25 22:13:27 +0000223 MF.setPhysRegUsed(MO.getReg());
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000224 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225 }
Chris Lattner886dd912005-04-04 21:35:34 +0000226
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000227 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000228 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000229 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000230 }
231 return true;
232}
233
234//===----------------------------------------------------------------------===//
235// Local Spiller Implementation
236//===----------------------------------------------------------------------===//
237
238namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000239 /// LocalSpiller - This spiller does a simple pass over the machine basic
240 /// block to attempt to keep spills in registers as much as possible for
241 /// blocks that have low register pressure (the vreg may be spilled due to
242 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000243 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000244 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000245 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000246 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000247 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000248 MRI = MF.getTarget().getRegisterInfo();
249 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000250 DOUT << "\n**** Local spiller rewriting function '"
251 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000252
Chris Lattner7fb64342004-10-01 19:04:51 +0000253 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
254 MBB != E; ++MBB)
Evan Cheng549f27d32007-08-13 23:45:17 +0000255 RewriteMBB(*MBB, VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000256 return true;
257 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000258 private:
Evan Cheng549f27d32007-08-13 23:45:17 +0000259 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000260 };
261}
262
Chris Lattner66cf80f2006-02-03 23:13:58 +0000263/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
Evan Cheng549f27d32007-08-13 23:45:17 +0000264/// top down, keep track of which spills slots or remat are available in each
265/// register.
Chris Lattner593c9582006-02-03 23:28:46 +0000266///
267/// Note that not all physregs are created equal here. In particular, some
268/// physregs are reloads that we are allowed to clobber or ignore at any time.
269/// Other physregs are values that the register allocated program is using that
270/// we cannot CHANGE, but we can read if we like. We keep track of this on a
Evan Cheng549f27d32007-08-13 23:45:17 +0000271/// per-stack-slot / remat id basis as the low bit in the value of the
272/// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
273/// this bit and addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000274namespace {
275class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000276 const MRegisterInfo *MRI;
277 const TargetInstrInfo *TII;
278
Evan Cheng549f27d32007-08-13 23:45:17 +0000279 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
280 // or remat'ed virtual register values that are still available, due to being
281 // loaded or stored to, but not invalidated yet.
282 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000283
Evan Cheng549f27d32007-08-13 23:45:17 +0000284 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
285 // indicating which stack slot values are currently held by a physreg. This
286 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
287 // physreg is modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000288 std::multimap<unsigned, int> PhysRegsAvailable;
289
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000290 void disallowClobberPhysRegOnly(unsigned PhysReg);
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 void ClobberPhysRegOnly(unsigned PhysReg);
293public:
294 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
295 : MRI(mri), TII(tii) {
296 }
297
Evan Cheng91e23902007-02-23 01:13:26 +0000298 const MRegisterInfo *getRegInfo() const { return MRI; }
299
Evan Cheng549f27d32007-08-13 23:45:17 +0000300 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
301 /// available in a physical register, return that PhysReg, otherwise
302 /// return 0.
303 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
304 std::map<int, unsigned>::const_iterator I =
305 SpillSlotsOrReMatsAvailable.find(Slot);
306 if (I != SpillSlotsOrReMatsAvailable.end()) {
Evan Chengb9591c62007-07-11 08:47:44 +0000307 return I->second >> 1; // Remove the CanClobber bit.
Evan Cheng91e23902007-02-23 01:13:26 +0000308 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000309 return 0;
310 }
Evan Chengde4e9422007-02-25 09:51:27 +0000311
Evan Cheng549f27d32007-08-13 23:45:17 +0000312 /// addAvailable - Mark that the specified stack slot / remat is available in
313 /// the specified physreg. If CanClobber is true, the physreg can be modified
314 /// at any time without changing the semantics of the program.
315 void addAvailable(int SlotOrReMat, MachineInstr *MI, unsigned Reg,
Evan Cheng91e23902007-02-23 01:13:26 +0000316 bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000317 // If this stack slot is thought to be available in some other physreg,
318 // remove its record.
Evan Cheng549f27d32007-08-13 23:45:17 +0000319 ModifyStackSlotOrReMat(SlotOrReMat);
Chris Lattner86662492006-02-03 23:50:46 +0000320
Evan Cheng549f27d32007-08-13 23:45:17 +0000321 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
322 SpillSlotsOrReMatsAvailable[SlotOrReMat] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000323
Evan Cheng549f27d32007-08-13 23:45:17 +0000324 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
325 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000326 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000327 DOUT << "Remembering SS#" << SlotOrReMat;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000328 DOUT << " in physreg " << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000329 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000330
Chris Lattner593c9582006-02-03 23:28:46 +0000331 /// canClobberPhysReg - Return true if the spiller is allowed to change the
332 /// value of the specified stackslot register if it desires. The specified
333 /// stack slot must be available in a physreg for this query to make sense.
Evan Cheng549f27d32007-08-13 23:45:17 +0000334 bool canClobberPhysReg(int SlotOrReMat) const {
335 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) && "Value not available!");
336 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
Chris Lattner593c9582006-02-03 23:28:46 +0000337 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000338
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000339 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
340 /// stackslot register. The register is still available but is no longer
341 /// allowed to be modifed.
342 void disallowClobberPhysReg(unsigned PhysReg);
343
Chris Lattner66cf80f2006-02-03 23:13:58 +0000344 /// ClobberPhysReg - This is called when the specified physreg changes
345 /// value. We use this to invalidate any info about stuff we thing lives in
346 /// it and any of its aliases.
347 void ClobberPhysReg(unsigned PhysReg);
348
Evan Cheng549f27d32007-08-13 23:45:17 +0000349 /// ModifyStackSlotOrReMat - This method is called when the value in a stack slot
Chris Lattner66cf80f2006-02-03 23:13:58 +0000350 /// changes. This removes information about which register the previous value
351 /// for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000352 void ModifyStackSlotOrReMat(int SlotOrReMat);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000353};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000354}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000355
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000356/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
357/// stackslot register. The register is still available but is no longer
358/// allowed to be modifed.
359void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
360 std::multimap<unsigned, int>::iterator I =
361 PhysRegsAvailable.lower_bound(PhysReg);
362 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000363 int SlotOrReMat = I->second;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000364 I++;
Evan Cheng549f27d32007-08-13 23:45:17 +0000365 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000366 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000367 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000368 DOUT << "PhysReg " << MRI->getName(PhysReg)
369 << " copied, it is available for use but can no longer be modified\n";
370 }
371}
372
373/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
374/// stackslot register and its aliases. The register and its aliases may
375/// still available but is no longer allowed to be modifed.
376void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
377 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
378 disallowClobberPhysRegOnly(*AS);
379 disallowClobberPhysRegOnly(PhysReg);
380}
381
Chris Lattner66cf80f2006-02-03 23:13:58 +0000382/// ClobberPhysRegOnly - This is called when the specified physreg changes
383/// value. We use this to invalidate any info about stuff we thing lives in it.
384void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
385 std::multimap<unsigned, int>::iterator I =
386 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000387 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Evan Cheng549f27d32007-08-13 23:45:17 +0000388 int SlotOrReMat = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000389 PhysRegsAvailable.erase(I++);
Evan Cheng549f27d32007-08-13 23:45:17 +0000390 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000391 "Bidirectional map mismatch!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000392 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000393 DOUT << "PhysReg " << MRI->getName(PhysReg)
Evan Cheng2638e1a2007-03-20 08:13:50 +0000394 << " clobbered, invalidating ";
Evan Cheng549f27d32007-08-13 23:45:17 +0000395 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
396 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
Evan Cheng2638e1a2007-03-20 08:13:50 +0000397 else
Evan Cheng549f27d32007-08-13 23:45:17 +0000398 DOUT << "SS#" << SlotOrReMat << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000399 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000400}
401
Chris Lattner66cf80f2006-02-03 23:13:58 +0000402/// ClobberPhysReg - This is called when the specified physreg changes
403/// value. We use this to invalidate any info about stuff we thing lives in
404/// it and any of its aliases.
405void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000406 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000407 ClobberPhysRegOnly(*AS);
408 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000409}
410
Evan Cheng549f27d32007-08-13 23:45:17 +0000411/// ModifyStackSlotOrReMat - This method is called when the value in a stack slot
Chris Lattner07cf1412006-02-03 00:36:31 +0000412/// changes. This removes information about which register the previous value
413/// for this slot lives in (as the previous value is dead now).
Evan Cheng549f27d32007-08-13 23:45:17 +0000414void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
415 std::map<int, unsigned>::iterator It = SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
416 if (It == SpillSlotsOrReMatsAvailable.end()) return;
Evan Chengb9591c62007-07-11 08:47:44 +0000417 unsigned Reg = It->second >> 1;
Evan Cheng549f27d32007-08-13 23:45:17 +0000418 SpillSlotsOrReMatsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000419
420 // This register may hold the value of multiple stack slots, only remove this
421 // stack slot from the set of values the register contains.
422 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
423 for (; ; ++I) {
424 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
425 "Map inverse broken!");
Evan Cheng549f27d32007-08-13 23:45:17 +0000426 if (I->second == SlotOrReMat) break;
Chris Lattner07cf1412006-02-03 00:36:31 +0000427 }
428 PhysRegsAvailable.erase(I);
429}
430
431
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000432
Evan Cheng28bb4622007-07-11 19:17:18 +0000433/// InvalidateKills - MI is going to be deleted. If any of its operands are
434/// marked kill, then invalidate the information.
435static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
436 std::vector<MachineOperand*> &KillOps) {
437 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
438 MachineOperand &MO = MI.getOperand(i);
439 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
440 continue;
441 unsigned Reg = MO.getReg();
442 if (KillOps[Reg] == &MO) {
443 RegKills.reset(Reg);
444 KillOps[Reg] = NULL;
445 }
446 }
447}
448
449/// UpdateKills - Track and update kill info. If a MI reads a register that is
450/// marked kill, then it must be due to register reuse. Transfer the kill info
451/// over.
452static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
453 std::vector<MachineOperand*> &KillOps) {
454 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
455 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
456 MachineOperand &MO = MI.getOperand(i);
457 if (!MO.isReg() || !MO.isUse())
458 continue;
459 unsigned Reg = MO.getReg();
460 if (Reg == 0)
461 continue;
462
463 if (RegKills[Reg]) {
464 // That can't be right. Register is killed but not re-defined and it's
465 // being reused. Let's fix that.
466 KillOps[Reg]->unsetIsKill();
467 if (i < TID->numOperands &&
468 TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
469 // Unless it's a two-address operand, this is the new kill.
470 MO.setIsKill();
471 }
472
473 if (MO.isKill()) {
474 RegKills.set(Reg);
475 KillOps[Reg] = &MO;
476 }
477 }
478
479 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
480 const MachineOperand &MO = MI.getOperand(i);
481 if (!MO.isReg() || !MO.isDef())
482 continue;
483 unsigned Reg = MO.getReg();
484 RegKills.reset(Reg);
485 KillOps[Reg] = NULL;
486 }
487}
488
489
Chris Lattner7fb64342004-10-01 19:04:51 +0000490// ReusedOp - For each reused operand, we keep track of a bit of information, in
491// case we need to rollback upon processing a new operand. See comments below.
492namespace {
493 struct ReusedOp {
494 // The MachineInstr operand that reused an available value.
495 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000496
Evan Cheng549f27d32007-08-13 23:45:17 +0000497 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
498 unsigned StackSlotOrReMat;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000499
Chris Lattner7fb64342004-10-01 19:04:51 +0000500 // PhysRegReused - The physical register the value was available in.
501 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000502
Chris Lattner7fb64342004-10-01 19:04:51 +0000503 // AssignedPhysReg - The physreg that was assigned for use by the reload.
504 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000505
506 // VirtReg - The virtual register itself.
507 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000508
Chris Lattner8a61a752005-10-06 17:19:06 +0000509 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
510 unsigned vreg)
Evan Cheng549f27d32007-08-13 23:45:17 +0000511 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr), AssignedPhysReg(apr),
Chris Lattner8a61a752005-10-06 17:19:06 +0000512 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000513 };
Chris Lattner540fec62006-02-25 01:51:33 +0000514
515 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
516 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000517 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000518 MachineInstr &MI;
519 std::vector<ReusedOp> Reuses;
Evan Cheng957840b2007-02-21 02:22:03 +0000520 BitVector PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000521 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000522 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
Evan Cheng957840b2007-02-21 02:22:03 +0000523 PhysRegsClobbered.resize(mri->getNumRegs());
Evan Chenge077ef62006-11-04 00:21:55 +0000524 }
Chris Lattner540fec62006-02-25 01:51:33 +0000525
526 bool hasReuses() const {
527 return !Reuses.empty();
528 }
529
530 /// addReuse - If we choose to reuse a virtual register that is already
531 /// available instead of reloading it, remember that we did so.
Evan Cheng549f27d32007-08-13 23:45:17 +0000532 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
Chris Lattner540fec62006-02-25 01:51:33 +0000533 unsigned PhysRegReused, unsigned AssignedPhysReg,
534 unsigned VirtReg) {
535 // If the reload is to the assigned register anyway, no undo will be
536 // required.
537 if (PhysRegReused == AssignedPhysReg) return;
538
539 // Otherwise, remember this.
Evan Cheng549f27d32007-08-13 23:45:17 +0000540 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
Chris Lattner540fec62006-02-25 01:51:33 +0000541 AssignedPhysReg, VirtReg));
542 }
Evan Chenge077ef62006-11-04 00:21:55 +0000543
544 void markClobbered(unsigned PhysReg) {
Evan Cheng957840b2007-02-21 02:22:03 +0000545 PhysRegsClobbered.set(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000546 }
547
548 bool isClobbered(unsigned PhysReg) const {
Evan Cheng957840b2007-02-21 02:22:03 +0000549 return PhysRegsClobbered.test(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000550 }
Chris Lattner540fec62006-02-25 01:51:33 +0000551
552 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
553 /// is some other operand that is using the specified register, either pick
554 /// a new register to use, or evict the previous reload and use this reg.
555 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
556 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000557 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000558 SmallSet<unsigned, 8> &Rejected,
559 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000560 std::vector<MachineOperand*> &KillOps,
561 VirtRegMap &VRM) {
Chris Lattner540fec62006-02-25 01:51:33 +0000562 if (Reuses.empty()) return PhysReg; // This is most often empty.
563
564 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
565 ReusedOp &Op = Reuses[ro];
566 // If we find some other reuse that was supposed to use this register
567 // exactly for its reload, we can change this reload to use ITS reload
Evan Cheng3c82cab2007-01-19 22:40:14 +0000568 // register. That is, unless its reload register has already been
569 // considered and subsequently rejected because it has also been reused
570 // by another operand.
571 if (Op.PhysRegReused == PhysReg &&
572 Rejected.count(Op.AssignedPhysReg) == 0) {
Chris Lattner540fec62006-02-25 01:51:33 +0000573 // Yup, use the reload register that we didn't use before.
Evan Cheng3c82cab2007-01-19 22:40:14 +0000574 unsigned NewReg = Op.AssignedPhysReg;
575 Rejected.insert(PhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000576 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000577 RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000578 } else {
579 // Otherwise, we might also have a problem if a previously reused
580 // value aliases the new register. If so, codegen the previous reload
581 // and use this one.
582 unsigned PRRU = Op.PhysRegReused;
583 const MRegisterInfo *MRI = Spills.getRegInfo();
584 if (MRI->areAliases(PRRU, PhysReg)) {
585 // Okay, we found out that an alias of a reused register
586 // was used. This isn't good because it means we have
587 // to undo a previous reuse.
588 MachineBasicBlock *MBB = MI->getParent();
589 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000590 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
591
592 // Copy Op out of the vector and remove it, we're going to insert an
593 // explicit load for it.
594 ReusedOp NewOp = Op;
595 Reuses.erase(Reuses.begin()+ro);
596
597 // Ok, we're going to try to reload the assigned physreg into the
598 // slot that we were supposed to in the first place. However, that
599 // register could hold a reuse. Check to see if it conflicts or
600 // would prefer us to use a different register.
601 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
Evan Cheng28bb4622007-07-11 19:17:18 +0000602 MI, Spills, MaybeDeadStores,
Evan Cheng549f27d32007-08-13 23:45:17 +0000603 Rejected, RegKills, KillOps, VRM);
Chris Lattner28bad082006-02-25 02:17:31 +0000604
Evan Cheng549f27d32007-08-13 23:45:17 +0000605 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
606 MRI->reMaterialize(*MBB, MI, NewPhysReg,
607 VRM.getReMaterializedMI(NewOp.VirtReg));
608 ++NumReMats;
609 } else {
610 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
611 NewOp.StackSlotOrReMat, AliasRC);
Evan Chengfff3e192007-08-14 09:11:18 +0000612 // Any stores to this stack slot are not dead anymore.
613 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000614 ++NumLoads;
615 }
Chris Lattner28bad082006-02-25 02:17:31 +0000616 Spills.ClobberPhysReg(NewPhysReg);
617 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000618
Chris Lattnere53f4a02006-05-04 17:52:23 +0000619 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000620
Evan Cheng549f27d32007-08-13 23:45:17 +0000621 Spills.addAvailable(NewOp.StackSlotOrReMat, MI, NewPhysReg);
Evan Cheng28bb4622007-07-11 19:17:18 +0000622 MachineBasicBlock::iterator MII = MI;
623 --MII;
624 UpdateKills(*MII, RegKills, KillOps);
625 DOUT << '\t' << *MII;
Chris Lattner540fec62006-02-25 01:51:33 +0000626
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000627 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000628 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000629
630 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000631 return PhysReg;
632 }
633 }
634 }
635 return PhysReg;
636 }
Evan Cheng3c82cab2007-01-19 22:40:14 +0000637
638 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
639 /// 'Rejected' set to remember which registers have been considered and
640 /// rejected for the reload. This avoids infinite looping in case like
641 /// this:
642 /// t1 := op t2, t3
643 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
644 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
645 /// t1 <- desires r1
646 /// sees r1 is taken by t2, tries t2's reload register r0
647 /// sees r0 is taken by t3, tries t3's reload register r1
648 /// sees r1 is taken by t2, tries t2's reload register r0 ...
649 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
650 AvailableSpills &Spills,
Evan Chengfff3e192007-08-14 09:11:18 +0000651 std::vector<MachineInstr*> &MaybeDeadStores,
Evan Cheng28bb4622007-07-11 19:17:18 +0000652 BitVector &RegKills,
Evan Cheng549f27d32007-08-13 23:45:17 +0000653 std::vector<MachineOperand*> &KillOps,
654 VirtRegMap &VRM) {
Chris Lattner08a4d5a2007-01-23 00:59:48 +0000655 SmallSet<unsigned, 8> Rejected;
Evan Cheng28bb4622007-07-11 19:17:18 +0000656 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
Evan Cheng549f27d32007-08-13 23:45:17 +0000657 RegKills, KillOps, VRM);
Evan Cheng3c82cab2007-01-19 22:40:14 +0000658 }
Chris Lattner540fec62006-02-25 01:51:33 +0000659 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000660}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000661
Chris Lattner7fb64342004-10-01 19:04:51 +0000662
663/// rewriteMBB - Keep track of which spills are available even after the
664/// register allocator is done with them. If possible, avoid reloading vregs.
Evan Cheng549f27d32007-08-13 23:45:17 +0000665void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000666 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000667
Evan Chengfff3e192007-08-14 09:11:18 +0000668 MachineFunction &MF = *MBB.getParent();
669
Chris Lattner66cf80f2006-02-03 23:13:58 +0000670 // Spills - Keep track of which spilled values are available in physregs so
671 // that we can choose to reuse the physregs instead of emitting reloads.
672 AvailableSpills Spills(MRI, TII);
673
Chris Lattner52b25db2004-10-01 19:47:12 +0000674 // MaybeDeadStores - When we need to write a value back into a stack slot,
675 // keep track of the inserted store. If the stack slot value is never read
676 // (because the value was used from some available register, for example), and
677 // subsequently stored to, the original store is dead. This map keeps track
678 // of inserted stores that are not used. If we see a subsequent store to the
679 // same stack slot, the original store is deleted.
Evan Chengfff3e192007-08-14 09:11:18 +0000680 std::vector<MachineInstr*> MaybeDeadStores;
681 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
Chris Lattner52b25db2004-10-01 19:47:12 +0000682
Evan Cheng0c40d722007-07-11 05:28:39 +0000683 // Keep track of kill information.
684 BitVector RegKills(MRI->getNumRegs());
685 std::vector<MachineOperand*> KillOps;
686 KillOps.resize(MRI->getNumRegs(), NULL);
687
Chris Lattner7fb64342004-10-01 19:04:51 +0000688 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
689 MII != E; ) {
690 MachineInstr &MI = *MII;
691 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
Evan Cheng0c40d722007-07-11 05:28:39 +0000692 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
693
694 bool Erased = false;
695 bool BackTracked = false;
Chris Lattner7fb64342004-10-01 19:04:51 +0000696
Chris Lattner540fec62006-02-25 01:51:33 +0000697 /// ReusedOperands - Keep track of operand reuse in case we need to undo
698 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000699 ReuseInfo ReusedOperands(MI, MRI);
700
701 // Loop over all of the implicit defs, clearing them from our available
702 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000703 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
Evan Cheng0c40d722007-07-11 05:28:39 +0000704 if (TID->ImplicitDefs) {
705 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000706 for ( ; *ImpDef; ++ImpDef) {
Evan Cheng6c087e52007-04-25 22:13:27 +0000707 MF.setPhysRegUsed(*ImpDef);
Evan Chenge077ef62006-11-04 00:21:55 +0000708 ReusedOperands.markClobbered(*ImpDef);
709 Spills.ClobberPhysReg(*ImpDef);
710 }
711 }
712
Chris Lattner7fb64342004-10-01 19:04:51 +0000713 // Process all of the spilled uses and all non spilled reg references.
714 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
715 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000716 if (!MO.isRegister() || MO.getReg() == 0)
717 continue; // Ignore non-register operands.
718
719 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
720 // Ignore physregs for spilling, but remember that it is used by this
721 // function.
Evan Cheng6c087e52007-04-25 22:13:27 +0000722 MF.setPhysRegUsed(MO.getReg());
Evan Chenge077ef62006-11-04 00:21:55 +0000723 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000724 continue;
725 }
726
727 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
728 "Not a virtual or a physical register?");
729
730 unsigned VirtReg = MO.getReg();
Evan Cheng549f27d32007-08-13 23:45:17 +0000731 if (VRM.isAssignedReg(VirtReg)) {
Chris Lattner50ea01e2005-09-09 20:29:51 +0000732 // This virtual register was assigned a physreg!
733 unsigned Phys = VRM.getPhys(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +0000734 MF.setPhysRegUsed(Phys);
Evan Chenge077ef62006-11-04 00:21:55 +0000735 if (MO.isDef())
736 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000737 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000738 continue;
739 }
740
741 // This virtual register is now known to be a spilled value.
742 if (!MO.isUse())
743 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000744
Evan Cheng549f27d32007-08-13 23:45:17 +0000745 bool DoReMat = VRM.isReMaterialized(VirtReg);
746 int SSorRMId = DoReMat
747 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
Evan Chengdc6be192007-08-14 05:42:54 +0000748 int ReuseSlot = SSorRMId;
Chris Lattner7fb64342004-10-01 19:04:51 +0000749
Chris Lattner50ea01e2005-09-09 20:29:51 +0000750 // Check to see if this stack slot is available.
Evan Chengdc6be192007-08-14 05:42:54 +0000751 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
752 if (!PhysReg && DoReMat) {
753 // This use is rematerializable. But perhaps the value is available in
754 // stack if the definition is not deleted. If so, check if we can
755 // reuse the value.
756 ReuseSlot = VRM.getStackSlot(VirtReg);
757 if (ReuseSlot != VirtRegMap::NO_STACK_SLOT)
758 PhysReg = Spills.getSpillSlotOrReMatPhysReg(ReuseSlot);
759 }
760 if (PhysReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000761 // This spilled operand might be part of a two-address operand. If this
762 // is the case, then changing it will necessarily require changing the
763 // def part of the instruction as well. However, in some cases, we
764 // aren't allowed to modify the reused register. If none of these cases
765 // apply, reuse it.
766 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000767 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000768 if (ti != -1 &&
769 MI.getOperand(ti).isReg() &&
770 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000771 // Okay, we have a two address operand. We can reuse this physreg as
Evan Cheng3c82cab2007-01-19 22:40:14 +0000772 // long as we are allowed to clobber the value and there isn't an
773 // earlier def that has already clobbered the physreg.
Evan Chengdc6be192007-08-14 05:42:54 +0000774 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
Evan Chenge077ef62006-11-04 00:21:55 +0000775 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000776 }
777
778 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000779 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000780 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
781 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000782 else
Evan Chengdc6be192007-08-14 05:42:54 +0000783 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000784 DOUT << " from physreg "
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000785 << MRI->getName(PhysReg) << " for vreg"
786 << VirtReg <<" instead of reloading into physreg "
787 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000788 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000789
790 // The only technical detail we have is that we don't know that
791 // PhysReg won't be clobbered by a reloaded stack slot that occurs
792 // later in the instruction. In particular, consider 'op V1, V2'.
793 // If V1 is available in physreg R0, we would choose to reuse it
794 // here, instead of reloading it into the register the allocator
795 // indicated (say R1). However, V2 might have to be reloaded
796 // later, and it might indicate that it needs to live in R0. When
797 // this occurs, we need to have information available that
798 // indicates it is safe to use R1 for the reload instead of R0.
799 //
800 // To further complicate matters, we might conflict with an alias,
801 // or R0 and R1 might not be compatible with each other. In this
802 // case, we actually insert a reload for V1 in R1, ensuring that
803 // we can get at R0 or its alias.
Evan Chengdc6be192007-08-14 05:42:54 +0000804 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
Chris Lattneraddc55a2006-04-28 01:46:50 +0000805 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000806 if (ti != -1)
807 // Only mark it clobbered if this is a use&def operand.
808 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000809 ++NumReused;
Evan Chengfff3e192007-08-14 09:11:18 +0000810
811 if (MI.getOperand(i).isKill() &&
812 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
813 // This was the last use and the spilled value is still available
814 // for reuse. That means the spill was unnecessary!
815 MachineInstr* DeadStore = MaybeDeadStores[ReuseSlot];
816 if (DeadStore) {
817 DOUT << "Removed dead store:\t" << *DeadStore;
818 InvalidateKills(*DeadStore, RegKills, KillOps);
819 MBB.erase(DeadStore);
820 VRM.RemoveFromFoldedVirtMap(DeadStore);
821 MaybeDeadStores[ReuseSlot] = NULL;
822 ++NumDSE;
823 }
824 }
Chris Lattneraddc55a2006-04-28 01:46:50 +0000825 continue;
826 }
827
828 // Otherwise we have a situation where we have a two-address instruction
829 // whose mod/ref operand needs to be reloaded. This reload is already
830 // available in some register "PhysReg", but if we used PhysReg as the
831 // operand to our 2-addr instruction, the instruction would modify
832 // PhysReg. This isn't cool if something later uses PhysReg and expects
833 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000834 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000835 // To avoid this problem, and to avoid doing a load right after a store,
836 // we emit a copy from PhysReg into the designated register for this
837 // operand.
838 unsigned DesignatedReg = VRM.getPhys(VirtReg);
839 assert(DesignatedReg && "Must map virtreg to physreg!");
840
841 // Note that, if we reused a register for a previous operand, the
842 // register we want to reload into might not actually be
843 // available. If this occurs, use the register indicated by the
844 // reuser.
845 if (ReusedOperands.hasReuses())
846 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000847 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000848
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000849 // If the mapped designated register is actually the physreg we have
850 // incoming, we don't need to inserted a dead copy.
851 if (DesignatedReg == PhysReg) {
852 // If this stack slot value is already available, reuse it!
Evan Chengdc6be192007-08-14 05:42:54 +0000853 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
854 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000855 else
Evan Chengdc6be192007-08-14 05:42:54 +0000856 DOUT << "Reusing SS#" << ReuseSlot;
Evan Cheng2638e1a2007-03-20 08:13:50 +0000857 DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg"
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000858 << VirtReg
859 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000860 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000861 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000862 ++NumReused;
863 continue;
864 }
865
Evan Cheng6c087e52007-04-25 22:13:27 +0000866 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
867 MF.setPhysRegUsed(DesignatedReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000868 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000869 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
Evan Chengde4e9422007-02-25 09:51:27 +0000870
Evan Cheng6b448092007-03-02 08:52:00 +0000871 MachineInstr *CopyMI = prior(MII);
Evan Cheng0c40d722007-07-11 05:28:39 +0000872 UpdateKills(*CopyMI, RegKills, KillOps);
Evan Chengde4e9422007-02-25 09:51:27 +0000873
Chris Lattneraddc55a2006-04-28 01:46:50 +0000874 // This invalidates DesignatedReg.
875 Spills.ClobberPhysReg(DesignatedReg);
876
Evan Chengdc6be192007-08-14 05:42:54 +0000877 Spills.addAvailable(ReuseSlot, &MI, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000878 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000879 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000880 ++NumReused;
881 continue;
882 }
883
884 // Otherwise, reload it and remember that we have it.
885 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000886 assert(PhysReg && "Must map virtreg to physreg!");
Evan Cheng6c087e52007-04-25 22:13:27 +0000887 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000888
Chris Lattner50ea01e2005-09-09 20:29:51 +0000889 // Note that, if we reused a register for a previous operand, the
890 // register we want to reload into might not actually be
891 // available. If this occurs, use the register indicated by the
892 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000893 if (ReusedOperands.hasReuses())
894 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +0000895 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Chris Lattner540fec62006-02-25 01:51:33 +0000896
Evan Cheng6c087e52007-04-25 22:13:27 +0000897 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000898 ReusedOperands.markClobbered(PhysReg);
Evan Cheng549f27d32007-08-13 23:45:17 +0000899 if (DoReMat) {
Evan Cheng2638e1a2007-03-20 08:13:50 +0000900 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
Evan Cheng91935142007-04-04 07:40:01 +0000901 ++NumReMats;
902 } else {
Evan Cheng549f27d32007-08-13 23:45:17 +0000903 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
Evan Cheng91935142007-04-04 07:40:01 +0000904 ++NumLoads;
905 }
Chris Lattner50ea01e2005-09-09 20:29:51 +0000906 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000907 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000908
909 // Any stores to this stack slot are not dead anymore.
Evan Cheng549f27d32007-08-13 23:45:17 +0000910 if (!DoReMat)
Evan Chengfff3e192007-08-14 09:11:18 +0000911 MaybeDeadStores[SSorRMId] = NULL;
Evan Cheng549f27d32007-08-13 23:45:17 +0000912 Spills.addAvailable(SSorRMId, &MI, PhysReg);
Evan Chengde4e9422007-02-25 09:51:27 +0000913 // Assumes this is the last use. IsKill will be unset if reg is reused
914 // unless it's a two-address operand.
915 if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
916 MI.getOperand(i).setIsKill();
Chris Lattnere53f4a02006-05-04 17:52:23 +0000917 MI.getOperand(i).setReg(PhysReg);
Evan Cheng0c40d722007-07-11 05:28:39 +0000918 UpdateKills(*prior(MII), RegKills, KillOps);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000919 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000920 }
921
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000922 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000923
Chris Lattner7fb64342004-10-01 19:04:51 +0000924 // If we have folded references to memory operands, make sure we clear all
925 // physical registers that may contain the value of the spilled virtual
926 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000927 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000928 DOUT << "Folded vreg: " << I->second.first << " MR: "
929 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000930 unsigned VirtReg = I->second.first;
931 VirtRegMap::ModRef MR = I->second.second;
Evan Cheng549f27d32007-08-13 23:45:17 +0000932 if (VRM.isAssignedReg(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000933 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000934 continue;
935 }
936 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000937 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000938
939 // If this folded instruction is just a use, check to see if it's a
940 // straight load from the virt reg slot.
941 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
942 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000943 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000944 if (FrameIdx == SS) {
945 // If this spill slot is available, turn it into a copy (or nothing)
946 // instead of leaving it as a load!
Evan Cheng549f27d32007-08-13 23:45:17 +0000947 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000948 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000949 if (DestReg != InReg) {
950 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
951 MF.getSSARegMap()->getRegClass(VirtReg));
952 // Revisit the copy so we make sure to notice the effects of the
953 // operation on the destreg (either needing to RA it if it's
954 // virtual or needing to clobber any values if it's physical).
955 NextMII = &MI;
956 --NextMII; // backtrack to the copy.
Evan Cheng0c40d722007-07-11 05:28:39 +0000957 BackTracked = true;
Evan Chengde4e9422007-02-25 09:51:27 +0000958 } else
959 DOUT << "Removing now-noop copy: " << MI;
960
Chris Lattner6ec36262006-10-12 17:45:38 +0000961 VRM.RemoveFromFoldedVirtMap(&MI);
962 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +0000963 Erased = true;
Chris Lattner6ec36262006-10-12 17:45:38 +0000964 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000965 }
Chris Lattnercea86882005-09-19 06:56:21 +0000966 }
967 }
968 }
969
970 // If this reference is not a use, any previous store is now dead.
971 // Otherwise, the store to this stack slot is not dead anymore.
Evan Chengfff3e192007-08-14 09:11:18 +0000972 MachineInstr* DeadStore = MaybeDeadStores[SS];
973 if (DeadStore) {
974 if (!(MR & VirtRegMap::isRef)) { // Previous store is dead.
Chris Lattnercea86882005-09-19 06:56:21 +0000975 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000976 assert(VirtRegMap::isMod && "Can't be modref!");
Evan Chengfff3e192007-08-14 09:11:18 +0000977 DOUT << "Removed dead store:\t" << *DeadStore;
978 InvalidateKills(*DeadStore, RegKills, KillOps);
979 MBB.erase(DeadStore);
980 VRM.RemoveFromFoldedVirtMap(DeadStore);
Chris Lattner35f27052006-05-01 21:16:03 +0000981 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000982 }
Evan Chengfff3e192007-08-14 09:11:18 +0000983 MaybeDeadStores[SS] = NULL;
Chris Lattnercea86882005-09-19 06:56:21 +0000984 }
985
986 // If the spill slot value is available, and this is a new definition of
987 // the value, the value is not available anymore.
988 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000989 // Notice that the value in this stack slot has been modified.
Evan Cheng549f27d32007-08-13 23:45:17 +0000990 Spills.ModifyStackSlotOrReMat(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000991
992 // If this is *just* a mod of the value, check to see if this is just a
993 // store to the spill slot (i.e. the spill got merged into the copy). If
994 // so, realize that the vreg is available now, and add the store to the
995 // MaybeDeadStore info.
996 int StackSlot;
997 if (!(MR & VirtRegMap::isRef)) {
998 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
999 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
1000 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +00001001 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +00001002 // this as a potentially dead store in case there is a subsequent
1003 // store into the stack slot without a read from it.
1004 MaybeDeadStores[StackSlot] = &MI;
1005
Chris Lattnercd816392006-02-02 23:29:36 +00001006 // If the stack slot value was previously available in some other
1007 // register, change it now. Otherwise, make the register available,
1008 // in PhysReg.
Evan Cheng91e23902007-02-23 01:13:26 +00001009 Spills.addAvailable(StackSlot, &MI, SrcReg, false/*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +00001010 }
1011 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001012 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001013 }
1014
Chris Lattner7fb64342004-10-01 19:04:51 +00001015 // Process all of the spilled defs.
1016 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1017 MachineOperand &MO = MI.getOperand(i);
1018 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
1019 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001020
Chris Lattner7fb64342004-10-01 19:04:51 +00001021 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +00001022 // Check to see if this is a noop copy. If so, eliminate the
1023 // instruction before considering the dest reg to be changed.
1024 unsigned Src, Dst;
1025 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1026 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001027 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +00001028 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001029 Erased = true;
Chris Lattner29268692006-09-05 02:12:02 +00001030 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +00001031 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +00001032 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +00001033 }
Chris Lattner6ec36262006-10-12 17:45:38 +00001034
1035 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +00001036 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001037 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001038
1039 // Check to see if this instruction is a load from a stack slot into
1040 // a register. If so, this provides the stack slot value in the reg.
1041 int FrameIdx;
1042 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1043 assert(DestReg == VirtReg && "Unknown load situation!");
1044
1045 // Otherwise, if it wasn't available, remember that it is now!
Evan Cheng91e23902007-02-23 01:13:26 +00001046 Spills.addAvailable(FrameIdx, &MI, DestReg);
Chris Lattner6ec36262006-10-12 17:45:38 +00001047 goto ProcessNextInst;
1048 }
1049
Chris Lattner29268692006-09-05 02:12:02 +00001050 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +00001051 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001052
Chris Lattner84e752a2006-02-03 03:06:49 +00001053 // The only vregs left are stack slot definitions.
1054 int StackSlot = VRM.getStackSlot(VirtReg);
Evan Cheng6c087e52007-04-25 22:13:27 +00001055 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001056
Chris Lattner29268692006-09-05 02:12:02 +00001057 // If this def is part of a two-address operand, make sure to execute
1058 // the store from the correct physical register.
1059 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +00001060 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +00001061 if (TiedOp != -1)
1062 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +00001063 else {
Chris Lattner29268692006-09-05 02:12:02 +00001064 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001065 if (ReusedOperands.isClobbered(PhysReg)) {
1066 // Another def has taken the assigned physreg. It must have been a
1067 // use&def which got it due to reuse. Undo the reuse!
1068 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
Evan Cheng549f27d32007-08-13 23:45:17 +00001069 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
Evan Chenge077ef62006-11-04 00:21:55 +00001070 }
1071 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001072
Evan Cheng6c087e52007-04-25 22:13:27 +00001073 MF.setPhysRegUsed(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +00001074 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001075 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001076 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +00001077 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +00001078
Chris Lattner84e752a2006-02-03 03:06:49 +00001079 // If there is a dead store to this stack slot, nuke it now.
1080 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1081 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +00001082 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +00001083 ++NumDSE;
Evan Cheng0c40d722007-07-11 05:28:39 +00001084 InvalidateKills(*LastStore, RegKills, KillOps);
Chris Lattner84e752a2006-02-03 03:06:49 +00001085 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +00001086 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +00001087 }
Chris Lattner84e752a2006-02-03 03:06:49 +00001088 LastStore = next(MII);
1089
1090 // If the stack slot value was previously available in some other
1091 // register, change it now. Otherwise, make the register available,
1092 // in PhysReg.
Evan Cheng549f27d32007-08-13 23:45:17 +00001093 Spills.ModifyStackSlotOrReMat(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +00001094 Spills.ClobberPhysReg(PhysReg);
Evan Cheng91e23902007-02-23 01:13:26 +00001095 Spills.addAvailable(StackSlot, LastStore, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +00001096 ++NumStores;
Evan Chengf50d09a2007-02-08 06:04:54 +00001097
1098 // Check to see if this is a noop copy. If so, eliminate the
1099 // instruction before considering the dest reg to be changed.
1100 {
1101 unsigned Src, Dst;
1102 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
1103 ++NumDCE;
1104 DOUT << "Removing now-noop copy: " << MI;
1105 MBB.erase(&MI);
Evan Cheng0c40d722007-07-11 05:28:39 +00001106 Erased = true;
Evan Chengf50d09a2007-02-08 06:04:54 +00001107 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng28bb4622007-07-11 19:17:18 +00001108 UpdateKills(*LastStore, RegKills, KillOps);
Evan Chengf50d09a2007-02-08 06:04:54 +00001109 goto ProcessNextInst;
1110 }
1111 }
Chris Lattner7fb64342004-10-01 19:04:51 +00001112 }
1113 }
Chris Lattnercea86882005-09-19 06:56:21 +00001114 ProcessNextInst:
Evan Cheng0c40d722007-07-11 05:28:39 +00001115 if (!Erased && !BackTracked)
1116 for (MachineBasicBlock::iterator II = MI; II != NextMII; ++II)
1117 UpdateKills(*II, RegKills, KillOps);
Chris Lattner7fb64342004-10-01 19:04:51 +00001118 MII = NextMII;
1119 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001120}
1121
Chris Lattnerf7da2c72006-08-24 22:43:55 +00001122
Chris Lattner8c4d88d2004-09-30 01:54:45 +00001123llvm::Spiller* llvm::createSpiller() {
1124 switch (SpillerOpt) {
1125 default: assert(0 && "Unreachable!");
1126 case local:
1127 return new LocalSpiller();
1128 case simple:
1129 return new SimpleSpiller();
1130 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +00001131}