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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 / . / lib / Target / Alpha / AlphaInstrInfo.h
blob: 063eb0c21813062e030120d7363e149b24fe4bf1 [file] [log] [blame]
Misha Brukmanbc9ccf62005-02-04 20:25:52 +0000[diff] [blame]1//===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===//
Misha Brukman4633f1c2005-04-21 23:13:11 +0000[diff] [blame]2//
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman4633f1c2005-04-21 23:13:11 +0000[diff] [blame]7//
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file contains the Alpha implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ALPHAINSTRUCTIONINFO_H
15#define ALPHAINSTRUCTIONINFO_H
16
17#include "llvm/Target/TargetInstrInfo.h"
18#include "AlphaRegisterInfo.h"
19
20namespace llvm {
21
Chris Lattner64105522008-01-01 01:03:04 +0000[diff] [blame]22class AlphaInstrInfo : public TargetInstrInfoImpl {
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000[diff] [blame]23 const AlphaRegisterInfo RI;
24public:
25 AlphaInstrInfo();
26
27 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
28 /// such, whenever a client has an instance of instruction info, it should
29 /// always be able to get register info as well (through this method).
30 ///
Dan Gohmanc9f5f3f2008-05-14 01:58:56 +0000[diff] [blame^]31 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; }
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000[diff] [blame]32
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
35 ///
36 virtual bool isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg) const;
Chris Lattner40839602006-02-02 20:12:32 +0000[diff] [blame]38
39 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
Andrew Lenharth133d3102006-02-03 03:07:37 +0000[diff] [blame]40 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
Chris Lattner0476b282006-10-24 16:41:36 +0000[diff] [blame]41
Evan Chengb5cdaa22007-05-18 00:05:48 +0000[diff] [blame]42 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Chris Lattner0476b282006-10-24 16:41:36 +0000[diff] [blame]43 MachineBasicBlock *FBB,
44 const std::vector<MachineOperand> &Cond) const;
Owen Andersond10fd972007-12-31 06:32:00 +0000[diff] [blame]45 virtual void copyRegToReg(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator MI,
47 unsigned DestReg, unsigned SrcReg,
48 const TargetRegisterClass *DestRC,
49 const TargetRegisterClass *SrcRC) const;
Owen Andersonf6372aa2008-01-01 21:11:32 +0000[diff] [blame]50 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator MBBI,
52 unsigned SrcReg, bool isKill, int FrameIndex,
53 const TargetRegisterClass *RC) const;
54
55 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
56 SmallVectorImpl<MachineOperand> &Addr,
57 const TargetRegisterClass *RC,
58 SmallVectorImpl<MachineInstr*> &NewMIs) const;
59
60 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MBBI,
62 unsigned DestReg, int FrameIndex,
63 const TargetRegisterClass *RC) const;
64
65 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
66 SmallVectorImpl<MachineOperand> &Addr,
67 const TargetRegisterClass *RC,
68 SmallVectorImpl<MachineInstr*> &NewMIs) const;
Owen Anderson43dbe052008-01-07 01:35:02 +0000[diff] [blame]69
Evan Cheng5fd79d02008-02-08 21:20:40 +0000[diff] [blame]70 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
71 MachineInstr* MI,
Owen Anderson43dbe052008-01-07 01:35:02 +0000[diff] [blame]72 SmallVectorImpl<unsigned> &Ops,
73 int FrameIndex) const;
74
Evan Cheng5fd79d02008-02-08 21:20:40 +0000[diff] [blame]75 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
76 MachineInstr* MI,
Owen Anderson43dbe052008-01-07 01:35:02 +0000[diff] [blame]77 SmallVectorImpl<unsigned> &Ops,
78 MachineInstr* LoadMI) const {
79 return 0;
80 }
81
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000[diff] [blame]82 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
83 MachineBasicBlock *&FBB,
84 std::vector<MachineOperand> &Cond) const;
Evan Chengb5cdaa22007-05-18 00:05:48 +0000[diff] [blame]85 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
Andrew Lenharthf81173f2006-10-31 16:49:55 +0000[diff] [blame]86 void insertNoop(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI) const;
88 bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
89 bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
Andrew Lenharth304d0f32005-01-22 23:41:55 +0000[diff] [blame]90};
91
92}
93
94#endif