blob: 111818b289e883824e17c399b2cae28e3c47c0aa [file] [log] [blame]
Jush Lu29465492012-08-03 02:37:48 +00001; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
2
3define i32 @shl() nounwind ssp {
4entry:
5; ARM: shl
6; ARM: lsl r0, r0, #2
7 %shl = shl i32 -1, 2
8 ret i32 %shl
9}
10
11define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
12entry:
13; ARM: shl_reg
14; ARM: lsl r0, r0, r1
15 %shl = shl i32 %src1, %src2
16 ret i32 %shl
17}
18
19define i32 @lshr() nounwind ssp {
20entry:
21; ARM: lshr
22; ARM: lsr r0, r0, #2
23 %lshr = lshr i32 -1, 2
24 ret i32 %lshr
25}
26
27define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
28entry:
29; ARM: lshr_reg
30; ARM: lsr r0, r0, r1
31 %lshr = lshr i32 %src1, %src2
32 ret i32 %lshr
33}
34
35define i32 @ashr() nounwind ssp {
36entry:
37; ARM: ashr
38; ARM: asr r0, r0, #2
39 %ashr = ashr i32 -1, 2
40 ret i32 %ashr
41}
42
43define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
44entry:
45; ARM: ashr_reg
46; ARM: asr r0, r0, r1
47 %ashr = ashr i32 %src1, %src2
48 ret i32 %ashr
49}
50