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Chris Lattnera5a91b12005-08-17 19:33:03 +00001//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines a pattern matching instruction selector for 32 bit PowerPC,
11// converting from a legalized dag to a PPC dag.
12//
13//===----------------------------------------------------------------------===//
14
15#include "PowerPC.h"
16#include "PPC32TargetMachine.h"
17#include "PPC32ISelLowering.h"
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/CodeGen/SelectionDAGISel.h"
20#include "llvm/Target/TargetOptions.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/Support/Debug.h"
23#include "llvm/Support/MathExtras.h"
24using namespace llvm;
25
26namespace {
27 Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
28 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
29 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
30
31 //===--------------------------------------------------------------------===//
32 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
33 /// instructions for SelectionDAG operations.
34 ///
35 class PPC32DAGToDAGISel : public SelectionDAGISel {
36 PPC32TargetLowering PPC32Lowering;
37
38 unsigned GlobalBaseReg;
39 bool GlobalBaseInitialized;
40 public:
41 PPC32DAGToDAGISel(TargetMachine &TM)
42 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
43
44 /// runOnFunction - Override this function in order to reset our
45 /// per-function variables.
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
48 GlobalBaseInitialized = false;
49 return SelectionDAGISel::runOnFunction(Fn);
50 }
51
52 /// getI32Imm - Return a target constant with the specified value, of type
53 /// i32.
54 inline SDOperand getI32Imm(unsigned Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i32);
56 }
57
58 // Select - Convert the specified operand from a target-independent to a
59 // target-specific node if it hasn't already been changed.
60 SDOperand Select(SDOperand Op);
61
62 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
63 unsigned OCHi, unsigned OCLo,
64 bool IsArithmetic = false,
65 bool Negate = false);
66
67 /// InstructionSelectBasicBlock - This callback is invoked by
68 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
69 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
70 DEBUG(BB->dump());
71 // Codegen the basic block.
72 Select(DAG.getRoot());
73 DAG.RemoveDeadNodes();
74 DAG.viewGraph();
75 }
76
77 virtual const char *getPassName() const {
78 return "PowerPC DAG->DAG Pattern Instruction Selection";
79 }
80 };
81}
82
Nate Begeman0f3257a2005-08-18 05:00:13 +000083// isIntImmediate - This method tests to see if a constant operand.
84// If so Imm will receive the 32 bit value.
85static bool isIntImmediate(SDNode *N, unsigned& Imm) {
86 if (N->getOpcode() == ISD::Constant) {
87 Imm = cast<ConstantSDNode>(N)->getValue();
88 return true;
89 }
90 return false;
91}
92
Nate Begemancffc32b2005-08-18 07:30:46 +000093// isOprShiftImm - Returns true if the specified operand is a shift opcode with
94// a immediate shift count less than 32.
95static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) {
96 Opc = N->getOpcode();
97 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) &&
98 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32;
99}
100
101// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with
102// any number of 0s on either side. The 1s are allowed to wrap from LSB to
103// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
104// not, since all 1s are not contiguous.
105static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
106 if (isShiftedMask_32(Val)) {
107 // look for the first non-zero bit
108 MB = CountLeadingZeros_32(Val);
109 // look for the first zero bit after the run of ones
110 ME = CountLeadingZeros_32((Val - 1) ^ Val);
111 return true;
112 } else if (isShiftedMask_32(Val = ~Val)) { // invert mask
113 // effectively look for the first zero bit
114 ME = CountLeadingZeros_32(Val) - 1;
115 // effectively look for the first one bit after the run of zeros
116 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
117 return true;
118 }
119 // no run present
120 return false;
121}
122
123// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate
124// and mask opcode and mask operation.
125static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
126 unsigned &SH, unsigned &MB, unsigned &ME) {
127 unsigned Shift = 32;
128 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
129 unsigned Opcode = N->getOpcode();
130 if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31))
131 return false;
132
133 if (Opcode == ISD::SHL) {
134 // apply shift left to mask if it comes first
135 if (IsShiftMask) Mask = Mask << Shift;
136 // determine which bits are made indeterminant by shift
137 Indeterminant = ~(0xFFFFFFFFu << Shift);
138 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) {
139 // apply shift right to mask if it comes first
140 if (IsShiftMask) Mask = Mask >> Shift;
141 // determine which bits are made indeterminant by shift
142 Indeterminant = ~(0xFFFFFFFFu >> Shift);
143 // adjust for the left rotate
144 Shift = 32 - Shift;
145 } else {
146 return false;
147 }
148
149 // if the mask doesn't intersect any Indeterminant bits
150 if (Mask && !(Mask & Indeterminant)) {
151 SH = Shift;
152 // make sure the mask is still a mask (wrap arounds may not be)
153 return isRunOfOnes(Mask, MB, ME);
154 }
155 return false;
156}
157
Nate Begeman0f3257a2005-08-18 05:00:13 +0000158// isOpcWithIntImmediate - This method tests to see if the node is a specific
159// opcode and that it has a immediate integer right operand.
160// If so Imm will receive the 32 bit value.
161static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
162 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm);
163}
164
165// isOprNot - Returns true if the specified operand is an xor with immediate -1.
166static bool isOprNot(SDNode *N) {
167 unsigned Imm;
168 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1;
169}
170
Chris Lattnera5a91b12005-08-17 19:33:03 +0000171// Immediate constant composers.
172// Lo16 - grabs the lo 16 bits from a 32 bit constant.
173// Hi16 - grabs the hi 16 bits from a 32 bit constant.
174// HA16 - computes the hi bits required if the lo bits are add/subtracted in
175// arithmethically.
176static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
177static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
178static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
179
180// isIntImmediate - This method tests to see if a constant operand.
181// If so Imm will receive the 32 bit value.
182static bool isIntImmediate(SDOperand N, unsigned& Imm) {
183 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
184 Imm = (unsigned)CN->getSignExtended();
185 return true;
186 }
187 return false;
188}
189
190// SelectIntImmediateExpr - Choose code for integer operations with an immediate
191// operand.
192SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
193 unsigned OCHi, unsigned OCLo,
194 bool IsArithmetic,
195 bool Negate) {
196 // Check to make sure this is a constant.
197 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
198 // Exit if not a constant.
199 if (!CN) return 0;
200 // Extract immediate.
201 unsigned C = (unsigned)CN->getValue();
202 // Negate if required (ISD::SUB).
203 if (Negate) C = -C;
204 // Get the hi and lo portions of constant.
205 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
206 unsigned Lo = Lo16(C);
207
208 // If two instructions are needed and usage indicates it would be better to
209 // load immediate into a register, bail out.
210 if (Hi && Lo && CN->use_size() > 2) return false;
211
212 // Select the first operand.
213 SDOperand Opr0 = Select(LHS);
214
215 if (Lo) // Add in the lo-part.
216 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
217 if (Hi) // Add in the hi-part.
218 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
219 return Opr0.Val;
220}
221
222
223// Select - Convert the specified operand from a target-independent to a
224// target-specific node if it hasn't already been changed.
225SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
226 SDNode *N = Op.Val;
227 if (N->getOpcode() >= ISD::BUILTIN_OP_END)
228 return Op; // Already selected.
229
230 switch (N->getOpcode()) {
231 default:
232 std::cerr << "Cannot yet select: ";
233 N->dump();
234 std::cerr << "\n";
235 abort();
236 case ISD::EntryToken: // These leaves remain the same.
237 case ISD::UNDEF:
238 return Op;
239 case ISD::TokenFactor: {
240 SDOperand New;
241 if (N->getNumOperands() == 2) {
242 SDOperand Op0 = Select(N->getOperand(0));
243 SDOperand Op1 = Select(N->getOperand(1));
244 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
245 } else {
246 std::vector<SDOperand> Ops;
247 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
248 Ops.push_back(Select(N->getOperand(0)));
249 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
250 }
251
252 if (New.Val != N) {
253 CurDAG->ReplaceAllUsesWith(N, New.Val);
254 N = New.Val;
255 }
256 break;
257 }
258 case ISD::CopyFromReg: {
259 SDOperand Chain = Select(N->getOperand(0));
260 if (Chain == N->getOperand(0)) return Op; // No change
261 SDOperand New = CurDAG->getCopyFromReg(Chain,
262 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
263 return New.getValue(Op.ResNo);
264 }
265 case ISD::CopyToReg: {
266 SDOperand Chain = Select(N->getOperand(0));
267 SDOperand Reg = N->getOperand(1);
268 SDOperand Val = Select(N->getOperand(2));
269 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
270 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
271 Chain, Reg, Val);
272 CurDAG->ReplaceAllUsesWith(N, New.Val);
273 N = New.Val;
274 }
275 break;
276 }
277 case ISD::Constant: {
278 assert(N->getValueType(0) == MVT::i32);
279 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
280 if ((unsigned)(short)v == v) {
281 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
282 break;
283 } else {
284 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
285 getI32Imm(unsigned(v) >> 16));
286 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
287 break;
288 }
289 }
Nate Begeman305a1c72005-08-18 03:04:18 +0000290 case ISD::SIGN_EXTEND_INREG:
291 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
292 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break;
293 case MVT::i16:
294 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0)));
295 break;
296 case MVT::i8:
297 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0)));
298 break;
Nate Begeman305a1c72005-08-18 03:04:18 +0000299 }
300 break;
301 case ISD::CTLZ:
302 assert(N->getValueType(0) == MVT::i32);
303 CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0)));
304 break;
Chris Lattnera5a91b12005-08-17 19:33:03 +0000305 case ISD::ADD: {
306 MVT::ValueType Ty = N->getValueType(0);
307 if (Ty == MVT::i32) {
308 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
309 PPC::ADDIS, PPC::ADDI, true)) {
310 CurDAG->ReplaceAllUsesWith(N, I);
311 N = I;
312 } else {
313 CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
314 Select(N->getOperand(1)));
315 }
316 break;
317 }
318
319 if (!NoExcessFPPrecision) { // Match FMA ops
320 if (N->getOperand(0).getOpcode() == ISD::MUL &&
321 N->getOperand(0).Val->hasOneUse()) {
322 ++FusedFP; // Statistic
323 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
324 Select(N->getOperand(0).getOperand(0)),
325 Select(N->getOperand(0).getOperand(1)),
326 Select(N->getOperand(1)));
327 break;
328 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
329 N->getOperand(1).hasOneUse()) {
330 ++FusedFP; // Statistic
331 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
332 Select(N->getOperand(1).getOperand(0)),
333 Select(N->getOperand(1).getOperand(1)),
334 Select(N->getOperand(0)));
335 break;
336 }
337 }
338
339 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
340 Select(N->getOperand(0)), Select(N->getOperand(1)));
341 break;
342 }
343 case ISD::SUB: {
344 MVT::ValueType Ty = N->getValueType(0);
345 if (Ty == MVT::i32) {
346 unsigned Imm;
347 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
348 CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
349 getI32Imm(Lo16(Imm)));
350 break;
351 }
352 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
353 PPC::ADDIS, PPC::ADDI, true, true)) {
354 CurDAG->ReplaceAllUsesWith(N, I);
355 N = I;
356 } else {
357 CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
358 Select(N->getOperand(0)));
359 }
360 break;
361 }
362
363 if (!NoExcessFPPrecision) { // Match FMA ops
364 if (N->getOperand(0).getOpcode() == ISD::MUL &&
365 N->getOperand(0).Val->hasOneUse()) {
366 ++FusedFP; // Statistic
367 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
368 Select(N->getOperand(0).getOperand(0)),
369 Select(N->getOperand(0).getOperand(1)),
370 Select(N->getOperand(1)));
371 break;
372 } else if (N->getOperand(1).getOpcode() == ISD::MUL &&
373 N->getOperand(1).Val->hasOneUse()) {
374 ++FusedFP; // Statistic
375 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
376 Select(N->getOperand(1).getOperand(0)),
377 Select(N->getOperand(1).getOperand(1)),
378 Select(N->getOperand(0)));
379 break;
380 }
381 }
382 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
383 Select(N->getOperand(0)),
384 Select(N->getOperand(1)));
385 break;
Nate Begeman26653502005-08-17 23:46:35 +0000386 }
Nate Begemanb5a06682005-08-18 00:21:41 +0000387 case ISD::MUL: {
388 unsigned Imm, Opc;
389 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
390 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI,
391 Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
392 break;
393 }
394 switch (N->getValueType(0)) {
395 default: assert(0 && "Unhandled multiply type!");
396 case MVT::i32: Opc = PPC::MULLW; break;
397 case MVT::f32: Opc = PPC::FMULS; break;
398 case MVT::f64: Opc = PPC::FMUL; break;
399 }
400 CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)),
401 Select(N->getOperand(1)));
402 break;
403 }
Nate Begeman305a1c72005-08-18 03:04:18 +0000404 case ISD::MULHS:
Nate Begemanb5a06682005-08-18 00:21:41 +0000405 assert(N->getValueType(0) == MVT::i32);
Nate Begeman305a1c72005-08-18 03:04:18 +0000406 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)),
407 Select(N->getOperand(1)));
Nate Begemanb5a06682005-08-18 00:21:41 +0000408 break;
Nate Begeman305a1c72005-08-18 03:04:18 +0000409 case ISD::MULHU:
Nate Begemanb5a06682005-08-18 00:21:41 +0000410 assert(N->getValueType(0) == MVT::i32);
Nate Begeman305a1c72005-08-18 03:04:18 +0000411 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)),
412 Select(N->getOperand(1)));
Nate Begemanb5a06682005-08-18 00:21:41 +0000413 break;
Nate Begemancffc32b2005-08-18 07:30:46 +0000414 case ISD::AND: {
415 unsigned Imm, SH, MB, ME;
416 // If this is an and of a value rotated between 0 and 31 bits and then and'd
417 // with a mask, emit rlwinm
418 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
419 isShiftedMask_32(~Imm))) {
420 SDOperand Val;
421 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
422 Val = Select(N->getOperand(0).getOperand(0));
423 } else {
424 Val = Select(N->getOperand(0));
425 isRunOfOnes(Imm, MB, ME);
426 SH = 0;
427 }
428 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH),
429 getI32Imm(MB), getI32Imm(ME));
430 break;
431 }
432 // If this is an and with an immediate that isn't a mask, then codegen it as
433 // high and low 16 bit immediate ands.
434 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
435 N->getOperand(1),
436 PPC::ANDISo, PPC::ANDIo)) {
437 CurDAG->ReplaceAllUsesWith(N, I);
438 N = I;
439 break;
440 }
441 // Finally, check for the case where we are being asked to select
442 // and (not(a), b) or and (a, not(b)) which can be selected as andc.
443 if (isOprNot(N->getOperand(0).Val))
444 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)),
445 Select(N->getOperand(0).getOperand(0)));
446 else if (isOprNot(N->getOperand(1).Val))
447 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)),
448 Select(N->getOperand(1).getOperand(0)));
449 else
450 CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)),
451 Select(N->getOperand(1)));
452 break;
453 }
Nate Begeman0f3257a2005-08-18 05:00:13 +0000454 case ISD::XOR:
455 // Check whether or not this node is a logical 'not'. This is represented
456 // by llvm as a xor with the constant value -1 (all bits set). If this is a
457 // 'not', then fold 'or' into 'nor', and so forth for the supported ops.
458 if (isOprNot(N)) {
459 unsigned Opc;
Nate Begeman131a8802005-08-18 05:44:50 +0000460 SDOperand Val = Select(N->getOperand(0));
461 switch (Val.getTargetOpcode()) {
Nate Begeman0f3257a2005-08-18 05:00:13 +0000462 default: Opc = 0; break;
Nate Begeman131a8802005-08-18 05:44:50 +0000463 case PPC::OR: Opc = PPC::NOR; break;
464 case PPC::AND: Opc = PPC::NAND; break;
465 case PPC::XOR: Opc = PPC::EQV; break;
Nate Begeman0f3257a2005-08-18 05:00:13 +0000466 }
467 if (Opc)
Nate Begeman131a8802005-08-18 05:44:50 +0000468 CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0),
469 Val.getOperand(1));
Nate Begeman0f3257a2005-08-18 05:00:13 +0000470 else
Nate Begeman131a8802005-08-18 05:44:50 +0000471 CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val);
Nate Begeman0f3257a2005-08-18 05:00:13 +0000472 break;
473 }
474 // If this is a xor with an immediate other than -1, then codegen it as high
475 // and low 16 bit immediate xors.
476 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0),
477 N->getOperand(1),
478 PPC::XORIS, PPC::XORI)) {
479 CurDAG->ReplaceAllUsesWith(N, I);
480 N = I;
481 break;
482 }
483 // Finally, check for the case where we are being asked to select
484 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv
485 if (isOprNot(N->getOperand(0).Val))
486 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV,
487 Select(N->getOperand(0).getOperand(0)),
488 Select(N->getOperand(1)));
489 else
490 CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)),
491 Select(N->getOperand(1)));
492 break;
Nate Begeman305a1c72005-08-18 03:04:18 +0000493 case ISD::FABS:
Nate Begeman6a7d6112005-08-18 00:53:47 +0000494 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS,
495 Select(N->getOperand(0)));
496 break;
Nate Begeman305a1c72005-08-18 03:04:18 +0000497 case ISD::FP_EXTEND:
498 assert(MVT::f64 == N->getValueType(0) &&
499 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND");
500 CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0)));
501 break;
502 case ISD::FP_ROUND:
503 assert(MVT::f32 == N->getValueType(0) &&
504 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND");
505 CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0)));
506 break;
Nate Begeman26653502005-08-17 23:46:35 +0000507 case ISD::FNEG: {
508 SDOperand Val = Select(N->getOperand(0));
509 MVT::ValueType Ty = N->getValueType(0);
510 if (Val.Val->hasOneUse()) {
511 unsigned Opc;
512 switch (Val.getTargetOpcode()) {
513 default: Opc = 0; break;
514 case PPC::FABS: Opc = PPC::FNABS; break;
515 case PPC::FMADD: Opc = PPC::FNMADD; break;
516 case PPC::FMADDS: Opc = PPC::FNMADDS; break;
517 case PPC::FMSUB: Opc = PPC::FNMSUB; break;
518 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break;
519 }
520 // If we inverted the opcode, then emit the new instruction with the
521 // inverted opcode and the original instruction's operands. Otherwise,
522 // fall through and generate a fneg instruction.
523 if (Opc) {
524 if (PPC::FNABS == Opc)
525 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0));
526 else
527 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0),
528 Val.getOperand(1), Val.getOperand(2));
529 break;
530 }
531 }
532 CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val);
533 break;
534 }
Nate Begeman6a7d6112005-08-18 00:53:47 +0000535 case ISD::FSQRT: {
536 MVT::ValueType Ty = N->getValueType(0);
537 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS,
538 Select(N->getOperand(0)));
539 break;
540 }
Chris Lattnera5a91b12005-08-17 19:33:03 +0000541 case ISD::RET: {
542 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
543
544 if (N->getNumOperands() > 1) {
545 SDOperand Val = Select(N->getOperand(1));
546 switch (N->getOperand(1).getValueType()) {
547 default: assert(0 && "Unknown return type!");
548 case MVT::f64:
549 case MVT::f32:
550 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
551 break;
552 case MVT::i32:
553 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
554 break;
555 }
556
557 if (N->getNumOperands() > 2) {
558 assert(N->getOperand(1).getValueType() == MVT::i32 &&
559 N->getOperand(2).getValueType() == MVT::i32 &&
560 N->getNumOperands() == 2 && "Unknown two-register ret value!");
561 Val = Select(N->getOperand(2));
562 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
563 }
564 }
565
566 // Finally, select this to a blr (return) instruction.
567 CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
568 break;
569 }
570 }
571 return SDOperand(N, 0);
572}
573
574
575/// createPPC32ISelDag - This pass converts a legalized DAG into a
576/// PowerPC-specific DAG, ready for instruction scheduling.
577///
578FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
579 return new PPC32DAGToDAGISel(TM);
580}
581