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Chris Lattner697954c2002-01-20 22:54:45 +00001/* Title: PhyRegAlloc.h -*- C++ -*-
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +00002 Author: Ruchira Sasanka
3 Date: Aug 20, 01
4 Purpose: This is the main entry point for register allocation.
5
6 Notes:
Ruchira Sasanka42bd1772002-01-07 19:16:26 +00007 =====
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +00008
9 * RegisterClasses: Each RegClass accepts a
Chris Lattnerd0f166a2002-12-29 03:13:05 +000010 TargetRegClass which contains machine specific info about that register
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000011 class. The code in the RegClass is machine independent and they use
Chris Lattnerd0f166a2002-12-29 03:13:05 +000012 access functions in the TargetRegClass object passed into it to get
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000013 machine specific info.
14
15 * Machine dependent work: All parts of the register coloring algorithm
16 except coloring of an individual node are machine independent.
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000017*/
18
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000019#ifndef PHY_REG_ALLOC_H
20#define PHY_REG_ALLOC_H
21
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000022#include "llvm/CodeGen/RegClass.h"
23#include "llvm/CodeGen/LiveRangeInfo.h"
Chris Lattner97453d62002-04-28 20:40:16 +000024#include <map>
25
Misha Brukmanfce11432002-10-28 00:28:31 +000026class MachineFunction;
Chris Lattnerd0f166a2002-12-29 03:13:05 +000027class TargetRegInfo;
Chris Lattner483e14e2002-04-27 07:27:19 +000028class FunctionLiveVarInfo;
Chris Lattner2182c782002-02-04 05:52:08 +000029class MachineInstr;
Chris Lattner8fc2f202002-04-28 16:19:42 +000030class LoopInfo;
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000031
32//----------------------------------------------------------------------------
33// Class AddedInstrns:
34// When register allocator inserts new instructions in to the existing
35// instruction stream, it does NOT directly modify the instruction stream.
36// Rather, it creates an object of AddedInstrns and stick it in the
37// AddedInstrMap for an existing instruction. This class contains two vectors
38// to store such instructions added before and after an existing instruction.
39//----------------------------------------------------------------------------
40
Chris Lattner0b0ffa02002-04-09 05:13:04 +000041struct AddedInstrns {
Chris Lattnerccdf23e2002-10-28 19:43:23 +000042 std::vector<MachineInstr*> InstrnsBefore;//Insts added BEFORE an existing inst
43 std::vector<MachineInstr*> InstrnsAfter; //Insts added AFTER an existing inst
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000044};
45
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000046//----------------------------------------------------------------------------
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000047// class PhyRegAlloc:
48// Main class the register allocator. Call allocateRegisters() to allocate
Chris Lattnerb7653df2002-04-08 22:03:57 +000049// registers for a Function.
Ruchira Sasanka20c82b12001-10-28 18:15:12 +000050//----------------------------------------------------------------------------
51
Chris Lattner3e0f8282002-02-04 17:38:48 +000052class PhyRegAlloc: public NonCopyable {
Chris Lattner697954c2002-01-20 22:54:45 +000053 std::vector<RegClass *> RegClassList; // vector of register classes
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000054 const TargetMachine &TM; // target machine
Chris Lattnerccdf23e2002-10-28 19:43:23 +000055 const Function *Fn; // name of the function we work on
56 MachineFunction &MF; // descriptor for method's native code
Chris Lattner8fc2f202002-04-28 16:19:42 +000057 FunctionLiveVarInfo *const LVI; // LV information for this method
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000058 // (already computed for BBs)
59 LiveRangeInfo LRI; // LR info (will be computed)
Chris Lattnerd0f166a2002-12-29 03:13:05 +000060 const TargetRegInfo &MRI; // Machine Register information
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000061 const unsigned NumOfRegClasses; // recorded here for efficiency
62
Ruchira Sasanka51bc0e72001-11-03 17:14:44 +000063
Chris Lattnerea9d2492002-10-29 17:08:05 +000064 // AddedInstrMap - Used to store instrns added in this phase
65 std::map<const MachineInstr *, AddedInstrns> AddedInstrMap;
66
Vikram S. Adved23a2292002-04-25 04:46:28 +000067 AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
Chris Lattner8fc2f202002-04-28 16:19:42 +000068 LoopInfo *LoopDepthCalc; // to calculate loop depths
Ruchira Sasanka42bd1772002-01-07 19:16:26 +000069 ReservedColorListType ResColList; // A set of reserved regs if desired.
70 // currently not used
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000071
Chris Lattner3e0f8282002-02-04 17:38:48 +000072public:
Chris Lattner483e14e2002-04-27 07:27:19 +000073 PhyRegAlloc(Function *F, const TargetMachine& TM, FunctionLiveVarInfo *Lvi,
Chris Lattner8fc2f202002-04-28 16:19:42 +000074 LoopInfo *LoopDepthCalc);
Chris Lattner3e0f8282002-02-04 17:38:48 +000075 ~PhyRegAlloc();
76
77 // main method called for allocating registers
78 //
79 void allocateRegisters();
Vikram S. Adve705f95e2002-03-18 03:26:48 +000080
81
82 // access to register classes by class ID
83 //
84 const RegClass* getRegClassByID(unsigned int id) const {
85 return RegClassList[id];
86 }
87 RegClass* getRegClassByID(unsigned int id) {
88 return RegClassList[id]; }
89
90
Chris Lattner3e0f8282002-02-04 17:38:48 +000091private:
Chris Lattner5e5dfa32002-02-05 02:51:01 +000092 void addInterference(const Value *Def, const ValueSet *LVSet,
93 bool isCallInst);
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +000094
95 void addInterferencesForArgs();
96 void createIGNodeListsAndIGs();
97 void buildInterferenceGraphs();
Ruchira Sasankac4d4b762001-10-16 01:23:19 +000098
Ruchira Sasanka36f77072001-10-19 17:21:59 +000099 void setCallInterferences(const MachineInstr *MInst,
Chris Lattner5e5dfa32002-02-05 02:51:01 +0000100 const ValueSet *LVSetAft );
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000101
Ruchira Sasankaf7434f02001-10-23 21:38:42 +0000102 void move2DelayedInstr(const MachineInstr *OrigMI,
103 const MachineInstr *DelayedMI );
104
Ruchira Sasanka44d2b942001-10-19 21:42:06 +0000105 void markUnusableSugColors();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000106 void allocateStackSpace4SpilledLRs();
107
Chris Lattner00d91c62001-11-08 20:55:05 +0000108 void insertCode4SpilledLR (const LiveRange *LR,
109 MachineInstr *MInst,
110 const BasicBlock *BB,
111 const unsigned OpNum);
Ruchira Sasanka44d2b942001-10-19 21:42:06 +0000112
Chris Lattner697954c2002-01-20 22:54:45 +0000113 inline void constructLiveRanges() { LRI.constructLiveRanges(); }
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000114
115 void colorIncomingArgs();
Ruchira Sasankaab304c42001-09-30 23:19:57 +0000116 void colorCallRetArgs();
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000117 void updateMachineCode();
Ruchira Sasankaab304c42001-09-30 23:19:57 +0000118
Ruchira Sasanka6053b932001-09-15 19:08:41 +0000119 void printLabel(const Value *const Val);
120 void printMachineCode();
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000121
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000122
Chris Lattnerea9d2492002-10-29 17:08:05 +0000123 friend class UltraSparcRegInfo; // FIXME: remove this
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000124
Vikram S. Advec2580dd2002-07-08 22:39:36 +0000125 int getUsableUniRegAtMI(int RegType,
126 const ValueSet *LVSetBef,
127 MachineInstr *MInst,
128 std::vector<MachineInstr*>& MIBef,
129 std::vector<MachineInstr*>& MIAft);
130
Ruchira Sasanka825dd552001-11-15 20:22:37 +0000131 int getUnusedUniRegAtMI(RegClass *RC, const MachineInstr *MInst,
Vikram S. Advec2580dd2002-07-08 22:39:36 +0000132 const ValueSet *LVSetBef);
Ruchira Sasanka80b1a1a2001-11-03 20:41:22 +0000133
Ruchira Sasanka825dd552001-11-15 20:22:37 +0000134 void setRelRegsUsedByThisInst(RegClass *RC, const MachineInstr *MInst );
135 int getUniRegNotUsedByThisInst(RegClass *RC, const MachineInstr *MInst);
Ruchira Sasanka20c82b12001-10-28 18:15:12 +0000136
Ruchira Sasankacbddf492001-11-14 15:37:13 +0000137 void addInterf4PseudoInstr(const MachineInstr *MInst);
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000138};
139
140
Ruchira Sasanka7cd2ca12001-09-08 14:22:50 +0000141#endif
142